Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33325	1			T2	12		T5	37		T6	71
auto[SpiFlashAddrCfg]	6362	1			T5	21		T6	24		T8	38
auto[SpiFlashAddr3b]	7717	1			T5	25		T6	17		T8	32
auto[SpiFlashAddr4b]	6382	1			T5	21		T6	19		T8	20

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30780

1

T2

12

T5

61

T6

88

auto[1]

23006

1

T5

43

T6

43

T8

87

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28217

1

T5

55

T6

57

T8

115

auto[1]

25569

1

T2

12

T5

49

T6

74

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37157	1			T2	12		T5	47		T6	77
values[1]	897	1			T5	4		T6	4		T8	9
values[2]	1265	1			T5	2		T6	6		T8	2
values[3]	1209	1			T5	6		T6	6		T8	5
values[4]	1243	1			T5	1		T8	4		T15	4
values[5]	1263	1			T5	10		T6	5		T8	4
values[6]	1251	1			T5	6		T6	5		T8	8
values[7]	1237	1			T5	7		T6	1		T8	8
values[8]	8264	1			T5	21		T6	27		T8	36

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24542

1

T2

12

T5

104

T6

131

auto[1]

29244

1

T8

189

T19

7

T20

139

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

51012

1

T2

12

T5

101

T6

125

write

2774

1

T5

3

T6

6

T8

15

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16293

1

T5

47

T6

45

T8

78

valids[0x1]

37493

1

T2

12

T5

57

T6

86

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1399	1			T2	6		T5	5		T6	5
internal_process_ops[0x5a]	1382	1			T5	3		T6	4		T8	7
internal_process_ops[0x05]	21188	1			T2	6		T5	8		T6	35
internal_process_ops[0x35]	1372	1			T5	1		T6	5		T8	5
internal_process_ops[0x15]	1433	1			T5	8		T6	4		T8	4
internal_process_ops[0x03]	879	1			T5	3		T6	6		T8	2
internal_process_ops[0x0b]	813	1			T5	4		T6	4		T8	1
internal_process_ops[0x3b]	857	1			T5	3		T6	3		T8	3
internal_process_ops[0x6b]	862	1			T5	3		T6	4		T8	3
internal_process_ops[0xbb]	872	1			T5	5		T6	1		T8	4
internal_process_ops[0xeb]	839	1			T5	3		T6	1		T8	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52421

1

T2

12

T5

101

T6

128

auto[1]

1365

1

T5

3

T6

3

T8

13

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51845

1

T2

12

T5

101

T6

128

auto[1]

1941

1

T5

3

T6

3

T8

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8991

1

T2

12

T5

23

T6

60

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4503

1

T5

11

T6

9

T15

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1625

1

T5

10

T6

8

T17

27

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1445

1

T5

11

T6

15

T15

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2040

1

T5

13

T6

10

T12

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1616

1

T5

12

T6

4

T15

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1702

1

T5

13

T6

8

T17

25

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1349

1

T5

8

T6

11

T15

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

111

1

T17

2

T47

3

T24

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

81

1

T5

2

T17

2

T46

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

60

1

T47

2

T43

1

T24

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

79

1

T5

1

T6

2

T17

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

89

1

T6

1

T24

1

T66

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

55

1

T46

2

T51

1

T26

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

73

1

T17

2

T47

2

T50

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

88

1

T17

1

T47

6

T50

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

102

1

T17

3

T51

4

T52

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

76

1

T6

1

T17

1

T49

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

71

1

T6

2

T17

2

T47

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

70

1

T15

2

T17

3

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

94

1

T47

2

T51

1

T155

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

80

1

T17

3

T47

3

T50

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

69

1

T47

1

T50

1

T24

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

73

1

T17

1

T50

3

T43

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10588

1

T8

50

T20

42

T45

11

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8557

1

T8

45

T20

40

T45

20

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1249

1

T8

12

T19

1

T20

6

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1349

1

T8

24

T20

10

T45

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1769

1

T8

18

T19

3

T20

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1614

1

T8

11

T20

12

T45

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1374

1

T8

10

T19

3

T20

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1241

1

T8

4

T20

6

T45

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

75

1

T8

1

T20

2

T21

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

102

1

T8

2

T45

1

T59

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

79

1

T59

1

T24

3

T27

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

99

1

T8

1

T54

4

T21

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

87

1

T59

1

T21

2

T24

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

87

1

T54

3

T59

2

T24

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

119

1

T8

1

T26

2

T28

10

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

96

1

T8

1

T24

1

T26

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

111

1

T20

5

T59

3

T24

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

85

1

T8

3

T20

1

T21

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

91

1

T59

2

T24

2

T25

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

72

1

T26

2

T156

1

T157

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

92

1

T45

1

T59

1

T21

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

115

1

T8

6

T59

2

T21

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

86

1

T21

1

T25

1

T27

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

107

1

T20

1

T54

2

T59

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3036	1			T5	14		T6	15		T17	43
auto[0]	values[0]	valids[0x1]	12689	1			T2	12		T5	33		T6	62
auto[0]	values[1]	valids[0x1]	408	1			T5	4		T6	4		T17	9
auto[0]	values[2]	valids[0x0]	446	1			T5	2		T6	4		T15	2
auto[0]	values[2]	valids[0x1]	252	1			T6	2		T17	3		T47	1
auto[0]	values[3]	valids[0x0]	428	1			T5	4		T6	4		T17	7
auto[0]	values[3]	valids[0x1]	232	1			T5	2		T6	2		T17	5
auto[0]	values[4]	valids[0x0]	424	1			T5	1		T17	9		T46	1
auto[0]	values[4]	valids[0x1]	249	1			T15	4		T47	9		T50	7
auto[0]	values[5]	valids[0x0]	410	1			T5	5		T6	4		T17	3
auto[0]	values[5]	valids[0x1]	243	1			T5	5		T6	1		T17	12
auto[0]	values[6]	valids[0x0]	432	1			T5	4		T6	4		T17	10
auto[0]	values[6]	valids[0x1]	230	1			T5	2		T6	1		T17	2
auto[0]	values[7]	valids[0x0]	420	1			T5	6		T15	4		T17	8
auto[0]	values[7]	valids[0x1]	251	1			T5	1		T6	1		T17	7
auto[0]	values[8]	valids[0x0]	2782	1			T5	11		T6	14		T15	2
auto[0]	values[8]	valids[0x1]	1610	1			T5	10		T6	13		T15	6
auto[1]	values[0]	valids[0x0]	3636	1			T8	36		T20	21		T45	8
auto[1]	values[0]	valids[0x1]	17796	1			T8	77		T19	3		T20	74
auto[1]	values[1]	valids[0x1]	489	1			T8	9		T20	2		T54	7
auto[1]	values[2]	valids[0x0]	318	1			T8	1		T54	1		T59	9
auto[1]	values[2]	valids[0x1]	249	1			T8	1		T20	2		T45	2
auto[1]	values[3]	valids[0x0]	311	1			T8	1		T20	1		T54	2
auto[1]	values[3]	valids[0x1]	238	1			T8	4		T45	4		T54	1
auto[1]	values[4]	valids[0x0]	338	1			T8	3		T20	3		T45	1
auto[1]	values[4]	valids[0x1]	232	1			T8	1		T59	3		T21	5
auto[1]	values[5]	valids[0x0]	352	1			T8	2		T54	4		T59	8
auto[1]	values[5]	valids[0x1]	258	1			T8	2		T20	3		T45	2
auto[1]	values[6]	valids[0x0]	347	1			T8	7		T20	5		T45	1
auto[1]	values[6]	valids[0x1]	242	1			T8	1		T20	2		T54	3
auto[1]	values[7]	valids[0x0]	359	1			T8	4		T20	6		T54	1
auto[1]	values[7]	valids[0x1]	207	1			T8	4		T54	1		T59	1
auto[1]	values[8]	valids[0x0]	2254	1			T8	24		T19	4		T20	10
auto[1]	values[8]	valids[0x1]	1618	1			T8	12		T20	10		T45	1