Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2815970

1

T2

24495

T5

7905

T6

7166

auto[1]

19857

1

T5

4

T6

31

T8

29

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

832971

1

T2

24495

T5

23

T6

37

auto[1]

2002856

1

T5

7886

T6

7160

T8

8894

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	504832	1			T2	342		T5	11		T6	130
auto[524288:1048575]	290938	1			T2	530		T5	2595		T6	4
auto[1048576:1572863]	297134	1			T2	11574		T5	1157		T8	634
auto[1572864:2097151]	294294	1			T5	264		T6	5053		T8	4
auto[2097152:2621439]	371921	1			T2	3203		T5	2854		T6	5
auto[2621440:3145727]	348678	1			T2	4		T8	567		T17	6713
auto[3145728:3670015]	375012	1			T2	2885		T6	2		T8	2266
auto[3670016:4194303]	353018	1			T2	5957		T5	1028		T6	2003

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2022801

1

T2

92

T5

7909

T6

7194

auto[1]

813026

1

T2

24403

T6

3

T12

10361

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2486134

1

T2

24495

T5

7905

T6

7184

auto[1]

349693

1

T5

4

T6

13

T8

3504

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	151573	1			T2	342		T5	4		T6	4
auto[0]	auto[0]	auto[0:524287]	auto[1]	304073	1			T5	6		T6	119		T8	259
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	75166	1			T2	530		T6	1		T8	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	163678	1			T5	2593		T6	2		T8	1960
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	88294	1			T2	11574		T5	5		T8	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	176498	1			T5	1152		T8	371		T17	257
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	78266	1			T5	3		T6	9		T8	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	178616	1			T5	258		T6	5038		T8	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	105561	1			T2	3203		T5	2		T8	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	218776	1			T5	2852		T8	1		T17	257
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	86895	1			T2	4		T8	14		T17	14
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	200141	1			T8	537		T17	5866		T20	387
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	118739	1			T2	2885		T6	1		T8	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	211595	1			T8	2260		T17	257		T20	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	115899	1			T2	5957		T5	2		T6	9
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	196996	1			T5	1024		T6	1970		T17	260
auto[0]	auto[1]	auto[0:524287]	auto[0]	662	1			T17	6		T20	2		T50	5
auto[0]	auto[1]	auto[0:524287]	auto[1]	45492	1			T17	515		T20	2153		T50	256
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1191	1			T5	2		T6	1		T8	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	48533	1			T8	3232		T50	1009		T54	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	335	1			T50	1		T45	1		T59	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	29694	1			T8	256		T50	1		T45	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2120	1			T6	3		T20	1		T50	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	33205	1			T6	3		T20	768		T50	257
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	316	1			T6	5		T17	1		T20	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	44746	1			T20	406		T47	3098		T54	2558
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2031	1			T8	1		T17	5		T50	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	57073	1			T17	738		T50	2455		T43	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	3139	1			T6	1		T8	2		T20	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	38889	1			T8	1		T20	133		T54	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	842	1			T5	2		T17	1		T21	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	36936	1			T17	2607		T59	640		T21	2668
auto[1]	auto[0]	auto[0:524287]	auto[0]	244	1			T5	1		T6	1		T20	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2319	1			T6	6		T20	2		T47	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	170	1			T17	2		T47	1		T43	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1544	1			T17	1		T47	10		T43	32
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	186	1			T8	2		T17	1		T47	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1691	1			T17	34		T47	7		T50	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	169	1			T5	2		T8	1		T17	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1503	1			T5	1		T8	1		T20	24
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	187	1			T8	1		T17	1		T47	8
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1724	1			T8	1		T17	36		T47	62
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	193	1			T8	5		T17	5		T47	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1660	1			T8	10		T17	80		T47	20
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	184	1			T20	3		T50	2		T59	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1766	1			T20	1		T50	4		T59	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	195	1			T6	2		T17	1		T54	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1633	1			T6	22		T17	6		T59	9
auto[1]	auto[1]	auto[0:524287]	auto[0]	50	1			T17	1		T59	1		T178	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	419	1			T17	1		T59	1		T178	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	60	1			T8	3		T50	2		T54	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	596	1			T8	4		T50	7		T27	51
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	41	1			T50	1		T51	3		T195	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	395	1			T50	1		T51	13		T195	25
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	43	1			T54	1		T24	1		T51	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	372	1			T54	1		T24	1		T51	10
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	58	1			T20	1		T47	2		T49	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	553	1			T20	2		T47	25		T49	10
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	50	1			T17	1		T43	1		T24	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	635	1			T17	4		T43	55		T24	6
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	57	1			T8	1		T54	1		T24	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	643	1			T24	9		T51	40		T52	54
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	55	1			T17	1		T21	2		T49	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	462	1			T17	46		T21	13		T49	26

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1666434	1			T2	92		T5	7901		T6	7152
auto[0]	auto[0]	auto[1]	804332	1			T2	24403		T6	1		T12	10361
auto[0]	auto[1]	auto[0]	336898	1			T5	4		T6	13		T8	3496
auto[0]	auto[1]	auto[1]	8306	1			T47	2		T89	4		T51	3
auto[1]	auto[0]	auto[0]	15070	1			T5	4		T6	29		T8	21
auto[1]	auto[0]	auto[1]	298	1			T6	2		T20	2		T47	10
auto[1]	auto[1]	auto[0]	4399	1			T8	8		T17	54		T20	2
auto[1]	auto[1]	auto[1]	90	1			T20	1		T47	1		T54	1