Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15046

1

T2

12

T5

61

T6

88

auto[1]

9496

1

T5

43

T6

43

T15

28

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2822	1			T5	40		T12	4		T17	47
values[1]	3120	1			T47	127		T50	53		T24	20
values[2]	3253	1			T17	209		T18	2		T46	20
values[3]	2821	1			T6	20		T47	44		T50	20
values[4]	3119	1			T2	12		T5	24		T6	20
values[5]	2895	1			T6	91		T15	28		T17	22
values[6]	3236	1			T5	40		T17	184		T47	71
values[7]	3276	1			T47	28		T48	23		T50	31

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3175	1			T2	12		T5	20		T6	20
values[1]	3340	1			T15	28		T17	25		T47	66
values[2]	3609	1			T5	24		T47	81		T50	58
values[3]	2931	1			T5	20		T12	4		T17	140
values[4]	3282	1			T6	40		T17	114		T47	88
values[5]	2504	1			T5	40		T17	54		T47	25
values[6]	2639	1			T6	71		T17	60		T18	2
values[7]	3062	1			T17	22		T47	55		T43	106

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	188	1			T205	22		T28	16		T209	9
auto[0]	values[0]	values[1]	210	1			T208	21		T182	8		T32	12
auto[0]	values[0]	values[2]	349	1			T172	10		T155	16		T194	14
auto[0]	values[0]	values[3]	194	1			T5	11		T12	4		T189	14
auto[0]	values[0]	values[4]	151	1			T47	12		T50	8		T172	14
auto[0]	values[0]	values[5]	175	1			T5	11		T17	17		T52	12
auto[0]	values[0]	values[6]	133	1			T17	9		T47	33		T24	19
auto[0]	values[0]	values[7]	295	1			T47	24		T43	7		T24	16
auto[0]	values[1]	values[0]	165	1			T47	32		T49	6		T81	10
auto[0]	values[1]	values[1]	252	1			T66	11		T31	12		T210	20
auto[0]	values[1]	values[2]	384	1			T47	44		T50	8		T52	8
auto[0]	values[1]	values[3]	302	1			T28	14		T171	13		T168	27
auto[0]	values[1]	values[4]	200	1			T47	9		T172	9		T181	13
auto[0]	values[1]	values[5]	225	1			T50	8		T24	17		T52	13
auto[0]	values[1]	values[6]	284	1			T66	19		T28	30		T188	53
auto[0]	values[1]	values[7]	147	1			T178	13		T155	11		T201	12
auto[0]	values[2]	values[0]	279	1			T17	25		T46	15		T50	21
auto[0]	values[2]	values[1]	262	1			T17	12		T81	15		T167	14
auto[0]	values[2]	values[2]	211	1			T199	12		T51	62		T187	9
auto[0]	values[2]	values[3]	241	1			T17	11		T176	14		T52	13
auto[0]	values[2]	values[4]	238	1			T50	9		T172	10		T124	4
auto[0]	values[2]	values[5]	251	1			T43	42		T178	8		T172	30
auto[0]	values[2]	values[6]	183	1			T17	17		T18	2		T52	15
auto[0]	values[2]	values[7]	216	1			T81	9		T185	7		T188	10
auto[0]	values[3]	values[0]	248	1			T33	16		T172	9		T81	70
auto[0]	values[3]	values[1]	226	1			T47	16		T52	12		T185	11
auto[0]	values[3]	values[2]	228	1			T52	63		T90	8		T195	8
auto[0]	values[3]	values[3]	160	1			T50	7		T52	26		T31	16
auto[0]	values[3]	values[4]	276	1			T185	18		T168	15		T211	13
auto[0]	values[3]	values[5]	195	1			T190	14		T43	10		T212	4
auto[0]	values[3]	values[6]	212	1			T6	8		T52	15		T77	17
auto[0]	values[3]	values[7]	156	1			T47	11		T206	10		T24	29
auto[0]	values[4]	values[0]	386	1			T2	12		T17	9		T194	21
auto[0]	values[4]	values[1]	209	1			T178	10		T171	8		T213	14
auto[0]	values[4]	values[2]	363	1			T5	11		T89	24		T214	4
auto[0]	values[4]	values[3]	228	1			T188	63		T182	12		T174	13
auto[0]	values[4]	values[4]	135	1			T6	8		T47	15		T49	11
auto[0]	values[4]	values[5]	248	1			T215	8		T181	7		T216	10
auto[0]	values[4]	values[6]	156	1			T28	8		T188	8		T217	8
auto[0]	values[4]	values[7]	310	1			T58	10		T28	6		T188	25
auto[0]	values[5]	values[0]	257	1			T6	14		T185	12		T182	11
auto[0]	values[5]	values[1]	242	1			T26	10		T28	14		T195	16
auto[0]	values[5]	values[2]	180	1			T172	13		T77	7		T188	33
auto[0]	values[5]	values[3]	225	1			T26	14		T155	16		T185	12
auto[0]	values[5]	values[4]	247	1			T6	17		T52	112		T31	9
auto[0]	values[5]	values[5]	237	1			T52	48		T185	15		T122	8
auto[0]	values[5]	values[6]	303	1			T6	41		T46	12		T50	12
auto[0]	values[5]	values[7]	135	1			T17	15		T51	8		T49	8
auto[0]	values[6]	values[0]	262	1			T5	10		T50	11		T218	15
auto[0]	values[6]	values[1]	200	1			T47	8		T155	12		T31	16
auto[0]	values[6]	values[2]	163	1			T51	9		T79	2		T31	24
auto[0]	values[6]	values[3]	106	1			T17	11		T51	13		T172	13
auto[0]	values[6]	values[4]	378	1			T17	104		T50	4		T208	8
auto[0]	values[6]	values[5]	176	1			T5	18		T17	12		T47	16
auto[0]	values[6]	values[6]	303	1			T17	13		T50	13		T51	18
auto[0]	values[6]	values[7]	330	1			T43	11		T219	2		T49	26
auto[0]	values[7]	values[0]	221	1			T81	10		T175	24		T220	2
auto[0]	values[7]	values[1]	237	1			T221	14		T49	33		T208	11
auto[0]	values[7]	values[2]	393	1			T47	10		T50	13		T155	10
auto[0]	values[7]	values[3]	456	1			T100	4		T57	16		T222	6
auto[0]	values[7]	values[4]	276	1			T48	23		T51	30		T155	19
auto[0]	values[7]	values[5]	118	1			T49	10		T223	9		T224	4
auto[0]	values[7]	values[6]	178	1			T66	32		T194	11		T195	14
auto[0]	values[7]	values[7]	152	1			T178	13		T172	14		T188	14
auto[1]	values[0]	values[0]	98	1			T28	6		T209	11		T197	11
auto[1]	values[0]	values[1]	185	1			T180	18		T208	7		T182	17
auto[1]	values[0]	values[2]	182	1			T172	10		T155	4		T194	38
auto[1]	values[0]	values[3]	104	1			T5	9		T189	6		T169	23
auto[1]	values[0]	values[4]	87	1			T47	8		T50	12		T172	10
auto[1]	values[0]	values[5]	98	1			T5	9		T17	10		T52	8
auto[1]	values[0]	values[6]	118	1			T17	11		T47	8		T24	27
auto[1]	values[0]	values[7]	255	1			T47	7		T43	79		T24	10
auto[1]	values[1]	values[0]	159	1			T47	22		T49	36		T81	38
auto[1]	values[1]	values[1]	202	1			T66	25		T31	11		T225	17
auto[1]	values[1]	values[2]	209	1			T47	9		T50	19		T52	12
auto[1]	values[1]	values[3]	106	1			T28	11		T171	10		T168	7
auto[1]	values[1]	values[4]	171	1			T47	11		T172	12		T181	10
auto[1]	values[1]	values[5]	114	1			T50	18		T24	3		T52	7
auto[1]	values[1]	values[6]	74	1			T66	1		T28	16		T188	7
auto[1]	values[1]	values[7]	126	1			T178	7		T155	35		T226	10
auto[1]	values[2]	values[0]	308	1			T17	22		T46	5		T50	3
auto[1]	values[2]	values[1]	208	1			T17	13		T81	13		T188	8
auto[1]	values[2]	values[2]	167	1			T51	11		T187	17		T227	10
auto[1]	values[2]	values[3]	189	1			T17	106		T52	7		T81	5
auto[1]	values[2]	values[4]	135	1			T50	11		T172	10		T174	5
auto[1]	values[2]	values[5]	144	1			T43	12		T178	12		T172	29
auto[1]	values[2]	values[6]	73	1			T17	3		T52	6		T81	10
auto[1]	values[2]	values[7]	148	1			T81	64		T185	13		T188	45
auto[1]	values[3]	values[0]	168	1			T172	11		T81	14		T194	24
auto[1]	values[3]	values[1]	194	1			T47	4		T52	8		T185	10
auto[1]	values[3]	values[2]	129	1			T52	8		T195	61		T188	5
auto[1]	values[3]	values[3]	82	1			T50	13		T52	8		T31	4
auto[1]	values[3]	values[4]	160	1			T185	5		T168	32		T211	20
auto[1]	values[3]	values[5]	108	1			T43	10		T228	13		T181	13
auto[1]	values[3]	values[6]	151	1			T6	12		T52	5		T229	8
auto[1]	values[3]	values[7]	128	1			T47	13		T24	22		T186	8
auto[1]	values[4]	values[0]	159	1			T17	11		T194	66		T171	8
auto[1]	values[4]	values[1]	89	1			T178	10		T171	12		T213	10
auto[1]	values[4]	values[2]	157	1			T5	13		T213	21		T55	39
auto[1]	values[4]	values[3]	101	1			T188	9		T182	11		T174	7
auto[1]	values[4]	values[4]	213	1			T6	12		T47	33		T49	9
auto[1]	values[4]	values[5]	48	1			T181	13		T200	13		T230	9
auto[1]	values[4]	values[6]	55	1			T28	12		T188	12		T231	18
auto[1]	values[4]	values[7]	262	1			T28	22		T232	2		T188	76
auto[1]	values[5]	values[0]	86	1			T6	6		T185	8		T182	12
auto[1]	values[5]	values[1]	200	1			T15	28		T26	17		T28	25
auto[1]	values[5]	values[2]	165	1			T172	7		T77	49		T188	4
auto[1]	values[5]	values[3]	116	1			T26	8		T155	16		T185	8
auto[1]	values[5]	values[4]	87	1			T6	3		T52	11		T31	12
auto[1]	values[5]	values[5]	178	1			T52	6		T185	5		T31	14
auto[1]	values[5]	values[6]	147	1			T6	10		T46	8		T50	8
auto[1]	values[5]	values[7]	90	1			T17	7		T51	12		T49	12
auto[1]	values[6]	values[0]	83	1			T5	10		T50	11		T218	5
auto[1]	values[6]	values[1]	323	1			T47	38		T155	9		T31	4
auto[1]	values[6]	values[2]	139	1			T51	84		T31	4		T55	18
auto[1]	values[6]	values[3]	144	1			T17	12		T51	12		T172	7
auto[1]	values[6]	values[4]	270	1			T17	10		T50	16		T208	12
auto[1]	values[6]	values[5]	105	1			T5	2		T17	15		T47	9
auto[1]	values[6]	values[6]	98	1			T17	7		T50	7		T51	9
auto[1]	values[6]	values[7]	156	1			T43	9		T49	39		T81	8
auto[1]	values[7]	values[0]	108	1			T81	11		T175	9		T233	10
auto[1]	values[7]	values[1]	101	1			T49	18		T208	12		T81	11
auto[1]	values[7]	values[2]	190	1			T47	18		T50	18		T155	12
auto[1]	values[7]	values[3]	177	1			T49	94		T81	9		T194	12
auto[1]	values[7]	values[4]	258	1			T51	66		T155	90		T28	13
auto[1]	values[7]	values[5]	84	1			T49	15		T223	11		T152	13
auto[1]	values[7]	values[6]	171	1			T66	12		T194	9		T195	12
auto[1]	values[7]	values[7]	156	1			T178	10		T172	7		T188	6