Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2439744	1			T1	1		T2	1		T3	519
all_pins[1]	2439744	1			T1	1		T2	1		T3	519
all_pins[2]	2439744	1			T1	1		T2	1		T3	519
all_pins[3]	2439744	1			T1	1		T2	1		T3	519
all_pins[4]	2439744	1			T1	1		T2	1		T3	519
all_pins[5]	2439744	1			T1	1		T2	1		T3	519
all_pins[6]	2439744	1			T1	1		T2	1		T3	519
all_pins[7]	2439744	1			T1	1		T2	1		T3	519

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19486382	1			T1	8		T2	8		T3	4152
values[0x1]	31570	1			T21	26		T66	224		T26	9
transitions[0x0=>0x1]	29834	1			T21	23		T66	188		T26	6
transitions[0x1=>0x0]	29845	1			T21	23		T66	188		T26	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2439246	1			T1	1		T2	1		T3	519
all_pins[0]	values[0x1]	498	1			T21	2		T66	2		T26	1
all_pins[0]	transitions[0x0=>0x1]	400	1			T21	2		T66	1		T26	1
all_pins[0]	transitions[0x1=>0x0]	440	1			T21	3		T66	1		T26	2
all_pins[1]	values[0x0]	2439206	1			T1	1		T2	1		T3	519
all_pins[1]	values[0x1]	538	1			T21	3		T66	2		T26	2
all_pins[1]	transitions[0x0=>0x1]	413	1			T21	3		T66	1		T30	1
all_pins[1]	transitions[0x1=>0x0]	180	1			T21	1		T30	5		T31	1
all_pins[2]	values[0x0]	2439439	1			T1	1		T2	1		T3	519
all_pins[2]	values[0x1]	305	1			T21	1		T66	1		T26	2
all_pins[2]	transitions[0x0=>0x1]	245	1			T21	1		T66	1		T26	2
all_pins[2]	transitions[0x1=>0x0]	131	1			T21	3		T66	2		T26	1
all_pins[3]	values[0x0]	2439553	1			T1	1		T2	1		T3	519
all_pins[3]	values[0x1]	191	1			T21	3		T66	2		T26	1
all_pins[3]	transitions[0x0=>0x1]	137	1			T21	1		T66	2		T26	1
all_pins[3]	transitions[0x1=>0x0]	141	1			T21	2		T30	2		T31	1
all_pins[4]	values[0x0]	2439549	1			T1	1		T2	1		T3	519
all_pins[4]	values[0x1]	195	1			T21	4		T30	2		T31	4
all_pins[4]	transitions[0x0=>0x1]	152	1			T21	3		T30	2		T31	4
all_pins[4]	transitions[0x1=>0x0]	1708	1			T21	3		T66	38		T30	2
all_pins[5]	values[0x0]	2437993	1			T1	1		T2	1		T3	519
all_pins[5]	values[0x1]	1751	1			T21	4		T66	38		T30	2
all_pins[5]	transitions[0x0=>0x1]	483	1			T21	4		T66	4		T30	2
all_pins[5]	transitions[0x1=>0x0]	26635	1			T21	5		T66	145		T26	1
all_pins[6]	values[0x0]	2411841	1			T1	1		T2	1		T3	519
all_pins[6]	values[0x1]	27903	1			T21	5		T66	179		T26	1
all_pins[6]	transitions[0x0=>0x1]	27861	1			T21	5		T66	179		T26	1
all_pins[6]	transitions[0x1=>0x0]	147	1			T21	4		T26	2		T31	2
all_pins[7]	values[0x0]	2439555	1			T1	1		T2	1		T3	519
all_pins[7]	values[0x1]	189	1			T21	4		T26	2		T30	1
all_pins[7]	transitions[0x0=>0x1]	143	1			T21	4		T26	1		T30	1
all_pins[7]	transitions[0x1=>0x0]	463	1			T21	2		T66	2		T30	1