Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	352	1			T6	3		T17	7		T47	8
auto[ReadAddrCrossIntoMailbox]	235	1			T6	1		T17	4		T47	5
auto[ReadAddrCrossOutOfMailbox]	207	1			T6	1		T17	5		T46	1
auto[ReadAddrCrossAllMailbox]	144	1			T6	1		T17	3		T47	2
auto[ReadAddrOutsideMailbox]	2846	1			T5	21		T6	13		T15	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1903

1

T5

14

T6

13

T15

5

auto[1]

1881

1

T5

7

T6

6

T15

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	651	1			T5	3		T6	6		T15	4
read_ops[0x0b]	589	1			T5	4		T6	4		T17	10
read_ops[0x3b]	639	1			T5	3		T6	3		T17	14
read_ops[0x6b]	655	1			T5	3		T6	4		T17	12
read_ops[0xbb]	641	1			T5	5		T6	1		T15	4
read_ops[0xeb]	609	1			T5	3		T6	1		T15	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T6	2		T17	1		T24	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T17	1		T49	2		T31	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T6	1		T47	1		T206	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T47	1		T206	1		T77	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T6	1		T51	2		T155	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T81	1		T77	1		T31	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T50	1		T206	1		T185	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T206	1		T51	1		T81	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	263	1			T5	3		T6	2		T15	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	228	1			T15	2		T17	3		T47	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T47	1		T50	1		T43	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T6	1		T17	1		T50	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T47	2		T24	1		T49	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T51	1		T49	1		T172	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T47	1		T24	1		T52	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	13	1			T49	1		T77	1		T188	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T17	2		T81	1		T32	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T17	1		T51	1		T81	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	221	1			T5	3		T6	3		T17	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	223	1			T5	1		T17	1		T46	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T17	1		T47	1		T52	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T47	2		T24	1		T51	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T17	2		T188	1		T182	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T17	1		T51	1		T81	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T17	2		T66	1		T208	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T17	1		T47	1		T66	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T186	1		T211	2		T152	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T24	2		T66	1		T182	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	230	1			T6	1		T17	2		T47	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	246	1			T5	3		T6	2		T17	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T17	2		T47	3		T52	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T50	1		T51	1		T52	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T17	1		T52	3		T26	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T66	1		T51	1		T171	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T47	1		T206	1		T155	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	13	1			T206	1		T49	1		T175	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T47	1		T52	1		T172	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T49	1		T172	2		T194	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T5	2		T6	2		T17	6
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	228	1			T5	1		T6	2		T17	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T49	2		T172	1		T195	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T17	1		T66	1		T51	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T172	2		T171	1		T182	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T51	1		T26	1		T155	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	14	1			T52	1		T155	2		T31	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	10	1			T46	1		T155	1		T188	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T6	1		T66	1		T49	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T47	1		T28	2		T188	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	232	1			T5	4		T15	2		T17	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	259	1			T5	1		T15	2		T17	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T52	1		T49	1		T172	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T47	1		T81	2		T185	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T50	1		T31	1		T234	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T47	1		T81	2		T185	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T17	1		T24	1		T228	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T17	1		T81	1		T194	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T50	1		T49	1		T188	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T81	1		T171	1		T211	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	221	1			T5	2		T15	1		T17	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	243	1			T5	1		T6	1		T15	1