Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3071	1			T2	12		T5	20		T17	114
values[1]	3033	1			T5	24		T15	28		T17	140
values[2]	3088	1			T17	22		T47	24		T50	67
values[3]	2737	1			T5	20		T17	20		T50	20
values[4]	3125	1			T5	20		T47	136		T50	51
values[5]	3171	1			T6	40		T17	20		T47	31
values[6]	2623	1			T6	20		T17	45		T47	131
values[7]	3694	1			T5	20		T6	71		T12	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2688	1			T5	20		T6	20		T17	47
values[1]	3549	1			T12	4		T17	154		T47	73
values[2]	3256	1			T2	12		T5	20		T17	27
values[3]	3536	1			T6	71		T17	20		T47	44
values[4]	2884	1			T5	20		T6	40		T17	20
values[5]	3277	1			T5	20		T15	28		T17	144
values[6]	2654	1			T5	24		T17	43		T47	70
values[7]	2698	1			T17	27		T50	40		T89	24

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23940

1

T2

12

T5

101

T6

128

auto[1]

602

1

T5

3

T6

3

T15

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	462	1			T5	18		T24	20		T66	20
auto[0]	values[0]	values[1]	517	1			T17	112		T52	20		T185	19
auto[0]	values[0]	values[2]	465	1			T2	12		T46	18		T206	10
auto[0]	values[0]	values[3]	501	1			T190	14		T51	93		T176	14
auto[0]	values[0]	values[4]	204	1			T172	23		T155	20		T77	20
auto[0]	values[0]	values[5]	467	1			T178	20		T81	20		T185	20
auto[0]	values[0]	values[6]	153	1			T81	20		T188	30		T235	4
auto[0]	values[0]	values[7]	239	1			T172	20		T185	20		T236	6
auto[0]	values[1]	values[0]	244	1			T178	20		T28	41		T175	22
auto[0]	values[1]	values[1]	388	1			T24	27		T49	67		T155	88
auto[0]	values[1]	values[2]	447	1			T50	20		T24	26		T49	29
auto[0]	values[1]	values[3]	567	1			T50	21		T24	21		T51	75
auto[0]	values[1]	values[4]	311	1			T46	17		T50	23		T185	31
auto[0]	values[1]	values[5]	473	1			T15	26		T17	113		T185	24
auto[0]	values[1]	values[6]	247	1			T5	24		T17	21		T172	20
auto[0]	values[1]	values[7]	282	1			T24	20		T188	18		T32	20
auto[0]	values[2]	values[0]	285	1			T17	21		T43	53		T31	26
auto[0]	values[2]	values[1]	730	1			T178	20		T31	48		T237	4
auto[0]	values[2]	values[2]	322	1			T189	20		T181	20		T238	4
auto[0]	values[2]	values[3]	433	1			T50	20		T57	16		T212	4
auto[0]	values[2]	values[4]	285	1			T50	27		T43	20		T49	42
auto[0]	values[2]	values[5]	390	1			T51	25		T28	25		T124	4
auto[0]	values[2]	values[6]	330	1			T47	23		T49	42		T81	36
auto[0]	values[2]	values[7]	242	1			T50	20		T194	20		T185	20
auto[0]	values[3]	values[0]	169	1			T31	21		T182	20		T189	19
auto[0]	values[3]	values[1]	261	1			T17	20		T239	4		T174	20
auto[0]	values[3]	values[2]	299	1			T31	24		T174	19		T211	41
auto[0]	values[3]	values[3]	500	1			T52	71		T172	20		T194	20
auto[0]	values[3]	values[4]	343	1			T43	20		T222	6		T208	17
auto[0]	values[3]	values[5]	358	1			T5	20		T51	150		T52	20
auto[0]	values[3]	values[6]	402	1			T43	83		T51	20		T155	65
auto[0]	values[3]	values[7]	347	1			T50	18		T89	24		T51	19
auto[0]	values[4]	values[0]	360	1			T47	24		T49	45		T172	22
auto[0]	values[4]	values[1]	252	1			T172	23		T171	20		T234	40
auto[0]	values[4]	values[2]	463	1			T5	19		T50	19		T199	12
auto[0]	values[4]	values[3]	499	1			T47	24		T172	19		T188	19
auto[0]	values[4]	values[4]	326	1			T26	22		T240	6		T28	20
auto[0]	values[4]	values[5]	396	1			T47	41		T51	19		T178	23
auto[0]	values[4]	values[6]	428	1			T47	43		T50	31		T195	45
auto[0]	values[4]	values[7]	328	1			T194	32		T185	23		T188	54
auto[0]	values[5]	values[0]	307	1			T241	6		T223	29		T242	2
auto[0]	values[5]	values[1]	486	1			T49	43		T181	34		T213	20
auto[0]	values[5]	values[2]	386	1			T52	53		T26	22		T185	21
auto[0]	values[5]	values[3]	344	1			T6	20		T17	20		T155	20
auto[0]	values[5]	values[4]	567	1			T6	20		T52	33		T155	30
auto[0]	values[5]	values[5]	311	1			T47	30		T58	10		T28	24
auto[0]	values[5]	values[6]	363	1			T43	20		T90	8		T205	22
auto[0]	values[5]	values[7]	322	1			T51	70		T243	10		T31	19
auto[0]	values[6]	values[0]	256	1			T6	20		T17	25		T47	28
auto[0]	values[6]	values[1]	373	1			T47	51		T100	4		T182	22
auto[0]	values[6]	values[2]	228	1			T50	23		T172	16		T28	27
auto[0]	values[6]	values[3]	186	1			T47	20		T155	27		T194	35
auto[0]	values[6]	values[4]	247	1			T47	28		T48	23		T66	36
auto[0]	values[6]	values[5]	518	1			T51	25		T28	23		T244	4
auto[0]	values[6]	values[6]	337	1			T17	20		T24	22		T52	40
auto[0]	values[6]	values[7]	405	1			T155	20		T81	19		T79	2
auto[0]	values[7]	values[0]	545	1			T47	44		T178	20		T49	108
auto[0]	values[7]	values[1]	455	1			T12	4		T17	18		T47	20
auto[0]	values[7]	values[2]	554	1			T17	26		T18	2		T221	14
auto[0]	values[7]	values[3]	430	1			T6	48		T172	36		T81	19
auto[0]	values[7]	values[4]	544	1			T5	20		T6	20		T17	20
auto[0]	values[7]	values[5]	270	1			T17	26		T47	20		T180	18
auto[0]	values[7]	values[6]	340	1			T50	20		T81	17		T213	20
auto[0]	values[7]	values[7]	451	1			T17	27		T33	16		T26	27
auto[1]	values[0]	values[0]	9	1			T5	2		T188	4		T245	3
auto[1]	values[0]	values[1]	13	1			T17	2		T185	1		T182	3
auto[1]	values[0]	values[2]	11	1			T46	2		T193	1		T246	3
auto[1]	values[0]	values[3]	6	1			T52	1		T208	1		T175	1
auto[1]	values[0]	values[4]	2	1			T172	1		T211	1		-	-
auto[1]	values[0]	values[5]	12	1			T185	1		T196	2		T247	4
auto[1]	values[0]	values[6]	1	1			T248	1		-	-		-	-
auto[1]	values[0]	values[7]	9	1			T172	1		T236	2		T211	1
auto[1]	values[1]	values[0]	4	1			T28	1		T175	1		T193	1
auto[1]	values[1]	values[1]	5	1			T24	1		T155	1		T188	2
auto[1]	values[1]	values[2]	11	1			T49	2		T28	1		T152	1
auto[1]	values[1]	values[3]	10	1			T50	1		T24	2		T51	1
auto[1]	values[1]	values[4]	9	1			T46	3		T50	1		T181	2
auto[1]	values[1]	values[5]	23	1			T15	2		T17	4		T185	1
auto[1]	values[1]	values[6]	6	1			T17	2		T81	2		T249	2
auto[1]	values[1]	values[7]	6	1			T188	2		T32	3		T211	1
auto[1]	values[2]	values[0]	8	1			T17	1		T43	1		T250	4
auto[1]	values[2]	values[1]	14	1			T251	3		T252	8		T253	3
auto[1]	values[2]	values[2]	6	1			T196	1		T254	1		T255	1
auto[1]	values[2]	values[3]	8	1			T223	2		T247	1		T256	4
auto[1]	values[2]	values[4]	11	1			T172	2		T229	4		T249	1
auto[1]	values[2]	values[5]	6	1			T182	1		T209	2		T257	2
auto[1]	values[2]	values[6]	10	1			T47	1		T49	3		T194	2
auto[1]	values[2]	values[7]	8	1			T231	1		T258	1		T230	4
auto[1]	values[3]	values[0]	9	1			T189	1		T259	8		-	-
auto[1]	values[3]	values[1]	3	1			T230	1		T255	2		-	-
auto[1]	values[3]	values[2]	5	1			T174	1		T258	2		T230	1
auto[1]	values[3]	values[3]	6	1			T211	1		T209	1		T260	4
auto[1]	values[3]	values[4]	9	1			T208	3		T194	1		T186	1
auto[1]	values[3]	values[5]	5	1			T51	3		T49	1		T261	1
auto[1]	values[3]	values[6]	9	1			T43	3		T155	3		T195	2
auto[1]	values[3]	values[7]	12	1			T50	2		T51	1		T182	1
auto[1]	values[4]	values[0]	8	1			T47	1		T182	1		T211	2
auto[1]	values[4]	values[1]	9	1			T172	2		T234	4		T213	1
auto[1]	values[4]	values[2]	10	1			T5	1		T50	1		T171	2
auto[1]	values[4]	values[3]	14	1			T172	1		T188	1		T187	3
auto[1]	values[4]	values[4]	5	1			T26	1		T152	2		T253	2
auto[1]	values[4]	values[5]	7	1			T51	1		T81	2		T188	1
auto[1]	values[4]	values[6]	9	1			T47	3		T195	1		T171	1
auto[1]	values[4]	values[7]	11	1			T194	3		T188	1		T182	1
auto[1]	values[5]	values[0]	7	1			T223	4		T230	2		T255	1
auto[1]	values[5]	values[1]	14	1			T181	4		T246	4		T248	2
auto[1]	values[5]	values[2]	13	1			T52	1		T185	1		T31	4
auto[1]	values[5]	values[3]	12	1			T155	1		T81	1		T225	3
auto[1]	values[5]	values[4]	10	1			T52	1		T155	2		T168	3
auto[1]	values[5]	values[5]	13	1			T47	1		T28	1		T175	1
auto[1]	values[5]	values[6]	1	1			T196	1		-	-		-	-
auto[1]	values[5]	values[7]	15	1			T51	3		T31	1		T218	1
auto[1]	values[6]	values[0]	4	1			T181	2		T55	2		-	-
auto[1]	values[6]	values[1]	8	1			T47	2		T197	1		T262	1
auto[1]	values[6]	values[2]	11	1			T50	3		T172	4		T28	1
auto[1]	values[6]	values[3]	5	1			T155	1		T263	2		T264	2
auto[1]	values[6]	values[4]	3	1			T47	2		T197	1		-	-
auto[1]	values[6]	values[5]	21	1			T51	2		T28	2		T196	3
auto[1]	values[6]	values[6]	9	1			T24	4		T52	1		T188	3
auto[1]	values[6]	values[7]	12	1			T81	2		T188	3		T197	3
auto[1]	values[7]	values[0]	11	1			T47	4		T182	1		T265	1
auto[1]	values[7]	values[1]	21	1			T17	2		T218	3		T152	5
auto[1]	values[7]	values[2]	25	1			T17	1		T52	3		T188	1
auto[1]	values[7]	values[3]	15	1			T6	3		T172	3		T81	1
auto[1]	values[7]	values[4]	8	1			T81	2		T246	1		T230	1
auto[1]	values[7]	values[5]	7	1			T17	1		T31	1		T230	1
auto[1]	values[7]	values[6]	9	1			T81	3		T200	1		T266	1
auto[1]	values[7]	values[7]	9	1			T188	3		T213	2		T247	1