Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1727

1

T4

3

T5

6

T7

6

auto[1]

1759

1

T4

10

T5

9

T7

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1884

1

T4

13

T5

15

T7

12

auto[1]

1602

1

T9

18

T22

28

T23

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2776

1

T4

8

T5

8

T7

7

auto[1]

710

1

T4

5

T5

7

T7

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	676	1			T4	4		T5	2		T7	2
valid[1]	664	1			T4	4		T5	4		T7	4
valid[2]	720	1			T4	1		T5	5		T7	2
valid[3]	705	1			T4	3		T5	2		T7	1
valid[4]	721	1			T4	1		T5	2		T7	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	120	1			T8	1		T11	1		T59	1
auto[0]	auto[0]	valid[0]	auto[1]	153	1			T9	4		T22	5		T87	1
auto[0]	auto[0]	valid[1]	auto[0]	108	1			T4	1		T5	2		T7	3
auto[0]	auto[0]	valid[1]	auto[1]	142	1			T9	1		T22	2		T87	2
auto[0]	auto[0]	valid[2]	auto[0]	94	1			T5	1		T8	1		T11	1
auto[0]	auto[0]	valid[2]	auto[1]	180	1			T22	2		T17	1		T86	1
auto[0]	auto[0]	valid[3]	auto[0]	112	1			T24	1		T178	1		T25	1
auto[0]	auto[0]	valid[3]	auto[1]	185	1			T9	1		T22	3		T23	1
auto[0]	auto[0]	valid[4]	auto[0]	136	1			T4	1		T5	1		T17	1
auto[0]	auto[0]	valid[4]	auto[1]	153	1			T9	2		T22	4		T17	1
auto[0]	auto[1]	valid[0]	auto[0]	113	1			T4	3		T5	1		T7	2
auto[0]	auto[1]	valid[0]	auto[1]	168	1			T9	2		T22	3		T50	1
auto[0]	auto[1]	valid[1]	auto[0]	118	1			T4	1		T5	1		T17	1
auto[0]	auto[1]	valid[1]	auto[1]	164	1			T9	2		T22	4		T17	1
auto[0]	auto[1]	valid[2]	auto[0]	121	1			T4	1		T5	1		T8	1
auto[0]	auto[1]	valid[2]	auto[1]	167	1			T9	3		T22	2		T23	1
auto[0]	auto[1]	valid[3]	auto[0]	121	1			T4	1		T5	1		T7	1
auto[0]	auto[1]	valid[3]	auto[1]	146	1			T9	1		T22	1		T17	1
auto[0]	auto[1]	valid[4]	auto[0]	131	1			T7	1		T8	1		T59	1
auto[0]	auto[1]	valid[4]	auto[1]	144	1			T9	2		T22	2		T50	1
auto[1]	auto[0]	valid[0]	auto[0]	53	1			T4	1		T17	1		T42	1
auto[1]	auto[0]	valid[1]	auto[0]	62	1			T7	1		T17	1		T54	1
auto[1]	auto[0]	valid[2]	auto[0]	87	1			T5	2		T7	1		T50	1
auto[1]	auto[0]	valid[3]	auto[0]	72	1			T20	1		T51	1		T275	1
auto[1]	auto[0]	valid[4]	auto[0]	70	1			T7	1		T53	1		T50	1
auto[1]	auto[1]	valid[0]	auto[0]	69	1			T5	1		T8	1		T17	1
auto[1]	auto[1]	valid[1]	auto[0]	70	1			T4	2		T5	1		T50	1
auto[1]	auto[1]	valid[2]	auto[0]	71	1			T5	1		T7	1		T54	1
auto[1]	auto[1]	valid[3]	auto[0]	69	1			T4	2		T5	1		T17	2
auto[1]	auto[1]	valid[4]	auto[0]	87	1			T5	1		T7	1		T17	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal