Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	793	1			T21	18		T66	7		T26	4
all_values[1]	793	1			T21	18		T66	7		T26	4
all_values[2]	793	1			T21	18		T66	7		T26	4
all_values[3]	793	1			T21	18		T66	7		T26	4
all_values[4]	793	1			T21	18		T66	7		T26	4
all_values[5]	793	1			T21	18		T66	7		T26	4
all_values[6]	793	1			T21	18		T66	7		T26	4
all_values[7]	793	1			T21	18		T66	7		T26	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3419

1

T21

73

T66

27

T26

17

auto[1]

2925

1

T21

71

T66

29

T26

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2602

1

T21

64

T66

25

T26

12

auto[1]

3742

1

T21

80

T66

31

T26

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3636

1

T21

84

T66

34

T26

18

auto[1]

2708

1

T21

60

T66

22

T26

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	179	1			T21	4		T66	2		T30	5
all_values[0]	auto[0]	auto[0]	auto[1]	65	1			T31	1		T153	2		T154	2
all_values[0]	auto[0]	auto[1]	auto[0]	142	1			T21	7		T26	1		T30	2
all_values[0]	auto[0]	auto[1]	auto[1]	63	1			T21	1		T26	1		T153	2
all_values[0]	auto[1]	auto[0]	auto[1]	177	1			T21	4		T66	1		T26	1
all_values[0]	auto[1]	auto[1]	auto[1]	167	1			T21	2		T66	4		T26	1
all_values[1]	auto[0]	auto[0]	auto[0]	186	1			T21	4		T66	2		T26	2
all_values[1]	auto[0]	auto[0]	auto[1]	73	1			T21	3		T66	1		T30	1
all_values[1]	auto[0]	auto[1]	auto[0]	134	1			T21	3		T66	1		T30	3
all_values[1]	auto[0]	auto[1]	auto[1]	65	1			T21	1		T66	1		T26	1
all_values[1]	auto[1]	auto[0]	auto[1]	186	1			T21	5		T26	1		T30	3
all_values[1]	auto[1]	auto[1]	auto[1]	149	1			T21	2		T66	2		T30	2
all_values[2]	auto[0]	auto[0]	auto[0]	178	1			T21	3		T66	1		T26	1
all_values[2]	auto[0]	auto[0]	auto[1]	80	1			T21	3		T66	1		T153	4
all_values[2]	auto[0]	auto[1]	auto[0]	119	1			T21	6		T66	2		T31	2
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T26	1		T30	2		T153	4
all_values[2]	auto[1]	auto[0]	auto[1]	180	1			T21	5		T66	2		T26	2
all_values[2]	auto[1]	auto[1]	auto[1]	168	1			T21	1		T66	1		T30	3
all_values[3]	auto[0]	auto[0]	auto[0]	183	1			T21	3		T66	2		T26	1
all_values[3]	auto[0]	auto[0]	auto[1]	68	1			T66	1		T26	1		T30	1
all_values[3]	auto[0]	auto[1]	auto[0]	128	1			T21	5		T66	1		T30	2
all_values[3]	auto[0]	auto[1]	auto[1]	84	1			T21	1		T66	1		T31	2
all_values[3]	auto[1]	auto[0]	auto[1]	184	1			T21	6		T66	1		T30	3
all_values[3]	auto[1]	auto[1]	auto[1]	146	1			T21	3		T66	1		T26	2
all_values[4]	auto[0]	auto[0]	auto[0]	166	1			T21	2		T66	4		T30	1
all_values[4]	auto[0]	auto[0]	auto[1]	70	1			T66	1		T30	1		T31	1
all_values[4]	auto[0]	auto[1]	auto[0]	132	1			T21	4		T66	1		T26	3
all_values[4]	auto[0]	auto[1]	auto[1]	70	1			T21	3		T30	2		T31	1
all_values[4]	auto[1]	auto[0]	auto[1]	190	1			T21	6		T26	1		T30	6
all_values[4]	auto[1]	auto[1]	auto[1]	165	1			T21	3		T66	1		T31	2
all_values[5]	auto[0]	auto[0]	auto[0]	209	1			T21	4		T26	1		T30	5
all_values[5]	auto[0]	auto[1]	auto[0]	232	1			T21	7		T66	2		T26	1
all_values[5]	auto[1]	auto[0]	auto[1]	178	1			T21	3		T66	1		T26	1
all_values[5]	auto[1]	auto[1]	auto[1]	174	1			T21	4		T66	4		T26	1
all_values[6]	auto[0]	auto[0]	auto[0]	176	1			T21	4		T66	1		T26	2
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T21	1		T30	1		T153	3
all_values[6]	auto[0]	auto[1]	auto[0]	129	1			T21	2		T66	1		T30	1
all_values[6]	auto[0]	auto[1]	auto[1]	89	1			T21	4		T66	2		T26	1
all_values[6]	auto[1]	auto[0]	auto[1]	179	1			T21	4		T66	2		T30	2
all_values[6]	auto[1]	auto[1]	auto[1]	139	1			T21	3		T66	1		T26	1
all_values[7]	auto[0]	auto[0]	auto[0]	172	1			T21	2		T66	2		T30	4
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T21	2		T66	1		T30	1
all_values[7]	auto[0]	auto[1]	auto[0]	137	1			T21	4		T66	3		T30	1
all_values[7]	auto[0]	auto[1]	auto[1]	81	1			T21	1		T26	1		T31	2
all_values[7]	auto[1]	auto[0]	auto[1]	182	1			T21	5		T66	1		T26	3
all_values[7]	auto[1]	auto[1]	auto[1]	144	1			T21	4		T30	1		T31	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal