Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47421

1

T3

7

T4

267

T5

254

auto[1]

16841

1

T9

366

T22

364

T23

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46918

1

T3

4

T4

178

T5

171

auto[1]

17344

1

T3

3

T4

89

T5

83

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33008	1			T3	6		T4	133		T5	145
others[1]	5464	1			T4	19		T5	17		T7	17
others[2]	5321	1			T4	26		T5	22		T7	17
others[3]	6223	1			T4	29		T5	21		T7	16
interest[1]	3578	1			T4	14		T5	11		T7	9
interest[4]	21635	1			T3	3		T4	82		T5	100
interest[64]	10668	1			T3	1		T4	46		T5	38

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15352	1			T3	4		T4	88		T5	101
auto[0]	auto[0]	others[1]	2620	1			T4	14		T5	11		T7	11
auto[0]	auto[0]	others[2]	2482	1			T4	20		T5	12		T7	5
auto[0]	auto[0]	others[3]	2910	1			T4	19		T5	14		T7	10
auto[0]	auto[0]	interest[1]	1701	1			T4	9		T5	9		T7	7
auto[0]	auto[0]	interest[4]	10036	1			T3	3		T4	55		T5	71
auto[0]	auto[0]	interest[64]	5012	1			T4	28		T5	24		T7	26
auto[0]	auto[1]	others[0]	8727	1			T9	178		T22	178		T23	2
auto[0]	auto[1]	others[1]	1428	1			T9	28		T22	37		T17	5
auto[0]	auto[1]	others[2]	1377	1			T9	32		T22	27		T17	5
auto[0]	auto[1]	others[3]	1569	1			T9	35		T22	32		T50	4
auto[0]	auto[1]	interest[1]	960	1			T9	24		T22	22		T17	1
auto[0]	auto[1]	interest[4]	5797	1			T9	123		T22	124		T23	2
auto[0]	auto[1]	interest[64]	2780	1			T9	69		T22	68		T17	11
auto[1]	auto[0]	others[0]	8929	1			T3	2		T4	45		T5	44
auto[1]	auto[0]	others[1]	1416	1			T4	5		T5	6		T7	6
auto[1]	auto[0]	others[2]	1462	1			T4	6		T5	10		T7	12
auto[1]	auto[0]	others[3]	1744	1			T4	10		T5	7		T7	6
auto[1]	auto[0]	interest[1]	917	1			T4	5		T5	2		T7	2
auto[1]	auto[0]	interest[4]	5802	1			T4	27		T5	29		T7	26
auto[1]	auto[0]	interest[64]	2876	1			T3	1		T4	18		T5	14

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal