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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.25


Total test records in report: 1081
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T144 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4253602451 Jun 26 04:43:54 PM PDT 24 Jun 26 04:44:05 PM PDT 24 44777844 ps
T1010 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2947718712 Jun 26 04:40:04 PM PDT 24 Jun 26 04:40:15 PM PDT 24 1530461465 ps
T1011 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3590792351 Jun 26 04:40:30 PM PDT 24 Jun 26 04:40:36 PM PDT 24 51165742 ps
T1012 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3232053712 Jun 26 04:40:28 PM PDT 24 Jun 26 04:40:35 PM PDT 24 248010232 ps
T1013 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2874284088 Jun 26 04:40:15 PM PDT 24 Jun 26 04:40:19 PM PDT 24 44629476 ps
T1014 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4009567737 Jun 26 04:40:27 PM PDT 24 Jun 26 04:40:31 PM PDT 24 14143536 ps
T118 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.660105195 Jun 26 04:40:04 PM PDT 24 Jun 26 04:40:29 PM PDT 24 1145099737 ps
T1015 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.419982323 Jun 26 04:40:21 PM PDT 24 Jun 26 04:40:32 PM PDT 24 377312758 ps
T1016 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1457679969 Jun 26 04:40:09 PM PDT 24 Jun 26 04:40:12 PM PDT 24 87023104 ps
T1017 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4045544985 Jun 26 04:40:09 PM PDT 24 Jun 26 04:40:15 PM PDT 24 253322393 ps
T1018 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3967923286 Jun 26 04:40:05 PM PDT 24 Jun 26 04:40:10 PM PDT 24 26598097 ps
T1019 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3869921761 Jun 26 04:40:21 PM PDT 24 Jun 26 04:40:28 PM PDT 24 447654399 ps
T1020 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1773818877 Jun 26 04:40:21 PM PDT 24 Jun 26 04:40:25 PM PDT 24 22967151 ps
T1021 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2527067448 Jun 26 04:40:27 PM PDT 24 Jun 26 04:40:34 PM PDT 24 492191897 ps
T1022 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3863678976 Jun 26 04:40:22 PM PDT 24 Jun 26 04:40:27 PM PDT 24 56822092 ps
T1023 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1252878466 Jun 26 04:40:06 PM PDT 24 Jun 26 04:40:09 PM PDT 24 32142776 ps
T1024 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3742331315 Jun 26 04:40:34 PM PDT 24 Jun 26 04:40:40 PM PDT 24 20289877 ps
T1025 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3722082141 Jun 26 04:40:33 PM PDT 24 Jun 26 04:40:56 PM PDT 24 3256261681 ps
T1026 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2667473454 Jun 26 04:40:23 PM PDT 24 Jun 26 04:40:31 PM PDT 24 602179019 ps
T1027 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1973515955 Jun 26 04:40:28 PM PDT 24 Jun 26 04:40:35 PM PDT 24 602294148 ps
T1028 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1671559156 Jun 26 04:40:23 PM PDT 24 Jun 26 04:40:28 PM PDT 24 45302420 ps
T1029 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.10961370 Jun 26 04:40:38 PM PDT 24 Jun 26 04:40:45 PM PDT 24 49565637 ps
T1030 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.912782820 Jun 26 04:40:24 PM PDT 24 Jun 26 04:40:31 PM PDT 24 97555422 ps
T1031 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1165797734 Jun 26 04:40:16 PM PDT 24 Jun 26 04:40:19 PM PDT 24 25483163 ps
T1032 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1203199367 Jun 26 04:40:21 PM PDT 24 Jun 26 04:40:24 PM PDT 24 25267068 ps
T1033 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.517496290 Jun 26 04:40:34 PM PDT 24 Jun 26 04:40:40 PM PDT 24 20908466 ps
T1034 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.801779870 Jun 26 04:40:29 PM PDT 24 Jun 26 04:40:35 PM PDT 24 630295271 ps
T1035 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1636833104 Jun 26 04:40:03 PM PDT 24 Jun 26 04:40:14 PM PDT 24 621295587 ps
T1036 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.777411012 Jun 26 04:40:32 PM PDT 24 Jun 26 04:40:36 PM PDT 24 34741579 ps
T1037 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.992161313 Jun 26 04:40:36 PM PDT 24 Jun 26 04:40:42 PM PDT 24 41834313 ps
T1038 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1436464196 Jun 26 04:40:20 PM PDT 24 Jun 26 04:40:23 PM PDT 24 19876358 ps
T1039 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1516661187 Jun 26 04:40:26 PM PDT 24 Jun 26 04:40:35 PM PDT 24 451715281 ps
T1040 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3959826719 Jun 26 04:40:12 PM PDT 24 Jun 26 04:40:30 PM PDT 24 14483529365 ps
T119 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3169827544 Jun 26 04:40:04 PM PDT 24 Jun 26 04:40:40 PM PDT 24 1490643109 ps
T1041 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1235732549 Jun 26 04:40:21 PM PDT 24 Jun 26 04:40:29 PM PDT 24 70311652 ps
T162 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1760406431 Jun 26 04:40:18 PM PDT 24 Jun 26 04:40:40 PM PDT 24 1223546445 ps
T1042 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3085804526 Jun 26 04:40:10 PM PDT 24 Jun 26 04:40:25 PM PDT 24 616985968 ps
T1043 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1906291711 Jun 26 04:40:29 PM PDT 24 Jun 26 04:40:36 PM PDT 24 124562330 ps
T1044 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3247742952 Jun 26 04:40:14 PM PDT 24 Jun 26 04:40:17 PM PDT 24 221141184 ps
T1045 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1616445689 Jun 26 04:40:18 PM PDT 24 Jun 26 04:40:25 PM PDT 24 326114356 ps
T1046 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2311477260 Jun 26 04:40:21 PM PDT 24 Jun 26 04:40:32 PM PDT 24 1300698128 ps
T1047 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1142630420 Jun 26 04:40:05 PM PDT 24 Jun 26 04:40:09 PM PDT 24 65550882 ps
T1048 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.469518849 Jun 26 04:40:36 PM PDT 24 Jun 26 04:40:43 PM PDT 24 41976668 ps
T1049 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1278399781 Jun 26 04:40:24 PM PDT 24 Jun 26 04:40:33 PM PDT 24 2237052758 ps
T120 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2575538857 Jun 26 04:40:33 PM PDT 24 Jun 26 04:40:40 PM PDT 24 852756266 ps
T85 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1731731758 Jun 26 04:40:10 PM PDT 24 Jun 26 04:40:14 PM PDT 24 35877624 ps
T1050 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1711075119 Jun 26 04:39:58 PM PDT 24 Jun 26 04:40:03 PM PDT 24 52083891 ps
T1051 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.279243719 Jun 26 04:40:34 PM PDT 24 Jun 26 04:40:39 PM PDT 24 12446196 ps
T1052 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3721272453 Jun 26 04:40:23 PM PDT 24 Jun 26 04:40:30 PM PDT 24 336692435 ps
T1053 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3533252573 Jun 26 04:40:16 PM PDT 24 Jun 26 04:40:20 PM PDT 24 264914080 ps
T1054 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3326184827 Jun 26 04:40:15 PM PDT 24 Jun 26 04:40:18 PM PDT 24 12151269 ps
T1055 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3536220755 Jun 26 04:40:13 PM PDT 24 Jun 26 04:40:17 PM PDT 24 431920959 ps
T1056 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1007603263 Jun 26 04:40:24 PM PDT 24 Jun 26 04:40:29 PM PDT 24 53143597 ps
T1057 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1331070575 Jun 26 04:40:28 PM PDT 24 Jun 26 04:40:32 PM PDT 24 40434090 ps
T1058 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3216224219 Jun 26 04:40:11 PM PDT 24 Jun 26 04:40:15 PM PDT 24 50974574 ps
T1059 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2945194087 Jun 26 04:40:40 PM PDT 24 Jun 26 04:40:48 PM PDT 24 28438837 ps
T1060 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2401287402 Jun 26 04:40:26 PM PDT 24 Jun 26 04:40:34 PM PDT 24 159340942 ps
T1061 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.622401026 Jun 26 04:40:09 PM PDT 24 Jun 26 04:40:13 PM PDT 24 766184279 ps
T1062 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3368251637 Jun 26 04:40:33 PM PDT 24 Jun 26 04:40:38 PM PDT 24 13463391 ps
T1063 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2195089573 Jun 26 04:40:33 PM PDT 24 Jun 26 04:40:38 PM PDT 24 32311424 ps
T1064 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2012368259 Jun 26 04:40:10 PM PDT 24 Jun 26 04:40:14 PM PDT 24 69252285 ps
T164 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1402112532 Jun 26 04:40:15 PM PDT 24 Jun 26 04:40:23 PM PDT 24 211184539 ps
T1065 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3617648882 Jun 26 04:40:16 PM PDT 24 Jun 26 04:40:20 PM PDT 24 468149784 ps
T1066 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3945099325 Jun 26 04:40:34 PM PDT 24 Jun 26 04:40:40 PM PDT 24 37052570 ps
T1067 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1114768721 Jun 26 04:40:27 PM PDT 24 Jun 26 04:40:31 PM PDT 24 68667280 ps
T1068 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.358597908 Jun 26 04:40:23 PM PDT 24 Jun 26 04:40:31 PM PDT 24 123657927 ps
T1069 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1939614033 Jun 26 04:40:35 PM PDT 24 Jun 26 04:40:41 PM PDT 24 18904650 ps
T1070 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2612425361 Jun 26 04:40:05 PM PDT 24 Jun 26 04:40:10 PM PDT 24 109703602 ps
T1071 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1582674590 Jun 26 04:40:09 PM PDT 24 Jun 26 04:40:13 PM PDT 24 23145464 ps
T1072 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1398170480 Jun 26 04:40:26 PM PDT 24 Jun 26 04:40:32 PM PDT 24 95387646 ps
T1073 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3800970484 Jun 26 04:40:23 PM PDT 24 Jun 26 04:40:28 PM PDT 24 17619497 ps
T1074 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1951578315 Jun 26 04:40:22 PM PDT 24 Jun 26 04:40:39 PM PDT 24 430247575 ps
T1075 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4278978753 Jun 26 04:40:23 PM PDT 24 Jun 26 04:40:34 PM PDT 24 266325416 ps
T1076 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3306295482 Jun 26 04:40:35 PM PDT 24 Jun 26 04:40:41 PM PDT 24 15373663 ps
T163 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2747593708 Jun 26 04:40:22 PM PDT 24 Jun 26 04:40:34 PM PDT 24 308874661 ps
T1077 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2585485529 Jun 26 04:39:59 PM PDT 24 Jun 26 04:40:04 PM PDT 24 34856245 ps
T1078 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3006935100 Jun 26 04:40:15 PM PDT 24 Jun 26 04:40:21 PM PDT 24 1137886504 ps
T1079 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3785351700 Jun 26 04:40:03 PM PDT 24 Jun 26 04:40:08 PM PDT 24 180887722 ps
T1080 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1111522961 Jun 26 04:40:34 PM PDT 24 Jun 26 04:40:40 PM PDT 24 25756238 ps
T1081 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.265475747 Jun 26 04:40:01 PM PDT 24 Jun 26 04:40:06 PM PDT 24 41295257 ps
T106 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3862533283 Jun 26 04:40:15 PM PDT 24 Jun 26 04:40:35 PM PDT 24 292291149 ps

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2022944482
Short name T5
Test name
Test status
Simulation time 115796064931 ps
CPU time 276.52 seconds
Started Jun 26 06:24:23 PM PDT 24
Finished Jun 26 06:29:01 PM PDT 24
Peak memory 250140 kb
Host smart-f1b2c19f-1a77-415f-b170-1f216ef924fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022944482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2022944482
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1129286126
Short name T47
Test name
Test status
Simulation time 85303478518 ps
CPU time 504.34 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:33:05 PM PDT 24
Peak memory 272188 kb
Host smart-b4353345-3a71-4348-ab82-be3a86d8fca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129286126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1129286126
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3044273157
Short name T24
Test name
Test status
Simulation time 93909425951 ps
CPU time 244.23 seconds
Started Jun 26 06:23:58 PM PDT 24
Finished Jun 26 06:28:03 PM PDT 24
Peak memory 273800 kb
Host smart-dc52dc36-be88-4628-86c5-d85078ba5f28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044273157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3044273157
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2476761446
Short name T31
Test name
Test status
Simulation time 70834074079 ps
CPU time 418.97 seconds
Started Jun 26 06:23:34 PM PDT 24
Finished Jun 26 06:30:35 PM PDT 24
Peak memory 272660 kb
Host smart-4f85e7cc-39e4-4459-b0a5-f78256278be6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476761446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2476761446
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2851228178
Short name T93
Test name
Test status
Simulation time 3598863134 ps
CPU time 20.67 seconds
Started Jun 26 04:40:08 PM PDT 24
Finished Jun 26 04:40:31 PM PDT 24
Peak memory 223056 kb
Host smart-1ccd90ff-3557-4b46-9efc-b9c4f5d72a7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851228178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2851228178
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4071370381
Short name T50
Test name
Test status
Simulation time 11232282385 ps
CPU time 181.86 seconds
Started Jun 26 06:25:40 PM PDT 24
Finished Jun 26 06:28:43 PM PDT 24
Peak memory 262092 kb
Host smart-40bde904-1527-4740-bff6-aa9c8feb9bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071370381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4071370381
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2696899480
Short name T28
Test name
Test status
Simulation time 268873614306 ps
CPU time 725.82 seconds
Started Jun 26 06:24:59 PM PDT 24
Finished Jun 26 06:37:06 PM PDT 24
Peak memory 290424 kb
Host smart-82d57ce0-9829-4953-a15b-21575a226d80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696899480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2696899480
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.473070208
Short name T67
Test name
Test status
Simulation time 31057220 ps
CPU time 0.75 seconds
Started Jun 26 06:23:19 PM PDT 24
Finished Jun 26 06:23:21 PM PDT 24
Peak memory 216808 kb
Host smart-3c888d0c-fbe0-43d4-bd45-63344dfcd3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473070208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.473070208
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2718828178
Short name T175
Test name
Test status
Simulation time 56026149588 ps
CPU time 483.5 seconds
Started Jun 26 06:24:54 PM PDT 24
Finished Jun 26 06:32:59 PM PDT 24
Peak memory 285944 kb
Host smart-7567477f-1e4c-42d4-8a96-9c00734632f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718828178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2718828178
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.858566979
Short name T98
Test name
Test status
Simulation time 364825819 ps
CPU time 1.78 seconds
Started Jun 26 04:40:15 PM PDT 24
Finished Jun 26 04:40:19 PM PDT 24
Peak memory 215020 kb
Host smart-3d826f90-5317-403c-9571-f40b4dd8ae5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858566979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.858566979
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3171277864
Short name T17
Test name
Test status
Simulation time 16868620647 ps
CPU time 170.44 seconds
Started Jun 26 06:23:33 PM PDT 24
Finished Jun 26 06:26:25 PM PDT 24
Peak memory 268420 kb
Host smart-ae5d75f9-67b1-4770-b7a9-7a9c4e9f6834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171277864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3171277864
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2942489239
Short name T37
Test name
Test status
Simulation time 16659016800 ps
CPU time 73.18 seconds
Started Jun 26 06:24:55 PM PDT 24
Finished Jun 26 06:26:09 PM PDT 24
Peak memory 234748 kb
Host smart-784c4c03-88da-448e-bb0b-2b17a006effb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942489239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2942489239
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.31888659
Short name T29
Test name
Test status
Simulation time 138216231 ps
CPU time 1.11 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:31 PM PDT 24
Peak memory 236384 kb
Host smart-12183de3-6f64-4097-a131-83b1bdb08afd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31888659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.31888659
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.588120918
Short name T182
Test name
Test status
Simulation time 533289214345 ps
CPU time 411.73 seconds
Started Jun 26 06:23:48 PM PDT 24
Finished Jun 26 06:30:43 PM PDT 24
Peak memory 257784 kb
Host smart-09ad7925-98bb-4b07-9deb-b4eeccc83b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588120918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.588120918
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1551627103
Short name T172
Test name
Test status
Simulation time 19772135877 ps
CPU time 269.92 seconds
Started Jun 26 06:25:52 PM PDT 24
Finished Jun 26 06:30:23 PM PDT 24
Peak memory 274772 kb
Host smart-a30662e8-0a1c-4e2f-bb2c-451950b16ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551627103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1551627103
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1562826337
Short name T110
Test name
Test status
Simulation time 35109004 ps
CPU time 2.3 seconds
Started Jun 26 04:40:27 PM PDT 24
Finished Jun 26 04:40:33 PM PDT 24
Peak memory 214836 kb
Host smart-febab53f-f20e-4784-a0ae-10b638e670ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562826337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1562826337
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.388917249
Short name T81
Test name
Test status
Simulation time 46557324246 ps
CPU time 386.73 seconds
Started Jun 26 06:23:18 PM PDT 24
Finished Jun 26 06:29:45 PM PDT 24
Peak memory 268976 kb
Host smart-f54d7a79-75a3-4e84-af05-9592b876ae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388917249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
388917249
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1716361720
Short name T230
Test name
Test status
Simulation time 668520697253 ps
CPU time 423.73 seconds
Started Jun 26 06:23:38 PM PDT 24
Finished Jun 26 06:30:43 PM PDT 24
Peak memory 289020 kb
Host smart-6aede930-a11c-4b45-b777-51a63bd09fbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716361720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1716361720
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.641920620
Short name T247
Test name
Test status
Simulation time 98044717852 ps
CPU time 484.14 seconds
Started Jun 26 06:24:12 PM PDT 24
Finished Jun 26 06:32:18 PM PDT 24
Peak memory 273060 kb
Host smart-bdd94973-11dd-494f-b1fa-ec39c3456ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641920620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.641920620
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.468454530
Short name T169
Test name
Test status
Simulation time 6072358076 ps
CPU time 125.02 seconds
Started Jun 26 06:25:22 PM PDT 24
Finished Jun 26 06:27:29 PM PDT 24
Peak memory 253256 kb
Host smart-ce394fc8-088c-4235-87d0-476956d683a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468454530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.468454530
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4256934091
Short name T181
Test name
Test status
Simulation time 40683081065 ps
CPU time 274.41 seconds
Started Jun 26 06:25:00 PM PDT 24
Finished Jun 26 06:29:36 PM PDT 24
Peak memory 250224 kb
Host smart-3d7dc106-253d-4848-9724-848bd27242d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256934091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4256934091
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2783262593
Short name T103
Test name
Test status
Simulation time 683043286 ps
CPU time 5.06 seconds
Started Jun 26 04:40:28 PM PDT 24
Finished Jun 26 04:40:37 PM PDT 24
Peak memory 214996 kb
Host smart-c3fd6f2b-e30e-48db-ad73-0be168437bc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783262593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2783262593
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1040559957
Short name T26
Test name
Test status
Simulation time 100892684237 ps
CPU time 261.88 seconds
Started Jun 26 06:25:44 PM PDT 24
Finished Jun 26 06:30:08 PM PDT 24
Peak memory 266644 kb
Host smart-a364d062-3268-4d84-92c8-2a1ae48a73d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040559957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1040559957
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1766438518
Short name T61
Test name
Test status
Simulation time 95350790 ps
CPU time 0.73 seconds
Started Jun 26 06:24:14 PM PDT 24
Finished Jun 26 06:24:17 PM PDT 24
Peak memory 206336 kb
Host smart-26479d08-b726-4927-aec8-e0775ac6e6fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766438518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1766438518
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.136538511
Short name T188
Test name
Test status
Simulation time 266981158355 ps
CPU time 482.11 seconds
Started Jun 26 06:25:10 PM PDT 24
Finished Jun 26 06:33:13 PM PDT 24
Peak memory 274364 kb
Host smart-70679a95-5101-477a-801f-bfd1e89f358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136538511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.136538511
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.325789326
Short name T260
Test name
Test status
Simulation time 596773374096 ps
CPU time 676.16 seconds
Started Jun 26 06:25:28 PM PDT 24
Finished Jun 26 06:36:46 PM PDT 24
Peak memory 273152 kb
Host smart-01c1c853-0eb7-4c4c-ac98-5f7af5660e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325789326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.325789326
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2369110037
Short name T42
Test name
Test status
Simulation time 18386616922 ps
CPU time 27.59 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:57 PM PDT 24
Peak memory 217432 kb
Host smart-3dfe4e5f-f09a-45a5-a076-8b839fd7cdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369110037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2369110037
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1924703302
Short name T197
Test name
Test status
Simulation time 10213817656 ps
CPU time 162.42 seconds
Started Jun 26 06:25:31 PM PDT 24
Finished Jun 26 06:28:15 PM PDT 24
Peak memory 269040 kb
Host smart-56c963f8-fcd0-4b2e-9c1d-e781bf332f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924703302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1924703302
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3151287722
Short name T165
Test name
Test status
Simulation time 2092909948 ps
CPU time 22.97 seconds
Started Jun 26 04:40:09 PM PDT 24
Finished Jun 26 04:40:33 PM PDT 24
Peak memory 214648 kb
Host smart-7f10a84d-4f0b-4c83-b97b-d5b5b4df4588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151287722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3151287722
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.883739386
Short name T159
Test name
Test status
Simulation time 774193734 ps
CPU time 13.19 seconds
Started Jun 26 04:40:21 PM PDT 24
Finished Jun 26 04:40:37 PM PDT 24
Peak memory 216592 kb
Host smart-4fd8994d-b2fc-4e51-912f-69cdd57e4296
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883739386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.883739386
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3447168957
Short name T51
Test name
Test status
Simulation time 8391079525 ps
CPU time 111.53 seconds
Started Jun 26 06:24:01 PM PDT 24
Finished Jun 26 06:25:54 PM PDT 24
Peak memory 258324 kb
Host smart-48f9ab19-82e3-4f57-8384-44937a9cd91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447168957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3447168957
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1143967863
Short name T268
Test name
Test status
Simulation time 555898718 ps
CPU time 18.44 seconds
Started Jun 26 06:24:06 PM PDT 24
Finished Jun 26 06:24:26 PM PDT 24
Peak memory 223212 kb
Host smart-fe8bc75b-3425-409a-ac42-c6249a1e1492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143967863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1143967863
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3157008229
Short name T155
Test name
Test status
Simulation time 37504266745 ps
CPU time 268.1 seconds
Started Jun 26 06:24:40 PM PDT 24
Finished Jun 26 06:29:10 PM PDT 24
Peak memory 250584 kb
Host smart-058c783e-3f2f-427c-a70f-09632c9dcafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157008229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3157008229
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.84576600
Short name T189
Test name
Test status
Simulation time 12989938518 ps
CPU time 119.54 seconds
Started Jun 26 06:25:39 PM PDT 24
Finished Jun 26 06:27:40 PM PDT 24
Peak memory 250244 kb
Host smart-775dffc8-22e9-4e9d-aabf-385629914feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84576600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress
_all.84576600
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2697649048
Short name T196
Test name
Test status
Simulation time 140022232753 ps
CPU time 284.73 seconds
Started Jun 26 06:23:35 PM PDT 24
Finished Jun 26 06:28:21 PM PDT 24
Peak memory 253156 kb
Host smart-b4a57f61-174d-4eca-8cf3-cf5ee2a26750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697649048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2697649048
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1106427932
Short name T650
Test name
Test status
Simulation time 373282312 ps
CPU time 6.02 seconds
Started Jun 26 06:25:33 PM PDT 24
Finished Jun 26 06:25:40 PM PDT 24
Peak memory 233576 kb
Host smart-f39154c9-b7e9-4c30-a30e-4473a0969d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106427932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1106427932
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3495219728
Short name T160
Test name
Test status
Simulation time 411653932 ps
CPU time 13.09 seconds
Started Jun 26 04:39:58 PM PDT 24
Finished Jun 26 04:40:15 PM PDT 24
Peak memory 214896 kb
Host smart-5f9255f6-6054-4574-a935-0f224ea5ca06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495219728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3495219728
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1680550434
Short name T22
Test name
Test status
Simulation time 830995973 ps
CPU time 5.94 seconds
Started Jun 26 06:23:20 PM PDT 24
Finished Jun 26 06:23:27 PM PDT 24
Peak memory 217092 kb
Host smart-6d0f6b8a-8633-4f33-96c0-2fed932498ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680550434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1680550434
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3382150474
Short name T743
Test name
Test status
Simulation time 62265232645 ps
CPU time 143.53 seconds
Started Jun 26 06:23:58 PM PDT 24
Finished Jun 26 06:26:23 PM PDT 24
Peak memory 239716 kb
Host smart-a4086ad7-5be2-4b51-90fa-7f0e46b4da3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382150474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3382150474
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3526069002
Short name T253
Test name
Test status
Simulation time 11510385268 ps
CPU time 32.44 seconds
Started Jun 26 06:24:04 PM PDT 24
Finished Jun 26 06:24:38 PM PDT 24
Peak memory 239988 kb
Host smart-8ad91ac8-7e40-4f37-8ada-414274db17ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526069002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3526069002
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1611134954
Short name T839
Test name
Test status
Simulation time 22649879983 ps
CPU time 69.79 seconds
Started Jun 26 06:24:50 PM PDT 24
Finished Jun 26 06:26:01 PM PDT 24
Peak memory 254552 kb
Host smart-ec29daaf-df33-4ab8-b33b-ad04b6b6def1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611134954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1611134954
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3643845865
Short name T248
Test name
Test status
Simulation time 59536618134 ps
CPU time 211.19 seconds
Started Jun 26 06:24:54 PM PDT 24
Finished Jun 26 06:28:26 PM PDT 24
Peak memory 266596 kb
Host smart-c744e035-28b9-4b47-83e9-7354b0275416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643845865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3643845865
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2755680005
Short name T939
Test name
Test status
Simulation time 365201409 ps
CPU time 7 seconds
Started Jun 26 06:24:22 PM PDT 24
Finished Jun 26 06:24:31 PM PDT 24
Peak memory 225416 kb
Host smart-af2f45b8-d8ec-4a35-9b44-50fb7b7343f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755680005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2755680005
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3858841509
Short name T298
Test name
Test status
Simulation time 988259607 ps
CPU time 8.2 seconds
Started Jun 26 06:23:26 PM PDT 24
Finished Jun 26 06:23:36 PM PDT 24
Peak memory 233592 kb
Host smart-1ad5e97f-7f85-42eb-bf4e-bf3e050c1818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858841509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3858841509
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2376796913
Short name T82
Test name
Test status
Simulation time 87005999 ps
CPU time 0.92 seconds
Started Jun 26 04:40:08 PM PDT 24
Finished Jun 26 04:40:11 PM PDT 24
Peak memory 206456 kb
Host smart-fe7e4792-6ce3-4cc1-9e25-6de5fa51a02e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376796913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2376796913
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3403398968
Short name T104
Test name
Test status
Simulation time 121788104 ps
CPU time 3.25 seconds
Started Jun 26 04:40:23 PM PDT 24
Finished Jun 26 04:40:30 PM PDT 24
Peak memory 214944 kb
Host smart-1799e855-f7e3-40ca-a4fa-c170e340c545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403398968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3403398968
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3862533283
Short name T106
Test name
Test status
Simulation time 292291149 ps
CPU time 18.92 seconds
Started Jun 26 04:40:15 PM PDT 24
Finished Jun 26 04:40:35 PM PDT 24
Peak memory 214820 kb
Host smart-56e9e77c-dc23-4739-8b93-f4fc82bc3628
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862533283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3862533283
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3687733362
Short name T41
Test name
Test status
Simulation time 26335720257 ps
CPU time 202.94 seconds
Started Jun 26 06:24:48 PM PDT 24
Finished Jun 26 06:28:12 PM PDT 24
Peak memory 268132 kb
Host smart-12b79114-80c5-460f-99eb-b09c526822cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687733362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3687733362
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.660105195
Short name T118
Test name
Test status
Simulation time 1145099737 ps
CPU time 23.17 seconds
Started Jun 26 04:40:04 PM PDT 24
Finished Jun 26 04:40:29 PM PDT 24
Peak memory 214832 kb
Host smart-15ceb6a5-b382-4084-97e0-b088d876de60
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660105195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.660105195
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1473016758
Short name T965
Test name
Test status
Simulation time 3542906529 ps
CPU time 12.82 seconds
Started Jun 26 04:40:03 PM PDT 24
Finished Jun 26 04:40:18 PM PDT 24
Peak memory 214844 kb
Host smart-06d71561-a8a9-4fac-b8a4-beb65cc0bb7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473016758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1473016758
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2614625397
Short name T84
Test name
Test status
Simulation time 15469234 ps
CPU time 1 seconds
Started Jun 26 04:40:06 PM PDT 24
Finished Jun 26 04:40:09 PM PDT 24
Peak memory 205904 kb
Host smart-638d61b3-743d-4c1a-b060-4b92db24069d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614625397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2614625397
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2023226165
Short name T996
Test name
Test status
Simulation time 219356361 ps
CPU time 2.73 seconds
Started Jun 26 04:40:06 PM PDT 24
Finished Jun 26 04:40:10 PM PDT 24
Peak memory 215964 kb
Host smart-6bbb2588-c83b-4f9d-8867-508782667765
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023226165 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2023226165
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1142630420
Short name T1047
Test name
Test status
Simulation time 65550882 ps
CPU time 1.94 seconds
Started Jun 26 04:40:05 PM PDT 24
Finished Jun 26 04:40:09 PM PDT 24
Peak memory 214772 kb
Host smart-f074f8dd-e59e-4e75-a5eb-7d1822b60b0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142630420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
142630420
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1711075119
Short name T1050
Test name
Test status
Simulation time 52083891 ps
CPU time 0.78 seconds
Started Jun 26 04:39:58 PM PDT 24
Finished Jun 26 04:40:03 PM PDT 24
Peak memory 203428 kb
Host smart-4d9bde6c-b2dd-439a-929b-6697b4042e98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711075119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
711075119
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.265475747
Short name T1081
Test name
Test status
Simulation time 41295257 ps
CPU time 1.21 seconds
Started Jun 26 04:40:01 PM PDT 24
Finished Jun 26 04:40:06 PM PDT 24
Peak memory 214796 kb
Host smart-75d49566-cb46-4814-b289-bb8c0654dbdb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265475747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.265475747
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2585485529
Short name T1077
Test name
Test status
Simulation time 34856245 ps
CPU time 0.68 seconds
Started Jun 26 04:39:59 PM PDT 24
Finished Jun 26 04:40:04 PM PDT 24
Peak memory 203320 kb
Host smart-e7c27fa2-ae86-4378-94f4-8d493473d4a1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585485529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2585485529
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3359288159
Short name T977
Test name
Test status
Simulation time 584423466 ps
CPU time 4.12 seconds
Started Jun 26 04:40:09 PM PDT 24
Finished Jun 26 04:40:15 PM PDT 24
Peak memory 214864 kb
Host smart-de8f82e6-6797-4189-8170-2adeb012ffa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359288159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3359288159
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4049971436
Short name T993
Test name
Test status
Simulation time 317255945 ps
CPU time 2.07 seconds
Started Jun 26 04:39:59 PM PDT 24
Finished Jun 26 04:40:06 PM PDT 24
Peak memory 215000 kb
Host smart-9bc081f0-d524-43e7-9645-712e2cbcebb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049971436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
049971436
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2947718712
Short name T1010
Test name
Test status
Simulation time 1530461465 ps
CPU time 8.76 seconds
Started Jun 26 04:40:04 PM PDT 24
Finished Jun 26 04:40:15 PM PDT 24
Peak memory 206596 kb
Host smart-c292e12c-714f-44e4-9749-7e715f3a42e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947718712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2947718712
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3169827544
Short name T119
Test name
Test status
Simulation time 1490643109 ps
CPU time 34.04 seconds
Started Jun 26 04:40:04 PM PDT 24
Finished Jun 26 04:40:40 PM PDT 24
Peak memory 206612 kb
Host smart-e1dc7bbe-4e6c-4463-a19e-b22c2bd28670
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169827544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3169827544
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1457679969
Short name T1016
Test name
Test status
Simulation time 87023104 ps
CPU time 1.67 seconds
Started Jun 26 04:40:09 PM PDT 24
Finished Jun 26 04:40:12 PM PDT 24
Peak memory 214800 kb
Host smart-30fcfc25-8c82-4160-8a29-9f5bab82acac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457679969 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1457679969
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2612425361
Short name T1070
Test name
Test status
Simulation time 109703602 ps
CPU time 2.42 seconds
Started Jun 26 04:40:05 PM PDT 24
Finished Jun 26 04:40:10 PM PDT 24
Peak memory 214832 kb
Host smart-2ced4c3c-0557-40ae-83e9-4cfe1d5e9388
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612425361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
612425361
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1252878466
Short name T1023
Test name
Test status
Simulation time 32142776 ps
CPU time 0.78 seconds
Started Jun 26 04:40:06 PM PDT 24
Finished Jun 26 04:40:09 PM PDT 24
Peak memory 202940 kb
Host smart-dda03050-006e-4150-8821-fb578243779c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252878466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
252878466
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3967923286
Short name T1018
Test name
Test status
Simulation time 26598097 ps
CPU time 2.19 seconds
Started Jun 26 04:40:05 PM PDT 24
Finished Jun 26 04:40:10 PM PDT 24
Peak memory 214820 kb
Host smart-2d86832d-125c-44f7-8371-99e0ee102ae9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967923286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3967923286
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.813283460
Short name T981
Test name
Test status
Simulation time 10637749 ps
CPU time 0.67 seconds
Started Jun 26 04:40:06 PM PDT 24
Finished Jun 26 04:40:09 PM PDT 24
Peak memory 203324 kb
Host smart-a7232b8c-ab2e-4cc8-a8e1-9b37c6666b66
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813283460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.813283460
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3785351700
Short name T1079
Test name
Test status
Simulation time 180887722 ps
CPU time 2.78 seconds
Started Jun 26 04:40:03 PM PDT 24
Finished Jun 26 04:40:08 PM PDT 24
Peak memory 214844 kb
Host smart-c5e9f6c0-1206-4759-9738-32aa7ee9dd67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785351700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3785351700
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2297315605
Short name T94
Test name
Test status
Simulation time 230291010 ps
CPU time 1.79 seconds
Started Jun 26 04:40:06 PM PDT 24
Finished Jun 26 04:40:09 PM PDT 24
Peak memory 215092 kb
Host smart-7601e232-f5fe-4c02-9583-347c9cb03eef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297315605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
297315605
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.912782820
Short name T1030
Test name
Test status
Simulation time 97555422 ps
CPU time 2.85 seconds
Started Jun 26 04:40:24 PM PDT 24
Finished Jun 26 04:40:31 PM PDT 24
Peak memory 215916 kb
Host smart-4ecbedc7-7221-491b-a620-edf2257437d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912782820 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.912782820
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1706728165
Short name T1002
Test name
Test status
Simulation time 36766516 ps
CPU time 1.38 seconds
Started Jun 26 04:40:22 PM PDT 24
Finished Jun 26 04:40:28 PM PDT 24
Peak memory 214860 kb
Host smart-99edc8c8-22c2-4157-a743-9e4971663017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706728165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1706728165
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.607136780
Short name T999
Test name
Test status
Simulation time 14115605 ps
CPU time 0.73 seconds
Started Jun 26 04:40:23 PM PDT 24
Finished Jun 26 04:40:28 PM PDT 24
Peak memory 203444 kb
Host smart-e0c1128b-8bf1-4d51-9381-069c0efb2199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607136780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.607136780
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1278399781
Short name T1049
Test name
Test status
Simulation time 2237052758 ps
CPU time 4.72 seconds
Started Jun 26 04:40:24 PM PDT 24
Finished Jun 26 04:40:33 PM PDT 24
Peak memory 214844 kb
Host smart-11feebce-b845-403b-a5dc-f9e9c58282ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278399781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1278399781
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2667473454
Short name T1026
Test name
Test status
Simulation time 602179019 ps
CPU time 3.25 seconds
Started Jun 26 04:40:23 PM PDT 24
Finished Jun 26 04:40:31 PM PDT 24
Peak memory 215108 kb
Host smart-de444da7-8add-4d8b-94a6-c32d210ce90b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667473454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2667473454
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1951578315
Short name T1074
Test name
Test status
Simulation time 430247575 ps
CPU time 12.62 seconds
Started Jun 26 04:40:22 PM PDT 24
Finished Jun 26 04:40:39 PM PDT 24
Peak memory 214848 kb
Host smart-03fcc8f8-9803-4e54-9ef4-567003e38fd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951578315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1951578315
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.358597908
Short name T1068
Test name
Test status
Simulation time 123657927 ps
CPU time 3.73 seconds
Started Jun 26 04:40:23 PM PDT 24
Finished Jun 26 04:40:31 PM PDT 24
Peak memory 216728 kb
Host smart-f595b4f0-ef33-4c01-8f2f-178443aa804e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358597908 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.358597908
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1671559156
Short name T1028
Test name
Test status
Simulation time 45302420 ps
CPU time 1.39 seconds
Started Jun 26 04:40:23 PM PDT 24
Finished Jun 26 04:40:28 PM PDT 24
Peak memory 214764 kb
Host smart-6c0192c5-4cd2-447d-b7d8-1c81f47bc361
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671559156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1671559156
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1007603263
Short name T1056
Test name
Test status
Simulation time 53143597 ps
CPU time 0.76 seconds
Started Jun 26 04:40:24 PM PDT 24
Finished Jun 26 04:40:29 PM PDT 24
Peak memory 203752 kb
Host smart-91197d0f-9fce-45d5-a9b2-c2f754c67c37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007603263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1007603263
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1174782237
Short name T1007
Test name
Test status
Simulation time 157592872 ps
CPU time 4.07 seconds
Started Jun 26 04:40:21 PM PDT 24
Finished Jun 26 04:40:28 PM PDT 24
Peak memory 214840 kb
Host smart-b6078a67-0c65-4456-9267-a7efe1fd586e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174782237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1174782237
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2819499276
Short name T158
Test name
Test status
Simulation time 1050112225 ps
CPU time 14.58 seconds
Started Jun 26 04:40:22 PM PDT 24
Finished Jun 26 04:40:41 PM PDT 24
Peak memory 214828 kb
Host smart-4d4e2ff4-1ace-45ae-a11e-251a44f722bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819499276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2819499276
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1672159346
Short name T64
Test name
Test status
Simulation time 99812091 ps
CPU time 2.07 seconds
Started Jun 26 04:40:22 PM PDT 24
Finished Jun 26 04:40:27 PM PDT 24
Peak memory 216028 kb
Host smart-b337e55f-15e7-4c79-b1d1-55ed48dbf318
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672159346 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1672159346
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2366971466
Short name T113
Test name
Test status
Simulation time 360272155 ps
CPU time 1.9 seconds
Started Jun 26 04:40:21 PM PDT 24
Finished Jun 26 04:40:26 PM PDT 24
Peak memory 214764 kb
Host smart-7a996a1e-20c0-4074-9061-0fa1c0ce6ef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366971466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2366971466
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3800970484
Short name T1073
Test name
Test status
Simulation time 17619497 ps
CPU time 0.75 seconds
Started Jun 26 04:40:23 PM PDT 24
Finished Jun 26 04:40:28 PM PDT 24
Peak memory 203544 kb
Host smart-e87f91d9-6e8f-4f39-bdbf-af5f95010ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800970484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3800970484
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3869921761
Short name T1019
Test name
Test status
Simulation time 447654399 ps
CPU time 4.62 seconds
Started Jun 26 04:40:21 PM PDT 24
Finished Jun 26 04:40:28 PM PDT 24
Peak memory 214864 kb
Host smart-b18b5d80-88be-474f-9034-25c03affed04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869921761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3869921761
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3844628401
Short name T146
Test name
Test status
Simulation time 685759130 ps
CPU time 2.35 seconds
Started Jun 26 04:40:20 PM PDT 24
Finished Jun 26 04:40:25 PM PDT 24
Peak memory 215004 kb
Host smart-6d88e6a8-43c0-4585-a01a-7baf9d070a39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844628401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3844628401
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.852459436
Short name T991
Test name
Test status
Simulation time 79260998 ps
CPU time 1.59 seconds
Started Jun 26 04:40:22 PM PDT 24
Finished Jun 26 04:40:27 PM PDT 24
Peak memory 214840 kb
Host smart-46cc00c2-3f00-45bd-b4e2-309d79d6e8ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852459436 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.852459436
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3901921593
Short name T116
Test name
Test status
Simulation time 439136221 ps
CPU time 2.74 seconds
Started Jun 26 04:40:22 PM PDT 24
Finished Jun 26 04:40:29 PM PDT 24
Peak memory 214924 kb
Host smart-136f3d7c-0b78-4b35-8960-e21de77df4d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901921593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3901921593
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1773818877
Short name T1020
Test name
Test status
Simulation time 22967151 ps
CPU time 0.71 seconds
Started Jun 26 04:40:21 PM PDT 24
Finished Jun 26 04:40:25 PM PDT 24
Peak memory 203736 kb
Host smart-6a31e3a6-82dd-4a57-87d0-973efeff4098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773818877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1773818877
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.5747754
Short name T145
Test name
Test status
Simulation time 188542806 ps
CPU time 2.08 seconds
Started Jun 26 04:40:21 PM PDT 24
Finished Jun 26 04:40:26 PM PDT 24
Peak memory 214764 kb
Host smart-261aed9c-419c-4d3b-9f0f-200cae9ef8c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5747754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi
_device_same_csr_outstanding.5747754
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1836768868
Short name T108
Test name
Test status
Simulation time 256734050 ps
CPU time 1.86 seconds
Started Jun 26 04:40:22 PM PDT 24
Finished Jun 26 04:40:27 PM PDT 24
Peak memory 215008 kb
Host smart-23acee27-3bef-4549-8fc5-d960c5728b4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836768868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1836768868
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.142575491
Short name T96
Test name
Test status
Simulation time 1073687522 ps
CPU time 7.64 seconds
Started Jun 26 04:40:23 PM PDT 24
Finished Jun 26 04:40:35 PM PDT 24
Peak memory 214808 kb
Host smart-a76dd257-1a9a-4fb4-8ba8-878437421d12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142575491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.142575491
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3721272453
Short name T1052
Test name
Test status
Simulation time 336692435 ps
CPU time 2.85 seconds
Started Jun 26 04:40:23 PM PDT 24
Finished Jun 26 04:40:30 PM PDT 24
Peak memory 216172 kb
Host smart-51f775a9-7e2c-42fc-9dd1-1542be877119
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721272453 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3721272453
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1436464196
Short name T1038
Test name
Test status
Simulation time 19876358 ps
CPU time 1.25 seconds
Started Jun 26 04:40:20 PM PDT 24
Finished Jun 26 04:40:23 PM PDT 24
Peak memory 214804 kb
Host smart-041744f2-b9ea-405b-88f3-1379d4d08964
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436464196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1436464196
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1203199367
Short name T1032
Test name
Test status
Simulation time 25267068 ps
CPU time 0.71 seconds
Started Jun 26 04:40:21 PM PDT 24
Finished Jun 26 04:40:24 PM PDT 24
Peak memory 203424 kb
Host smart-72425ab5-59d3-4a05-a681-9afcb273011b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203199367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1203199367
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.977013541
Short name T139
Test name
Test status
Simulation time 814652618 ps
CPU time 4.63 seconds
Started Jun 26 04:40:22 PM PDT 24
Finished Jun 26 04:40:30 PM PDT 24
Peak memory 214772 kb
Host smart-310e1d8e-6e3a-4ef0-a75e-eee05848912f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977013541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.977013541
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1173151178
Short name T107
Test name
Test status
Simulation time 1068091065 ps
CPU time 3.47 seconds
Started Jun 26 04:40:21 PM PDT 24
Finished Jun 26 04:40:28 PM PDT 24
Peak memory 216016 kb
Host smart-585efa30-b5e6-497c-997b-bbf03ad2a609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173151178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1173151178
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4278978753
Short name T1075
Test name
Test status
Simulation time 266325416 ps
CPU time 7.26 seconds
Started Jun 26 04:40:23 PM PDT 24
Finished Jun 26 04:40:34 PM PDT 24
Peak memory 215184 kb
Host smart-a31872ed-0a14-416f-a6c6-fa24ce1406f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278978753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.4278978753
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1930166375
Short name T983
Test name
Test status
Simulation time 143418182 ps
CPU time 2.56 seconds
Started Jun 26 04:40:27 PM PDT 24
Finished Jun 26 04:40:33 PM PDT 24
Peak memory 216628 kb
Host smart-3a7d79a5-5220-4063-99ba-c218e85b8b61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930166375 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1930166375
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1398170480
Short name T1072
Test name
Test status
Simulation time 95387646 ps
CPU time 1.8 seconds
Started Jun 26 04:40:26 PM PDT 24
Finished Jun 26 04:40:32 PM PDT 24
Peak memory 214872 kb
Host smart-8a7c3cc4-087f-46d2-b9f7-7d5cf751f836
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398170480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1398170480
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1535327013
Short name T987
Test name
Test status
Simulation time 50480217 ps
CPU time 0.71 seconds
Started Jun 26 04:40:25 PM PDT 24
Finished Jun 26 04:40:30 PM PDT 24
Peak memory 203724 kb
Host smart-31eed188-2c4a-49d9-95f9-c86d54eba0dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535327013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1535327013
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2401287402
Short name T1060
Test name
Test status
Simulation time 159340942 ps
CPU time 4.33 seconds
Started Jun 26 04:40:26 PM PDT 24
Finished Jun 26 04:40:34 PM PDT 24
Peak memory 215240 kb
Host smart-4d83c335-94de-4f0c-aaa0-11db63ffc0d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401287402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2401287402
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.117157016
Short name T63
Test name
Test status
Simulation time 246240653 ps
CPU time 1.96 seconds
Started Jun 26 04:40:23 PM PDT 24
Finished Jun 26 04:40:29 PM PDT 24
Peak memory 215960 kb
Host smart-74872d06-2c39-4f57-9a4a-46c185054702
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117157016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.117157016
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2747593708
Short name T163
Test name
Test status
Simulation time 308874661 ps
CPU time 7.96 seconds
Started Jun 26 04:40:22 PM PDT 24
Finished Jun 26 04:40:34 PM PDT 24
Peak memory 214940 kb
Host smart-a798d7e2-1184-4b74-a37f-1a4af8b7b12a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747593708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2747593708
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1973515955
Short name T1027
Test name
Test status
Simulation time 602294148 ps
CPU time 3.65 seconds
Started Jun 26 04:40:28 PM PDT 24
Finished Jun 26 04:40:35 PM PDT 24
Peak memory 217936 kb
Host smart-5e7366eb-6354-47e8-a978-b3215089ec4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973515955 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1973515955
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4253602451
Short name T144
Test name
Test status
Simulation time 44777844 ps
CPU time 1.29 seconds
Started Jun 26 04:43:54 PM PDT 24
Finished Jun 26 04:44:05 PM PDT 24
Peak memory 214964 kb
Host smart-e0cce655-915c-44a0-98d4-c644406a5841
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253602451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4253602451
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4009567737
Short name T1014
Test name
Test status
Simulation time 14143536 ps
CPU time 0.69 seconds
Started Jun 26 04:40:27 PM PDT 24
Finished Jun 26 04:40:31 PM PDT 24
Peak memory 203736 kb
Host smart-c9861311-c3b3-46dd-8b7e-8c474ce46d97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009567737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4009567737
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1205614614
Short name T128
Test name
Test status
Simulation time 61896158 ps
CPU time 3.98 seconds
Started Jun 26 04:40:27 PM PDT 24
Finished Jun 26 04:40:35 PM PDT 24
Peak memory 215148 kb
Host smart-4c1c55e2-8345-4543-9437-4c226b188d65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205614614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1205614614
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.103250664
Short name T97
Test name
Test status
Simulation time 334677213 ps
CPU time 2.6 seconds
Started Jun 26 04:40:26 PM PDT 24
Finished Jun 26 04:40:32 PM PDT 24
Peak memory 216412 kb
Host smart-71223e0d-f984-4bdc-80ee-660ed6b7a7a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103250664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.103250664
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3556566067
Short name T161
Test name
Test status
Simulation time 2127347235 ps
CPU time 7.22 seconds
Started Jun 26 04:40:28 PM PDT 24
Finished Jun 26 04:40:39 PM PDT 24
Peak memory 214996 kb
Host smart-9978eb77-71bb-48c3-87f5-d2276ac5b449
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556566067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3556566067
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2527067448
Short name T1021
Test name
Test status
Simulation time 492191897 ps
CPU time 3.76 seconds
Started Jun 26 04:40:27 PM PDT 24
Finished Jun 26 04:40:34 PM PDT 24
Peak memory 216588 kb
Host smart-b9604bdb-795d-4129-8bfb-2382a18febca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527067448 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2527067448
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.429232691
Short name T117
Test name
Test status
Simulation time 26406306 ps
CPU time 1.89 seconds
Started Jun 26 04:40:28 PM PDT 24
Finished Jun 26 04:40:33 PM PDT 24
Peak memory 206588 kb
Host smart-feb32908-7b29-4e0a-a3fa-91e9ac7da01e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429232691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.429232691
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4189259214
Short name T998
Test name
Test status
Simulation time 42752366 ps
CPU time 0.73 seconds
Started Jun 26 04:40:28 PM PDT 24
Finished Jun 26 04:40:32 PM PDT 24
Peak memory 203388 kb
Host smart-6bf2d558-0535-4bc8-afd3-70ce14005517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189259214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
4189259214
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1906291711
Short name T1043
Test name
Test status
Simulation time 124562330 ps
CPU time 3.96 seconds
Started Jun 26 04:40:29 PM PDT 24
Finished Jun 26 04:40:36 PM PDT 24
Peak memory 214792 kb
Host smart-cc51c7a2-fd45-4de6-88f2-3f3f348dcb2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906291711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1906291711
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4207162445
Short name T992
Test name
Test status
Simulation time 110042263 ps
CPU time 1.93 seconds
Started Jun 26 04:40:27 PM PDT 24
Finished Jun 26 04:40:33 PM PDT 24
Peak memory 215952 kb
Host smart-349294e7-4faa-4c2b-b195-402686b37f91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207162445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
4207162445
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3722082141
Short name T1025
Test name
Test status
Simulation time 3256261681 ps
CPU time 19.47 seconds
Started Jun 26 04:40:33 PM PDT 24
Finished Jun 26 04:40:56 PM PDT 24
Peak memory 214840 kb
Host smart-bf974da8-b085-4785-8978-fde5e8e07bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722082141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3722082141
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3590792351
Short name T1011
Test name
Test status
Simulation time 51165742 ps
CPU time 2.96 seconds
Started Jun 26 04:40:30 PM PDT 24
Finished Jun 26 04:40:36 PM PDT 24
Peak memory 217316 kb
Host smart-e779643c-6abc-4b3e-99f5-7573c0a611f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590792351 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3590792351
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2575538857
Short name T120
Test name
Test status
Simulation time 852756266 ps
CPU time 2.69 seconds
Started Jun 26 04:40:33 PM PDT 24
Finished Jun 26 04:40:40 PM PDT 24
Peak memory 214836 kb
Host smart-4d8f39d7-cdc9-40fd-a7dc-7ec54abecd76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575538857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2575538857
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3152218209
Short name T971
Test name
Test status
Simulation time 43390064 ps
CPU time 0.75 seconds
Started Jun 26 04:40:27 PM PDT 24
Finished Jun 26 04:40:32 PM PDT 24
Peak memory 203432 kb
Host smart-bc7d81f3-f338-42c2-98c2-e4a44fcd3f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152218209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3152218209
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2553431572
Short name T1001
Test name
Test status
Simulation time 596914185 ps
CPU time 3.88 seconds
Started Jun 26 04:40:29 PM PDT 24
Finished Jun 26 04:40:36 PM PDT 24
Peak memory 214840 kb
Host smart-2d8ab679-6e75-402c-ba3b-06d2959278e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553431572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2553431572
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.801779870
Short name T1034
Test name
Test status
Simulation time 630295271 ps
CPU time 3.14 seconds
Started Jun 26 04:40:29 PM PDT 24
Finished Jun 26 04:40:35 PM PDT 24
Peak memory 214996 kb
Host smart-91c2160a-a4a3-489e-80bc-80b00c460a94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801779870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.801779870
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2831195437
Short name T142
Test name
Test status
Simulation time 2045062549 ps
CPU time 22.65 seconds
Started Jun 26 04:40:28 PM PDT 24
Finished Jun 26 04:40:54 PM PDT 24
Peak memory 214944 kb
Host smart-e1e73428-a0d8-4093-b177-045af45dfbaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831195437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2831195437
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3232053712
Short name T1012
Test name
Test status
Simulation time 248010232 ps
CPU time 3.41 seconds
Started Jun 26 04:40:28 PM PDT 24
Finished Jun 26 04:40:35 PM PDT 24
Peak memory 217416 kb
Host smart-477e762d-6e8f-4d82-ab39-0f77055bb88c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232053712 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3232053712
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3236105130
Short name T989
Test name
Test status
Simulation time 21359432 ps
CPU time 0.72 seconds
Started Jun 26 04:40:30 PM PDT 24
Finished Jun 26 04:40:34 PM PDT 24
Peak memory 203744 kb
Host smart-43d38ccf-51d3-4e55-83fb-e6139173fabd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236105130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3236105130
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1516661187
Short name T1039
Test name
Test status
Simulation time 451715281 ps
CPU time 4.71 seconds
Started Jun 26 04:40:26 PM PDT 24
Finished Jun 26 04:40:35 PM PDT 24
Peak memory 214792 kb
Host smart-89fb50d8-62e7-4feb-97ba-a8580b27b0d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516661187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1516661187
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1828387591
Short name T109
Test name
Test status
Simulation time 2238419937 ps
CPU time 15.95 seconds
Started Jun 26 04:40:29 PM PDT 24
Finished Jun 26 04:40:49 PM PDT 24
Peak memory 214900 kb
Host smart-5fb56549-f8a1-4403-9836-741b2ed0dd39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828387591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1828387591
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.950333667
Short name T986
Test name
Test status
Simulation time 622875628 ps
CPU time 8.02 seconds
Started Jun 26 04:40:10 PM PDT 24
Finished Jun 26 04:40:20 PM PDT 24
Peak memory 206636 kb
Host smart-ff022aa2-3beb-4534-b7a9-b1630fcb57e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950333667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.950333667
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3085804526
Short name T1042
Test name
Test status
Simulation time 616985968 ps
CPU time 12.64 seconds
Started Jun 26 04:40:10 PM PDT 24
Finished Jun 26 04:40:25 PM PDT 24
Peak memory 214868 kb
Host smart-0628061d-22d8-4dca-ad74-c5de2435e528
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085804526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3085804526
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.471936314
Short name T83
Test name
Test status
Simulation time 61938222 ps
CPU time 1.19 seconds
Started Jun 26 04:40:09 PM PDT 24
Finished Jun 26 04:40:12 PM PDT 24
Peak memory 206604 kb
Host smart-669af318-4e47-4e4e-bf6e-decc5559ac97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471936314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.471936314
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3591151881
Short name T997
Test name
Test status
Simulation time 503825355 ps
CPU time 3.61 seconds
Started Jun 26 04:40:12 PM PDT 24
Finished Jun 26 04:40:18 PM PDT 24
Peak memory 215940 kb
Host smart-36fa0fd0-4b60-421f-8985-e091b74b9a1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591151881 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3591151881
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3998084147
Short name T995
Test name
Test status
Simulation time 187504771 ps
CPU time 2.3 seconds
Started Jun 26 04:40:10 PM PDT 24
Finished Jun 26 04:40:14 PM PDT 24
Peak memory 214968 kb
Host smart-35a71bf6-b3d7-49d8-8c7c-d20cb159ab92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998084147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
998084147
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3301445322
Short name T967
Test name
Test status
Simulation time 48992149 ps
CPU time 0.77 seconds
Started Jun 26 04:40:11 PM PDT 24
Finished Jun 26 04:40:14 PM PDT 24
Peak memory 203452 kb
Host smart-7d351683-7056-4f9d-9fc3-fc9402299f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301445322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
301445322
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1582674590
Short name T1071
Test name
Test status
Simulation time 23145464 ps
CPU time 1.73 seconds
Started Jun 26 04:40:09 PM PDT 24
Finished Jun 26 04:40:13 PM PDT 24
Peak memory 214848 kb
Host smart-6857278c-057b-4a52-af2a-d887fa3f0617
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582674590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1582674590
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.160804475
Short name T982
Test name
Test status
Simulation time 59023687 ps
CPU time 0.65 seconds
Started Jun 26 04:40:08 PM PDT 24
Finished Jun 26 04:40:11 PM PDT 24
Peak memory 203320 kb
Host smart-5d8e62f8-991b-43bf-9947-1cb527aaa04f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160804475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.160804475
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.898206488
Short name T131
Test name
Test status
Simulation time 85859715 ps
CPU time 1.65 seconds
Started Jun 26 04:40:12 PM PDT 24
Finished Jun 26 04:40:15 PM PDT 24
Peak memory 206624 kb
Host smart-2ec53155-876d-4f0a-bdb2-53891052a9c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898206488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.898206488
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1108752388
Short name T105
Test name
Test status
Simulation time 31485369 ps
CPU time 2.04 seconds
Started Jun 26 04:40:04 PM PDT 24
Finished Jun 26 04:40:08 PM PDT 24
Peak memory 214988 kb
Host smart-ea39501c-8823-41d9-8861-b6c3e8ed1f75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108752388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
108752388
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1636833104
Short name T1035
Test name
Test status
Simulation time 621295587 ps
CPU time 8.25 seconds
Started Jun 26 04:40:03 PM PDT 24
Finished Jun 26 04:40:14 PM PDT 24
Peak memory 214800 kb
Host smart-69b1b9e8-263f-48c6-94d7-b9cbe2daa657
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636833104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1636833104
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1331070575
Short name T1057
Test name
Test status
Simulation time 40434090 ps
CPU time 0.7 seconds
Started Jun 26 04:40:28 PM PDT 24
Finished Jun 26 04:40:32 PM PDT 24
Peak memory 203392 kb
Host smart-fb4d8ee5-5aeb-42bd-967d-9b0eb7c2c533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331070575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1331070575
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1114768721
Short name T1067
Test name
Test status
Simulation time 68667280 ps
CPU time 0.72 seconds
Started Jun 26 04:40:27 PM PDT 24
Finished Jun 26 04:40:31 PM PDT 24
Peak memory 203736 kb
Host smart-83eba19b-0ea1-4896-aa12-e005d71bbb7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114768721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1114768721
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2295455141
Short name T968
Test name
Test status
Simulation time 37833317 ps
CPU time 0.66 seconds
Started Jun 26 04:40:25 PM PDT 24
Finished Jun 26 04:40:30 PM PDT 24
Peak memory 203412 kb
Host smart-286796d1-8075-444a-973e-8a7cb2764c7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295455141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2295455141
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3742331315
Short name T1024
Test name
Test status
Simulation time 20289877 ps
CPU time 0.75 seconds
Started Jun 26 04:40:34 PM PDT 24
Finished Jun 26 04:40:40 PM PDT 24
Peak memory 203740 kb
Host smart-f90c3f09-2e00-41c6-900b-455c01451db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742331315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3742331315
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.639004369
Short name T966
Test name
Test status
Simulation time 14426778 ps
CPU time 0.75 seconds
Started Jun 26 04:40:36 PM PDT 24
Finished Jun 26 04:40:43 PM PDT 24
Peak memory 203712 kb
Host smart-8f7fe6d5-8233-4809-b062-a43b852f49d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639004369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.639004369
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2286702990
Short name T962
Test name
Test status
Simulation time 14647004 ps
CPU time 0.76 seconds
Started Jun 26 04:40:34 PM PDT 24
Finished Jun 26 04:40:40 PM PDT 24
Peak memory 203744 kb
Host smart-6c48837c-0bb3-4f37-9f21-5181e10034dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286702990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2286702990
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2853508934
Short name T1005
Test name
Test status
Simulation time 84582610 ps
CPU time 0.71 seconds
Started Jun 26 04:40:35 PM PDT 24
Finished Jun 26 04:40:42 PM PDT 24
Peak memory 203428 kb
Host smart-2d9e0a54-a1de-49ae-959e-6a4e1d60fc2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853508934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2853508934
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3299426952
Short name T994
Test name
Test status
Simulation time 24541151 ps
CPU time 0.8 seconds
Started Jun 26 04:40:33 PM PDT 24
Finished Jun 26 04:40:38 PM PDT 24
Peak memory 203436 kb
Host smart-4d2aa3f9-7c49-4b18-9d8a-523f4fdd6b3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299426952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3299426952
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.15822390
Short name T979
Test name
Test status
Simulation time 66465048 ps
CPU time 0.73 seconds
Started Jun 26 04:40:34 PM PDT 24
Finished Jun 26 04:40:40 PM PDT 24
Peak memory 203396 kb
Host smart-863adb5f-3ccd-4196-9173-8019bf2e1303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15822390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.15822390
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.414639061
Short name T980
Test name
Test status
Simulation time 11761317 ps
CPU time 0.76 seconds
Started Jun 26 04:40:35 PM PDT 24
Finished Jun 26 04:40:41 PM PDT 24
Peak memory 203768 kb
Host smart-bdc4bd4a-2044-427a-b661-bf7d7729397b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414639061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.414639061
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.419982323
Short name T1015
Test name
Test status
Simulation time 377312758 ps
CPU time 8.87 seconds
Started Jun 26 04:40:21 PM PDT 24
Finished Jun 26 04:40:32 PM PDT 24
Peak memory 206536 kb
Host smart-472965d2-5858-4f38-8917-721f40e76049
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419982323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.419982323
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.996104863
Short name T1009
Test name
Test status
Simulation time 644188188 ps
CPU time 11.02 seconds
Started Jun 26 04:40:11 PM PDT 24
Finished Jun 26 04:40:24 PM PDT 24
Peak memory 215964 kb
Host smart-2dae3d5b-ba2e-48ed-a429-71008abf98a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996104863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.996104863
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1731731758
Short name T85
Test name
Test status
Simulation time 35877624 ps
CPU time 1.25 seconds
Started Jun 26 04:40:10 PM PDT 24
Finished Jun 26 04:40:14 PM PDT 24
Peak memory 206676 kb
Host smart-009a0b6c-6064-419a-919d-defb38a144a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731731758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1731731758
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3767859739
Short name T65
Test name
Test status
Simulation time 61263094 ps
CPU time 2.74 seconds
Started Jun 26 04:40:11 PM PDT 24
Finished Jun 26 04:40:16 PM PDT 24
Peak memory 216332 kb
Host smart-dde5c60e-7aea-4ebf-b02d-5362c9b9919d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767859739 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3767859739
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4057904278
Short name T140
Test name
Test status
Simulation time 504674093 ps
CPU time 1.95 seconds
Started Jun 26 04:40:21 PM PDT 24
Finished Jun 26 04:40:25 PM PDT 24
Peak memory 206576 kb
Host smart-e418c919-45e5-49c7-bb90-711d2ddafa22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057904278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
057904278
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2620305226
Short name T1000
Test name
Test status
Simulation time 25279981 ps
CPU time 0.77 seconds
Started Jun 26 04:40:11 PM PDT 24
Finished Jun 26 04:40:14 PM PDT 24
Peak memory 203424 kb
Host smart-88d0cdaa-9da4-4e42-a48b-0610f0272dc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620305226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
620305226
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4004186530
Short name T1003
Test name
Test status
Simulation time 31403129 ps
CPU time 1.34 seconds
Started Jun 26 04:40:12 PM PDT 24
Finished Jun 26 04:40:15 PM PDT 24
Peak memory 214836 kb
Host smart-4fecb27d-934b-469c-b030-abb4b7523bad
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004186530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4004186530
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.501828283
Short name T976
Test name
Test status
Simulation time 81932989 ps
CPU time 0.66 seconds
Started Jun 26 04:40:11 PM PDT 24
Finished Jun 26 04:40:14 PM PDT 24
Peak memory 203328 kb
Host smart-86bf88af-cf70-4f27-b097-119b03d67f39
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501828283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.501828283
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3302799861
Short name T975
Test name
Test status
Simulation time 332664540 ps
CPU time 4.23 seconds
Started Jun 26 04:40:11 PM PDT 24
Finished Jun 26 04:40:17 PM PDT 24
Peak memory 214816 kb
Host smart-ac4d44c3-85ef-4cdb-8e08-ae566c8258a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302799861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3302799861
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1285869271
Short name T101
Test name
Test status
Simulation time 60044705 ps
CPU time 1.66 seconds
Started Jun 26 04:40:09 PM PDT 24
Finished Jun 26 04:40:13 PM PDT 24
Peak memory 214956 kb
Host smart-5482b2bf-6dc7-4963-a39d-8959e6a29f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285869271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
285869271
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.469518849
Short name T1048
Test name
Test status
Simulation time 41976668 ps
CPU time 0.71 seconds
Started Jun 26 04:40:36 PM PDT 24
Finished Jun 26 04:40:43 PM PDT 24
Peak memory 203436 kb
Host smart-6de8d60e-1de0-49df-8fe2-19815d09f4c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469518849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.469518849
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3306295482
Short name T1076
Test name
Test status
Simulation time 15373663 ps
CPU time 0.71 seconds
Started Jun 26 04:40:35 PM PDT 24
Finished Jun 26 04:40:41 PM PDT 24
Peak memory 203408 kb
Host smart-99ec1ac1-3766-48dd-a18b-aacbfaa4884a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306295482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3306295482
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3368251637
Short name T1062
Test name
Test status
Simulation time 13463391 ps
CPU time 0.69 seconds
Started Jun 26 04:40:33 PM PDT 24
Finished Jun 26 04:40:38 PM PDT 24
Peak memory 203436 kb
Host smart-c2ad4c01-e862-4348-859a-3fe50d76655a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368251637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3368251637
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.10961370
Short name T1029
Test name
Test status
Simulation time 49565637 ps
CPU time 0.77 seconds
Started Jun 26 04:40:38 PM PDT 24
Finished Jun 26 04:40:45 PM PDT 24
Peak memory 203432 kb
Host smart-810c03f3-de71-4d4e-a7f2-bac421b2df3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10961370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.10961370
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.517496290
Short name T1033
Test name
Test status
Simulation time 20908466 ps
CPU time 0.71 seconds
Started Jun 26 04:40:34 PM PDT 24
Finished Jun 26 04:40:40 PM PDT 24
Peak memory 203440 kb
Host smart-4ee10a5f-3412-4a1b-b906-88962f4bcd36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517496290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.517496290
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2343031371
Short name T1006
Test name
Test status
Simulation time 22157829 ps
CPU time 0.74 seconds
Started Jun 26 04:40:32 PM PDT 24
Finished Jun 26 04:40:35 PM PDT 24
Peak memory 203800 kb
Host smart-db85943f-fb1b-4f9e-a6c0-e17278d34507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343031371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2343031371
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3870979391
Short name T963
Test name
Test status
Simulation time 14823138 ps
CPU time 0.73 seconds
Started Jun 26 04:40:33 PM PDT 24
Finished Jun 26 04:40:37 PM PDT 24
Peak memory 204112 kb
Host smart-d453c765-062f-4833-8e99-410c0dd924b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870979391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3870979391
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.992161313
Short name T1037
Test name
Test status
Simulation time 41834313 ps
CPU time 0.72 seconds
Started Jun 26 04:40:36 PM PDT 24
Finished Jun 26 04:40:42 PM PDT 24
Peak memory 203396 kb
Host smart-c29b0811-3bd5-48e4-ab8f-0fffc9174f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992161313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.992161313
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3945099325
Short name T1066
Test name
Test status
Simulation time 37052570 ps
CPU time 0.74 seconds
Started Jun 26 04:40:34 PM PDT 24
Finished Jun 26 04:40:40 PM PDT 24
Peak memory 203432 kb
Host smart-2c5420df-2aad-4a98-9eb7-036fc19fff71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945099325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3945099325
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3274809468
Short name T1004
Test name
Test status
Simulation time 18547282 ps
CPU time 0.75 seconds
Started Jun 26 04:40:35 PM PDT 24
Finished Jun 26 04:40:42 PM PDT 24
Peak memory 203708 kb
Host smart-81e692ae-dae1-4454-b4d8-74e3cad72307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274809468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3274809468
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2311477260
Short name T1046
Test name
Test status
Simulation time 1300698128 ps
CPU time 8.82 seconds
Started Jun 26 04:40:21 PM PDT 24
Finished Jun 26 04:40:32 PM PDT 24
Peak memory 206560 kb
Host smart-bf393e41-b4cb-4b03-9911-7d7a069c063f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311477260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2311477260
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1344953310
Short name T111
Test name
Test status
Simulation time 1902837277 ps
CPU time 27.41 seconds
Started Jun 26 04:40:11 PM PDT 24
Finished Jun 26 04:40:41 PM PDT 24
Peak memory 206612 kb
Host smart-613785de-3cba-40c6-972d-8c8e7bf30c30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344953310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1344953310
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1810670094
Short name T115
Test name
Test status
Simulation time 20401298 ps
CPU time 1 seconds
Started Jun 26 04:40:08 PM PDT 24
Finished Jun 26 04:40:11 PM PDT 24
Peak memory 206468 kb
Host smart-47c0fea5-cecc-46e7-86e4-e24db69eb5fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810670094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1810670094
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4045544985
Short name T1017
Test name
Test status
Simulation time 253322393 ps
CPU time 3.95 seconds
Started Jun 26 04:40:09 PM PDT 24
Finished Jun 26 04:40:15 PM PDT 24
Peak memory 217636 kb
Host smart-85438f63-c5aa-402d-9cde-0a591712ccc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045544985 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4045544985
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2012368259
Short name T1064
Test name
Test status
Simulation time 69252285 ps
CPU time 1.98 seconds
Started Jun 26 04:40:10 PM PDT 24
Finished Jun 26 04:40:14 PM PDT 24
Peak memory 206612 kb
Host smart-7740bf0b-94c9-498a-89fa-121f004ccccb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012368259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
012368259
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3123509847
Short name T988
Test name
Test status
Simulation time 13260034 ps
CPU time 0.77 seconds
Started Jun 26 04:40:10 PM PDT 24
Finished Jun 26 04:40:13 PM PDT 24
Peak memory 203776 kb
Host smart-16866724-3065-4c13-a268-ecb354a210be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123509847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
123509847
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3216224219
Short name T1058
Test name
Test status
Simulation time 50974574 ps
CPU time 1.64 seconds
Started Jun 26 04:40:11 PM PDT 24
Finished Jun 26 04:40:15 PM PDT 24
Peak memory 214832 kb
Host smart-ec60fec6-4c47-4cca-bc01-bae1992f97a8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216224219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3216224219
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2450568181
Short name T1008
Test name
Test status
Simulation time 14009573 ps
CPU time 0.64 seconds
Started Jun 26 04:40:11 PM PDT 24
Finished Jun 26 04:40:14 PM PDT 24
Peak memory 203628 kb
Host smart-dd265505-6b11-4625-9e7e-85bd7d461df1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450568181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2450568181
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1816298245
Short name T985
Test name
Test status
Simulation time 30666382 ps
CPU time 1.85 seconds
Started Jun 26 04:40:20 PM PDT 24
Finished Jun 26 04:40:24 PM PDT 24
Peak memory 214748 kb
Host smart-21c513f6-aa84-47c2-8fff-021e37cfc3d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816298245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1816298245
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.173402937
Short name T102
Test name
Test status
Simulation time 355429948 ps
CPU time 4.64 seconds
Started Jun 26 04:40:10 PM PDT 24
Finished Jun 26 04:40:17 PM PDT 24
Peak memory 216064 kb
Host smart-66c4e643-b598-499e-bba6-50c409ea2061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173402937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.173402937
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3959826719
Short name T1040
Test name
Test status
Simulation time 14483529365 ps
CPU time 16.23 seconds
Started Jun 26 04:40:12 PM PDT 24
Finished Jun 26 04:40:30 PM PDT 24
Peak memory 215448 kb
Host smart-c83128b5-0c22-4c16-b4b2-863c686fd4b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959826719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3959826719
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1309896511
Short name T984
Test name
Test status
Simulation time 17197866 ps
CPU time 0.76 seconds
Started Jun 26 04:40:37 PM PDT 24
Finished Jun 26 04:40:45 PM PDT 24
Peak memory 203732 kb
Host smart-7a6ebd44-273e-4a80-994c-fb5478136d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309896511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1309896511
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2195089573
Short name T1063
Test name
Test status
Simulation time 32311424 ps
CPU time 0.82 seconds
Started Jun 26 04:40:33 PM PDT 24
Finished Jun 26 04:40:38 PM PDT 24
Peak memory 203548 kb
Host smart-16760b20-914f-4003-9818-6f7f41be2f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195089573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2195089573
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2945194087
Short name T1059
Test name
Test status
Simulation time 28438837 ps
CPU time 0.73 seconds
Started Jun 26 04:40:40 PM PDT 24
Finished Jun 26 04:40:48 PM PDT 24
Peak memory 203736 kb
Host smart-fa5761bb-4b09-4adf-950c-c51f54f14f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945194087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2945194087
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1111522961
Short name T1080
Test name
Test status
Simulation time 25756238 ps
CPU time 0.74 seconds
Started Jun 26 04:40:34 PM PDT 24
Finished Jun 26 04:40:40 PM PDT 24
Peak memory 203400 kb
Host smart-5ddf0334-3b8a-4f58-95a2-275317913132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111522961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1111522961
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3591676978
Short name T990
Test name
Test status
Simulation time 21216338 ps
CPU time 0.7 seconds
Started Jun 26 04:40:34 PM PDT 24
Finished Jun 26 04:40:39 PM PDT 24
Peak memory 203440 kb
Host smart-b04a0d89-a2c9-44fe-9b80-b772499401c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591676978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3591676978
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1491311385
Short name T964
Test name
Test status
Simulation time 68262104 ps
CPU time 0.76 seconds
Started Jun 26 04:40:36 PM PDT 24
Finished Jun 26 04:40:43 PM PDT 24
Peak memory 203420 kb
Host smart-b33c65f2-f961-4ec5-aee8-2d0db259ee27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491311385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1491311385
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.279243719
Short name T1051
Test name
Test status
Simulation time 12446196 ps
CPU time 0.74 seconds
Started Jun 26 04:40:34 PM PDT 24
Finished Jun 26 04:40:39 PM PDT 24
Peak memory 203420 kb
Host smart-de4a6088-2cc1-4215-9741-03976955806e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279243719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.279243719
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1939614033
Short name T1069
Test name
Test status
Simulation time 18904650 ps
CPU time 0.73 seconds
Started Jun 26 04:40:35 PM PDT 24
Finished Jun 26 04:40:41 PM PDT 24
Peak memory 203708 kb
Host smart-2041506d-6742-45dd-8542-fcd2da8a7f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939614033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1939614033
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.777411012
Short name T1036
Test name
Test status
Simulation time 34741579 ps
CPU time 0.73 seconds
Started Jun 26 04:40:32 PM PDT 24
Finished Jun 26 04:40:36 PM PDT 24
Peak memory 203716 kb
Host smart-5cf3660c-763a-4188-bb21-a4ec84d235cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777411012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.777411012
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2126441062
Short name T970
Test name
Test status
Simulation time 19604850 ps
CPU time 0.76 seconds
Started Jun 26 04:40:33 PM PDT 24
Finished Jun 26 04:40:37 PM PDT 24
Peak memory 203432 kb
Host smart-057d2186-c288-4da6-bbbc-2580efd8b9c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126441062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2126441062
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3533252573
Short name T1053
Test name
Test status
Simulation time 264914080 ps
CPU time 1.96 seconds
Started Jun 26 04:40:16 PM PDT 24
Finished Jun 26 04:40:20 PM PDT 24
Peak memory 214896 kb
Host smart-27a772a9-fa68-4c78-9181-169c541edc8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533252573 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3533252573
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.622401026
Short name T1061
Test name
Test status
Simulation time 766184279 ps
CPU time 2 seconds
Started Jun 26 04:40:09 PM PDT 24
Finished Jun 26 04:40:13 PM PDT 24
Peak memory 206688 kb
Host smart-8d33505d-a8f1-4b1c-9b50-739e7b5f1015
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622401026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.622401026
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3256023759
Short name T972
Test name
Test status
Simulation time 13922580 ps
CPU time 0.75 seconds
Started Jun 26 04:40:11 PM PDT 24
Finished Jun 26 04:40:14 PM PDT 24
Peak memory 203704 kb
Host smart-af3d7a7b-376f-4d08-a8b1-4759a1422ed2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256023759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
256023759
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3897149866
Short name T132
Test name
Test status
Simulation time 209878860 ps
CPU time 4.49 seconds
Started Jun 26 04:40:09 PM PDT 24
Finished Jun 26 04:40:16 PM PDT 24
Peak memory 214800 kb
Host smart-fba6d3a9-b021-4c67-885b-8a77265adbb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897149866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3897149866
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3536220755
Short name T1055
Test name
Test status
Simulation time 431920959 ps
CPU time 3.04 seconds
Started Jun 26 04:40:13 PM PDT 24
Finished Jun 26 04:40:17 PM PDT 24
Peak memory 215140 kb
Host smart-1064f41b-7341-46d2-b9fc-931056eeb831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536220755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
536220755
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.535081769
Short name T95
Test name
Test status
Simulation time 1100747267 ps
CPU time 13.15 seconds
Started Jun 26 04:40:09 PM PDT 24
Finished Jun 26 04:40:25 PM PDT 24
Peak memory 214812 kb
Host smart-b5f496b9-3bd2-48b2-b9a5-066b52040eab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535081769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.535081769
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1616445689
Short name T1045
Test name
Test status
Simulation time 326114356 ps
CPU time 4.2 seconds
Started Jun 26 04:40:18 PM PDT 24
Finished Jun 26 04:40:25 PM PDT 24
Peak memory 217208 kb
Host smart-ff43056c-b160-43b9-b859-d2f93c0a650d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616445689 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1616445689
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3521414670
Short name T114
Test name
Test status
Simulation time 1176295873 ps
CPU time 2.67 seconds
Started Jun 26 04:40:19 PM PDT 24
Finished Jun 26 04:40:24 PM PDT 24
Peak memory 214828 kb
Host smart-1f5b4cec-6ded-436c-a5cc-b805e87b5238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521414670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
521414670
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.468830600
Short name T969
Test name
Test status
Simulation time 24804056 ps
CPU time 0.74 seconds
Started Jun 26 04:40:17 PM PDT 24
Finished Jun 26 04:40:20 PM PDT 24
Peak memory 203436 kb
Host smart-54fd3d48-710e-4ef5-a930-6e1365ccb2ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468830600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.468830600
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1377352853
Short name T143
Test name
Test status
Simulation time 308722184 ps
CPU time 2.1 seconds
Started Jun 26 04:40:18 PM PDT 24
Finished Jun 26 04:40:22 PM PDT 24
Peak memory 206580 kb
Host smart-a85c58b0-677a-4d5f-be9e-3a7c22bc9dfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377352853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1377352853
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3863678976
Short name T1022
Test name
Test status
Simulation time 56822092 ps
CPU time 1.72 seconds
Started Jun 26 04:40:22 PM PDT 24
Finished Jun 26 04:40:27 PM PDT 24
Peak memory 214904 kb
Host smart-d2e38b4f-d1ad-4192-b43f-45b6747d5f77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863678976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
863678976
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1760406431
Short name T162
Test name
Test status
Simulation time 1223546445 ps
CPU time 19.53 seconds
Started Jun 26 04:40:18 PM PDT 24
Finished Jun 26 04:40:40 PM PDT 24
Peak memory 214904 kb
Host smart-11c1854f-858a-4b83-ac4c-754638b28868
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760406431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1760406431
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3247742952
Short name T1044
Test name
Test status
Simulation time 221141184 ps
CPU time 1.79 seconds
Started Jun 26 04:40:14 PM PDT 24
Finished Jun 26 04:40:17 PM PDT 24
Peak memory 215000 kb
Host smart-339ee621-e2fd-4d8f-b475-7056cc081108
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247742952 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3247742952
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2800696810
Short name T112
Test name
Test status
Simulation time 29822244 ps
CPU time 1.9 seconds
Started Jun 26 04:40:17 PM PDT 24
Finished Jun 26 04:40:22 PM PDT 24
Peak memory 214796 kb
Host smart-968addf9-f3a0-4617-b1a5-dbbc2ff3f0f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800696810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
800696810
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3326184827
Short name T1054
Test name
Test status
Simulation time 12151269 ps
CPU time 0.78 seconds
Started Jun 26 04:40:15 PM PDT 24
Finished Jun 26 04:40:18 PM PDT 24
Peak memory 203424 kb
Host smart-fd9fe83e-8d0a-4b0b-a801-62115ad79824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326184827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
326184827
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1280280745
Short name T130
Test name
Test status
Simulation time 389607462 ps
CPU time 1.78 seconds
Started Jun 26 04:40:14 PM PDT 24
Finished Jun 26 04:40:18 PM PDT 24
Peak memory 214868 kb
Host smart-09f71903-c86c-4905-84b6-b94da14fc718
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280280745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1280280745
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1402112532
Short name T164
Test name
Test status
Simulation time 211184539 ps
CPU time 6.46 seconds
Started Jun 26 04:40:15 PM PDT 24
Finished Jun 26 04:40:23 PM PDT 24
Peak memory 214816 kb
Host smart-5528f253-3efa-47df-931c-9b496714a053
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402112532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1402112532
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2369538799
Short name T974
Test name
Test status
Simulation time 170964200 ps
CPU time 3.1 seconds
Started Jun 26 04:40:17 PM PDT 24
Finished Jun 26 04:40:22 PM PDT 24
Peak memory 217248 kb
Host smart-aaa171db-271a-439c-a69d-dcb5069752f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369538799 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2369538799
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2874284088
Short name T1013
Test name
Test status
Simulation time 44629476 ps
CPU time 1.5 seconds
Started Jun 26 04:40:15 PM PDT 24
Finished Jun 26 04:40:19 PM PDT 24
Peak memory 206676 kb
Host smart-34da8bfa-22f0-4ab4-9ad8-ac5deec364cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874284088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
874284088
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1165797734
Short name T1031
Test name
Test status
Simulation time 25483163 ps
CPU time 0.72 seconds
Started Jun 26 04:40:16 PM PDT 24
Finished Jun 26 04:40:19 PM PDT 24
Peak memory 203400 kb
Host smart-ba03ec27-6cbe-4770-a16e-5ee87bb68786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165797734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
165797734
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4056278908
Short name T127
Test name
Test status
Simulation time 822582985 ps
CPU time 2.81 seconds
Started Jun 26 04:40:14 PM PDT 24
Finished Jun 26 04:40:19 PM PDT 24
Peak memory 215216 kb
Host smart-64575f12-c29b-4cca-bf42-76d388ace75c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056278908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.4056278908
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3006935100
Short name T1078
Test name
Test status
Simulation time 1137886504 ps
CPU time 4.42 seconds
Started Jun 26 04:40:15 PM PDT 24
Finished Jun 26 04:40:21 PM PDT 24
Peak memory 214992 kb
Host smart-c7273dc2-4042-43cc-ba13-30d23adfb669
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006935100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
006935100
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2349188693
Short name T978
Test name
Test status
Simulation time 2279540964 ps
CPU time 19.37 seconds
Started Jun 26 04:40:17 PM PDT 24
Finished Jun 26 04:40:39 PM PDT 24
Peak memory 214924 kb
Host smart-5195f0fa-f4a5-4eea-a80f-8be30e5e40c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349188693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2349188693
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2932630016
Short name T141
Test name
Test status
Simulation time 576331837 ps
CPU time 3.77 seconds
Started Jun 26 04:40:22 PM PDT 24
Finished Jun 26 04:40:30 PM PDT 24
Peak memory 217044 kb
Host smart-169ca986-a221-47f2-86f4-a0f5bce3668b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932630016 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2932630016
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3617648882
Short name T1065
Test name
Test status
Simulation time 468149784 ps
CPU time 2.62 seconds
Started Jun 26 04:40:16 PM PDT 24
Finished Jun 26 04:40:20 PM PDT 24
Peak memory 214876 kb
Host smart-ca4feabf-c54d-48bc-9ebc-aeefd2482cad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617648882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
617648882
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1403511693
Short name T973
Test name
Test status
Simulation time 24878870 ps
CPU time 0.7 seconds
Started Jun 26 04:40:21 PM PDT 24
Finished Jun 26 04:40:25 PM PDT 24
Peak memory 203368 kb
Host smart-a45bf817-6b3e-44fc-b7ef-86f7aa083a6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403511693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
403511693
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.27560524
Short name T129
Test name
Test status
Simulation time 68683253 ps
CPU time 1.88 seconds
Started Jun 26 04:40:15 PM PDT 24
Finished Jun 26 04:40:19 PM PDT 24
Peak memory 214952 kb
Host smart-f8f6caad-8919-49ff-8855-a32a8d90b040
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27560524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi
_device_same_csr_outstanding.27560524
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1235732549
Short name T1041
Test name
Test status
Simulation time 70311652 ps
CPU time 5.1 seconds
Started Jun 26 04:40:21 PM PDT 24
Finished Jun 26 04:40:29 PM PDT 24
Peak memory 214948 kb
Host smart-21540916-dd43-470a-a258-bd274d5f00c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235732549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
235732549
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2492586262
Short name T606
Test name
Test status
Simulation time 28639279 ps
CPU time 0.71 seconds
Started Jun 26 06:23:24 PM PDT 24
Finished Jun 26 06:23:26 PM PDT 24
Peak memory 205768 kb
Host smart-50893e3b-05f5-4017-8443-3c295edad3b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492586262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
492586262
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.45189573
Short name T167
Test name
Test status
Simulation time 455989086 ps
CPU time 7.09 seconds
Started Jun 26 06:23:19 PM PDT 24
Finished Jun 26 06:23:27 PM PDT 24
Peak memory 233648 kb
Host smart-8d7f87d1-f14e-47f5-9d70-ab88261b90d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45189573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.45189573
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1934363608
Short name T400
Test name
Test status
Simulation time 56681960 ps
CPU time 0.81 seconds
Started Jun 26 06:23:22 PM PDT 24
Finished Jun 26 06:23:24 PM PDT 24
Peak memory 206392 kb
Host smart-6f7c71a9-2521-49cf-be89-325d6353984c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934363608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1934363608
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4239055690
Short name T546
Test name
Test status
Simulation time 6000115397 ps
CPU time 80.45 seconds
Started Jun 26 06:23:17 PM PDT 24
Finished Jun 26 06:24:39 PM PDT 24
Peak memory 269252 kb
Host smart-f02f1604-b690-459d-87e3-3ab990c418ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239055690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4239055690
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.706702639
Short name T884
Test name
Test status
Simulation time 37689579658 ps
CPU time 27.14 seconds
Started Jun 26 06:23:20 PM PDT 24
Finished Jun 26 06:23:49 PM PDT 24
Peak memory 225540 kb
Host smart-94b777b5-f9cf-4b92-8fd9-7cd1fa6f5f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706702639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.706702639
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2620199661
Short name T485
Test name
Test status
Simulation time 397889536 ps
CPU time 3.24 seconds
Started Jun 26 06:23:24 PM PDT 24
Finished Jun 26 06:23:27 PM PDT 24
Peak memory 225420 kb
Host smart-e998042d-2747-416d-bd0f-2b90c8bda140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620199661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2620199661
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3597856745
Short name T768
Test name
Test status
Simulation time 117462137 ps
CPU time 2.47 seconds
Started Jun 26 06:23:21 PM PDT 24
Finished Jun 26 06:23:24 PM PDT 24
Peak memory 233324 kb
Host smart-16415336-180f-444c-b4ca-a7adc4ad212c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597856745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3597856745
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3666953934
Short name T926
Test name
Test status
Simulation time 5595627608 ps
CPU time 7.95 seconds
Started Jun 26 06:23:20 PM PDT 24
Finished Jun 26 06:23:29 PM PDT 24
Peak memory 233716 kb
Host smart-07ce0922-ae15-47eb-b0e4-6505c3e7bb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666953934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3666953934
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1184819678
Short name T550
Test name
Test status
Simulation time 3226605630 ps
CPU time 7.27 seconds
Started Jun 26 06:23:23 PM PDT 24
Finished Jun 26 06:23:31 PM PDT 24
Peak memory 241416 kb
Host smart-3f7fe1e9-0efd-4c6e-a09a-72142237d081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184819678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1184819678
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3699972559
Short name T122
Test name
Test status
Simulation time 2534548288 ps
CPU time 6.56 seconds
Started Jun 26 06:23:24 PM PDT 24
Finished Jun 26 06:23:31 PM PDT 24
Peak memory 225556 kb
Host smart-4cf9c1aa-2aa5-4609-b7a8-3f9e0b23767c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699972559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3699972559
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2553003471
Short name T376
Test name
Test status
Simulation time 1217194967 ps
CPU time 13.9 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:43 PM PDT 24
Peak memory 221540 kb
Host smart-e61c5ff4-5b38-4c31-b4c2-0bdda652a5ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2553003471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2553003471
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2288132345
Short name T71
Test name
Test status
Simulation time 83621018 ps
CPU time 1.22 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:30 PM PDT 24
Peak memory 236568 kb
Host smart-74688de7-0bfa-4f88-b200-4475d206389e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288132345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2288132345
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1258479607
Short name T147
Test name
Test status
Simulation time 35578082328 ps
CPU time 274.99 seconds
Started Jun 26 06:23:19 PM PDT 24
Finished Jun 26 06:27:55 PM PDT 24
Peak memory 252352 kb
Host smart-a41a3289-3c8f-4f5a-8f0b-569ebe10f4df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258479607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1258479607
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.139228472
Short name T560
Test name
Test status
Simulation time 1741387965 ps
CPU time 3.48 seconds
Started Jun 26 06:23:19 PM PDT 24
Finished Jun 26 06:23:23 PM PDT 24
Peak memory 217244 kb
Host smart-e05e7ae6-0869-40a1-b8dc-2a0a1cb27ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139228472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.139228472
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2989980283
Short name T716
Test name
Test status
Simulation time 16050977 ps
CPU time 0.81 seconds
Started Jun 26 06:23:21 PM PDT 24
Finished Jun 26 06:23:23 PM PDT 24
Peak memory 207744 kb
Host smart-dcc3242f-e6ac-4b9e-8092-a6653e168016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989980283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2989980283
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3249803001
Short name T794
Test name
Test status
Simulation time 40927875 ps
CPU time 0.89 seconds
Started Jun 26 06:23:18 PM PDT 24
Finished Jun 26 06:23:20 PM PDT 24
Peak memory 206752 kb
Host smart-f26f38fc-b0d2-420a-8f98-3b7806483b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249803001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3249803001
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3034161130
Short name T377
Test name
Test status
Simulation time 512497980 ps
CPU time 4.36 seconds
Started Jun 26 06:23:20 PM PDT 24
Finished Jun 26 06:23:25 PM PDT 24
Peak memory 233596 kb
Host smart-c0c93c44-f456-48fd-8b15-6d1bedfe9ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034161130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3034161130
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2098534773
Short name T508
Test name
Test status
Simulation time 128377376 ps
CPU time 0.77 seconds
Started Jun 26 06:23:26 PM PDT 24
Finished Jun 26 06:23:29 PM PDT 24
Peak memory 206320 kb
Host smart-56d590fe-2fa8-4915-b92d-5db1bfbbbbce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098534773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
098534773
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.291534542
Short name T804
Test name
Test status
Simulation time 228832308 ps
CPU time 4.48 seconds
Started Jun 26 06:23:25 PM PDT 24
Finished Jun 26 06:23:30 PM PDT 24
Peak memory 233640 kb
Host smart-44a1ec6a-daa9-4601-82db-e7456d3325ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291534542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.291534542
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1272106369
Short name T284
Test name
Test status
Simulation time 16913861 ps
CPU time 0.79 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:30 PM PDT 24
Peak memory 207752 kb
Host smart-6b28fff4-9af3-4387-8b56-52832fc3c5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272106369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1272106369
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3348592090
Short name T309
Test name
Test status
Simulation time 11394909457 ps
CPU time 87.63 seconds
Started Jun 26 06:23:25 PM PDT 24
Finished Jun 26 06:24:54 PM PDT 24
Peak memory 257784 kb
Host smart-fb1fe48c-bdbd-4eee-80bc-50365fa92b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348592090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3348592090
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.526654567
Short name T203
Test name
Test status
Simulation time 4152097469 ps
CPU time 103.34 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:25:13 PM PDT 24
Peak memory 250120 kb
Host smart-ce13aba9-e349-4861-b9dd-0edc53a1ab88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526654567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.526654567
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2342421779
Short name T300
Test name
Test status
Simulation time 3095821049 ps
CPU time 54.97 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:24:24 PM PDT 24
Peak memory 250216 kb
Host smart-2239a0f4-2039-48f0-a60c-8797ba9ba94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342421779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2342421779
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2444183678
Short name T906
Test name
Test status
Simulation time 386279733 ps
CPU time 7.38 seconds
Started Jun 26 06:23:26 PM PDT 24
Finished Jun 26 06:23:36 PM PDT 24
Peak memory 233664 kb
Host smart-8bfb7d6f-b61b-4ab0-a3c5-1b416775dd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444183678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2444183678
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3802281784
Short name T527
Test name
Test status
Simulation time 41101913 ps
CPU time 2.41 seconds
Started Jun 26 06:23:28 PM PDT 24
Finished Jun 26 06:23:32 PM PDT 24
Peak memory 225452 kb
Host smart-c7225826-e806-4a42-8e9f-53b6d64cf1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802281784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3802281784
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3663920268
Short name T242
Test name
Test status
Simulation time 764278117 ps
CPU time 3.25 seconds
Started Jun 26 06:23:26 PM PDT 24
Finished Jun 26 06:23:31 PM PDT 24
Peak memory 225392 kb
Host smart-478ab42f-ebca-400d-98eb-ec15d2bc1b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663920268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3663920268
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1608171788
Short name T543
Test name
Test status
Simulation time 12955625899 ps
CPU time 8.38 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:38 PM PDT 24
Peak memory 233728 kb
Host smart-f827c6b7-a467-48d1-87ed-e75585881d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608171788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1608171788
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.507743664
Short name T383
Test name
Test status
Simulation time 3349161395 ps
CPU time 11.1 seconds
Started Jun 26 06:23:28 PM PDT 24
Finished Jun 26 06:23:42 PM PDT 24
Peak memory 223132 kb
Host smart-99e4a81a-a78b-47ae-8cba-afbff5184200
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=507743664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.507743664
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.56590091
Short name T568
Test name
Test status
Simulation time 55272248910 ps
CPU time 218.54 seconds
Started Jun 26 06:23:26 PM PDT 24
Finished Jun 26 06:27:07 PM PDT 24
Peak memory 283360 kb
Host smart-99a15c60-8782-463f-afa9-b8893363a63d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56590091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_
all.56590091
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.633380146
Short name T7
Test name
Test status
Simulation time 7781967140 ps
CPU time 14.97 seconds
Started Jun 26 06:23:28 PM PDT 24
Finished Jun 26 06:23:45 PM PDT 24
Peak memory 220172 kb
Host smart-8a716e23-fc56-45e8-a3ef-3fecfb59eb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633380146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.633380146
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2149473564
Short name T38
Test name
Test status
Simulation time 687088204 ps
CPU time 1.36 seconds
Started Jun 26 06:23:25 PM PDT 24
Finished Jun 26 06:23:28 PM PDT 24
Peak memory 208684 kb
Host smart-b2760e50-04ac-487e-b8df-fad2fd6c0777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149473564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2149473564
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2134535602
Short name T312
Test name
Test status
Simulation time 741959369 ps
CPU time 1.87 seconds
Started Jun 26 06:23:25 PM PDT 24
Finished Jun 26 06:23:28 PM PDT 24
Peak memory 217316 kb
Host smart-6f4c3d7f-0475-4af7-9b72-8d955a61956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134535602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2134535602
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2050247002
Short name T306
Test name
Test status
Simulation time 150302252 ps
CPU time 1.11 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:30 PM PDT 24
Peak memory 207768 kb
Host smart-adaaa123-e703-4ef9-98b1-fb69028a1d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050247002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2050247002
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.934032299
Short name T591
Test name
Test status
Simulation time 1256768937 ps
CPU time 6.8 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:36 PM PDT 24
Peak memory 241724 kb
Host smart-5f58f8ec-e669-4526-be54-6f2a31d62058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934032299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.934032299
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1619302134
Short name T825
Test name
Test status
Simulation time 123525644 ps
CPU time 0.71 seconds
Started Jun 26 06:23:50 PM PDT 24
Finished Jun 26 06:23:55 PM PDT 24
Peak memory 206588 kb
Host smart-4f905217-998f-4560-a2f5-e64e4f5d7332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619302134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1619302134
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1594289044
Short name T689
Test name
Test status
Simulation time 1241984155 ps
CPU time 4.57 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:23:56 PM PDT 24
Peak memory 225456 kb
Host smart-541b4642-6391-4090-b433-823391b0e6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594289044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1594289044
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.307539855
Short name T664
Test name
Test status
Simulation time 52019776 ps
CPU time 0.79 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:23:53 PM PDT 24
Peak memory 207436 kb
Host smart-ae0501b6-8d7b-4a78-a165-b27d78cc3eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307539855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.307539855
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3122051112
Short name T460
Test name
Test status
Simulation time 23576556491 ps
CPU time 168.32 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:26:41 PM PDT 24
Peak memory 251140 kb
Host smart-34c512f0-0124-4394-a318-2a11577bff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122051112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3122051112
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2740766375
Short name T889
Test name
Test status
Simulation time 100565160224 ps
CPU time 106.41 seconds
Started Jun 26 06:23:50 PM PDT 24
Finished Jun 26 06:25:40 PM PDT 24
Peak memory 241936 kb
Host smart-594ca82f-c275-419c-89c6-f5b835fb3f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740766375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2740766375
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2908690918
Short name T226
Test name
Test status
Simulation time 20535530170 ps
CPU time 85.17 seconds
Started Jun 26 06:23:52 PM PDT 24
Finished Jun 26 06:25:20 PM PDT 24
Peak memory 252964 kb
Host smart-2716a7d9-7387-4ce1-bdab-dda9dc121908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908690918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2908690918
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2042439821
Short name T738
Test name
Test status
Simulation time 2408675273 ps
CPU time 8.97 seconds
Started Jun 26 06:23:52 PM PDT 24
Finished Jun 26 06:24:04 PM PDT 24
Peak memory 225444 kb
Host smart-9d78c756-1dd9-481c-ba94-82d6a76bb2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042439821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2042439821
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1006520129
Short name T744
Test name
Test status
Simulation time 2919717751 ps
CPU time 24.02 seconds
Started Jun 26 06:23:51 PM PDT 24
Finished Jun 26 06:24:18 PM PDT 24
Peak memory 225548 kb
Host smart-87c7918f-54b7-4fa8-b700-c086b3a70d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006520129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1006520129
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4235072032
Short name T938
Test name
Test status
Simulation time 1588829490 ps
CPU time 7.41 seconds
Started Jun 26 06:23:51 PM PDT 24
Finished Jun 26 06:24:02 PM PDT 24
Peak memory 233600 kb
Host smart-d3cbc420-4e92-46f3-8112-3109abc69354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235072032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4235072032
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3164737038
Short name T697
Test name
Test status
Simulation time 1589543690 ps
CPU time 8.09 seconds
Started Jun 26 06:23:53 PM PDT 24
Finished Jun 26 06:24:04 PM PDT 24
Peak memory 233572 kb
Host smart-6f5c5a36-d1b3-4e87-a0fe-790296784b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164737038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3164737038
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.589968748
Short name T675
Test name
Test status
Simulation time 7097397293 ps
CPU time 21.76 seconds
Started Jun 26 06:23:48 PM PDT 24
Finished Jun 26 06:24:13 PM PDT 24
Peak memory 233692 kb
Host smart-a066009b-bce4-4cfc-b359-3d9f42c53fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589968748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.589968748
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.208812128
Short name T838
Test name
Test status
Simulation time 4343340492 ps
CPU time 13.04 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:24:06 PM PDT 24
Peak memory 224240 kb
Host smart-363731b6-9724-4b7b-98fa-289bf8d27701
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=208812128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.208812128
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.684230997
Short name T209
Test name
Test status
Simulation time 59851578328 ps
CPU time 230.6 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:27:44 PM PDT 24
Peak memory 271704 kb
Host smart-c03bbcae-147c-48fc-8428-ec9632eecf97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684230997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.684230997
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1884207329
Short name T436
Test name
Test status
Simulation time 13859146598 ps
CPU time 23.41 seconds
Started Jun 26 06:23:54 PM PDT 24
Finished Jun 26 06:24:20 PM PDT 24
Peak memory 217324 kb
Host smart-a9dcdecd-3394-49cd-9807-5958c6935d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884207329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1884207329
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.4015345303
Short name T422
Test name
Test status
Simulation time 5796986677 ps
CPU time 4.52 seconds
Started Jun 26 06:23:50 PM PDT 24
Finished Jun 26 06:23:58 PM PDT 24
Peak memory 218268 kb
Host smart-467001c2-bc5d-4a4e-acc3-90a06724d19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015345303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4015345303
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1585180672
Short name T720
Test name
Test status
Simulation time 425263560 ps
CPU time 4.79 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:23:57 PM PDT 24
Peak memory 217120 kb
Host smart-e192f460-db61-43f5-bca6-4b0166a0476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585180672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1585180672
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2583338286
Short name T797
Test name
Test status
Simulation time 40229246 ps
CPU time 0.87 seconds
Started Jun 26 06:23:54 PM PDT 24
Finished Jun 26 06:23:57 PM PDT 24
Peak memory 206628 kb
Host smart-ca034dc8-cb1d-48b9-bc3f-4df72e672a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583338286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2583338286
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.4177227689
Short name T79
Test name
Test status
Simulation time 326598466 ps
CPU time 3.56 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:23:56 PM PDT 24
Peak memory 225300 kb
Host smart-2cbec257-64c6-4e5c-b5a8-149e9beff33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177227689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.4177227689
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1603562086
Short name T623
Test name
Test status
Simulation time 51731135 ps
CPU time 0.72 seconds
Started Jun 26 06:23:51 PM PDT 24
Finished Jun 26 06:23:56 PM PDT 24
Peak memory 205800 kb
Host smart-88a9b3d1-e0c5-4e16-8d53-4b1f21c228d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603562086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1603562086
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.187782690
Short name T243
Test name
Test status
Simulation time 2545322453 ps
CPU time 4.81 seconds
Started Jun 26 06:23:50 PM PDT 24
Finished Jun 26 06:23:59 PM PDT 24
Peak memory 233692 kb
Host smart-368b5498-1c18-4b69-9825-f1f4baa5f83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187782690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.187782690
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4161799020
Short name T674
Test name
Test status
Simulation time 44675563 ps
CPU time 0.8 seconds
Started Jun 26 06:23:48 PM PDT 24
Finished Jun 26 06:23:52 PM PDT 24
Peak memory 207476 kb
Host smart-6ae6f3ee-51c8-4d0d-bf87-57346029d2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161799020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4161799020
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2474866875
Short name T194
Test name
Test status
Simulation time 55589021040 ps
CPU time 210.32 seconds
Started Jun 26 06:23:50 PM PDT 24
Finished Jun 26 06:27:25 PM PDT 24
Peak memory 257884 kb
Host smart-bbef9ee6-9bbc-4f48-868f-2fe75c27cb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474866875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2474866875
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3212330669
Short name T254
Test name
Test status
Simulation time 8302463888 ps
CPU time 103.04 seconds
Started Jun 26 06:23:50 PM PDT 24
Finished Jun 26 06:25:36 PM PDT 24
Peak memory 250184 kb
Host smart-d309724f-736d-4b01-9c8e-4bec7a3a8a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212330669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3212330669
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.864057804
Short name T258
Test name
Test status
Simulation time 159721020022 ps
CPU time 364.71 seconds
Started Jun 26 06:23:52 PM PDT 24
Finished Jun 26 06:30:00 PM PDT 24
Peak memory 258360 kb
Host smart-9d643154-9bff-4a16-b1d3-62c59e3d434d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864057804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.864057804
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.33007634
Short name T292
Test name
Test status
Simulation time 22329878780 ps
CPU time 41.07 seconds
Started Jun 26 06:23:48 PM PDT 24
Finished Jun 26 06:24:32 PM PDT 24
Peak memory 233796 kb
Host smart-a114dfe6-3995-433c-b43b-b27ecb5876fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33007634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.33007634
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4232869637
Short name T696
Test name
Test status
Simulation time 1213754602 ps
CPU time 5.58 seconds
Started Jun 26 06:23:51 PM PDT 24
Finished Jun 26 06:24:01 PM PDT 24
Peak memory 233828 kb
Host smart-b482aad2-7478-4e16-a084-82ca24a35352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232869637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4232869637
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2929113889
Short name T576
Test name
Test status
Simulation time 997112250 ps
CPU time 12.39 seconds
Started Jun 26 06:23:51 PM PDT 24
Finished Jun 26 06:24:07 PM PDT 24
Peak memory 234508 kb
Host smart-37a9234f-c8a6-4370-88b1-14692df5521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929113889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2929113889
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1466843585
Short name T818
Test name
Test status
Simulation time 2566037312 ps
CPU time 3.92 seconds
Started Jun 26 06:23:50 PM PDT 24
Finished Jun 26 06:23:58 PM PDT 24
Peak memory 233712 kb
Host smart-0dd08543-317a-408c-9ebd-1df226e3cd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466843585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1466843585
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1007441552
Short name T723
Test name
Test status
Simulation time 382654606 ps
CPU time 3.12 seconds
Started Jun 26 06:23:48 PM PDT 24
Finished Jun 26 06:23:54 PM PDT 24
Peak memory 225444 kb
Host smart-7c226667-622c-434f-b5d7-8d0e92cc37fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007441552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1007441552
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3236868625
Short name T736
Test name
Test status
Simulation time 1458504126 ps
CPU time 4.06 seconds
Started Jun 26 06:23:53 PM PDT 24
Finished Jun 26 06:24:00 PM PDT 24
Peak memory 219616 kb
Host smart-4d0e7f85-49f4-4c13-acfd-8cd82cd98e89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3236868625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3236868625
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1095673890
Short name T187
Test name
Test status
Simulation time 27125814919 ps
CPU time 139.21 seconds
Started Jun 26 06:23:52 PM PDT 24
Finished Jun 26 06:26:15 PM PDT 24
Peak memory 258360 kb
Host smart-8fab504f-550b-418b-b22c-4884d3b87631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095673890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1095673890
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2670798786
Short name T442
Test name
Test status
Simulation time 12549790049 ps
CPU time 35.4 seconds
Started Jun 26 06:23:51 PM PDT 24
Finished Jun 26 06:24:30 PM PDT 24
Peak memory 217352 kb
Host smart-0c1de02b-ee34-4650-8214-3175ec213ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670798786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2670798786
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.207610662
Short name T72
Test name
Test status
Simulation time 116754740 ps
CPU time 1.29 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:23:53 PM PDT 24
Peak memory 208620 kb
Host smart-5f267618-5dbd-49f8-b222-b10e11af2ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207610662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.207610662
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.886983014
Short name T695
Test name
Test status
Simulation time 69172571 ps
CPU time 0.89 seconds
Started Jun 26 06:23:53 PM PDT 24
Finished Jun 26 06:23:57 PM PDT 24
Peak memory 207792 kb
Host smart-ce2348e4-061f-46c5-84dc-ef44385bfcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886983014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.886983014
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1320182680
Short name T565
Test name
Test status
Simulation time 72229369 ps
CPU time 0.87 seconds
Started Jun 26 06:23:48 PM PDT 24
Finished Jun 26 06:23:52 PM PDT 24
Peak memory 206736 kb
Host smart-eae8dbcd-2763-48c6-a535-e4590ce4f87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320182680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1320182680
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.463294862
Short name T322
Test name
Test status
Simulation time 289314951 ps
CPU time 3.85 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:23:56 PM PDT 24
Peak memory 233592 kb
Host smart-884d1182-9470-472d-8835-9b935cd1a4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463294862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.463294862
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2622657327
Short name T427
Test name
Test status
Simulation time 44482477 ps
CPU time 0.74 seconds
Started Jun 26 06:24:02 PM PDT 24
Finished Jun 26 06:24:04 PM PDT 24
Peak memory 206696 kb
Host smart-63d765bc-a07e-4e20-b470-1f3adc924493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622657327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2622657327
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2060986673
Short name T777
Test name
Test status
Simulation time 728551768 ps
CPU time 6.96 seconds
Started Jun 26 06:23:50 PM PDT 24
Finished Jun 26 06:24:01 PM PDT 24
Peak memory 225392 kb
Host smart-813456a9-365b-476b-bd80-3fb2f491d6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060986673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2060986673
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2053735544
Short name T299
Test name
Test status
Simulation time 57114845 ps
CPU time 0.77 seconds
Started Jun 26 06:23:51 PM PDT 24
Finished Jun 26 06:23:55 PM PDT 24
Peak memory 207280 kb
Host smart-24d12254-f35e-4eef-9f31-128dde272629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053735544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2053735544
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2347646040
Short name T959
Test name
Test status
Simulation time 14408012328 ps
CPU time 60.14 seconds
Started Jun 26 06:23:50 PM PDT 24
Finished Jun 26 06:24:54 PM PDT 24
Peak memory 239316 kb
Host smart-13bee75c-7a1f-4061-ac97-18d6c1331bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347646040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2347646040
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.4108780595
Short name T186
Test name
Test status
Simulation time 23191640027 ps
CPU time 72.37 seconds
Started Jun 26 06:23:50 PM PDT 24
Finished Jun 26 06:25:06 PM PDT 24
Peak memory 250196 kb
Host smart-6c9bc098-206f-4de6-820d-7cb1b58535e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108780595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4108780595
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.260479419
Short name T462
Test name
Test status
Simulation time 2083611311 ps
CPU time 23.34 seconds
Started Jun 26 06:24:02 PM PDT 24
Finished Jun 26 06:24:27 PM PDT 24
Peak memory 225400 kb
Host smart-6091f7d9-7fb2-479b-8527-010757a125a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260479419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.260479419
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2893499627
Short name T721
Test name
Test status
Simulation time 439449509 ps
CPU time 8.08 seconds
Started Jun 26 06:23:51 PM PDT 24
Finished Jun 26 06:24:03 PM PDT 24
Peak memory 225416 kb
Host smart-b13c62db-a85a-45af-9980-8ee56c6baf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893499627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2893499627
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3460443655
Short name T776
Test name
Test status
Simulation time 339116733 ps
CPU time 4.84 seconds
Started Jun 26 06:23:50 PM PDT 24
Finished Jun 26 06:23:58 PM PDT 24
Peak memory 233660 kb
Host smart-2a6a75f3-b8a3-4838-b473-910d33e57a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460443655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3460443655
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1747153999
Short name T349
Test name
Test status
Simulation time 185331152 ps
CPU time 6.54 seconds
Started Jun 26 06:23:54 PM PDT 24
Finished Jun 26 06:24:03 PM PDT 24
Peak memory 225452 kb
Host smart-1192984a-5343-4a03-9077-97fc89cd2b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747153999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1747153999
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2524888359
Short name T464
Test name
Test status
Simulation time 8499469881 ps
CPU time 7.71 seconds
Started Jun 26 06:23:50 PM PDT 24
Finished Jun 26 06:24:01 PM PDT 24
Peak memory 233716 kb
Host smart-87e780f4-d7e0-42e2-baf8-33e1dfe51ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524888359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2524888359
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.9521373
Short name T500
Test name
Test status
Simulation time 4859362364 ps
CPU time 4.79 seconds
Started Jun 26 06:23:53 PM PDT 24
Finished Jun 26 06:24:01 PM PDT 24
Peak memory 225532 kb
Host smart-05e6e27e-89ab-4951-a348-3f5faffc165f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9521373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.9521373
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4244692879
Short name T806
Test name
Test status
Simulation time 2274471476 ps
CPU time 9.48 seconds
Started Jun 26 06:23:50 PM PDT 24
Finished Jun 26 06:24:03 PM PDT 24
Peak memory 224056 kb
Host smart-5437a7fd-0916-4166-98ec-0a51dd02d90e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4244692879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4244692879
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3033167256
Short name T388
Test name
Test status
Simulation time 76068854029 ps
CPU time 203.74 seconds
Started Jun 26 06:24:01 PM PDT 24
Finished Jun 26 06:27:26 PM PDT 24
Peak memory 258092 kb
Host smart-d42e5f7d-2b5d-47f5-995b-d9cfab4a37c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033167256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3033167256
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3722806958
Short name T326
Test name
Test status
Simulation time 2200075981 ps
CPU time 5.46 seconds
Started Jun 26 06:23:53 PM PDT 24
Finished Jun 26 06:24:01 PM PDT 24
Peak memory 217160 kb
Host smart-d942cce9-49e6-4a0c-b61d-bec04c1f406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722806958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3722806958
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.727142284
Short name T596
Test name
Test status
Simulation time 1206083186 ps
CPU time 2.79 seconds
Started Jun 26 06:23:53 PM PDT 24
Finished Jun 26 06:23:59 PM PDT 24
Peak memory 217140 kb
Host smart-91a354f7-2254-4d97-b1b8-7219cb08c5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727142284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.727142284
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1272771181
Short name T342
Test name
Test status
Simulation time 114223145 ps
CPU time 1 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:23:54 PM PDT 24
Peak memory 208316 kb
Host smart-ee9f430a-beb1-404f-9ff9-e081def3ff24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272771181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1272771181
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.431877550
Short name T440
Test name
Test status
Simulation time 221562103 ps
CPU time 0.86 seconds
Started Jun 26 06:23:48 PM PDT 24
Finished Jun 26 06:23:52 PM PDT 24
Peak memory 206708 kb
Host smart-c768bf34-8427-498e-a936-6fd616e545b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431877550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.431877550
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2349266961
Short name T201
Test name
Test status
Simulation time 4732341678 ps
CPU time 7.93 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:24:01 PM PDT 24
Peak memory 233772 kb
Host smart-c798661b-2c52-4c71-b31d-cd1f938b64c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349266961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2349266961
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3898263834
Short name T764
Test name
Test status
Simulation time 27899109 ps
CPU time 0.75 seconds
Started Jun 26 06:24:01 PM PDT 24
Finished Jun 26 06:24:03 PM PDT 24
Peak memory 205784 kb
Host smart-ff8b10f8-d6fd-4284-b430-435099186493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898263834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3898263834
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1970406220
Short name T535
Test name
Test status
Simulation time 9671851650 ps
CPU time 13.72 seconds
Started Jun 26 06:23:59 PM PDT 24
Finished Jun 26 06:24:14 PM PDT 24
Peak memory 233748 kb
Host smart-63674e98-ccc9-4329-8cf4-687b4151cb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970406220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1970406220
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3182962388
Short name T693
Test name
Test status
Simulation time 114481938 ps
CPU time 0.82 seconds
Started Jun 26 06:23:59 PM PDT 24
Finished Jun 26 06:24:01 PM PDT 24
Peak memory 206320 kb
Host smart-86bcc5ad-b114-418a-a886-7307c7e3397e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182962388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3182962388
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1135250839
Short name T532
Test name
Test status
Simulation time 42433999895 ps
CPU time 308.83 seconds
Started Jun 26 06:24:00 PM PDT 24
Finished Jun 26 06:29:11 PM PDT 24
Peak memory 265296 kb
Host smart-2bfe65de-a4a8-4490-bf7c-895ffb33bf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135250839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1135250839
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.4243554082
Short name T899
Test name
Test status
Simulation time 924509563 ps
CPU time 7.03 seconds
Started Jun 26 06:23:59 PM PDT 24
Finished Jun 26 06:24:08 PM PDT 24
Peak memory 218536 kb
Host smart-54d4916e-c0c2-4582-a11f-08c3e238dc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243554082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4243554082
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1282378379
Short name T725
Test name
Test status
Simulation time 32903961617 ps
CPU time 73.91 seconds
Started Jun 26 06:24:00 PM PDT 24
Finished Jun 26 06:25:15 PM PDT 24
Peak memory 250144 kb
Host smart-b25df4c7-9e10-4609-9da5-96745bdf23dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282378379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1282378379
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2351725124
Short name T709
Test name
Test status
Simulation time 52433547 ps
CPU time 3.46 seconds
Started Jun 26 06:24:03 PM PDT 24
Finished Jun 26 06:24:08 PM PDT 24
Peak memory 233600 kb
Host smart-32ff8cc8-e333-4104-9a77-6e6fc8c4a8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351725124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2351725124
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4286994442
Short name T796
Test name
Test status
Simulation time 448335291 ps
CPU time 2.63 seconds
Started Jun 26 06:24:03 PM PDT 24
Finished Jun 26 06:24:07 PM PDT 24
Peak memory 225096 kb
Host smart-92d19514-eadf-4be4-bf69-36ac243dbaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286994442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4286994442
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2753118942
Short name T861
Test name
Test status
Simulation time 14015369836 ps
CPU time 10.38 seconds
Started Jun 26 06:24:01 PM PDT 24
Finished Jun 26 06:24:12 PM PDT 24
Peak memory 235848 kb
Host smart-9b3f6356-ae64-4036-ba4a-69f03004f54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753118942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2753118942
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2104470725
Short name T297
Test name
Test status
Simulation time 264908571 ps
CPU time 3.09 seconds
Started Jun 26 06:24:00 PM PDT 24
Finished Jun 26 06:24:05 PM PDT 24
Peak memory 233580 kb
Host smart-a0e588fc-2750-4b20-b194-77319b7b7aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104470725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2104470725
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1589326835
Short name T767
Test name
Test status
Simulation time 8152895766 ps
CPU time 8.77 seconds
Started Jun 26 06:23:59 PM PDT 24
Finished Jun 26 06:24:09 PM PDT 24
Peak memory 233772 kb
Host smart-19326cf2-c43c-4335-afb8-be8ae45f2eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589326835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1589326835
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1893313796
Short name T921
Test name
Test status
Simulation time 2698436761 ps
CPU time 7.17 seconds
Started Jun 26 06:24:01 PM PDT 24
Finished Jun 26 06:24:10 PM PDT 24
Peak memory 224280 kb
Host smart-4969bf0e-2031-4d85-8943-76faa66541f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1893313796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1893313796
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3625233100
Short name T567
Test name
Test status
Simulation time 16058636505 ps
CPU time 99.77 seconds
Started Jun 26 06:24:00 PM PDT 24
Finished Jun 26 06:25:42 PM PDT 24
Peak memory 256000 kb
Host smart-0895fa87-33da-450b-9305-b1f1d755a9da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625233100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3625233100
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4069179773
Short name T420
Test name
Test status
Simulation time 718870930 ps
CPU time 6.47 seconds
Started Jun 26 06:24:03 PM PDT 24
Finished Jun 26 06:24:11 PM PDT 24
Peak memory 217060 kb
Host smart-d803b2d8-85e6-4618-b35d-564e97769c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069179773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4069179773
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1804334765
Short name T407
Test name
Test status
Simulation time 853852073 ps
CPU time 5.38 seconds
Started Jun 26 06:24:01 PM PDT 24
Finished Jun 26 06:24:08 PM PDT 24
Peak memory 217080 kb
Host smart-a3b8cb02-0d00-4a1e-9086-7d94c009d3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804334765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1804334765
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3186563078
Short name T445
Test name
Test status
Simulation time 60579932 ps
CPU time 1.34 seconds
Started Jun 26 06:24:01 PM PDT 24
Finished Jun 26 06:24:04 PM PDT 24
Peak memory 217124 kb
Host smart-93e783df-eb22-4a8c-b0ac-5d0181498574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186563078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3186563078
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3450150790
Short name T501
Test name
Test status
Simulation time 39318150 ps
CPU time 0.72 seconds
Started Jun 26 06:23:58 PM PDT 24
Finished Jun 26 06:24:00 PM PDT 24
Peak memory 206472 kb
Host smart-ac3c5bf0-aea4-423a-ba7b-82a0da054c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450150790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3450150790
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3559892048
Short name T858
Test name
Test status
Simulation time 851967735 ps
CPU time 4.28 seconds
Started Jun 26 06:24:00 PM PDT 24
Finished Jun 26 06:24:05 PM PDT 24
Peak memory 233684 kb
Host smart-4c38e436-2b7d-4caa-a5c0-04c9cfb0ce67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559892048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3559892048
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1985564692
Short name T888
Test name
Test status
Simulation time 13722458 ps
CPU time 0.76 seconds
Started Jun 26 06:24:03 PM PDT 24
Finished Jun 26 06:24:06 PM PDT 24
Peak memory 206236 kb
Host smart-034846bc-187c-4ca5-86ce-1d8351594097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985564692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1985564692
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3851696296
Short name T240
Test name
Test status
Simulation time 276606828 ps
CPU time 5.43 seconds
Started Jun 26 06:23:59 PM PDT 24
Finished Jun 26 06:24:05 PM PDT 24
Peak memory 233644 kb
Host smart-c501bf3b-554c-4ad0-8669-c0c346b623c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851696296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3851696296
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3979135551
Short name T14
Test name
Test status
Simulation time 18198439 ps
CPU time 0.82 seconds
Started Jun 26 06:24:04 PM PDT 24
Finished Jun 26 06:24:06 PM PDT 24
Peak memory 207388 kb
Host smart-8a8bcaaa-aaf4-4cda-aa44-f7c6c182f8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979135551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3979135551
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1097136889
Short name T910
Test name
Test status
Simulation time 3458237327 ps
CPU time 15.42 seconds
Started Jun 26 06:24:04 PM PDT 24
Finished Jun 26 06:24:21 PM PDT 24
Peak memory 225472 kb
Host smart-3f261796-dcfd-4133-bfc5-b9abd051b8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097136889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1097136889
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2986949135
Short name T338
Test name
Test status
Simulation time 751435777 ps
CPU time 4.63 seconds
Started Jun 26 06:24:00 PM PDT 24
Finished Jun 26 06:24:06 PM PDT 24
Peak memory 225404 kb
Host smart-e041aa95-6b15-4c04-8fd1-015b3a7a01df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986949135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2986949135
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1808405981
Short name T551
Test name
Test status
Simulation time 15933585217 ps
CPU time 28.66 seconds
Started Jun 26 06:23:57 PM PDT 24
Finished Jun 26 06:24:26 PM PDT 24
Peak memory 233676 kb
Host smart-8b4cdfef-8202-41fb-b92c-43c7009d5c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808405981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1808405981
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1821848483
Short name T75
Test name
Test status
Simulation time 2101917041 ps
CPU time 5.77 seconds
Started Jun 26 06:24:02 PM PDT 24
Finished Jun 26 06:24:09 PM PDT 24
Peak memory 241820 kb
Host smart-53babcd2-8849-4b7e-9aa2-5d641d4e8d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821848483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1821848483
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3889747064
Short name T857
Test name
Test status
Simulation time 1254973207 ps
CPU time 8.36 seconds
Started Jun 26 06:24:02 PM PDT 24
Finished Jun 26 06:24:12 PM PDT 24
Peak memory 233544 kb
Host smart-65006040-0af5-4bbd-a536-c44292b727ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889747064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3889747064
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4268048902
Short name T394
Test name
Test status
Simulation time 930783865 ps
CPU time 5 seconds
Started Jun 26 06:23:59 PM PDT 24
Finished Jun 26 06:24:05 PM PDT 24
Peak memory 223500 kb
Host smart-d684d2e7-e3e9-4307-8ebb-f6c8ab32c73f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4268048902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4268048902
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2676030947
Short name T519
Test name
Test status
Simulation time 2241097986 ps
CPU time 15.09 seconds
Started Jun 26 06:23:59 PM PDT 24
Finished Jun 26 06:24:15 PM PDT 24
Peak memory 217228 kb
Host smart-85e468ea-c425-4baf-a181-345de3a81a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676030947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2676030947
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3184773547
Short name T305
Test name
Test status
Simulation time 4469642936 ps
CPU time 9.73 seconds
Started Jun 26 06:24:06 PM PDT 24
Finished Jun 26 06:24:17 PM PDT 24
Peak memory 217176 kb
Host smart-6314026c-0ca6-42c6-9288-a34e21836fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184773547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3184773547
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1782893800
Short name T430
Test name
Test status
Simulation time 73947616 ps
CPU time 1.66 seconds
Started Jun 26 06:24:02 PM PDT 24
Finished Jun 26 06:24:05 PM PDT 24
Peak memory 217084 kb
Host smart-7f23113e-e2fb-4697-a420-0a89dde952aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782893800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1782893800
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2379919128
Short name T499
Test name
Test status
Simulation time 240882623 ps
CPU time 0.91 seconds
Started Jun 26 06:23:58 PM PDT 24
Finished Jun 26 06:24:00 PM PDT 24
Peak memory 206744 kb
Host smart-0f342d27-9d8e-42e1-9fc3-44a56ce248f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379919128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2379919128
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2155954658
Short name T435
Test name
Test status
Simulation time 49633215776 ps
CPU time 28.75 seconds
Started Jun 26 06:24:02 PM PDT 24
Finished Jun 26 06:24:32 PM PDT 24
Peak memory 241888 kb
Host smart-6ed11369-4192-4f31-a54a-0bfbca239ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155954658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2155954658
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2373421831
Short name T491
Test name
Test status
Simulation time 40536999 ps
CPU time 0.73 seconds
Started Jun 26 06:24:08 PM PDT 24
Finished Jun 26 06:24:09 PM PDT 24
Peak memory 206528 kb
Host smart-27db99bd-9e84-4856-9007-437da3357d2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373421831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2373421831
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1366195347
Short name T530
Test name
Test status
Simulation time 313973187 ps
CPU time 2.99 seconds
Started Jun 26 06:24:09 PM PDT 24
Finished Jun 26 06:24:13 PM PDT 24
Peak memory 225280 kb
Host smart-2ff23c41-c6d5-4725-8421-7901c9b532a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366195347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1366195347
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.917304979
Short name T340
Test name
Test status
Simulation time 15713838 ps
CPU time 0.8 seconds
Started Jun 26 06:23:58 PM PDT 24
Finished Jun 26 06:24:00 PM PDT 24
Peak memory 206392 kb
Host smart-75adf31b-1bfa-4584-b610-c671f6508203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917304979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.917304979
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3260515269
Short name T561
Test name
Test status
Simulation time 10445191221 ps
CPU time 42.02 seconds
Started Jun 26 06:24:07 PM PDT 24
Finished Jun 26 06:24:50 PM PDT 24
Peak memory 250704 kb
Host smart-72d9c415-4fa0-4c43-a36e-03beb3110773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260515269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3260515269
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1114122387
Short name T882
Test name
Test status
Simulation time 80031364475 ps
CPU time 372.33 seconds
Started Jun 26 06:24:12 PM PDT 24
Finished Jun 26 06:30:26 PM PDT 24
Peak memory 250120 kb
Host smart-9e778728-f31d-4585-bc48-41f413517924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114122387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1114122387
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1534400647
Short name T185
Test name
Test status
Simulation time 60409289597 ps
CPU time 544.61 seconds
Started Jun 26 06:24:09 PM PDT 24
Finished Jun 26 06:33:15 PM PDT 24
Peak memory 254528 kb
Host smart-7c947372-f315-4d23-b2a1-49e2f38973ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534400647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1534400647
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1563324915
Short name T210
Test name
Test status
Simulation time 2330919373 ps
CPU time 7.95 seconds
Started Jun 26 06:24:14 PM PDT 24
Finished Jun 26 06:24:24 PM PDT 24
Peak memory 233792 kb
Host smart-0c966599-124a-4480-a1e1-2513ba5b3cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563324915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1563324915
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1589293803
Short name T216
Test name
Test status
Simulation time 28199172726 ps
CPU time 75.05 seconds
Started Jun 26 06:24:05 PM PDT 24
Finished Jun 26 06:25:21 PM PDT 24
Peak memory 233712 kb
Host smart-dc7f8855-6f9a-4fe7-abef-ad2f3818b8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589293803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1589293803
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3371511534
Short name T192
Test name
Test status
Simulation time 3535670915 ps
CPU time 8.34 seconds
Started Jun 26 06:24:03 PM PDT 24
Finished Jun 26 06:24:13 PM PDT 24
Peak memory 237624 kb
Host smart-98781cc5-66a4-4ebe-b412-0b06cce27799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371511534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3371511534
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2746624889
Short name T397
Test name
Test status
Simulation time 1240994655 ps
CPU time 3.03 seconds
Started Jun 26 06:24:00 PM PDT 24
Finished Jun 26 06:24:05 PM PDT 24
Peak memory 225328 kb
Host smart-ecc0f33c-c49c-41b3-8039-c698c521a206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746624889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2746624889
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1592986485
Short name T503
Test name
Test status
Simulation time 1006197575 ps
CPU time 5.91 seconds
Started Jun 26 06:24:06 PM PDT 24
Finished Jun 26 06:24:14 PM PDT 24
Peak memory 223484 kb
Host smart-baa315a1-f767-44b1-b714-395786b3b0f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1592986485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1592986485
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1477684798
Short name T441
Test name
Test status
Simulation time 17201286019 ps
CPU time 85.83 seconds
Started Jun 26 06:24:12 PM PDT 24
Finished Jun 26 06:25:39 PM PDT 24
Peak memory 253476 kb
Host smart-ff7af253-370e-4eb6-a9d7-14f2fec585b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477684798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1477684798
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.374795015
Short name T558
Test name
Test status
Simulation time 1938707841 ps
CPU time 12.58 seconds
Started Jun 26 06:24:00 PM PDT 24
Finished Jun 26 06:24:14 PM PDT 24
Peak memory 217104 kb
Host smart-4a2e9ef3-6d8d-426d-bca4-afed609489aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374795015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.374795015
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3841688881
Short name T417
Test name
Test status
Simulation time 20057865822 ps
CPU time 7.89 seconds
Started Jun 26 06:24:01 PM PDT 24
Finished Jun 26 06:24:10 PM PDT 24
Peak memory 218084 kb
Host smart-44197f79-b691-4ac8-8336-b19f6c58b8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841688881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3841688881
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3250636119
Short name T334
Test name
Test status
Simulation time 195873968 ps
CPU time 1.22 seconds
Started Jun 26 06:24:00 PM PDT 24
Finished Jun 26 06:24:03 PM PDT 24
Peak memory 217108 kb
Host smart-0c8f8b00-cb08-4c22-89fb-d4e12e3a1f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250636119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3250636119
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3684660877
Short name T313
Test name
Test status
Simulation time 133591092 ps
CPU time 1 seconds
Started Jun 26 06:24:03 PM PDT 24
Finished Jun 26 06:24:06 PM PDT 24
Peak memory 207464 kb
Host smart-c9af9f47-ce60-4ca8-ac73-2edd283c283b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684660877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3684660877
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2908478836
Short name T654
Test name
Test status
Simulation time 1863599699 ps
CPU time 10.94 seconds
Started Jun 26 06:24:06 PM PDT 24
Finished Jun 26 06:24:19 PM PDT 24
Peak memory 233612 kb
Host smart-3cf3c522-4c00-49e8-bcf7-48f2f8b87f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908478836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2908478836
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4215265551
Short name T487
Test name
Test status
Simulation time 25549904 ps
CPU time 0.76 seconds
Started Jun 26 06:24:12 PM PDT 24
Finished Jun 26 06:24:14 PM PDT 24
Peak memory 206296 kb
Host smart-ce9b2168-a457-4a44-8992-c8e622d2dec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215265551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4215265551
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3837464107
Short name T727
Test name
Test status
Simulation time 114743133 ps
CPU time 2.13 seconds
Started Jun 26 06:24:06 PM PDT 24
Finished Jun 26 06:24:10 PM PDT 24
Peak memory 225240 kb
Host smart-a4f3c216-c2dd-4e36-8db6-bcd5570041f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837464107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3837464107
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2943846759
Short name T793
Test name
Test status
Simulation time 52304123 ps
CPU time 0.77 seconds
Started Jun 26 06:24:11 PM PDT 24
Finished Jun 26 06:24:13 PM PDT 24
Peak memory 206396 kb
Host smart-a8661e25-358d-4de3-9e4f-90adc3dfa08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943846759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2943846759
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4014083192
Short name T640
Test name
Test status
Simulation time 28555700226 ps
CPU time 136.96 seconds
Started Jun 26 06:24:11 PM PDT 24
Finished Jun 26 06:26:29 PM PDT 24
Peak memory 256412 kb
Host smart-ed70ae43-0dc8-40f2-8371-8161c6775ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014083192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4014083192
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.891836959
Short name T257
Test name
Test status
Simulation time 7355633126 ps
CPU time 79.48 seconds
Started Jun 26 06:24:09 PM PDT 24
Finished Jun 26 06:25:29 PM PDT 24
Peak memory 255412 kb
Host smart-58ff4b60-e218-4b18-a05e-dbcebf77c011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891836959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.891836959
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3814692049
Short name T479
Test name
Test status
Simulation time 17832533876 ps
CPU time 103.2 seconds
Started Jun 26 06:24:14 PM PDT 24
Finished Jun 26 06:26:00 PM PDT 24
Peak memory 254080 kb
Host smart-3aa0c3f4-0acb-41f2-892d-94e0fd44d4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814692049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3814692049
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.309947151
Short name T270
Test name
Test status
Simulation time 190024471 ps
CPU time 6.25 seconds
Started Jun 26 06:24:14 PM PDT 24
Finished Jun 26 06:24:23 PM PDT 24
Peak memory 225488 kb
Host smart-82103d95-cc16-4ecb-9423-d6e9079e2a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309947151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.309947151
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4270312373
Short name T871
Test name
Test status
Simulation time 229874176 ps
CPU time 5.38 seconds
Started Jun 26 06:24:12 PM PDT 24
Finished Jun 26 06:24:19 PM PDT 24
Peak memory 233608 kb
Host smart-70e79d6c-0221-485d-9c95-196d4289fd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270312373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4270312373
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3500346500
Short name T406
Test name
Test status
Simulation time 8506319562 ps
CPU time 13.29 seconds
Started Jun 26 06:24:06 PM PDT 24
Finished Jun 26 06:24:21 PM PDT 24
Peak memory 225460 kb
Host smart-2b758cc3-8c2c-4202-8eb3-02609b8f4b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500346500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3500346500
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4073321938
Short name T518
Test name
Test status
Simulation time 6711126508 ps
CPU time 20.12 seconds
Started Jun 26 06:24:06 PM PDT 24
Finished Jun 26 06:24:28 PM PDT 24
Peak memory 225536 kb
Host smart-4b08e040-dc6c-43e5-b0b3-219c7ef0d6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073321938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4073321938
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1266021404
Short name T933
Test name
Test status
Simulation time 284898654 ps
CPU time 3.8 seconds
Started Jun 26 06:24:13 PM PDT 24
Finished Jun 26 06:24:19 PM PDT 24
Peak memory 233564 kb
Host smart-1d149b7e-491f-4bc6-bc45-fcefbba56965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266021404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1266021404
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2208540249
Short name T465
Test name
Test status
Simulation time 601098479 ps
CPU time 3.91 seconds
Started Jun 26 06:24:07 PM PDT 24
Finished Jun 26 06:24:12 PM PDT 24
Peak memory 223512 kb
Host smart-012647ca-9a55-48de-9267-8b863f31fde4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2208540249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2208540249
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1059261121
Short name T704
Test name
Test status
Simulation time 218757865 ps
CPU time 1.16 seconds
Started Jun 26 06:24:12 PM PDT 24
Finished Jun 26 06:24:15 PM PDT 24
Peak memory 208084 kb
Host smart-54f49ccc-39ad-4615-a4df-193356de1f47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059261121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1059261121
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.504358747
Short name T275
Test name
Test status
Simulation time 9718143472 ps
CPU time 23.07 seconds
Started Jun 26 06:24:06 PM PDT 24
Finished Jun 26 06:24:31 PM PDT 24
Peak memory 217188 kb
Host smart-cddf462b-44c2-4733-ab34-f8c590bfd77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504358747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.504358747
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2528065310
Short name T421
Test name
Test status
Simulation time 7704141625 ps
CPU time 21.6 seconds
Started Jun 26 06:24:15 PM PDT 24
Finished Jun 26 06:24:38 PM PDT 24
Peak memory 217192 kb
Host smart-9445a6f9-e0c2-49f0-b261-73b366a47d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528065310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2528065310
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1655337880
Short name T378
Test name
Test status
Simulation time 82122878 ps
CPU time 1.39 seconds
Started Jun 26 06:24:16 PM PDT 24
Finished Jun 26 06:24:19 PM PDT 24
Peak memory 217108 kb
Host smart-1bc95162-388c-42eb-bda7-f2e011194752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655337880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1655337880
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2213171968
Short name T391
Test name
Test status
Simulation time 73003273 ps
CPU time 0.97 seconds
Started Jun 26 06:24:15 PM PDT 24
Finished Jun 26 06:24:18 PM PDT 24
Peak memory 206736 kb
Host smart-8021aa7e-2eac-4499-8da5-d752a334c85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213171968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2213171968
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2910502288
Short name T476
Test name
Test status
Simulation time 1054127077 ps
CPU time 6.17 seconds
Started Jun 26 06:24:05 PM PDT 24
Finished Jun 26 06:24:12 PM PDT 24
Peak memory 241184 kb
Host smart-0919b0fa-3eee-4bb2-b7a7-e2ffc1660e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910502288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2910502288
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1370644878
Short name T486
Test name
Test status
Simulation time 185845310 ps
CPU time 3.53 seconds
Started Jun 26 06:24:18 PM PDT 24
Finished Jun 26 06:24:23 PM PDT 24
Peak memory 225368 kb
Host smart-58a795b4-1dc3-42ce-96b7-8f541ba34451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370644878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1370644878
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1555495167
Short name T290
Test name
Test status
Simulation time 28356838 ps
CPU time 0.76 seconds
Started Jun 26 06:24:04 PM PDT 24
Finished Jun 26 06:24:06 PM PDT 24
Peak memory 206284 kb
Host smart-1cae0d72-93f3-4fdf-92f3-f4feaa157f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555495167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1555495167
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2297675032
Short name T783
Test name
Test status
Simulation time 58962809731 ps
CPU time 420.02 seconds
Started Jun 26 06:24:21 PM PDT 24
Finished Jun 26 06:31:22 PM PDT 24
Peak memory 258220 kb
Host smart-3288aa6c-7a1f-4462-95c7-0b55c137dc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297675032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2297675032
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2782697305
Short name T468
Test name
Test status
Simulation time 4285730460 ps
CPU time 72.61 seconds
Started Jun 26 06:24:21 PM PDT 24
Finished Jun 26 06:25:35 PM PDT 24
Peak memory 250448 kb
Host smart-a1d6152b-5e24-4cdf-a499-e46ea8bee48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782697305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2782697305
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1984031590
Short name T136
Test name
Test status
Simulation time 848984295 ps
CPU time 5.99 seconds
Started Jun 26 06:24:13 PM PDT 24
Finished Jun 26 06:24:21 PM PDT 24
Peak memory 233648 kb
Host smart-c9ab8588-0460-434d-ac04-9a3ab4de8faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984031590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1984031590
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.4190018182
Short name T496
Test name
Test status
Simulation time 1167100240 ps
CPU time 3.62 seconds
Started Jun 26 06:24:19 PM PDT 24
Finished Jun 26 06:24:23 PM PDT 24
Peak memory 233604 kb
Host smart-757f6c0f-8cdd-40a9-9c89-5d06b52f9537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190018182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4190018182
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.333915910
Short name T731
Test name
Test status
Simulation time 639134368 ps
CPU time 8.45 seconds
Started Jun 26 06:24:12 PM PDT 24
Finished Jun 26 06:24:22 PM PDT 24
Peak memory 225436 kb
Host smart-bcbcf941-25fb-4fd0-a4aa-d5898dda65ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333915910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.333915910
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3361228630
Short name T726
Test name
Test status
Simulation time 6564356460 ps
CPU time 7.73 seconds
Started Jun 26 06:24:15 PM PDT 24
Finished Jun 26 06:24:25 PM PDT 24
Peak memory 233672 kb
Host smart-fd808376-7516-4694-a01d-52c60d673994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361228630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3361228630
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2394787513
Short name T220
Test name
Test status
Simulation time 251772978 ps
CPU time 2.57 seconds
Started Jun 26 06:24:14 PM PDT 24
Finished Jun 26 06:24:19 PM PDT 24
Peak memory 225368 kb
Host smart-9491de2c-0081-4587-b50c-55f824b8c585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394787513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2394787513
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3026385328
Short name T685
Test name
Test status
Simulation time 873967630 ps
CPU time 7.04 seconds
Started Jun 26 06:24:13 PM PDT 24
Finished Jun 26 06:24:22 PM PDT 24
Peak memory 224024 kb
Host smart-bdd879f4-17e1-4542-bb81-4e2482490d50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3026385328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3026385328
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.963042662
Short name T593
Test name
Test status
Simulation time 39343307 ps
CPU time 1 seconds
Started Jun 26 06:24:13 PM PDT 24
Finished Jun 26 06:24:17 PM PDT 24
Peak memory 207580 kb
Host smart-654fd381-ffb4-4cfb-a227-105e0e6288f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963042662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.963042662
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3067301633
Short name T866
Test name
Test status
Simulation time 953534314 ps
CPU time 16.3 seconds
Started Jun 26 06:24:12 PM PDT 24
Finished Jun 26 06:24:29 PM PDT 24
Peak memory 217408 kb
Host smart-70e832b2-4171-4f8c-a2f4-e9661485fd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067301633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3067301633
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1961648465
Short name T454
Test name
Test status
Simulation time 8659021532 ps
CPU time 5.87 seconds
Started Jun 26 06:24:13 PM PDT 24
Finished Jun 26 06:24:22 PM PDT 24
Peak memory 217216 kb
Host smart-841df90e-c1cd-41a8-bafb-6f1f137f4266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961648465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1961648465
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1473906496
Short name T809
Test name
Test status
Simulation time 32804072 ps
CPU time 1.03 seconds
Started Jun 26 06:24:13 PM PDT 24
Finished Jun 26 06:24:17 PM PDT 24
Peak memory 208076 kb
Host smart-442122c2-632d-4ceb-b276-1a2945ce54ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473906496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1473906496
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3703658724
Short name T925
Test name
Test status
Simulation time 93269993 ps
CPU time 0.9 seconds
Started Jun 26 06:24:13 PM PDT 24
Finished Jun 26 06:24:16 PM PDT 24
Peak memory 206748 kb
Host smart-794d4450-c476-4a70-8d3f-1bcacdff3e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703658724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3703658724
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1732596554
Short name T452
Test name
Test status
Simulation time 2045498242 ps
CPU time 11.39 seconds
Started Jun 26 06:24:14 PM PDT 24
Finished Jun 26 06:24:27 PM PDT 24
Peak memory 239160 kb
Host smart-64c06bcb-b881-4e4b-95e3-d10c6622c706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732596554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1732596554
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2033904747
Short name T62
Test name
Test status
Simulation time 14829452 ps
CPU time 0.77 seconds
Started Jun 26 06:24:15 PM PDT 24
Finished Jun 26 06:24:18 PM PDT 24
Peak memory 205772 kb
Host smart-3607324e-f7f4-412f-91d1-998fec8e10c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033904747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2033904747
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2557504245
Short name T343
Test name
Test status
Simulation time 2583657538 ps
CPU time 5.2 seconds
Started Jun 26 06:24:16 PM PDT 24
Finished Jun 26 06:24:23 PM PDT 24
Peak memory 225560 kb
Host smart-a0999705-61e5-4f89-9df3-0543f7b1defb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557504245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2557504245
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2818004034
Short name T708
Test name
Test status
Simulation time 22187600 ps
CPU time 0.82 seconds
Started Jun 26 06:24:22 PM PDT 24
Finished Jun 26 06:24:23 PM PDT 24
Peak memory 207408 kb
Host smart-f2e9f9fd-1f7e-46ab-a752-9f82a59f3925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818004034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2818004034
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2889609109
Short name T509
Test name
Test status
Simulation time 30614166024 ps
CPU time 125.48 seconds
Started Jun 26 06:24:15 PM PDT 24
Finished Jun 26 06:26:23 PM PDT 24
Peak memory 252128 kb
Host smart-9a7ad52b-5faa-4a5c-b9ae-405480fd985d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889609109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2889609109
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.34235306
Short name T251
Test name
Test status
Simulation time 29845941600 ps
CPU time 311.96 seconds
Started Jun 26 06:24:21 PM PDT 24
Finished Jun 26 06:29:34 PM PDT 24
Peak memory 257292 kb
Host smart-ea76b4d8-7924-438b-b794-859b592baf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34235306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.34235306
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2572939909
Short name T638
Test name
Test status
Simulation time 16904177069 ps
CPU time 175.8 seconds
Started Jun 26 06:24:18 PM PDT 24
Finished Jun 26 06:27:15 PM PDT 24
Peak memory 250352 kb
Host smart-64e0852c-d373-4de4-8cd0-2dc34d3a1f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572939909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2572939909
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1497111912
Short name T316
Test name
Test status
Simulation time 84054674 ps
CPU time 4.08 seconds
Started Jun 26 06:24:11 PM PDT 24
Finished Jun 26 06:24:16 PM PDT 24
Peak memory 233644 kb
Host smart-68d52520-e9a7-41f3-91ff-6371118e17b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497111912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1497111912
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1293270514
Short name T433
Test name
Test status
Simulation time 19295075968 ps
CPU time 47.12 seconds
Started Jun 26 06:24:20 PM PDT 24
Finished Jun 26 06:25:08 PM PDT 24
Peak memory 225480 kb
Host smart-d27377b1-170c-4d7c-b47b-c8ac15cf1929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293270514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1293270514
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1616766637
Short name T327
Test name
Test status
Simulation time 4885190858 ps
CPU time 16.19 seconds
Started Jun 26 06:24:14 PM PDT 24
Finished Jun 26 06:24:32 PM PDT 24
Peak memory 257204 kb
Host smart-d27574d8-2ef5-436f-b7ec-b45a3062f1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616766637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1616766637
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2731141927
Short name T344
Test name
Test status
Simulation time 147420089 ps
CPU time 2.23 seconds
Started Jun 26 06:24:14 PM PDT 24
Finished Jun 26 06:24:18 PM PDT 24
Peak memory 223864 kb
Host smart-a88539ec-64d9-433c-8ed6-b6a07f2f34d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731141927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2731141927
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.163411293
Short name T385
Test name
Test status
Simulation time 7581620162 ps
CPU time 22.82 seconds
Started Jun 26 06:24:20 PM PDT 24
Finished Jun 26 06:24:43 PM PDT 24
Peak memory 225484 kb
Host smart-d5e24be8-f4f9-482c-b9d7-05e1dc90deb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163411293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.163411293
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1715770766
Short name T581
Test name
Test status
Simulation time 541656178 ps
CPU time 3.79 seconds
Started Jun 26 06:24:17 PM PDT 24
Finished Jun 26 06:24:22 PM PDT 24
Peak memory 219772 kb
Host smart-37295a62-ea1a-4d1b-a8f3-5959a4a5c38f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1715770766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1715770766
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1576447764
Short name T55
Test name
Test status
Simulation time 168517798275 ps
CPU time 454.59 seconds
Started Jun 26 06:24:12 PM PDT 24
Finished Jun 26 06:31:49 PM PDT 24
Peak memory 257888 kb
Host smart-27dd56ab-2ff4-4f34-b174-dbe01c25e214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576447764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1576447764
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.963263568
Short name T703
Test name
Test status
Simulation time 4101433735 ps
CPU time 27.11 seconds
Started Jun 26 06:24:13 PM PDT 24
Finished Jun 26 06:24:42 PM PDT 24
Peak memory 217272 kb
Host smart-2c191ed4-02de-4a4f-854f-66521c9ae283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963263568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.963263568
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1115927400
Short name T369
Test name
Test status
Simulation time 29729810 ps
CPU time 0.73 seconds
Started Jun 26 06:24:16 PM PDT 24
Finished Jun 26 06:24:18 PM PDT 24
Peak memory 206564 kb
Host smart-26c39c0a-64f1-4738-b488-fd3586453be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115927400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1115927400
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1762763161
Short name T687
Test name
Test status
Simulation time 36102817 ps
CPU time 1.07 seconds
Started Jun 26 06:24:14 PM PDT 24
Finished Jun 26 06:24:17 PM PDT 24
Peak memory 208720 kb
Host smart-0aa830a1-907e-4f31-8f85-77a8c0611231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762763161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1762763161
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3097838196
Short name T477
Test name
Test status
Simulation time 181630387 ps
CPU time 0.81 seconds
Started Jun 26 06:24:18 PM PDT 24
Finished Jun 26 06:24:20 PM PDT 24
Peak memory 206676 kb
Host smart-891c4d12-6894-4fc2-b996-9d070cdf9b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097838196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3097838196
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2198598192
Short name T374
Test name
Test status
Simulation time 338598240 ps
CPU time 5.49 seconds
Started Jun 26 06:24:13 PM PDT 24
Finished Jun 26 06:24:21 PM PDT 24
Peak memory 233644 kb
Host smart-a1c707c0-2ff3-4efa-8405-aef76ded75b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198598192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2198598192
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.314137445
Short name T934
Test name
Test status
Simulation time 24507432 ps
CPU time 0.73 seconds
Started Jun 26 06:24:21 PM PDT 24
Finished Jun 26 06:24:22 PM PDT 24
Peak memory 206280 kb
Host smart-9d296f36-ad06-40c9-9492-83a2dbeb7776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314137445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.314137445
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.580416620
Short name T814
Test name
Test status
Simulation time 231280238 ps
CPU time 5.97 seconds
Started Jun 26 06:24:24 PM PDT 24
Finished Jun 26 06:24:32 PM PDT 24
Peak memory 233660 kb
Host smart-6f433be4-47c2-426a-ab19-89c9e759749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580416620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.580416620
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1550924256
Short name T886
Test name
Test status
Simulation time 41358371 ps
CPU time 0.8 seconds
Started Jun 26 06:24:16 PM PDT 24
Finished Jun 26 06:24:19 PM PDT 24
Peak memory 207696 kb
Host smart-f0a2402e-2f50-4fd9-aa03-ea018dc23ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550924256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1550924256
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3278363138
Short name T350
Test name
Test status
Simulation time 23253925841 ps
CPU time 38.77 seconds
Started Jun 26 06:24:23 PM PDT 24
Finished Jun 26 06:25:04 PM PDT 24
Peak memory 253076 kb
Host smart-a62ec61e-a4b2-4a40-a924-6b6cb97e0478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278363138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3278363138
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.945605529
Short name T59
Test name
Test status
Simulation time 14954514253 ps
CPU time 153.42 seconds
Started Jun 26 06:24:22 PM PDT 24
Finished Jun 26 06:26:57 PM PDT 24
Peak memory 251500 kb
Host smart-fe101c4d-86c3-4a54-9ddd-fe00aeb02d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945605529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.945605529
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2537683053
Short name T843
Test name
Test status
Simulation time 1118093854 ps
CPU time 8.83 seconds
Started Jun 26 06:24:20 PM PDT 24
Finished Jun 26 06:24:30 PM PDT 24
Peak memory 250052 kb
Host smart-1fcdb174-8c1a-4a85-9e6f-f9418f3c4aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537683053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2537683053
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.968497705
Short name T800
Test name
Test status
Simulation time 959227134 ps
CPU time 6.62 seconds
Started Jun 26 06:24:24 PM PDT 24
Finished Jun 26 06:24:32 PM PDT 24
Peak memory 233660 kb
Host smart-81c11670-b149-44ab-a3e4-c74b432bda7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968497705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.968497705
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2979359973
Short name T252
Test name
Test status
Simulation time 6214485019 ps
CPU time 12.08 seconds
Started Jun 26 06:24:21 PM PDT 24
Finished Jun 26 06:24:34 PM PDT 24
Peak memory 225556 kb
Host smart-7f3c55ac-0e3c-42b5-b8c1-4db97d66763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979359973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2979359973
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1019647110
Short name T207
Test name
Test status
Simulation time 5832409412 ps
CPU time 20.01 seconds
Started Jun 26 06:24:25 PM PDT 24
Finished Jun 26 06:24:47 PM PDT 24
Peak memory 233664 kb
Host smart-16e0a1df-87d0-4283-afd3-971d8e2d8d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019647110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1019647110
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1203078516
Short name T44
Test name
Test status
Simulation time 143277021 ps
CPU time 4.46 seconds
Started Jun 26 06:24:24 PM PDT 24
Finished Jun 26 06:24:30 PM PDT 24
Peak memory 219800 kb
Host smart-3080821a-33f2-4d9a-b029-874ee0c21aa9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1203078516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1203078516
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.329935800
Short name T691
Test name
Test status
Simulation time 79072055745 ps
CPU time 403.4 seconds
Started Jun 26 06:24:24 PM PDT 24
Finished Jun 26 06:31:09 PM PDT 24
Peak memory 274764 kb
Host smart-83455d43-6ac5-4271-bdac-a5ff7fa96c8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329935800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.329935800
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3645781278
Short name T304
Test name
Test status
Simulation time 22819371 ps
CPU time 0.72 seconds
Started Jun 26 06:24:26 PM PDT 24
Finished Jun 26 06:24:29 PM PDT 24
Peak memory 206484 kb
Host smart-f13ec0d6-6a00-40c1-ab17-3d6cc282d305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645781278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3645781278
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1845795932
Short name T881
Test name
Test status
Simulation time 12249194577 ps
CPU time 10.25 seconds
Started Jun 26 06:24:15 PM PDT 24
Finished Jun 26 06:24:27 PM PDT 24
Peak memory 217220 kb
Host smart-64efdf5a-1699-400c-8b6d-c60ffc0e8937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845795932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1845795932
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.4180481361
Short name T36
Test name
Test status
Simulation time 772360412 ps
CPU time 1.51 seconds
Started Jun 26 06:24:22 PM PDT 24
Finished Jun 26 06:24:24 PM PDT 24
Peak memory 217148 kb
Host smart-af7f4530-0245-40e4-820e-ed929c12d9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180481361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.4180481361
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.724597341
Short name T521
Test name
Test status
Simulation time 66007959 ps
CPU time 0.94 seconds
Started Jun 26 06:24:22 PM PDT 24
Finished Jun 26 06:24:24 PM PDT 24
Peak memory 206672 kb
Host smart-b86eab4c-ae09-42c5-ba04-4196e9280f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724597341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.724597341
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1600379258
Short name T237
Test name
Test status
Simulation time 93354315 ps
CPU time 2.33 seconds
Started Jun 26 06:24:22 PM PDT 24
Finished Jun 26 06:24:27 PM PDT 24
Peak memory 225348 kb
Host smart-96500f0d-127b-4e47-919e-3b6711186839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600379258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1600379258
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1827184387
Short name T404
Test name
Test status
Simulation time 16631459 ps
CPU time 0.77 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:30 PM PDT 24
Peak memory 206636 kb
Host smart-85ac52c5-f24b-4ce2-bdb0-4b2ef17a1df1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827184387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
827184387
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2752177056
Short name T557
Test name
Test status
Simulation time 33894866 ps
CPU time 2.93 seconds
Started Jun 26 06:23:25 PM PDT 24
Finished Jun 26 06:23:29 PM PDT 24
Peak memory 233312 kb
Host smart-5b9ca9f3-6253-4483-9f11-78b9a7c2d3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752177056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2752177056
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3937436960
Short name T778
Test name
Test status
Simulation time 15028294 ps
CPU time 0.77 seconds
Started Jun 26 06:23:26 PM PDT 24
Finished Jun 26 06:23:29 PM PDT 24
Peak memory 206364 kb
Host smart-b60b0d11-472a-4501-bf70-6f084a8b38ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937436960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3937436960
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3434523327
Short name T6
Test name
Test status
Simulation time 68225934306 ps
CPU time 120.59 seconds
Started Jun 26 06:23:25 PM PDT 24
Finished Jun 26 06:25:27 PM PDT 24
Peak memory 241892 kb
Host smart-68aa205d-e161-4833-97c0-539b64e59ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434523327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3434523327
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2054173868
Short name T935
Test name
Test status
Simulation time 8123138322 ps
CPU time 85.72 seconds
Started Jun 26 06:23:24 PM PDT 24
Finished Jun 26 06:24:51 PM PDT 24
Peak memory 250188 kb
Host smart-844e160b-106d-4f65-8666-3a04ea3ad726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054173868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2054173868
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2152884942
Short name T876
Test name
Test status
Simulation time 9829699551 ps
CPU time 45.89 seconds
Started Jun 26 06:23:29 PM PDT 24
Finished Jun 26 06:24:17 PM PDT 24
Peak memory 238352 kb
Host smart-e200aa36-e17e-417e-a2c1-bdb7cdd4df38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152884942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2152884942
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1553766278
Short name T832
Test name
Test status
Simulation time 140689625 ps
CPU time 4.71 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:34 PM PDT 24
Peak memory 233680 kb
Host smart-6f84a8e8-e40a-4641-874d-45cf499c173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553766278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1553766278
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.92999287
Short name T879
Test name
Test status
Simulation time 122326527 ps
CPU time 3.98 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:33 PM PDT 24
Peak memory 233656 kb
Host smart-55fe5104-e175-4422-9397-041993a0cebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92999287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.92999287
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3727804538
Short name T380
Test name
Test status
Simulation time 335802722 ps
CPU time 9.44 seconds
Started Jun 26 06:23:26 PM PDT 24
Finished Jun 26 06:23:37 PM PDT 24
Peak memory 233616 kb
Host smart-cb87934e-b271-4d6e-9593-bab172f3b3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727804538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3727804538
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.499800839
Short name T773
Test name
Test status
Simulation time 745837161 ps
CPU time 4.37 seconds
Started Jun 26 06:23:28 PM PDT 24
Finished Jun 26 06:23:35 PM PDT 24
Peak memory 241700 kb
Host smart-4cc65564-0e53-4916-a4c1-950ed78d9a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499800839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
499800839
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4212029311
Short name T311
Test name
Test status
Simulation time 251468150 ps
CPU time 3.09 seconds
Started Jun 26 06:23:28 PM PDT 24
Finished Jun 26 06:23:33 PM PDT 24
Peak memory 233624 kb
Host smart-55e7870d-1b9e-4e95-bc1e-c8c42edcb1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212029311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4212029311
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3229530176
Short name T133
Test name
Test status
Simulation time 509694998 ps
CPU time 5.63 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:35 PM PDT 24
Peak memory 222856 kb
Host smart-31260d0e-edb3-4237-9833-9cbfbd0cd735
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3229530176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3229530176
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3531097539
Short name T68
Test name
Test status
Simulation time 119990512 ps
CPU time 1.2 seconds
Started Jun 26 06:23:28 PM PDT 24
Finished Jun 26 06:23:32 PM PDT 24
Peak memory 236616 kb
Host smart-de02994e-c579-4246-8ae0-3ec0522e5c17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531097539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3531097539
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3500311095
Short name T604
Test name
Test status
Simulation time 12632492439 ps
CPU time 50.31 seconds
Started Jun 26 06:23:24 PM PDT 24
Finished Jun 26 06:24:16 PM PDT 24
Peak memory 250352 kb
Host smart-857843d1-fd8b-440c-b009-bbdcb1f028d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500311095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3500311095
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3370773735
Short name T289
Test name
Test status
Simulation time 21619337 ps
CPU time 0.77 seconds
Started Jun 26 06:23:28 PM PDT 24
Finished Jun 26 06:23:31 PM PDT 24
Peak memory 206564 kb
Host smart-4283ddf2-9953-4f80-bef7-b12f9041a038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370773735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3370773735
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.58478988
Short name T611
Test name
Test status
Simulation time 1830354973 ps
CPU time 4.68 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:34 PM PDT 24
Peak memory 217080 kb
Host smart-bfe969b1-6c16-4955-a35b-aea0af79231f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58478988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.58478988
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3070818576
Short name T405
Test name
Test status
Simulation time 50777689 ps
CPU time 1.5 seconds
Started Jun 26 06:23:28 PM PDT 24
Finished Jun 26 06:23:31 PM PDT 24
Peak memory 217100 kb
Host smart-56cde916-e3e5-4471-8e9f-64137ec841fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070818576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3070818576
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4196585245
Short name T909
Test name
Test status
Simulation time 80998211 ps
CPU time 0.74 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:30 PM PDT 24
Peak memory 206756 kb
Host smart-8fccf6dc-2127-42ae-bc11-24daabe0b1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196585245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4196585245
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3467215749
Short name T895
Test name
Test status
Simulation time 326954959 ps
CPU time 2.48 seconds
Started Jun 26 06:23:26 PM PDT 24
Finished Jun 26 06:23:31 PM PDT 24
Peak memory 225096 kb
Host smart-6ade1c06-0bec-4515-a776-0ae0c8e71c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467215749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3467215749
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3016794735
Short name T636
Test name
Test status
Simulation time 21549383 ps
CPU time 0.79 seconds
Started Jun 26 06:24:22 PM PDT 24
Finished Jun 26 06:24:24 PM PDT 24
Peak memory 206352 kb
Host smart-5922aefa-67fe-4bd8-8943-770c50657c48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016794735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3016794735
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.469175932
Short name T874
Test name
Test status
Simulation time 3090284186 ps
CPU time 4.59 seconds
Started Jun 26 06:24:22 PM PDT 24
Finished Jun 26 06:24:29 PM PDT 24
Peak memory 233752 kb
Host smart-6ad275c8-65f6-409c-8e88-13970dc630c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469175932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.469175932
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1186780018
Short name T288
Test name
Test status
Simulation time 16375138 ps
CPU time 0.8 seconds
Started Jun 26 06:24:23 PM PDT 24
Finished Jun 26 06:24:25 PM PDT 24
Peak memory 206376 kb
Host smart-4dba4ddd-5201-4cb4-ac3d-f180c5287dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186780018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1186780018
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2393427800
Short name T735
Test name
Test status
Simulation time 1297428851 ps
CPU time 7.08 seconds
Started Jun 26 06:24:23 PM PDT 24
Finished Jun 26 06:24:31 PM PDT 24
Peak memory 235480 kb
Host smart-11dfb51d-56f2-45ef-bc4e-06dcbe360aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393427800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2393427800
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1851242362
Short name T931
Test name
Test status
Simulation time 5764796618 ps
CPU time 65.23 seconds
Started Jun 26 06:24:19 PM PDT 24
Finished Jun 26 06:25:25 PM PDT 24
Peak memory 273200 kb
Host smart-0cc7ea56-1609-4713-a409-f45f06c7dd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851242362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1851242362
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3514631753
Short name T281
Test name
Test status
Simulation time 16893253169 ps
CPU time 41.64 seconds
Started Jun 26 06:24:23 PM PDT 24
Finished Jun 26 06:25:06 PM PDT 24
Peak memory 218616 kb
Host smart-94a12000-9b6d-4100-a64f-4b3169b0e6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514631753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3514631753
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2362064231
Short name T911
Test name
Test status
Simulation time 713989343 ps
CPU time 13.13 seconds
Started Jun 26 06:24:25 PM PDT 24
Finished Jun 26 06:24:41 PM PDT 24
Peak memory 236872 kb
Host smart-85b8d15d-08cb-49a4-997a-50a307e2bc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362064231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2362064231
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4279852083
Short name T739
Test name
Test status
Simulation time 122957830 ps
CPU time 3.52 seconds
Started Jun 26 06:24:27 PM PDT 24
Finished Jun 26 06:24:33 PM PDT 24
Peak memory 233568 kb
Host smart-ab6c582e-ef68-4ce1-9552-e34d4da61ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279852083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4279852083
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2341826447
Short name T330
Test name
Test status
Simulation time 75732973 ps
CPU time 2.23 seconds
Started Jun 26 06:24:22 PM PDT 24
Finished Jun 26 06:24:26 PM PDT 24
Peak memory 225420 kb
Host smart-65a022da-07e9-4916-ba01-ee1cc8cda79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341826447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2341826447
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2569533209
Short name T544
Test name
Test status
Simulation time 640431662 ps
CPU time 4.09 seconds
Started Jun 26 06:24:23 PM PDT 24
Finished Jun 26 06:24:29 PM PDT 24
Peak memory 225416 kb
Host smart-37b82ea5-3593-4190-b46b-9647629847a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569533209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2569533209
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.910821470
Short name T642
Test name
Test status
Simulation time 1810554793 ps
CPU time 8.51 seconds
Started Jun 26 06:24:22 PM PDT 24
Finished Jun 26 06:24:31 PM PDT 24
Peak memory 233632 kb
Host smart-c30de9be-08c7-4ad8-8d19-027871a5ecf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910821470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.910821470
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2085924782
Short name T352
Test name
Test status
Simulation time 3577025028 ps
CPU time 6.35 seconds
Started Jun 26 06:24:21 PM PDT 24
Finished Jun 26 06:24:29 PM PDT 24
Peak memory 224192 kb
Host smart-da332bef-de75-481a-8f35-c783cb4a3061
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2085924782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2085924782
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2890260126
Short name T152
Test name
Test status
Simulation time 354186760807 ps
CPU time 614.34 seconds
Started Jun 26 06:24:24 PM PDT 24
Finished Jun 26 06:34:40 PM PDT 24
Peak memory 273608 kb
Host smart-2872c543-c454-4563-9d6b-298f1338f6f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890260126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2890260126
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1517934031
Short name T671
Test name
Test status
Simulation time 13401032416 ps
CPU time 23.88 seconds
Started Jun 26 06:24:25 PM PDT 24
Finished Jun 26 06:24:51 PM PDT 24
Peak memory 217132 kb
Host smart-a4dc2aad-ed43-43a6-b466-f043cbee4555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517934031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1517934031
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1245144597
Short name T348
Test name
Test status
Simulation time 17648240 ps
CPU time 0.76 seconds
Started Jun 26 06:24:20 PM PDT 24
Finished Jun 26 06:24:21 PM PDT 24
Peak memory 206588 kb
Host smart-754cd0d0-979f-42d2-a18a-bd3c1e775395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245144597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1245144597
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.636330733
Short name T842
Test name
Test status
Simulation time 84608202 ps
CPU time 1.92 seconds
Started Jun 26 06:24:24 PM PDT 24
Finished Jun 26 06:24:28 PM PDT 24
Peak memory 217104 kb
Host smart-cfeefbac-ff53-447c-ba31-3f5de288a2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636330733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.636330733
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1053800911
Short name T853
Test name
Test status
Simulation time 215488451 ps
CPU time 1.01 seconds
Started Jun 26 06:24:24 PM PDT 24
Finished Jun 26 06:24:26 PM PDT 24
Peak memory 207700 kb
Host smart-fb96c3f2-f0c9-4ad1-b9ed-7cb6013185b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053800911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1053800911
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3489393455
Short name T826
Test name
Test status
Simulation time 3763618969 ps
CPU time 6.75 seconds
Started Jun 26 06:24:19 PM PDT 24
Finished Jun 26 06:24:26 PM PDT 24
Peak memory 233796 kb
Host smart-ba1b2d66-4372-44a7-89f3-16868b74ca43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489393455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3489393455
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1343705288
Short name T679
Test name
Test status
Simulation time 14081472 ps
CPU time 0.75 seconds
Started Jun 26 06:24:29 PM PDT 24
Finished Jun 26 06:24:32 PM PDT 24
Peak memory 206284 kb
Host smart-62709ed0-cec2-4b74-a4eb-2157d6dab665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343705288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1343705288
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2637631231
Short name T315
Test name
Test status
Simulation time 2863470546 ps
CPU time 10.02 seconds
Started Jun 26 06:24:30 PM PDT 24
Finished Jun 26 06:24:42 PM PDT 24
Peak memory 225572 kb
Host smart-ede7bf0c-9988-40f7-8077-200ae85eb8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637631231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2637631231
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2945292990
Short name T915
Test name
Test status
Simulation time 35230195 ps
CPU time 0.83 seconds
Started Jun 26 06:24:23 PM PDT 24
Finished Jun 26 06:24:25 PM PDT 24
Peak memory 207416 kb
Host smart-95f91e44-38fb-43d6-8110-8c532a2b8156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945292990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2945292990
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1139034215
Short name T200
Test name
Test status
Simulation time 27877412436 ps
CPU time 209.87 seconds
Started Jun 26 06:24:27 PM PDT 24
Finished Jun 26 06:28:00 PM PDT 24
Peak memory 250184 kb
Host smart-d246f25f-a003-4562-ac88-25e7d2421928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139034215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1139034215
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.795743255
Short name T785
Test name
Test status
Simulation time 3343491200 ps
CPU time 42.07 seconds
Started Jun 26 06:24:30 PM PDT 24
Finished Jun 26 06:25:14 PM PDT 24
Peak memory 253420 kb
Host smart-8019f307-b5da-477d-989f-13c24f9269e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795743255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.795743255
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3826441539
Short name T157
Test name
Test status
Simulation time 98042686264 ps
CPU time 142.1 seconds
Started Jun 26 06:24:31 PM PDT 24
Finished Jun 26 06:26:55 PM PDT 24
Peak memory 257384 kb
Host smart-3e56340d-c6c3-4753-bde1-8202e4bd8e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826441539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3826441539
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2509432295
Short name T692
Test name
Test status
Simulation time 625933706 ps
CPU time 3.72 seconds
Started Jun 26 06:24:34 PM PDT 24
Finished Jun 26 06:24:39 PM PDT 24
Peak memory 225428 kb
Host smart-fac1dd21-c255-4082-89a1-48f85829e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509432295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2509432295
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3341826015
Short name T541
Test name
Test status
Simulation time 1480040213 ps
CPU time 9.86 seconds
Started Jun 26 06:24:31 PM PDT 24
Finished Jun 26 06:24:43 PM PDT 24
Peak memory 225572 kb
Host smart-265527ff-fa53-470c-baf4-8bc3ea04f382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341826015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3341826015
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2155544008
Short name T206
Test name
Test status
Simulation time 11605070887 ps
CPU time 59.87 seconds
Started Jun 26 06:24:27 PM PDT 24
Finished Jun 26 06:25:29 PM PDT 24
Peak memory 233724 kb
Host smart-330990cd-b8b0-47aa-8301-c090827254e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155544008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2155544008
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3001943520
Short name T469
Test name
Test status
Simulation time 1963595310 ps
CPU time 7.46 seconds
Started Jun 26 06:24:28 PM PDT 24
Finished Jun 26 06:24:38 PM PDT 24
Peak memory 233640 kb
Host smart-634a2e95-7b2e-4992-8893-c3cdb7537139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001943520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3001943520
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2476999562
Short name T241
Test name
Test status
Simulation time 4143589308 ps
CPU time 11.58 seconds
Started Jun 26 06:24:27 PM PDT 24
Finished Jun 26 06:24:41 PM PDT 24
Peak memory 233780 kb
Host smart-b9bdc329-2138-409a-91c7-26c99873ddb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476999562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2476999562
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2568643884
Short name T771
Test name
Test status
Simulation time 94727811 ps
CPU time 4.15 seconds
Started Jun 26 06:24:28 PM PDT 24
Finished Jun 26 06:24:35 PM PDT 24
Peak memory 223996 kb
Host smart-8c9e6d55-6cd3-41e1-89e2-69c4c6e9c767
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2568643884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2568643884
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.689451504
Short name T455
Test name
Test status
Simulation time 34476720 ps
CPU time 0.95 seconds
Started Jun 26 06:24:28 PM PDT 24
Finished Jun 26 06:24:31 PM PDT 24
Peak memory 207404 kb
Host smart-68bfa19c-41bf-4f8a-85ae-f04eb945718a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689451504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.689451504
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1223541502
Short name T648
Test name
Test status
Simulation time 84757512 ps
CPU time 0.74 seconds
Started Jun 26 06:24:23 PM PDT 24
Finished Jun 26 06:24:25 PM PDT 24
Peak memory 206576 kb
Host smart-33828c14-aafa-4b8f-9177-c181a6adc147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223541502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1223541502
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1885885986
Short name T409
Test name
Test status
Simulation time 10902307 ps
CPU time 0.72 seconds
Started Jun 26 06:24:19 PM PDT 24
Finished Jun 26 06:24:21 PM PDT 24
Peak memory 206508 kb
Host smart-c388df28-9f3f-4fc3-9903-f943d27c17c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885885986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1885885986
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2562115962
Short name T317
Test name
Test status
Simulation time 87288603 ps
CPU time 1.89 seconds
Started Jun 26 06:24:24 PM PDT 24
Finished Jun 26 06:24:28 PM PDT 24
Peak memory 217052 kb
Host smart-a73cd071-523a-4a36-961d-3e00373628ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562115962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2562115962
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1810345760
Short name T619
Test name
Test status
Simulation time 22625266 ps
CPU time 0.72 seconds
Started Jun 26 06:24:24 PM PDT 24
Finished Jun 26 06:24:27 PM PDT 24
Peak memory 206432 kb
Host smart-36adec1c-d5ee-4853-8e5c-7f03768b7e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810345760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1810345760
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4061111557
Short name T754
Test name
Test status
Simulation time 451147950 ps
CPU time 7.39 seconds
Started Jun 26 06:24:28 PM PDT 24
Finished Jun 26 06:24:37 PM PDT 24
Peak memory 233636 kb
Host smart-1a6e263e-b80f-41bb-a988-30ac660251c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061111557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4061111557
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3622903301
Short name T320
Test name
Test status
Simulation time 43803690 ps
CPU time 0.73 seconds
Started Jun 26 06:24:28 PM PDT 24
Finished Jun 26 06:24:31 PM PDT 24
Peak memory 205784 kb
Host smart-bc306d4f-f7da-4b02-89b7-4212140ba5eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622903301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3622903301
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1098913705
Short name T802
Test name
Test status
Simulation time 1724230693 ps
CPU time 9.44 seconds
Started Jun 26 06:24:31 PM PDT 24
Finished Jun 26 06:24:42 PM PDT 24
Peak memory 225452 kb
Host smart-375e80d3-8542-4afe-aa8e-8ba62fba95c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098913705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1098913705
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2205138073
Short name T296
Test name
Test status
Simulation time 16471474 ps
CPU time 0.79 seconds
Started Jun 26 06:24:28 PM PDT 24
Finished Jun 26 06:24:31 PM PDT 24
Peak memory 207428 kb
Host smart-660ed027-dbb7-4178-b856-488f8b635657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205138073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2205138073
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2109518767
Short name T536
Test name
Test status
Simulation time 58839218953 ps
CPU time 31.12 seconds
Started Jun 26 06:24:31 PM PDT 24
Finished Jun 26 06:25:04 PM PDT 24
Peak memory 239964 kb
Host smart-5514ad0f-e386-4f89-9518-4069b366f8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109518767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2109518767
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4255997620
Short name T20
Test name
Test status
Simulation time 14182533948 ps
CPU time 109.41 seconds
Started Jun 26 06:24:28 PM PDT 24
Finished Jun 26 06:26:20 PM PDT 24
Peak memory 253640 kb
Host smart-c7781606-4334-4804-b061-e9b73f859fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255997620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4255997620
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.325181899
Short name T820
Test name
Test status
Simulation time 29943150844 ps
CPU time 65.54 seconds
Started Jun 26 06:24:32 PM PDT 24
Finished Jun 26 06:25:39 PM PDT 24
Peak memory 225760 kb
Host smart-ab9bc65a-1efc-4fac-b4bd-6175e0c3d4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325181899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.325181899
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2275233372
Short name T799
Test name
Test status
Simulation time 934910318 ps
CPU time 6.42 seconds
Started Jun 26 06:24:26 PM PDT 24
Finished Jun 26 06:24:35 PM PDT 24
Peak memory 225432 kb
Host smart-978eccab-0d4d-473e-8489-a6e3ce722f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275233372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2275233372
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2363057349
Short name T607
Test name
Test status
Simulation time 1905189267 ps
CPU time 7.96 seconds
Started Jun 26 06:24:26 PM PDT 24
Finished Jun 26 06:24:37 PM PDT 24
Peak memory 225448 kb
Host smart-035f4e65-9b1d-488b-9330-eb5d66cc31af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363057349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2363057349
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3872769515
Short name T942
Test name
Test status
Simulation time 945261246 ps
CPU time 8.64 seconds
Started Jun 26 06:24:28 PM PDT 24
Finished Jun 26 06:24:40 PM PDT 24
Peak memory 250040 kb
Host smart-c20ec7fc-02a0-488d-960a-d3a6c09914a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872769515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3872769515
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1963989575
Short name T683
Test name
Test status
Simulation time 1990350578 ps
CPU time 9.07 seconds
Started Jun 26 06:24:34 PM PDT 24
Finished Jun 26 06:24:44 PM PDT 24
Peak memory 233604 kb
Host smart-ef104fec-65a4-4e2e-83a3-0961e991a838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963989575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1963989575
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.177578738
Short name T585
Test name
Test status
Simulation time 804534239 ps
CPU time 5.94 seconds
Started Jun 26 06:24:30 PM PDT 24
Finished Jun 26 06:24:38 PM PDT 24
Peak memory 241860 kb
Host smart-7489c552-db72-479b-ab85-925307338579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177578738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.177578738
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.182580321
Short name T728
Test name
Test status
Simulation time 4552732510 ps
CPU time 10.86 seconds
Started Jun 26 06:24:31 PM PDT 24
Finished Jun 26 06:24:44 PM PDT 24
Peak memory 223668 kb
Host smart-78fdf35f-f025-450d-bed4-a4ea2e9a7eeb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=182580321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.182580321
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3604883873
Short name T790
Test name
Test status
Simulation time 22776271398 ps
CPU time 221.21 seconds
Started Jun 26 06:24:28 PM PDT 24
Finished Jun 26 06:28:11 PM PDT 24
Peak memory 253092 kb
Host smart-177fcaa8-e99b-4f5d-bb6e-b6658cbf8113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604883873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3604883873
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.599071574
Short name T573
Test name
Test status
Simulation time 604255122 ps
CPU time 7.9 seconds
Started Jun 26 06:24:30 PM PDT 24
Finished Jun 26 06:24:40 PM PDT 24
Peak memory 220880 kb
Host smart-c96ae01f-6caf-4406-9c89-6a6848316c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599071574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.599071574
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.446632406
Short name T863
Test name
Test status
Simulation time 20629245002 ps
CPU time 10.76 seconds
Started Jun 26 06:24:30 PM PDT 24
Finished Jun 26 06:24:43 PM PDT 24
Peak memory 218236 kb
Host smart-a4298c84-1773-4333-a51a-a734cb998285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446632406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.446632406
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1542140195
Short name T346
Test name
Test status
Simulation time 116955253 ps
CPU time 0.7 seconds
Started Jun 26 06:24:29 PM PDT 24
Finished Jun 26 06:24:32 PM PDT 24
Peak memory 206484 kb
Host smart-29feabe8-b382-4cc6-a688-c7230c90ebbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542140195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1542140195
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2331932361
Short name T293
Test name
Test status
Simulation time 108421636 ps
CPU time 0.86 seconds
Started Jun 26 06:24:31 PM PDT 24
Finished Jun 26 06:24:34 PM PDT 24
Peak memory 206692 kb
Host smart-250387d0-14d2-40c8-8bf9-4a568cb1b9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331932361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2331932361
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.510508984
Short name T813
Test name
Test status
Simulation time 2780372274 ps
CPU time 6.55 seconds
Started Jun 26 06:24:34 PM PDT 24
Finished Jun 26 06:24:41 PM PDT 24
Peak memory 243044 kb
Host smart-6b01f891-1185-4899-ad27-fd8cae2b274b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510508984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.510508984
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2355237336
Short name T351
Test name
Test status
Simulation time 19183357 ps
CPU time 0.71 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:24:40 PM PDT 24
Peak memory 205792 kb
Host smart-c964782c-3354-4e52-88f6-bed140d505e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355237336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2355237336
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2250647548
Short name T528
Test name
Test status
Simulation time 1383804222 ps
CPU time 3.71 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:24:44 PM PDT 24
Peak memory 233648 kb
Host smart-feeb5366-3bfd-498a-87b1-8163162520a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250647548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2250647548
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1304372809
Short name T795
Test name
Test status
Simulation time 73529929 ps
CPU time 0.84 seconds
Started Jun 26 06:24:31 PM PDT 24
Finished Jun 26 06:24:34 PM PDT 24
Peak memory 207944 kb
Host smart-a75733aa-472c-47c9-82ec-29691c27170a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304372809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1304372809
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1637405733
Short name T249
Test name
Test status
Simulation time 4046075960 ps
CPU time 72.85 seconds
Started Jun 26 06:24:35 PM PDT 24
Finished Jun 26 06:25:49 PM PDT 24
Peak memory 258340 kb
Host smart-43785351-ef86-4620-a8ce-7c5e40ae57f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637405733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1637405733
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1342755757
Short name T923
Test name
Test status
Simulation time 8281055207 ps
CPU time 99.5 seconds
Started Jun 26 06:24:40 PM PDT 24
Finished Jun 26 06:26:21 PM PDT 24
Peak memory 257752 kb
Host smart-fc08af46-348e-41f7-aaac-8c3cc2146f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342755757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1342755757
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3167929629
Short name T245
Test name
Test status
Simulation time 40380400318 ps
CPU time 104.42 seconds
Started Jun 26 06:24:39 PM PDT 24
Finished Jun 26 06:26:25 PM PDT 24
Peak memory 266344 kb
Host smart-7e223a98-e89d-4985-9091-1136393d4245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167929629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3167929629
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1786828552
Short name T446
Test name
Test status
Simulation time 76395421 ps
CPU time 3.24 seconds
Started Jun 26 06:24:37 PM PDT 24
Finished Jun 26 06:24:42 PM PDT 24
Peak memory 233572 kb
Host smart-51afa75e-a5c7-4dc6-b3d6-d164e1ab757d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786828552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1786828552
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2844459941
Short name T224
Test name
Test status
Simulation time 601032271 ps
CPU time 7.71 seconds
Started Jun 26 06:24:36 PM PDT 24
Finished Jun 26 06:24:45 PM PDT 24
Peak memory 233600 kb
Host smart-0cb814c8-1c37-453c-b62b-a0247d10ce15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844459941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2844459941
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1319565737
Short name T92
Test name
Test status
Simulation time 945006624 ps
CPU time 13.25 seconds
Started Jun 26 06:24:36 PM PDT 24
Finished Jun 26 06:24:50 PM PDT 24
Peak memory 233596 kb
Host smart-fc1a673e-4e68-44d4-a7be-3c0bccc4376b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319565737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1319565737
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3709331282
Short name T229
Test name
Test status
Simulation time 5389956613 ps
CPU time 3.67 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:24:44 PM PDT 24
Peak memory 225528 kb
Host smart-296cd045-0fc0-4f69-a39e-007463c0d64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709331282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3709331282
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3503090640
Short name T746
Test name
Test status
Simulation time 3001718095 ps
CPU time 6.45 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:24:47 PM PDT 24
Peak memory 233720 kb
Host smart-88988583-db6c-4f27-a023-6847e76a1554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503090640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3503090640
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2435482059
Short name T880
Test name
Test status
Simulation time 155559410 ps
CPU time 3.76 seconds
Started Jun 26 06:24:37 PM PDT 24
Finished Jun 26 06:24:42 PM PDT 24
Peak memory 220348 kb
Host smart-502f31d9-4fee-4aac-b806-9ce868e756f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2435482059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2435482059
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.4170981779
Short name T213
Test name
Test status
Simulation time 281011169703 ps
CPU time 480.87 seconds
Started Jun 26 06:24:35 PM PDT 24
Finished Jun 26 06:32:37 PM PDT 24
Peak memory 282720 kb
Host smart-02748502-9a2a-45a0-8e05-941d7c690824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170981779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.4170981779
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.244189436
Short name T586
Test name
Test status
Simulation time 10734492527 ps
CPU time 18.66 seconds
Started Jun 26 06:24:37 PM PDT 24
Finished Jun 26 06:24:58 PM PDT 24
Peak memory 217292 kb
Host smart-f3574fcb-ea48-44e9-9e14-246e0a95c964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244189436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.244189436
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2918667668
Short name T336
Test name
Test status
Simulation time 1275761206 ps
CPU time 4.4 seconds
Started Jun 26 06:24:28 PM PDT 24
Finished Jun 26 06:24:34 PM PDT 24
Peak memory 217140 kb
Host smart-cbeecac8-2135-4936-92a3-60ebe49f7f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918667668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2918667668
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1314280691
Short name T335
Test name
Test status
Simulation time 12663967 ps
CPU time 0.82 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:24:41 PM PDT 24
Peak memory 206764 kb
Host smart-98608c08-a058-4961-938b-ffa3394800cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314280691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1314280691
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1056401569
Short name T415
Test name
Test status
Simulation time 69511394 ps
CPU time 0.75 seconds
Started Jun 26 06:24:39 PM PDT 24
Finished Jun 26 06:24:42 PM PDT 24
Peak memory 206748 kb
Host smart-07897a2b-a281-4693-a255-9e3033fb7d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056401569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1056401569
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1023451947
Short name T177
Test name
Test status
Simulation time 13956761615 ps
CPU time 14.75 seconds
Started Jun 26 06:24:37 PM PDT 24
Finished Jun 26 06:24:53 PM PDT 24
Peak memory 233648 kb
Host smart-a59c23e7-7d37-4f0a-87a2-3a0788c36add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023451947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1023451947
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4097947897
Short name T765
Test name
Test status
Simulation time 112909064 ps
CPU time 0.75 seconds
Started Jun 26 06:24:39 PM PDT 24
Finished Jun 26 06:24:42 PM PDT 24
Peak memory 206328 kb
Host smart-2c22df3b-de70-42e5-b56c-777a4de46bd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097947897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4097947897
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3383316814
Short name T893
Test name
Test status
Simulation time 54573073 ps
CPU time 2.99 seconds
Started Jun 26 06:24:40 PM PDT 24
Finished Jun 26 06:24:45 PM PDT 24
Peak memory 233576 kb
Host smart-58aa5b76-8602-42cf-841c-6ba38eb607aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383316814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3383316814
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1400309394
Short name T34
Test name
Test status
Simulation time 17009814 ps
CPU time 0.74 seconds
Started Jun 26 06:24:36 PM PDT 24
Finished Jun 26 06:24:38 PM PDT 24
Peak memory 206388 kb
Host smart-d961909e-70e7-48db-8cf3-221466b9cb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400309394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1400309394
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.168945375
Short name T722
Test name
Test status
Simulation time 56166322972 ps
CPU time 193.97 seconds
Started Jun 26 06:24:37 PM PDT 24
Finished Jun 26 06:27:52 PM PDT 24
Peak memory 250128 kb
Host smart-9d378af8-11db-4ed0-896b-bdf976717f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168945375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.168945375
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3237179360
Short name T628
Test name
Test status
Simulation time 10864101032 ps
CPU time 128.42 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:26:49 PM PDT 24
Peak memory 258392 kb
Host smart-f1589732-6678-431f-9bab-1d92b185dc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237179360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3237179360
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3795028007
Short name T617
Test name
Test status
Simulation time 139358899 ps
CPU time 3.45 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:24:43 PM PDT 24
Peak memory 233652 kb
Host smart-54957867-da30-4db2-b8d1-7c74b0c7adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795028007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3795028007
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2735414352
Short name T584
Test name
Test status
Simulation time 2350326258 ps
CPU time 21.67 seconds
Started Jun 26 06:24:36 PM PDT 24
Finished Jun 26 06:24:58 PM PDT 24
Peak memory 225616 kb
Host smart-e4377af4-f9f7-410c-9d26-9d67ed9c0d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735414352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2735414352
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2677060126
Short name T907
Test name
Test status
Simulation time 1213406199 ps
CPU time 11.85 seconds
Started Jun 26 06:24:42 PM PDT 24
Finished Jun 26 06:24:55 PM PDT 24
Peak memory 219728 kb
Host smart-6fab651a-7391-418e-aca6-947db8d8e5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677060126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2677060126
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4258009074
Short name T386
Test name
Test status
Simulation time 4364183988 ps
CPU time 7.27 seconds
Started Jun 26 06:24:40 PM PDT 24
Finished Jun 26 06:24:49 PM PDT 24
Peak memory 233780 kb
Host smart-8746f5b8-926d-42d6-9247-2eb7ab889009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258009074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4258009074
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3796840605
Short name T643
Test name
Test status
Simulation time 1772392729 ps
CPU time 7.68 seconds
Started Jun 26 06:24:37 PM PDT 24
Finished Jun 26 06:24:45 PM PDT 24
Peak memory 233656 kb
Host smart-604e4eb2-ce43-4424-ac45-e87f808baf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796840605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3796840605
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.42385558
Short name T562
Test name
Test status
Simulation time 356168513 ps
CPU time 5.08 seconds
Started Jun 26 06:24:34 PM PDT 24
Finished Jun 26 06:24:40 PM PDT 24
Peak memory 223936 kb
Host smart-bff2c63d-1fec-45ce-bb7f-433b8d281573
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=42385558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direc
t.42385558
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3921704418
Short name T851
Test name
Test status
Simulation time 261947008 ps
CPU time 5.1 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:24:45 PM PDT 24
Peak memory 225472 kb
Host smart-504b47b2-cc34-446e-9445-f04f2b1049ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921704418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3921704418
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2136356471
Short name T364
Test name
Test status
Simulation time 653143929 ps
CPU time 9.4 seconds
Started Jun 26 06:24:37 PM PDT 24
Finished Jun 26 06:24:47 PM PDT 24
Peak memory 220224 kb
Host smart-07e2b96a-b9ea-42c0-93e1-11311a0edd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136356471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2136356471
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2251716321
Short name T597
Test name
Test status
Simulation time 140456040 ps
CPU time 1.25 seconds
Started Jun 26 06:24:37 PM PDT 24
Finished Jun 26 06:24:39 PM PDT 24
Peak memory 207964 kb
Host smart-e1be83b4-2a81-47fe-ae11-6ae6a6a7797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251716321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2251716321
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1554748197
Short name T928
Test name
Test status
Simulation time 93687513 ps
CPU time 1.4 seconds
Started Jun 26 06:24:39 PM PDT 24
Finished Jun 26 06:24:42 PM PDT 24
Peak memory 208904 kb
Host smart-2b4454eb-950f-4e08-ba43-b6f5076ea4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554748197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1554748197
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1191759752
Short name T810
Test name
Test status
Simulation time 39974677 ps
CPU time 0.82 seconds
Started Jun 26 06:24:41 PM PDT 24
Finished Jun 26 06:24:43 PM PDT 24
Peak memory 206744 kb
Host smart-39fa09c8-94d3-4f85-97d0-39c8bcce3dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191759752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1191759752
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.179564800
Short name T769
Test name
Test status
Simulation time 17778535645 ps
CPU time 19.86 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:25:00 PM PDT 24
Peak memory 233704 kb
Host smart-6cc02994-4262-4286-9a9e-a1b67adcd92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179564800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.179564800
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.582684772
Short name T538
Test name
Test status
Simulation time 10597892 ps
CPU time 0.72 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:24:41 PM PDT 24
Peak memory 206340 kb
Host smart-2eed5145-9130-4484-9731-ed5d13b421d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582684772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.582684772
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1987474983
Short name T645
Test name
Test status
Simulation time 241885620 ps
CPU time 4.07 seconds
Started Jun 26 06:24:35 PM PDT 24
Finished Jun 26 06:24:40 PM PDT 24
Peak memory 233544 kb
Host smart-04535af6-701d-4c46-b407-dc148a483968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987474983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1987474983
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4196949257
Short name T690
Test name
Test status
Simulation time 16642079 ps
CPU time 0.77 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:24:40 PM PDT 24
Peak memory 206280 kb
Host smart-a7e76c17-ada7-4b0a-b517-0eb67d1cb44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196949257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4196949257
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2324729525
Short name T653
Test name
Test status
Simulation time 20653535016 ps
CPU time 63.93 seconds
Started Jun 26 06:24:41 PM PDT 24
Finished Jun 26 06:25:46 PM PDT 24
Peak memory 250216 kb
Host smart-efdb7d5e-82ef-420a-a386-ca39786ee484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324729525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2324729525
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2134918809
Short name T845
Test name
Test status
Simulation time 123964682090 ps
CPU time 88.45 seconds
Started Jun 26 06:24:39 PM PDT 24
Finished Jun 26 06:26:09 PM PDT 24
Peak memory 250184 kb
Host smart-70024ccf-db11-433f-957a-35d653de3bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134918809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2134918809
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1677283797
Short name T273
Test name
Test status
Simulation time 469865721 ps
CPU time 10.74 seconds
Started Jun 26 06:24:42 PM PDT 24
Finished Jun 26 06:24:54 PM PDT 24
Peak memory 233604 kb
Host smart-46412cd5-510d-4bbf-96b6-5c5322b7a40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677283797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1677283797
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.627727424
Short name T362
Test name
Test status
Simulation time 3906025925 ps
CPU time 12.35 seconds
Started Jun 26 06:24:41 PM PDT 24
Finished Jun 26 06:24:55 PM PDT 24
Peak memory 233736 kb
Host smart-0469c43d-1a7c-4954-be2f-7bc2e12e8b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627727424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.627727424
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2602812295
Short name T667
Test name
Test status
Simulation time 12807526678 ps
CPU time 28.16 seconds
Started Jun 26 06:24:36 PM PDT 24
Finished Jun 26 06:25:05 PM PDT 24
Peak memory 225536 kb
Host smart-80eb95de-829e-4c39-b650-0ff592c7c473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602812295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2602812295
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1788681058
Short name T15
Test name
Test status
Simulation time 2518285133 ps
CPU time 9.79 seconds
Started Jun 26 06:24:36 PM PDT 24
Finished Jun 26 06:24:47 PM PDT 24
Peak memory 225584 kb
Host smart-87634ab5-58d8-445a-a3dd-d3f8cdfda303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788681058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1788681058
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1616296269
Short name T616
Test name
Test status
Simulation time 19672413152 ps
CPU time 31.67 seconds
Started Jun 26 06:24:36 PM PDT 24
Finished Jun 26 06:25:08 PM PDT 24
Peak memory 241852 kb
Host smart-18da7797-4515-416d-814d-3086f409197a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616296269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1616296269
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3873518953
Short name T137
Test name
Test status
Simulation time 636831140 ps
CPU time 4.51 seconds
Started Jun 26 06:24:35 PM PDT 24
Finished Jun 26 06:24:40 PM PDT 24
Peak memory 224100 kb
Host smart-341c77f1-55f0-4d92-8327-b68b5bbf6e61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3873518953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3873518953
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1818844994
Short name T30
Test name
Test status
Simulation time 84313523 ps
CPU time 1.09 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:24:41 PM PDT 24
Peak memory 207728 kb
Host smart-8ec122d7-7472-404f-9a2b-d35d7a7a0718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818844994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1818844994
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1256563134
Short name T99
Test name
Test status
Simulation time 9601675068 ps
CPU time 16.34 seconds
Started Jun 26 06:24:39 PM PDT 24
Finished Jun 26 06:24:57 PM PDT 24
Peak memory 217228 kb
Host smart-f7c179e4-a266-4c08-aec1-c2251199371e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256563134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1256563134
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3687012526
Short name T711
Test name
Test status
Simulation time 14912996 ps
CPU time 0.73 seconds
Started Jun 26 06:24:39 PM PDT 24
Finished Jun 26 06:24:42 PM PDT 24
Peak memory 206528 kb
Host smart-9c8a8324-b95c-4f9b-b9c0-26119a263acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687012526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3687012526
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1329353406
Short name T506
Test name
Test status
Simulation time 21273955 ps
CPU time 0.89 seconds
Started Jun 26 06:24:36 PM PDT 24
Finished Jun 26 06:24:38 PM PDT 24
Peak memory 207760 kb
Host smart-3bdebd0a-976d-444f-816d-cb832c1d9663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329353406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1329353406
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.290320543
Short name T816
Test name
Test status
Simulation time 126001285 ps
CPU time 0.78 seconds
Started Jun 26 06:24:37 PM PDT 24
Finished Jun 26 06:24:39 PM PDT 24
Peak memory 206764 kb
Host smart-e5e6d514-4fda-494f-8862-86f63b721e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290320543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.290320543
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3108589352
Short name T860
Test name
Test status
Simulation time 815357318 ps
CPU time 3.1 seconds
Started Jun 26 06:24:38 PM PDT 24
Finished Jun 26 06:24:44 PM PDT 24
Peak memory 233660 kb
Host smart-938dab3d-ccfe-4d76-ad57-798ed452790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108589352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3108589352
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.253128337
Short name T633
Test name
Test status
Simulation time 15969742 ps
CPU time 0.79 seconds
Started Jun 26 06:24:46 PM PDT 24
Finished Jun 26 06:24:49 PM PDT 24
Peak memory 206284 kb
Host smart-2e57e594-6cae-4221-8134-088661f70bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253128337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.253128337
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.228238928
Short name T958
Test name
Test status
Simulation time 1736577655 ps
CPU time 4.9 seconds
Started Jun 26 06:24:51 PM PDT 24
Finished Jun 26 06:24:57 PM PDT 24
Peak memory 225368 kb
Host smart-6ffdfaac-1baa-44cd-aa8f-65b256c5589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228238928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.228238928
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.768771391
Short name T283
Test name
Test status
Simulation time 35185529 ps
CPU time 0.8 seconds
Started Jun 26 06:24:36 PM PDT 24
Finished Jun 26 06:24:38 PM PDT 24
Peak memory 207416 kb
Host smart-a197e57f-ac41-400a-9359-bd647aa5c5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768771391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.768771391
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2593772897
Short name T49
Test name
Test status
Simulation time 17315479965 ps
CPU time 113.72 seconds
Started Jun 26 06:24:43 PM PDT 24
Finished Jun 26 06:26:38 PM PDT 24
Peak memory 257440 kb
Host smart-1f42339c-7922-4dae-a114-e3981bb649e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593772897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2593772897
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3753431254
Short name T812
Test name
Test status
Simulation time 6605438731 ps
CPU time 48.52 seconds
Started Jun 26 06:24:49 PM PDT 24
Finished Jun 26 06:25:38 PM PDT 24
Peak memory 251136 kb
Host smart-9b185b5f-12e0-45d4-82a5-cd3a7b171774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753431254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3753431254
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.902593267
Short name T156
Test name
Test status
Simulation time 5423489399 ps
CPU time 42.87 seconds
Started Jun 26 06:24:46 PM PDT 24
Finished Jun 26 06:25:30 PM PDT 24
Peak memory 251128 kb
Host smart-dccef828-c62c-4e2a-b5d3-e35f266c4d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902593267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.902593267
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1701282408
Short name T681
Test name
Test status
Simulation time 667129442 ps
CPU time 6.74 seconds
Started Jun 26 06:24:44 PM PDT 24
Finished Jun 26 06:24:52 PM PDT 24
Peak memory 225432 kb
Host smart-fde4358a-dd84-46c1-94d0-8e0bad1edf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701282408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1701282408
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1824092105
Short name T100
Test name
Test status
Simulation time 73933561 ps
CPU time 3.21 seconds
Started Jun 26 06:24:48 PM PDT 24
Finished Jun 26 06:24:52 PM PDT 24
Peak memory 225372 kb
Host smart-86d9bd86-0d87-44f5-83c0-d7d76570770e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824092105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1824092105
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.99369393
Short name T631
Test name
Test status
Simulation time 4444781313 ps
CPU time 42.25 seconds
Started Jun 26 06:24:47 PM PDT 24
Finished Jun 26 06:25:31 PM PDT 24
Peak memory 241444 kb
Host smart-90a3a6ec-8bc9-4875-9ba0-c7335ab6a89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99369393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.99369393
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4289341895
Short name T583
Test name
Test status
Simulation time 28359483833 ps
CPU time 20.51 seconds
Started Jun 26 06:24:46 PM PDT 24
Finished Jun 26 06:25:08 PM PDT 24
Peak memory 235584 kb
Host smart-2ff73d9c-5a0c-49c5-9e59-8c901cc6cf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289341895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4289341895
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.888754983
Short name T900
Test name
Test status
Simulation time 1866390942 ps
CPU time 6.27 seconds
Started Jun 26 06:24:46 PM PDT 24
Finished Jun 26 06:24:53 PM PDT 24
Peak memory 233676 kb
Host smart-f600d198-247c-4ac3-af5a-4b03f5ed4290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888754983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.888754983
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2749136953
Short name T829
Test name
Test status
Simulation time 3192147755 ps
CPU time 10.77 seconds
Started Jun 26 06:24:47 PM PDT 24
Finished Jun 26 06:24:59 PM PDT 24
Peak memory 224160 kb
Host smart-7d63efd5-e87f-4d40-9d79-3a5b2a8b24be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2749136953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2749136953
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.126492445
Short name T32
Test name
Test status
Simulation time 25799042585 ps
CPU time 194.92 seconds
Started Jun 26 06:24:44 PM PDT 24
Finished Jun 26 06:28:00 PM PDT 24
Peak memory 234028 kb
Host smart-2c18dd5c-01fa-4548-b1bc-1447fd63ee9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126492445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.126492445
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3008025361
Short name T356
Test name
Test status
Simulation time 5171998943 ps
CPU time 14.53 seconds
Started Jun 26 06:24:36 PM PDT 24
Finished Jun 26 06:24:52 PM PDT 24
Peak memory 217200 kb
Host smart-058afe5b-898b-4c09-b96c-d90e2ad01212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008025361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3008025361
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2593469060
Short name T587
Test name
Test status
Simulation time 6095701837 ps
CPU time 8.43 seconds
Started Jun 26 06:24:36 PM PDT 24
Finished Jun 26 06:24:46 PM PDT 24
Peak memory 217220 kb
Host smart-1657d90e-28b4-4607-9e61-77dc910edffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593469060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2593469060
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2901185089
Short name T782
Test name
Test status
Simulation time 12607417 ps
CPU time 0.74 seconds
Started Jun 26 06:24:46 PM PDT 24
Finished Jun 26 06:24:48 PM PDT 24
Peak memory 206468 kb
Host smart-02e7c2cf-d2fe-486a-a26f-087e10ee6aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901185089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2901185089
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1914455211
Short name T23
Test name
Test status
Simulation time 31701024 ps
CPU time 0.76 seconds
Started Jun 26 06:24:43 PM PDT 24
Finished Jun 26 06:24:45 PM PDT 24
Peak memory 206636 kb
Host smart-150def2b-430e-4b1c-9a55-6f030bcbd198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914455211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1914455211
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3032234817
Short name T750
Test name
Test status
Simulation time 2463207022 ps
CPU time 9.67 seconds
Started Jun 26 06:24:50 PM PDT 24
Finished Jun 26 06:25:01 PM PDT 24
Peak memory 233696 kb
Host smart-0f49b502-37d8-4991-a4a6-162e05d56821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032234817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3032234817
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.492150469
Short name T449
Test name
Test status
Simulation time 14693612 ps
CPU time 0.73 seconds
Started Jun 26 06:24:43 PM PDT 24
Finished Jun 26 06:24:45 PM PDT 24
Peak memory 205728 kb
Host smart-d76701f2-b40f-45f2-955f-58fb3826efb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492150469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.492150469
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3324930993
Short name T822
Test name
Test status
Simulation time 1021616251 ps
CPU time 11.34 seconds
Started Jun 26 06:24:44 PM PDT 24
Finished Jun 26 06:24:56 PM PDT 24
Peak memory 233584 kb
Host smart-af422178-bd50-4ce7-85dc-dbced314b459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324930993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3324930993
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1974193872
Short name T303
Test name
Test status
Simulation time 15370241 ps
CPU time 0.75 seconds
Started Jun 26 06:24:50 PM PDT 24
Finished Jun 26 06:24:52 PM PDT 24
Peak memory 206728 kb
Host smart-ba7ac4a9-47cf-408f-b706-c1ea96287af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974193872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1974193872
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1769144
Short name T494
Test name
Test status
Simulation time 797556796 ps
CPU time 15.36 seconds
Started Jun 26 06:24:48 PM PDT 24
Finished Jun 26 06:25:05 PM PDT 24
Peak memory 239188 kb
Host smart-658d505d-4e34-4fbc-b940-7718bc1d883e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1769144
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.654184384
Short name T437
Test name
Test status
Simulation time 39887391959 ps
CPU time 40.22 seconds
Started Jun 26 06:24:46 PM PDT 24
Finished Jun 26 06:25:27 PM PDT 24
Peak memory 225636 kb
Host smart-d5130566-c32b-4181-9035-9141a550b13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654184384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.654184384
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.646988994
Short name T54
Test name
Test status
Simulation time 104218720758 ps
CPU time 234.23 seconds
Started Jun 26 06:24:44 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 254692 kb
Host smart-64bb85c6-e744-4b50-8a90-b5922253ab53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646988994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.646988994
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3986682771
Short name T622
Test name
Test status
Simulation time 671942190 ps
CPU time 5.1 seconds
Started Jun 26 06:24:46 PM PDT 24
Finished Jun 26 06:24:52 PM PDT 24
Peak memory 233676 kb
Host smart-b3ccb5ea-8b8d-4622-ba6a-283ec935b9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986682771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3986682771
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2581609630
Short name T426
Test name
Test status
Simulation time 1711058502 ps
CPU time 12.96 seconds
Started Jun 26 06:24:44 PM PDT 24
Finished Jun 26 06:24:57 PM PDT 24
Peak memory 233612 kb
Host smart-a17c1631-3b28-4291-88cb-dd95a5978c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581609630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2581609630
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3083776947
Short name T902
Test name
Test status
Simulation time 3220335969 ps
CPU time 13.09 seconds
Started Jun 26 06:24:44 PM PDT 24
Finished Jun 26 06:24:58 PM PDT 24
Peak memory 233760 kb
Host smart-e1f97f7f-2ec7-48de-aece-d0a1572ae18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083776947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3083776947
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2823480939
Short name T847
Test name
Test status
Simulation time 65686812 ps
CPU time 2.47 seconds
Started Jun 26 06:24:46 PM PDT 24
Finished Jun 26 06:24:50 PM PDT 24
Peak memory 233328 kb
Host smart-a87cebba-3713-41f2-b73b-58036ec252dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823480939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2823480939
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3470424271
Short name T552
Test name
Test status
Simulation time 294163710 ps
CPU time 3.81 seconds
Started Jun 26 06:24:48 PM PDT 24
Finished Jun 26 06:24:53 PM PDT 24
Peak memory 219764 kb
Host smart-44919a09-2129-4e42-a399-27b752841ce1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3470424271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3470424271
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1531972756
Short name T613
Test name
Test status
Simulation time 38644952 ps
CPU time 1.04 seconds
Started Jun 26 06:24:47 PM PDT 24
Finished Jun 26 06:24:49 PM PDT 24
Peak memory 207608 kb
Host smart-9dadd7a3-e3c0-4cfb-8a32-c0ff135918e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531972756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1531972756
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.475614796
Short name T339
Test name
Test status
Simulation time 1539851977 ps
CPU time 24.7 seconds
Started Jun 26 06:24:45 PM PDT 24
Finished Jun 26 06:25:11 PM PDT 24
Peak memory 217028 kb
Host smart-e0b54915-f2b6-460c-a689-297758ba3b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475614796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.475614796
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4251305841
Short name T483
Test name
Test status
Simulation time 4971453995 ps
CPU time 4.82 seconds
Started Jun 26 06:24:47 PM PDT 24
Finished Jun 26 06:24:53 PM PDT 24
Peak memory 217144 kb
Host smart-66bbf95d-5137-43cc-b1ac-535c7ac5b713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251305841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4251305841
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1211483429
Short name T955
Test name
Test status
Simulation time 450998444 ps
CPU time 2.68 seconds
Started Jun 26 06:24:45 PM PDT 24
Finished Jun 26 06:24:49 PM PDT 24
Peak memory 217128 kb
Host smart-a5ecb7bb-ae77-4417-b6b7-71d43a80fd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211483429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1211483429
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3483109650
Short name T403
Test name
Test status
Simulation time 48291169 ps
CPU time 0.78 seconds
Started Jun 26 06:24:47 PM PDT 24
Finished Jun 26 06:24:49 PM PDT 24
Peak memory 206720 kb
Host smart-486499b9-8c3b-475b-b628-b6b8b38508af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483109650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3483109650
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1835183960
Short name T411
Test name
Test status
Simulation time 3219923111 ps
CPU time 11.17 seconds
Started Jun 26 06:24:45 PM PDT 24
Finished Jun 26 06:24:57 PM PDT 24
Peak memory 233732 kb
Host smart-7162f3d8-6c75-4992-99d4-7e3337fb9aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835183960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1835183960
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.544167664
Short name T918
Test name
Test status
Simulation time 14514998 ps
CPU time 0.76 seconds
Started Jun 26 06:24:54 PM PDT 24
Finished Jun 26 06:24:56 PM PDT 24
Peak memory 205760 kb
Host smart-9d2568db-a73b-49e3-8b3d-8ba780216af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544167664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.544167664
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1801942520
Short name T419
Test name
Test status
Simulation time 8282332688 ps
CPU time 15.48 seconds
Started Jun 26 06:24:46 PM PDT 24
Finished Jun 26 06:25:03 PM PDT 24
Peak memory 233732 kb
Host smart-55d9786d-a849-4d79-9ceb-d2e58fbeb055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801942520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1801942520
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4230362944
Short name T571
Test name
Test status
Simulation time 29119857 ps
CPU time 0.81 seconds
Started Jun 26 06:24:48 PM PDT 24
Finished Jun 26 06:24:50 PM PDT 24
Peak memory 207384 kb
Host smart-420a8a6e-40ba-4318-81d1-90c43a323728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230362944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4230362944
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1758864437
Short name T878
Test name
Test status
Simulation time 31354491242 ps
CPU time 120.62 seconds
Started Jun 26 06:24:45 PM PDT 24
Finished Jun 26 06:26:46 PM PDT 24
Peak memory 258376 kb
Host smart-f930dc91-4d1d-4883-94d8-775d1276bb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758864437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1758864437
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.26459137
Short name T43
Test name
Test status
Simulation time 2286089270 ps
CPU time 27.94 seconds
Started Jun 26 06:24:46 PM PDT 24
Finished Jun 26 06:25:15 PM PDT 24
Peak memory 250172 kb
Host smart-61629bab-b987-4643-8946-3901207aceae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26459137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.26459137
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3708555495
Short name T191
Test name
Test status
Simulation time 53075699384 ps
CPU time 111.22 seconds
Started Jun 26 06:24:51 PM PDT 24
Finished Jun 26 06:26:43 PM PDT 24
Peak memory 241720 kb
Host smart-4faa2762-0ee5-4e8a-b131-e26cde002364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708555495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3708555495
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.53712359
Short name T762
Test name
Test status
Simulation time 539133948 ps
CPU time 6.3 seconds
Started Jun 26 06:24:48 PM PDT 24
Finished Jun 26 06:24:55 PM PDT 24
Peak memory 241768 kb
Host smart-73dab2a3-01d4-49d8-bcb8-dac167d374f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53712359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.53712359
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1411784567
Short name T523
Test name
Test status
Simulation time 391494426 ps
CPU time 2.81 seconds
Started Jun 26 06:24:43 PM PDT 24
Finished Jun 26 06:24:46 PM PDT 24
Peak memory 233676 kb
Host smart-aead15c2-db34-4f93-8077-3ff943a5a427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411784567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1411784567
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1975321504
Short name T214
Test name
Test status
Simulation time 38773500537 ps
CPU time 98.09 seconds
Started Jun 26 06:24:48 PM PDT 24
Finished Jun 26 06:26:27 PM PDT 24
Peak memory 233700 kb
Host smart-141f1020-6047-485c-98b0-daa5f54d96ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975321504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1975321504
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3111235553
Short name T321
Test name
Test status
Simulation time 1160318644 ps
CPU time 3.15 seconds
Started Jun 26 06:24:50 PM PDT 24
Finished Jun 26 06:24:54 PM PDT 24
Peak memory 233608 kb
Host smart-efb2ca92-91d8-458b-932d-b24d99b40ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111235553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3111235553
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.973385687
Short name T542
Test name
Test status
Simulation time 1433897856 ps
CPU time 3.49 seconds
Started Jun 26 06:24:47 PM PDT 24
Finished Jun 26 06:24:52 PM PDT 24
Peak memory 225412 kb
Host smart-238b800e-665b-47d7-b4aa-c0c650361603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973385687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.973385687
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.527584211
Short name T672
Test name
Test status
Simulation time 610665579 ps
CPU time 3.97 seconds
Started Jun 26 06:24:46 PM PDT 24
Finished Jun 26 06:24:52 PM PDT 24
Peak memory 223628 kb
Host smart-ea6e23a0-e693-49a0-9328-964a16593272
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=527584211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.527584211
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.928357735
Short name T601
Test name
Test status
Simulation time 9959849491 ps
CPU time 27.85 seconds
Started Jun 26 06:24:45 PM PDT 24
Finished Jun 26 06:25:14 PM PDT 24
Peak memory 217260 kb
Host smart-1d919a7e-315d-444f-a237-4c83dec1bf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928357735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.928357735
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1547108677
Short name T87
Test name
Test status
Simulation time 2886953999 ps
CPU time 7.18 seconds
Started Jun 26 06:24:50 PM PDT 24
Finished Jun 26 06:24:58 PM PDT 24
Peak memory 217248 kb
Host smart-fd622d72-388e-4132-a795-fef1255aa85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547108677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1547108677
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1634642368
Short name T319
Test name
Test status
Simulation time 215728874 ps
CPU time 2.29 seconds
Started Jun 26 06:24:46 PM PDT 24
Finished Jun 26 06:24:50 PM PDT 24
Peak memory 216988 kb
Host smart-3e178856-fabd-4747-9a61-6a4eafcf27d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634642368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1634642368
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.802698326
Short name T658
Test name
Test status
Simulation time 175068265 ps
CPU time 0.81 seconds
Started Jun 26 06:24:46 PM PDT 24
Finished Jun 26 06:24:48 PM PDT 24
Peak memory 206672 kb
Host smart-80c2ea2e-238b-4d05-8d4f-6c4ec9dc80db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802698326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.802698326
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3721755555
Short name T205
Test name
Test status
Simulation time 2310516151 ps
CPU time 12.34 seconds
Started Jun 26 06:24:48 PM PDT 24
Finished Jun 26 06:25:01 PM PDT 24
Peak memory 233784 kb
Host smart-3c6f73a1-a150-41a1-9f09-2bdaab3c19d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721755555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3721755555
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.4245663319
Short name T924
Test name
Test status
Simulation time 48243010 ps
CPU time 0.75 seconds
Started Jun 26 06:24:52 PM PDT 24
Finished Jun 26 06:24:54 PM PDT 24
Peak memory 206292 kb
Host smart-39b68f52-9585-4e7d-bdc7-5b8878c51194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245663319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
4245663319
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2619453588
Short name T432
Test name
Test status
Simulation time 1209014445 ps
CPU time 3.39 seconds
Started Jun 26 06:24:53 PM PDT 24
Finished Jun 26 06:24:57 PM PDT 24
Peak memory 225300 kb
Host smart-423a37c4-9266-488d-a17a-d7e96279b6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619453588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2619453588
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1369412260
Short name T16
Test name
Test status
Simulation time 15284170 ps
CPU time 0.76 seconds
Started Jun 26 06:24:52 PM PDT 24
Finished Jun 26 06:24:53 PM PDT 24
Peak memory 206732 kb
Host smart-1ad7878b-69f2-42c3-8655-8c9f1927903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369412260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1369412260
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3617571579
Short name T684
Test name
Test status
Simulation time 2730117808 ps
CPU time 17.5 seconds
Started Jun 26 06:24:53 PM PDT 24
Finished Jun 26 06:25:12 PM PDT 24
Peak memory 233728 kb
Host smart-83da5007-2fd1-4a74-9ea8-e5a815a98207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617571579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3617571579
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1778071791
Short name T387
Test name
Test status
Simulation time 16725901554 ps
CPU time 160.55 seconds
Started Jun 26 06:24:52 PM PDT 24
Finished Jun 26 06:27:34 PM PDT 24
Peak memory 256560 kb
Host smart-7e7793a3-1b81-4012-8bcd-d8ae41274474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778071791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1778071791
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1538203251
Short name T635
Test name
Test status
Simulation time 1668364882 ps
CPU time 12.9 seconds
Started Jun 26 06:24:53 PM PDT 24
Finished Jun 26 06:25:08 PM PDT 24
Peak memory 250852 kb
Host smart-a02aa939-3677-4a63-ae1f-467264bf578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538203251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1538203251
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3851093366
Short name T873
Test name
Test status
Simulation time 3507120553 ps
CPU time 10.9 seconds
Started Jun 26 06:24:52 PM PDT 24
Finished Jun 26 06:25:04 PM PDT 24
Peak memory 233768 kb
Host smart-403d940f-36f6-4384-9895-e03c2a8d4a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851093366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3851093366
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1388859010
Short name T952
Test name
Test status
Simulation time 2712025379 ps
CPU time 19.82 seconds
Started Jun 26 06:24:54 PM PDT 24
Finished Jun 26 06:25:15 PM PDT 24
Peak memory 250448 kb
Host smart-1f6bfef5-f52a-4c5c-87a1-7cb66d78165e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388859010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1388859010
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3236791492
Short name T180
Test name
Test status
Simulation time 4322028325 ps
CPU time 14.91 seconds
Started Jun 26 06:24:52 PM PDT 24
Finished Jun 26 06:25:08 PM PDT 24
Peak memory 225452 kb
Host smart-d5ec3e58-0d5f-4451-a410-da6391596397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236791492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3236791492
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1277029008
Short name T655
Test name
Test status
Simulation time 22073129064 ps
CPU time 17.95 seconds
Started Jun 26 06:24:55 PM PDT 24
Finished Jun 26 06:25:14 PM PDT 24
Peak memory 233736 kb
Host smart-d6b60daf-7511-46eb-9222-6af5b0888e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277029008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1277029008
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.925130932
Short name T135
Test name
Test status
Simulation time 15692800943 ps
CPU time 14.08 seconds
Started Jun 26 06:24:55 PM PDT 24
Finished Jun 26 06:25:10 PM PDT 24
Peak memory 224140 kb
Host smart-37ce99c0-4dec-4696-92b4-cdb18974de57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=925130932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.925130932
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3911380128
Short name T470
Test name
Test status
Simulation time 2272480755 ps
CPU time 14.41 seconds
Started Jun 26 06:24:54 PM PDT 24
Finished Jun 26 06:25:10 PM PDT 24
Peak memory 217248 kb
Host smart-c75afdb9-e152-49fb-b1fd-2bb0a8ca2d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911380128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3911380128
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1739942392
Short name T301
Test name
Test status
Simulation time 1033913622 ps
CPU time 2.29 seconds
Started Jun 26 06:24:51 PM PDT 24
Finished Jun 26 06:24:54 PM PDT 24
Peak memory 216884 kb
Host smart-2e9d46b3-5e10-4837-aa0b-f6a1c7a2d61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739942392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1739942392
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.984232358
Short name T357
Test name
Test status
Simulation time 203107848 ps
CPU time 1.86 seconds
Started Jun 26 06:24:52 PM PDT 24
Finished Jun 26 06:24:55 PM PDT 24
Peak memory 217096 kb
Host smart-16c64173-1b88-491f-a991-f55868af68cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984232358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.984232358
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1576827182
Short name T747
Test name
Test status
Simulation time 444518258 ps
CPU time 0.94 seconds
Started Jun 26 06:24:51 PM PDT 24
Finished Jun 26 06:24:53 PM PDT 24
Peak memory 206716 kb
Host smart-466b562d-ce83-4157-988c-d725c446f919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576827182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1576827182
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.428425031
Short name T846
Test name
Test status
Simulation time 9891318381 ps
CPU time 8.22 seconds
Started Jun 26 06:24:51 PM PDT 24
Finished Jun 26 06:25:00 PM PDT 24
Peak memory 240588 kb
Host smart-473d6281-176d-4b92-87ba-e63235342e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428425031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.428425031
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2226893977
Short name T729
Test name
Test status
Simulation time 30197031 ps
CPU time 0.7 seconds
Started Jun 26 06:23:34 PM PDT 24
Finished Jun 26 06:23:37 PM PDT 24
Peak memory 206376 kb
Host smart-50c52c98-ba26-4302-8678-6906b70f2728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226893977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
226893977
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2761436969
Short name T830
Test name
Test status
Simulation time 696623289 ps
CPU time 7.86 seconds
Started Jun 26 06:24:04 PM PDT 24
Finished Jun 26 06:24:13 PM PDT 24
Peak memory 224788 kb
Host smart-e51dd44f-4545-453c-ad11-c91f7e64b5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761436969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2761436969
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3364193511
Short name T125
Test name
Test status
Simulation time 35581226 ps
CPU time 0.87 seconds
Started Jun 26 06:23:25 PM PDT 24
Finished Jun 26 06:23:27 PM PDT 24
Peak memory 207740 kb
Host smart-ff642ae1-ab90-4e20-95c4-65fa2d7193bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364193511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3364193511
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3768675170
Short name T678
Test name
Test status
Simulation time 55801913 ps
CPU time 0.92 seconds
Started Jun 26 06:23:35 PM PDT 24
Finished Jun 26 06:23:37 PM PDT 24
Peak memory 216996 kb
Host smart-deef0933-b0d9-40df-ac8d-f56107e7e4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768675170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3768675170
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2605189684
Short name T792
Test name
Test status
Simulation time 34867676104 ps
CPU time 153.18 seconds
Started Jun 26 06:23:34 PM PDT 24
Finished Jun 26 06:26:09 PM PDT 24
Peak memory 251180 kb
Host smart-b2f9c39f-51ea-4401-bf32-9352a99f6f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605189684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2605189684
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2434085023
Short name T46
Test name
Test status
Simulation time 4161808084 ps
CPU time 21.46 seconds
Started Jun 26 06:23:34 PM PDT 24
Finished Jun 26 06:23:57 PM PDT 24
Peak memory 251436 kb
Host smart-a2969ad7-6ac7-407e-8429-3415188dc878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434085023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2434085023
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1266989786
Short name T570
Test name
Test status
Simulation time 843201041 ps
CPU time 16.45 seconds
Started Jun 26 06:23:33 PM PDT 24
Finished Jun 26 06:23:50 PM PDT 24
Peak memory 233612 kb
Host smart-1f0ff069-4baa-46c8-82d4-c7e811066e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266989786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1266989786
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.640790490
Short name T365
Test name
Test status
Simulation time 151355574 ps
CPU time 4.01 seconds
Started Jun 26 06:23:35 PM PDT 24
Finished Jun 26 06:23:41 PM PDT 24
Peak memory 225472 kb
Host smart-fb90bbe9-bd51-43db-b8ae-bd835c4eed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640790490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.640790490
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1133057547
Short name T217
Test name
Test status
Simulation time 73189748311 ps
CPU time 123.43 seconds
Started Jun 26 06:23:34 PM PDT 24
Finished Jun 26 06:25:40 PM PDT 24
Peak memory 225516 kb
Host smart-2e698edf-17d6-481c-b02c-c036d22743ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133057547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1133057547
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3751539999
Short name T434
Test name
Test status
Simulation time 30558530 ps
CPU time 2.18 seconds
Started Jun 26 06:23:27 PM PDT 24
Finished Jun 26 06:23:31 PM PDT 24
Peak memory 225284 kb
Host smart-6a6a69d3-b1c9-4b86-ba51-1ea6c2d5a503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751539999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3751539999
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3737559855
Short name T698
Test name
Test status
Simulation time 1080378180 ps
CPU time 4.51 seconds
Started Jun 26 06:23:28 PM PDT 24
Finished Jun 26 06:23:35 PM PDT 24
Peak memory 225368 kb
Host smart-0250e0ae-23fb-427e-83c3-1c730d92336b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737559855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3737559855
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1585151305
Short name T787
Test name
Test status
Simulation time 731123849 ps
CPU time 8.77 seconds
Started Jun 26 06:23:34 PM PDT 24
Finished Jun 26 06:23:45 PM PDT 24
Peak memory 220848 kb
Host smart-f699e78a-4762-46e8-a184-90dff27afed8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1585151305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1585151305
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2871522281
Short name T70
Test name
Test status
Simulation time 38711964 ps
CPU time 1.02 seconds
Started Jun 26 06:23:35 PM PDT 24
Finished Jun 26 06:23:38 PM PDT 24
Peak memory 237068 kb
Host smart-15a04701-51f4-4882-9345-dec606627fab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871522281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2871522281
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.374088957
Short name T798
Test name
Test status
Simulation time 2906002893 ps
CPU time 3.09 seconds
Started Jun 26 06:23:26 PM PDT 24
Finished Jun 26 06:23:32 PM PDT 24
Peak memory 208816 kb
Host smart-10e960ea-5632-4421-9e10-4d72fd1ba553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374088957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.374088957
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1163543272
Short name T277
Test name
Test status
Simulation time 136841611 ps
CPU time 4.94 seconds
Started Jun 26 06:23:29 PM PDT 24
Finished Jun 26 06:23:36 PM PDT 24
Peak memory 217072 kb
Host smart-96d4dfdc-2280-43f7-abd1-4805aa836e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163543272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1163543272
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.119876555
Short name T467
Test name
Test status
Simulation time 98506290 ps
CPU time 1 seconds
Started Jun 26 06:23:23 PM PDT 24
Finished Jun 26 06:23:25 PM PDT 24
Peak memory 206632 kb
Host smart-cf4e1a4d-cb4f-4eb2-873b-5e2066c6ca63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119876555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.119876555
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3189139564
Short name T761
Test name
Test status
Simulation time 2853056880 ps
CPU time 8.38 seconds
Started Jun 26 06:23:33 PM PDT 24
Finished Jun 26 06:23:42 PM PDT 24
Peak memory 225524 kb
Host smart-8ee1c513-bbd3-47c9-9863-ea219237e311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189139564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3189139564
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3956425320
Short name T428
Test name
Test status
Simulation time 12929839 ps
CPU time 0.73 seconds
Started Jun 26 06:25:01 PM PDT 24
Finished Jun 26 06:25:03 PM PDT 24
Peak memory 205740 kb
Host smart-fd8a6c1a-71e1-4a73-9b62-0f8f0e70ad31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956425320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3956425320
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.389767331
Short name T758
Test name
Test status
Simulation time 2572963140 ps
CPU time 8.25 seconds
Started Jun 26 06:24:52 PM PDT 24
Finished Jun 26 06:25:01 PM PDT 24
Peak memory 233768 kb
Host smart-8cb7ac42-441d-410f-83b7-97f184598e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389767331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.389767331
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1257474161
Short name T564
Test name
Test status
Simulation time 43421604 ps
CPU time 0.83 seconds
Started Jun 26 06:24:52 PM PDT 24
Finished Jun 26 06:24:55 PM PDT 24
Peak memory 207408 kb
Host smart-5d023721-e406-45d2-98be-d6de4884239b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257474161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1257474161
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1067759532
Short name T225
Test name
Test status
Simulation time 84078188079 ps
CPU time 191.29 seconds
Started Jun 26 06:24:53 PM PDT 24
Finished Jun 26 06:28:06 PM PDT 24
Peak memory 265208 kb
Host smart-ae852438-551e-4616-99ce-359a7ae53a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067759532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1067759532
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3397617418
Short name T512
Test name
Test status
Simulation time 6861817696 ps
CPU time 79.77 seconds
Started Jun 26 06:24:59 PM PDT 24
Finished Jun 26 06:26:19 PM PDT 24
Peak memory 241720 kb
Host smart-77e6eb19-fc4b-435a-a4b5-e8762dd520a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397617418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3397617418
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3804663550
Short name T261
Test name
Test status
Simulation time 3331392352 ps
CPU time 59.2 seconds
Started Jun 26 06:25:02 PM PDT 24
Finished Jun 26 06:26:03 PM PDT 24
Peak memory 257884 kb
Host smart-fafbfe28-0a83-451c-a8ad-1d802c90e5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804663550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3804663550
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3334241127
Short name T480
Test name
Test status
Simulation time 2754326270 ps
CPU time 15.72 seconds
Started Jun 26 06:24:53 PM PDT 24
Finished Jun 26 06:25:10 PM PDT 24
Peak memory 230576 kb
Host smart-a7c1e01a-0c15-4cd1-83c1-b49287943e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334241127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3334241127
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.192292904
Short name T840
Test name
Test status
Simulation time 72428411 ps
CPU time 2.86 seconds
Started Jun 26 06:24:53 PM PDT 24
Finished Jun 26 06:24:58 PM PDT 24
Peak memory 225388 kb
Host smart-ac5ed85d-941a-4d6b-bd02-88866975e785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192292904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.192292904
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2822823942
Short name T901
Test name
Test status
Simulation time 61712956686 ps
CPU time 18.77 seconds
Started Jun 26 06:24:55 PM PDT 24
Finished Jun 26 06:25:15 PM PDT 24
Peak memory 241804 kb
Host smart-79a0c7f3-353a-4f3d-9929-fd9b51ad19d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822823942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2822823942
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2416596948
Short name T954
Test name
Test status
Simulation time 11849127694 ps
CPU time 16.59 seconds
Started Jun 26 06:24:53 PM PDT 24
Finished Jun 26 06:25:11 PM PDT 24
Peak memory 241752 kb
Host smart-6eaebb59-3f81-4566-9b69-e612e318edb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416596948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2416596948
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2207123366
Short name T553
Test name
Test status
Simulation time 3198641378 ps
CPU time 20.8 seconds
Started Jun 26 06:24:51 PM PDT 24
Finished Jun 26 06:25:13 PM PDT 24
Peak memory 221588 kb
Host smart-1ca720be-84c5-4350-8f88-b7afaad11025
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2207123366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2207123366
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3261207887
Short name T4
Test name
Test status
Simulation time 18357968540 ps
CPU time 20.08 seconds
Started Jun 26 06:24:55 PM PDT 24
Finished Jun 26 06:25:16 PM PDT 24
Peak memory 217216 kb
Host smart-b100c02b-ce33-4fbe-bc8c-52d038596488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261207887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3261207887
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.204689137
Short name T368
Test name
Test status
Simulation time 2931340914 ps
CPU time 6.28 seconds
Started Jun 26 06:24:53 PM PDT 24
Finished Jun 26 06:25:01 PM PDT 24
Peak memory 217156 kb
Host smart-504f87c7-5d39-47ae-99cb-20cc962dba40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204689137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.204689137
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2567548113
Short name T484
Test name
Test status
Simulation time 39093048 ps
CPU time 0.96 seconds
Started Jun 26 06:24:52 PM PDT 24
Finished Jun 26 06:24:54 PM PDT 24
Peak memory 208220 kb
Host smart-2b30e7f1-1eb4-4dca-9091-f2890313e05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567548113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2567548113
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2898207091
Short name T953
Test name
Test status
Simulation time 134270252 ps
CPU time 1 seconds
Started Jun 26 06:24:54 PM PDT 24
Finished Jun 26 06:24:56 PM PDT 24
Peak memory 206724 kb
Host smart-4a4eb0ec-12e3-4d75-a791-a7630c80e7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898207091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2898207091
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1528274610
Short name T329
Test name
Test status
Simulation time 5883608209 ps
CPU time 7.66 seconds
Started Jun 26 06:24:54 PM PDT 24
Finished Jun 26 06:25:03 PM PDT 24
Peak memory 233772 kb
Host smart-395b4674-ec7d-4958-9c90-617b2cc17e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528274610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1528274610
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.844607698
Short name T905
Test name
Test status
Simulation time 19404485 ps
CPU time 0.71 seconds
Started Jun 26 06:24:58 PM PDT 24
Finished Jun 26 06:24:59 PM PDT 24
Peak memory 206640 kb
Host smart-fc52f4ae-f900-4e1c-8127-0cd84c8ce705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844607698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.844607698
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3121407311
Short name T676
Test name
Test status
Simulation time 387342241 ps
CPU time 9.62 seconds
Started Jun 26 06:25:02 PM PDT 24
Finished Jun 26 06:25:13 PM PDT 24
Peak memory 225372 kb
Host smart-ffd700eb-0a3e-40cc-80c7-b83c51d1a7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121407311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3121407311
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.557563139
Short name T74
Test name
Test status
Simulation time 24585939 ps
CPU time 0.87 seconds
Started Jun 26 06:25:01 PM PDT 24
Finished Jun 26 06:25:03 PM PDT 24
Peak memory 207452 kb
Host smart-31700d65-d30b-4f6f-952a-23b831d0f459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557563139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.557563139
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.439435675
Short name T193
Test name
Test status
Simulation time 2821958016 ps
CPU time 51.42 seconds
Started Jun 26 06:25:02 PM PDT 24
Finished Jun 26 06:25:55 PM PDT 24
Peak memory 253220 kb
Host smart-cda92c0d-9dd9-4c2c-bdaf-9cff5b895261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439435675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.439435675
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3224031679
Short name T929
Test name
Test status
Simulation time 13105221189 ps
CPU time 133.14 seconds
Started Jun 26 06:25:01 PM PDT 24
Finished Jun 26 06:27:17 PM PDT 24
Peak memory 255584 kb
Host smart-872aa107-0362-4ac9-9b01-52d56e0af59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224031679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3224031679
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.390820334
Short name T267
Test name
Test status
Simulation time 238095913 ps
CPU time 4.57 seconds
Started Jun 26 06:25:02 PM PDT 24
Finished Jun 26 06:25:09 PM PDT 24
Peak memory 233612 kb
Host smart-0ac49359-8540-4170-8965-959458dec8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390820334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.390820334
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.519243023
Short name T511
Test name
Test status
Simulation time 265937630 ps
CPU time 3.18 seconds
Started Jun 26 06:25:00 PM PDT 24
Finished Jun 26 06:25:05 PM PDT 24
Peak memory 225320 kb
Host smart-02522bea-eac3-4315-a9c0-cde9b0d34972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519243023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.519243023
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.704992821
Short name T345
Test name
Test status
Simulation time 5602539037 ps
CPU time 13.84 seconds
Started Jun 26 06:25:00 PM PDT 24
Finished Jun 26 06:25:15 PM PDT 24
Peak memory 233760 kb
Host smart-1cc9cfe3-ec39-42f7-8419-4f5a64dbad9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704992821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.704992821
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1257332182
Short name T236
Test name
Test status
Simulation time 4591225368 ps
CPU time 5.79 seconds
Started Jun 26 06:25:02 PM PDT 24
Finished Jun 26 06:25:10 PM PDT 24
Peak memory 233712 kb
Host smart-b6882c23-b3f3-4bef-98f3-f63c1904d1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257332182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1257332182
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2973595892
Short name T444
Test name
Test status
Simulation time 204979559 ps
CPU time 3.5 seconds
Started Jun 26 06:25:03 PM PDT 24
Finished Jun 26 06:25:09 PM PDT 24
Peak memory 225388 kb
Host smart-aa67f4e8-2ee4-40d9-8663-bf560d60dd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973595892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2973595892
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.470833238
Short name T706
Test name
Test status
Simulation time 495584969 ps
CPU time 6.18 seconds
Started Jun 26 06:24:59 PM PDT 24
Finished Jun 26 06:25:06 PM PDT 24
Peak memory 224084 kb
Host smart-e63fbf7d-b8a5-4ea8-bc3b-d9b9e3c7000f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=470833238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.470833238
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1316594168
Short name T149
Test name
Test status
Simulation time 3468599911 ps
CPU time 22.66 seconds
Started Jun 26 06:25:02 PM PDT 24
Finished Jun 26 06:25:27 PM PDT 24
Peak memory 237140 kb
Host smart-d68db0a2-bb45-4ec9-add4-7cece9db2377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316594168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1316594168
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1524663059
Short name T53
Test name
Test status
Simulation time 8508232659 ps
CPU time 22.79 seconds
Started Jun 26 06:25:00 PM PDT 24
Finished Jun 26 06:25:25 PM PDT 24
Peak memory 217152 kb
Host smart-46175354-610c-4049-ac4b-a7233639ce88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524663059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1524663059
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2849376677
Short name T663
Test name
Test status
Simulation time 888024837 ps
CPU time 4.93 seconds
Started Jun 26 06:25:00 PM PDT 24
Finished Jun 26 06:25:07 PM PDT 24
Peak memory 217092 kb
Host smart-3d278b14-c24e-4fdf-87fc-be8f102f4662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849376677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2849376677
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.927160410
Short name T579
Test name
Test status
Simulation time 278670678 ps
CPU time 3.7 seconds
Started Jun 26 06:25:00 PM PDT 24
Finished Jun 26 06:25:06 PM PDT 24
Peak memory 217176 kb
Host smart-331e1358-aacb-4122-bb69-17fec5f78320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927160410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.927160410
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.12002106
Short name T294
Test name
Test status
Simulation time 61183061 ps
CPU time 0.72 seconds
Started Jun 26 06:25:03 PM PDT 24
Finished Jun 26 06:25:06 PM PDT 24
Peak memory 206752 kb
Host smart-553100d1-2383-4201-a707-db72ee4192e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12002106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.12002106
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1428875863
Short name T639
Test name
Test status
Simulation time 1068892529 ps
CPU time 6.58 seconds
Started Jun 26 06:25:05 PM PDT 24
Finished Jun 26 06:25:13 PM PDT 24
Peak memory 241764 kb
Host smart-aaaa11e3-a52c-4251-a49f-9b480542a808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428875863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1428875863
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3946402687
Short name T569
Test name
Test status
Simulation time 44282946 ps
CPU time 0.73 seconds
Started Jun 26 06:24:59 PM PDT 24
Finished Jun 26 06:25:01 PM PDT 24
Peak memory 206276 kb
Host smart-f59479bf-5922-4b77-9cdf-aef5dcb60cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946402687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3946402687
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1983134788
Short name T515
Test name
Test status
Simulation time 861217472 ps
CPU time 5.7 seconds
Started Jun 26 06:25:03 PM PDT 24
Finished Jun 26 06:25:11 PM PDT 24
Peak memory 225400 kb
Host smart-a788eedc-6de1-4a9e-ac52-f5dfa4159a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983134788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1983134788
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1863231842
Short name T282
Test name
Test status
Simulation time 62335711 ps
CPU time 0.83 seconds
Started Jun 26 06:25:01 PM PDT 24
Finished Jun 26 06:25:04 PM PDT 24
Peak memory 207396 kb
Host smart-378cc34c-f516-41ac-a20e-1e8a31962d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863231842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1863231842
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1027852522
Short name T425
Test name
Test status
Simulation time 17075107753 ps
CPU time 33.24 seconds
Started Jun 26 06:24:59 PM PDT 24
Finished Jun 26 06:25:33 PM PDT 24
Peak memory 236100 kb
Host smart-211e3b4a-bd58-4fe0-81a6-f30436a335f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027852522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1027852522
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.4002835968
Short name T276
Test name
Test status
Simulation time 10359440216 ps
CPU time 38.46 seconds
Started Jun 26 06:25:00 PM PDT 24
Finished Jun 26 06:25:40 PM PDT 24
Peak memory 218632 kb
Host smart-89c878cc-27aa-47f3-8e4d-a2b2ca232c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002835968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.4002835968
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1289203745
Short name T896
Test name
Test status
Simulation time 2264840596 ps
CPU time 45 seconds
Started Jun 26 06:25:04 PM PDT 24
Finished Jun 26 06:25:50 PM PDT 24
Peak memory 250468 kb
Host smart-c9d07457-2b55-49a1-8b01-caf2944207b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289203745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1289203745
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2191867833
Short name T308
Test name
Test status
Simulation time 297250037 ps
CPU time 3.8 seconds
Started Jun 26 06:25:02 PM PDT 24
Finished Jun 26 06:25:08 PM PDT 24
Peak memory 225400 kb
Host smart-a0ce0538-0601-4242-8cd4-f8e84ca0cb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191867833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2191867833
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1472493983
Short name T58
Test name
Test status
Simulation time 1440410413 ps
CPU time 13.32 seconds
Started Jun 26 06:25:00 PM PDT 24
Finished Jun 26 06:25:15 PM PDT 24
Peak memory 233648 kb
Host smart-c5d17506-6feb-4019-9a7d-886797cbaee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472493983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1472493983
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3655400308
Short name T2
Test name
Test status
Simulation time 14035394563 ps
CPU time 65.68 seconds
Started Jun 26 06:25:00 PM PDT 24
Finished Jun 26 06:26:07 PM PDT 24
Peak memory 249628 kb
Host smart-598d9bc3-893e-4868-b20d-e72c90b54731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655400308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3655400308
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3095818526
Short name T250
Test name
Test status
Simulation time 1039957743 ps
CPU time 4.54 seconds
Started Jun 26 06:25:02 PM PDT 24
Finished Jun 26 06:25:09 PM PDT 24
Peak memory 233592 kb
Host smart-bf96fdd1-fbe8-4ed7-8ae3-f2b705247764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095818526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3095818526
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.416389381
Short name T190
Test name
Test status
Simulation time 2310680833 ps
CPU time 6.9 seconds
Started Jun 26 06:25:01 PM PDT 24
Finished Jun 26 06:25:10 PM PDT 24
Peak memory 233752 kb
Host smart-695f90fe-ec45-4c7c-82ed-5b35da951a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416389381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.416389381
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2549808934
Short name T608
Test name
Test status
Simulation time 321074805 ps
CPU time 6.73 seconds
Started Jun 26 06:25:02 PM PDT 24
Finished Jun 26 06:25:11 PM PDT 24
Peak memory 224096 kb
Host smart-99ce63a0-475d-419f-8052-db429dced83a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2549808934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2549808934
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2877510161
Short name T852
Test name
Test status
Simulation time 19747276171 ps
CPU time 153.29 seconds
Started Jun 26 06:25:02 PM PDT 24
Finished Jun 26 06:27:38 PM PDT 24
Peak memory 271176 kb
Host smart-e6820a9a-7c32-46f2-910a-13baeb1d25dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877510161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2877510161
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3569879520
Short name T439
Test name
Test status
Simulation time 33387662521 ps
CPU time 30.63 seconds
Started Jun 26 06:25:04 PM PDT 24
Finished Jun 26 06:25:36 PM PDT 24
Peak memory 217184 kb
Host smart-98f3f2f8-4e08-428d-a47b-f860796d4fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569879520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3569879520
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4011344023
Short name T781
Test name
Test status
Simulation time 2745939444 ps
CPU time 5.26 seconds
Started Jun 26 06:24:58 PM PDT 24
Finished Jun 26 06:25:04 PM PDT 24
Peak memory 217260 kb
Host smart-79d218aa-b8c4-45c6-83af-27664a5d430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011344023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4011344023
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1224724718
Short name T450
Test name
Test status
Simulation time 1100044535 ps
CPU time 12.19 seconds
Started Jun 26 06:25:00 PM PDT 24
Finished Jun 26 06:25:14 PM PDT 24
Peak memory 217192 kb
Host smart-40ee34af-8867-44d6-8ab7-02f419948c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224724718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1224724718
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2107566125
Short name T872
Test name
Test status
Simulation time 66179939 ps
CPU time 0.77 seconds
Started Jun 26 06:25:01 PM PDT 24
Finished Jun 26 06:25:03 PM PDT 24
Peak memory 206780 kb
Host smart-36d1f73e-a4ca-465b-a705-06fe0756ded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107566125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2107566125
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3365961170
Short name T504
Test name
Test status
Simulation time 59249440 ps
CPU time 2.3 seconds
Started Jun 26 06:25:03 PM PDT 24
Finished Jun 26 06:25:07 PM PDT 24
Peak memory 225120 kb
Host smart-c320e172-327b-40d1-b6a8-1ba8948dde8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365961170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3365961170
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2977586421
Short name T372
Test name
Test status
Simulation time 33569128 ps
CPU time 0.72 seconds
Started Jun 26 06:25:08 PM PDT 24
Finished Jun 26 06:25:11 PM PDT 24
Peak memory 206368 kb
Host smart-2d11ce3a-8cf0-407b-8305-fab244ee0a27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977586421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2977586421
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4088462882
Short name T598
Test name
Test status
Simulation time 2049728593 ps
CPU time 18.44 seconds
Started Jun 26 06:25:08 PM PDT 24
Finished Jun 26 06:25:28 PM PDT 24
Peak memory 233572 kb
Host smart-9ab49a25-1ab1-4fb4-8fa1-371c74627895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088462882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4088462882
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4134001761
Short name T390
Test name
Test status
Simulation time 54952183 ps
CPU time 0.82 seconds
Started Jun 26 06:25:02 PM PDT 24
Finished Jun 26 06:25:05 PM PDT 24
Peak memory 207364 kb
Host smart-9b6be354-47d8-4f94-bf38-55a81b85ea2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134001761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4134001761
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3123610942
Short name T522
Test name
Test status
Simulation time 26523632933 ps
CPU time 176.23 seconds
Started Jun 26 06:25:07 PM PDT 24
Finished Jun 26 06:28:05 PM PDT 24
Peak memory 256008 kb
Host smart-a58c17ae-4e24-40ae-9ac9-cf05e3c78a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123610942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3123610942
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2552445494
Short name T171
Test name
Test status
Simulation time 46984027079 ps
CPU time 201.21 seconds
Started Jun 26 06:25:07 PM PDT 24
Finished Jun 26 06:28:30 PM PDT 24
Peak memory 254528 kb
Host smart-f169d03a-53f2-48c5-af6b-e9a1ce0bb804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552445494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2552445494
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1528631653
Short name T715
Test name
Test status
Simulation time 1610453505 ps
CPU time 32.34 seconds
Started Jun 26 06:25:08 PM PDT 24
Finished Jun 26 06:25:42 PM PDT 24
Peak memory 249976 kb
Host smart-2ec5c1ce-dee0-466b-8836-8d2a26ba6d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528631653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1528631653
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.559323304
Short name T702
Test name
Test status
Simulation time 857060877 ps
CPU time 6.52 seconds
Started Jun 26 06:25:10 PM PDT 24
Finished Jun 26 06:25:18 PM PDT 24
Peak memory 234888 kb
Host smart-f5ea7f7c-e72f-47f0-8a9a-5741729628c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559323304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.559323304
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1221427264
Short name T359
Test name
Test status
Simulation time 103924239 ps
CPU time 2.13 seconds
Started Jun 26 06:25:06 PM PDT 24
Finished Jun 26 06:25:09 PM PDT 24
Peak memory 223804 kb
Host smart-8497d296-2f9d-4ab9-ab1d-dfe5f78c0c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221427264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1221427264
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2312692432
Short name T183
Test name
Test status
Simulation time 5074288570 ps
CPU time 14.47 seconds
Started Jun 26 06:25:06 PM PDT 24
Finished Jun 26 06:25:22 PM PDT 24
Peak memory 225448 kb
Host smart-f144c821-6186-43af-8245-d52c4d9b4b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312692432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2312692432
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2543562292
Short name T556
Test name
Test status
Simulation time 1850084750 ps
CPU time 2.56 seconds
Started Jun 26 06:25:01 PM PDT 24
Finished Jun 26 06:25:06 PM PDT 24
Peak memory 225344 kb
Host smart-9ccac54f-cfd1-472c-9644-f41e4227b992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543562292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2543562292
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3248111968
Short name T961
Test name
Test status
Simulation time 5280659475 ps
CPU time 22.85 seconds
Started Jun 26 06:25:00 PM PDT 24
Finished Jun 26 06:25:24 PM PDT 24
Peak memory 250048 kb
Host smart-9ff17d21-fb28-4d7f-9b09-e07bbc1708af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248111968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3248111968
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.851216322
Short name T890
Test name
Test status
Simulation time 264185226 ps
CPU time 4.27 seconds
Started Jun 26 06:25:04 PM PDT 24
Finished Jun 26 06:25:10 PM PDT 24
Peak memory 224204 kb
Host smart-30f00776-34a7-46bb-b1c4-8598c5b56430
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=851216322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.851216322
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.518831393
Short name T56
Test name
Test status
Simulation time 36446794715 ps
CPU time 203.47 seconds
Started Jun 26 06:25:11 PM PDT 24
Finished Jun 26 06:28:35 PM PDT 24
Peak memory 274748 kb
Host smart-d85941e2-5552-4251-a0b3-d048d93fa556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518831393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.518831393
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.191168857
Short name T78
Test name
Test status
Simulation time 725368338 ps
CPU time 7.87 seconds
Started Jun 26 06:25:00 PM PDT 24
Finished Jun 26 06:25:09 PM PDT 24
Peak memory 217064 kb
Host smart-6d04b2a5-a887-46b5-b6e5-86575a2aa46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191168857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.191168857
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.803015512
Short name T824
Test name
Test status
Simulation time 1182390644 ps
CPU time 6.93 seconds
Started Jun 26 06:25:01 PM PDT 24
Finished Jun 26 06:25:10 PM PDT 24
Peak memory 217112 kb
Host smart-b04792eb-5a6a-40c7-8f0f-a4ca3c6e18ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803015512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.803015512
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.510743057
Short name T531
Test name
Test status
Simulation time 87042157 ps
CPU time 2.3 seconds
Started Jun 26 06:25:01 PM PDT 24
Finished Jun 26 06:25:05 PM PDT 24
Peak memory 217028 kb
Host smart-c19d4f30-eaa1-481b-a0ff-43af0e864011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510743057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.510743057
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3357590024
Short name T605
Test name
Test status
Simulation time 40492443 ps
CPU time 0.92 seconds
Started Jun 26 06:25:01 PM PDT 24
Finished Jun 26 06:25:04 PM PDT 24
Peak memory 206740 kb
Host smart-e58651ac-5e22-4dba-941c-835bccff02b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357590024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3357590024
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1156801847
Short name T48
Test name
Test status
Simulation time 269389727 ps
CPU time 4.38 seconds
Started Jun 26 06:25:08 PM PDT 24
Finished Jun 26 06:25:14 PM PDT 24
Peak memory 233620 kb
Host smart-1f5871c1-24e0-4f81-a54f-cc0b3d1c7563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156801847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1156801847
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.831558073
Short name T811
Test name
Test status
Simulation time 44309548 ps
CPU time 0.72 seconds
Started Jun 26 06:25:07 PM PDT 24
Finished Jun 26 06:25:09 PM PDT 24
Peak memory 206676 kb
Host smart-9aa68c3f-467a-4388-81d7-12941434161c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831558073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.831558073
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2757506534
Short name T575
Test name
Test status
Simulation time 660705320 ps
CPU time 4.37 seconds
Started Jun 26 06:25:11 PM PDT 24
Finished Jun 26 06:25:16 PM PDT 24
Peak memory 233620 kb
Host smart-4a30258e-dfd5-408b-ad58-2cf588666b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757506534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2757506534
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2555011110
Short name T448
Test name
Test status
Simulation time 63518011 ps
CPU time 0.86 seconds
Started Jun 26 06:25:05 PM PDT 24
Finished Jun 26 06:25:07 PM PDT 24
Peak memory 207380 kb
Host smart-8cf0cd6c-7c45-4076-beec-eeca1b5f541a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555011110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2555011110
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1404788523
Short name T956
Test name
Test status
Simulation time 6975742677 ps
CPU time 105.75 seconds
Started Jun 26 06:25:06 PM PDT 24
Finished Jun 26 06:26:53 PM PDT 24
Peak memory 258300 kb
Host smart-329f269a-8916-4bac-8f23-77c43f7aa7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404788523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1404788523
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2078451070
Short name T937
Test name
Test status
Simulation time 3204121239 ps
CPU time 79.55 seconds
Started Jun 26 06:25:11 PM PDT 24
Finished Jun 26 06:26:32 PM PDT 24
Peak memory 251228 kb
Host smart-bbfdb203-b391-4ed9-81ed-f8e127890a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078451070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2078451070
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3400443079
Short name T269
Test name
Test status
Simulation time 15975913593 ps
CPU time 48.99 seconds
Started Jun 26 06:25:06 PM PDT 24
Finished Jun 26 06:25:57 PM PDT 24
Peak memory 241972 kb
Host smart-bfb3a0f3-5b38-4e3a-9d39-0cb51039f865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400443079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3400443079
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3327281520
Short name T413
Test name
Test status
Simulation time 949280301 ps
CPU time 9.32 seconds
Started Jun 26 06:25:06 PM PDT 24
Finished Jun 26 06:25:17 PM PDT 24
Peak memory 225416 kb
Host smart-4c86e102-dcbc-4714-a320-a72d3602d101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327281520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3327281520
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2489666911
Short name T670
Test name
Test status
Simulation time 5542804314 ps
CPU time 58.99 seconds
Started Jun 26 06:25:07 PM PDT 24
Finished Jun 26 06:26:08 PM PDT 24
Peak memory 241252 kb
Host smart-7cef973e-dd83-4733-b330-2d953422a4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489666911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2489666911
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1752093725
Short name T877
Test name
Test status
Simulation time 355763866 ps
CPU time 2.85 seconds
Started Jun 26 06:25:07 PM PDT 24
Finished Jun 26 06:25:12 PM PDT 24
Peak memory 225436 kb
Host smart-fae62e77-34ea-42df-a01a-eb51cc72c380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752093725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1752093725
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1348708401
Short name T775
Test name
Test status
Simulation time 338284159 ps
CPU time 7.1 seconds
Started Jun 26 06:25:08 PM PDT 24
Finished Jun 26 06:25:17 PM PDT 24
Peak memory 233640 kb
Host smart-8cdae401-4260-49f0-aa79-5e668c3cf32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348708401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1348708401
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2100412964
Short name T885
Test name
Test status
Simulation time 281155265 ps
CPU time 4.78 seconds
Started Jun 26 06:25:06 PM PDT 24
Finished Jun 26 06:25:12 PM PDT 24
Peak memory 221344 kb
Host smart-120ab299-866b-49ae-9924-74c9ff2dc201
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2100412964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2100412964
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3488813047
Short name T66
Test name
Test status
Simulation time 7028820662 ps
CPU time 41.47 seconds
Started Jun 26 06:25:08 PM PDT 24
Finished Jun 26 06:25:51 PM PDT 24
Peak memory 241284 kb
Host smart-e218e8dc-74ee-4d97-ad75-1130e6166aa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488813047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3488813047
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1191571149
Short name T755
Test name
Test status
Simulation time 15444985500 ps
CPU time 11.01 seconds
Started Jun 26 06:25:07 PM PDT 24
Finished Jun 26 06:25:20 PM PDT 24
Peak memory 217244 kb
Host smart-35ee6d3e-31fd-4687-99ac-be088b7e2c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191571149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1191571149
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2324503763
Short name T396
Test name
Test status
Simulation time 2974797633 ps
CPU time 6.69 seconds
Started Jun 26 06:25:07 PM PDT 24
Finished Jun 26 06:25:15 PM PDT 24
Peak memory 217156 kb
Host smart-18ce5313-7eeb-45fc-b620-333b2774b0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324503763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2324503763
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2391632698
Short name T749
Test name
Test status
Simulation time 343664051 ps
CPU time 1.42 seconds
Started Jun 26 06:25:05 PM PDT 24
Finished Jun 26 06:25:08 PM PDT 24
Peak memory 217192 kb
Host smart-4b007bca-b30a-47dd-94f3-150ec3ccfbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391632698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2391632698
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1395077412
Short name T516
Test name
Test status
Simulation time 257877022 ps
CPU time 0.97 seconds
Started Jun 26 06:25:05 PM PDT 24
Finished Jun 26 06:25:08 PM PDT 24
Peak memory 206716 kb
Host smart-63f621b9-8bd6-4246-b04a-9835f9ed5bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395077412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1395077412
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1379485103
Short name T582
Test name
Test status
Simulation time 3998754480 ps
CPU time 3.65 seconds
Started Jun 26 06:25:08 PM PDT 24
Finished Jun 26 06:25:14 PM PDT 24
Peak memory 225448 kb
Host smart-4856892b-6dec-4927-97f2-0325d160fb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379485103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1379485103
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1316164000
Short name T410
Test name
Test status
Simulation time 13702532 ps
CPU time 0.75 seconds
Started Jun 26 06:25:17 PM PDT 24
Finished Jun 26 06:25:19 PM PDT 24
Peak memory 206616 kb
Host smart-4a046ad7-d997-414a-80c9-ad60936d2fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316164000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1316164000
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.272835156
Short name T898
Test name
Test status
Simulation time 417523353 ps
CPU time 2.46 seconds
Started Jun 26 06:25:17 PM PDT 24
Finished Jun 26 06:25:21 PM PDT 24
Peak memory 225376 kb
Host smart-a5d45356-4960-4d03-b4ae-28511b5b62e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272835156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.272835156
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3440381537
Short name T324
Test name
Test status
Simulation time 152698041 ps
CPU time 0.87 seconds
Started Jun 26 06:25:07 PM PDT 24
Finished Jun 26 06:25:10 PM PDT 24
Peak memory 207392 kb
Host smart-c508b5cc-619b-4e21-8018-9a06b7cfafd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440381537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3440381537
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.751847505
Short name T77
Test name
Test status
Simulation time 3699963229 ps
CPU time 47.3 seconds
Started Jun 26 06:25:16 PM PDT 24
Finished Jun 26 06:26:04 PM PDT 24
Peak memory 237108 kb
Host smart-9689de5c-6ae3-4e85-af46-40ecf397389b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751847505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.751847505
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2646820158
Short name T577
Test name
Test status
Simulation time 25928409212 ps
CPU time 39.86 seconds
Started Jun 26 06:25:14 PM PDT 24
Finished Jun 26 06:25:54 PM PDT 24
Peak memory 250332 kb
Host smart-3dbd4b8b-444e-43e7-9853-626e23aebecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646820158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2646820158
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.90810802
Short name T234
Test name
Test status
Simulation time 29441447280 ps
CPU time 228.85 seconds
Started Jun 26 06:25:15 PM PDT 24
Finished Jun 26 06:29:05 PM PDT 24
Peak memory 250092 kb
Host smart-e3eb8704-a439-4115-82d3-65c93fe85778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90810802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.90810802
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1726112475
Short name T271
Test name
Test status
Simulation time 287723875 ps
CPU time 10.4 seconds
Started Jun 26 06:25:15 PM PDT 24
Finished Jun 26 06:25:27 PM PDT 24
Peak memory 234844 kb
Host smart-9a5c889b-642a-40f1-a509-079095e01b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726112475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1726112475
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2341594813
Short name T389
Test name
Test status
Simulation time 1049159924 ps
CPU time 6.05 seconds
Started Jun 26 06:25:17 PM PDT 24
Finished Jun 26 06:25:24 PM PDT 24
Peak memory 233636 kb
Host smart-b4e1e435-3d38-45e5-8e8f-3132d544ee91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341594813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2341594813
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.249438119
Short name T548
Test name
Test status
Simulation time 127381365 ps
CPU time 3.78 seconds
Started Jun 26 06:25:15 PM PDT 24
Finished Jun 26 06:25:19 PM PDT 24
Peak memory 225368 kb
Host smart-9b05239a-d4d1-4e49-a337-0a8ccc82c5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249438119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.249438119
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1741037994
Short name T402
Test name
Test status
Simulation time 95094388 ps
CPU time 2.22 seconds
Started Jun 26 06:25:16 PM PDT 24
Finished Jun 26 06:25:19 PM PDT 24
Peak memory 233316 kb
Host smart-93ebee62-7366-4d1e-ad45-404ed57bbcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741037994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1741037994
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3871809734
Short name T199
Test name
Test status
Simulation time 7831519034 ps
CPU time 16.4 seconds
Started Jun 26 06:25:07 PM PDT 24
Finished Jun 26 06:25:25 PM PDT 24
Peak memory 225600 kb
Host smart-7291047e-a0ce-4424-a552-09cc782feaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871809734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3871809734
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2936779428
Short name T614
Test name
Test status
Simulation time 2535588944 ps
CPU time 9.37 seconds
Started Jun 26 06:25:15 PM PDT 24
Finished Jun 26 06:25:26 PM PDT 24
Peak memory 219728 kb
Host smart-9dcfaf2c-6782-4914-be5b-5a62550805a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2936779428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2936779428
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2055334852
Short name T337
Test name
Test status
Simulation time 55312864 ps
CPU time 1.12 seconds
Started Jun 26 06:25:15 PM PDT 24
Finished Jun 26 06:25:17 PM PDT 24
Peak memory 208100 kb
Host smart-99a3bc1b-5c13-4595-919b-573cce4aaacd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055334852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2055334852
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.237485086
Short name T815
Test name
Test status
Simulation time 614498731 ps
CPU time 6.12 seconds
Started Jun 26 06:25:05 PM PDT 24
Finished Jun 26 06:25:12 PM PDT 24
Peak memory 217044 kb
Host smart-b21af61c-2349-4fa3-b63a-c6c1fe830c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237485086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.237485086
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2667945773
Short name T599
Test name
Test status
Simulation time 1127661128 ps
CPU time 8.29 seconds
Started Jun 26 06:25:05 PM PDT 24
Finished Jun 26 06:25:15 PM PDT 24
Peak memory 217120 kb
Host smart-9049fead-0096-49cf-9b0c-f203368ce658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667945773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2667945773
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2556099871
Short name T11
Test name
Test status
Simulation time 56460512 ps
CPU time 1.45 seconds
Started Jun 26 06:25:08 PM PDT 24
Finished Jun 26 06:25:11 PM PDT 24
Peak memory 217068 kb
Host smart-8340c62b-d412-4580-beca-0af17bcdf3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556099871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2556099871
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1302098386
Short name T626
Test name
Test status
Simulation time 10556998 ps
CPU time 0.72 seconds
Started Jun 26 06:25:08 PM PDT 24
Finished Jun 26 06:25:10 PM PDT 24
Peak memory 206396 kb
Host smart-80687519-4537-401c-9a0f-65f246a3ed1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302098386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1302098386
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3507184064
Short name T694
Test name
Test status
Simulation time 9486543178 ps
CPU time 9.35 seconds
Started Jun 26 06:25:13 PM PDT 24
Finished Jun 26 06:25:23 PM PDT 24
Peak memory 233736 kb
Host smart-1e51475b-2829-47ba-9a63-9f45c71bdc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507184064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3507184064
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.633821785
Short name T423
Test name
Test status
Simulation time 12909743 ps
CPU time 0.76 seconds
Started Jun 26 06:25:22 PM PDT 24
Finished Jun 26 06:25:24 PM PDT 24
Peak memory 206584 kb
Host smart-69c380c3-b3e1-43de-8dab-aa0dffc52f8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633821785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.633821785
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3118954774
Short name T580
Test name
Test status
Simulation time 1658595197 ps
CPU time 7.45 seconds
Started Jun 26 06:25:13 PM PDT 24
Finished Jun 26 06:25:22 PM PDT 24
Peak memory 225424 kb
Host smart-c23774d7-4265-4c61-909c-ea412175417c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118954774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3118954774
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2746758366
Short name T471
Test name
Test status
Simulation time 36883740 ps
CPU time 0.79 seconds
Started Jun 26 06:25:14 PM PDT 24
Finished Jun 26 06:25:16 PM PDT 24
Peak memory 207456 kb
Host smart-7838715b-ea60-4f36-9da9-7777d7c261ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746758366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2746758366
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.258168928
Short name T474
Test name
Test status
Simulation time 9464284087 ps
CPU time 26.78 seconds
Started Jun 26 06:25:24 PM PDT 24
Finished Jun 26 06:25:54 PM PDT 24
Peak memory 237240 kb
Host smart-d3d88ab5-0c2b-4858-a422-573c747400e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258168928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.258168928
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2117466251
Short name T264
Test name
Test status
Simulation time 248378550654 ps
CPU time 585.29 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:35:11 PM PDT 24
Peak memory 252744 kb
Host smart-8dce6dfa-3ab1-41ab-b13b-827136c42362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117466251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2117466251
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.589820406
Short name T588
Test name
Test status
Simulation time 666047401 ps
CPU time 3.67 seconds
Started Jun 26 06:25:15 PM PDT 24
Finished Jun 26 06:25:20 PM PDT 24
Peak memory 225472 kb
Host smart-17c934d6-e9fd-4bf7-965f-b26cc3105989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589820406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.589820406
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3998162584
Short name T219
Test name
Test status
Simulation time 381046007 ps
CPU time 5.71 seconds
Started Jun 26 06:25:15 PM PDT 24
Finished Jun 26 06:25:22 PM PDT 24
Peak memory 233656 kb
Host smart-9728ca49-d2f4-4877-922f-cbb885606f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998162584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3998162584
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1298882138
Short name T392
Test name
Test status
Simulation time 31608211 ps
CPU time 2.36 seconds
Started Jun 26 06:25:16 PM PDT 24
Finished Jun 26 06:25:20 PM PDT 24
Peak memory 224936 kb
Host smart-13065d2b-38eb-4369-9697-adb2443756be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298882138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1298882138
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3559064359
Short name T948
Test name
Test status
Simulation time 2347532727 ps
CPU time 7.27 seconds
Started Jun 26 06:25:16 PM PDT 24
Finished Jun 26 06:25:25 PM PDT 24
Peak memory 233732 kb
Host smart-9e4131d2-9835-4a3d-a975-a841db5ebe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559064359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3559064359
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2405548499
Short name T855
Test name
Test status
Simulation time 8358750531 ps
CPU time 24.89 seconds
Started Jun 26 06:25:16 PM PDT 24
Finished Jun 26 06:25:42 PM PDT 24
Peak memory 233752 kb
Host smart-a46c0d0c-2f8f-42bc-90bd-f52d47b48fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405548499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2405548499
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3524213970
Short name T668
Test name
Test status
Simulation time 838761417 ps
CPU time 3.72 seconds
Started Jun 26 06:25:14 PM PDT 24
Finished Jun 26 06:25:19 PM PDT 24
Peak memory 221352 kb
Host smart-a7048ed6-8528-4819-ae3e-c484dafebe4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3524213970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3524213970
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3800785958
Short name T25
Test name
Test status
Simulation time 50863249924 ps
CPU time 190.78 seconds
Started Jun 26 06:25:24 PM PDT 24
Finished Jun 26 06:28:38 PM PDT 24
Peak memory 256308 kb
Host smart-83297250-718d-48c6-a8da-8b7149ae0258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800785958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3800785958
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3621712261
Short name T466
Test name
Test status
Simulation time 4524683588 ps
CPU time 26.89 seconds
Started Jun 26 06:25:15 PM PDT 24
Finished Jun 26 06:25:43 PM PDT 24
Peak memory 217180 kb
Host smart-96a5ec89-e8b0-4d58-928f-34f92e5a66fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621712261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3621712261
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2778647930
Short name T844
Test name
Test status
Simulation time 1336699930 ps
CPU time 2.74 seconds
Started Jun 26 06:25:17 PM PDT 24
Finished Jun 26 06:25:21 PM PDT 24
Peak memory 217108 kb
Host smart-cc94c82f-04e8-46ba-9f27-ae5ab715d747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778647930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2778647930
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3766279010
Short name T827
Test name
Test status
Simulation time 314595171 ps
CPU time 5.13 seconds
Started Jun 26 06:25:14 PM PDT 24
Finished Jun 26 06:25:20 PM PDT 24
Peak memory 217100 kb
Host smart-79a23094-c200-4469-8f0f-40827f790df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766279010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3766279010
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.401843967
Short name T287
Test name
Test status
Simulation time 259381875 ps
CPU time 0.94 seconds
Started Jun 26 06:25:16 PM PDT 24
Finished Jun 26 06:25:18 PM PDT 24
Peak memory 206968 kb
Host smart-24aa6e6f-d13b-4c9d-adab-6f20f177c07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401843967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.401843967
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1315392956
Short name T354
Test name
Test status
Simulation time 218804851 ps
CPU time 4.62 seconds
Started Jun 26 06:25:15 PM PDT 24
Finished Jun 26 06:25:21 PM PDT 24
Peak memory 225480 kb
Host smart-29663463-f6a1-4954-a10d-060a07d8398c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315392956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1315392956
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1177469037
Short name T627
Test name
Test status
Simulation time 37152340 ps
CPU time 0.72 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:25:26 PM PDT 24
Peak memory 206276 kb
Host smart-e839564f-0185-41dd-b6ff-263c475ea454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177469037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1177469037
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4245230858
Short name T819
Test name
Test status
Simulation time 240064737 ps
CPU time 2.57 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:25:28 PM PDT 24
Peak memory 225344 kb
Host smart-d23eb173-b597-447a-9d17-271149af41c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245230858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4245230858
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3657050876
Short name T705
Test name
Test status
Simulation time 56391009 ps
CPU time 0.8 seconds
Started Jun 26 06:25:25 PM PDT 24
Finished Jun 26 06:25:28 PM PDT 24
Peak memory 207380 kb
Host smart-870ecb9b-4004-434a-83ac-d7ea1c71a4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657050876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3657050876
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2312505502
Short name T733
Test name
Test status
Simulation time 31655348895 ps
CPU time 223.94 seconds
Started Jun 26 06:25:24 PM PDT 24
Finished Jun 26 06:29:10 PM PDT 24
Peak memory 255220 kb
Host smart-f57a89ea-7429-4b59-9135-2cf5bc234fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312505502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2312505502
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2989979651
Short name T121
Test name
Test status
Simulation time 9380110403 ps
CPU time 145.62 seconds
Started Jun 26 06:25:22 PM PDT 24
Finished Jun 26 06:27:49 PM PDT 24
Peak memory 264720 kb
Host smart-a406f8e3-a9a3-4adb-a093-f0b120e49ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989979651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2989979651
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.349685693
Short name T661
Test name
Test status
Simulation time 239121167206 ps
CPU time 182.71 seconds
Started Jun 26 06:25:21 PM PDT 24
Finished Jun 26 06:28:26 PM PDT 24
Peak memory 251248 kb
Host smart-caca75f7-14c3-48ae-a7b4-4188f20c9492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349685693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.349685693
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2087801120
Short name T892
Test name
Test status
Simulation time 3207162786 ps
CPU time 19.75 seconds
Started Jun 26 06:25:24 PM PDT 24
Finished Jun 26 06:25:46 PM PDT 24
Peak memory 246596 kb
Host smart-b568bd1f-fad4-4503-a80a-ade9373b657b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087801120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2087801120
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.179512937
Short name T592
Test name
Test status
Simulation time 443781650 ps
CPU time 5.35 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:25:31 PM PDT 24
Peak memory 233648 kb
Host smart-8c7073b8-1c3b-4149-a44d-5629b901f840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179512937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.179512937
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4271208862
Short name T944
Test name
Test status
Simulation time 57572608048 ps
CPU time 123.27 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:27:28 PM PDT 24
Peak memory 233804 kb
Host smart-3b2189b8-8739-4ca6-82f9-c96d6de4d607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271208862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4271208862
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.448487794
Short name T232
Test name
Test status
Simulation time 783684171 ps
CPU time 2.29 seconds
Started Jun 26 06:25:22 PM PDT 24
Finished Jun 26 06:25:25 PM PDT 24
Peak memory 225292 kb
Host smart-9dc943c4-9206-4dc4-b7d8-ef611dd9db77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448487794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.448487794
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2274875823
Short name T318
Test name
Test status
Simulation time 3351390798 ps
CPU time 6.01 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:25:31 PM PDT 24
Peak memory 233708 kb
Host smart-544ec25b-f975-4e59-83c1-121a5dedaa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274875823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2274875823
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2238111629
Short name T138
Test name
Test status
Simulation time 296609284 ps
CPU time 3.51 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:25:28 PM PDT 24
Peak memory 224040 kb
Host smart-b112f486-2945-4e7c-b88c-ef006c4a95e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2238111629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2238111629
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2679333975
Short name T517
Test name
Test status
Simulation time 48832539 ps
CPU time 1.08 seconds
Started Jun 26 06:25:26 PM PDT 24
Finished Jun 26 06:25:29 PM PDT 24
Peak memory 208596 kb
Host smart-0fcdf10b-bcc0-4f93-b9ba-37b76deb6216
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679333975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2679333975
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1877293543
Short name T647
Test name
Test status
Simulation time 534727319 ps
CPU time 4.55 seconds
Started Jun 26 06:25:25 PM PDT 24
Finished Jun 26 06:25:32 PM PDT 24
Peak memory 217064 kb
Host smart-99e507e3-0e07-419e-b00b-fba63d75f3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877293543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1877293543
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4118646398
Short name T680
Test name
Test status
Simulation time 1210919300 ps
CPU time 3.4 seconds
Started Jun 26 06:25:22 PM PDT 24
Finished Jun 26 06:25:27 PM PDT 24
Peak memory 217116 kb
Host smart-6508d195-0838-4b4f-94bb-24f7235c0060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118646398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4118646398
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1643399219
Short name T39
Test name
Test status
Simulation time 397890697 ps
CPU time 2.42 seconds
Started Jun 26 06:25:24 PM PDT 24
Finished Jun 26 06:25:29 PM PDT 24
Peak memory 217124 kb
Host smart-37a60c3d-2d7c-4fc4-a7da-ae0e3d9c05b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643399219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1643399219
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3750652496
Short name T370
Test name
Test status
Simulation time 90862135 ps
CPU time 0.82 seconds
Started Jun 26 06:25:25 PM PDT 24
Finished Jun 26 06:25:28 PM PDT 24
Peak memory 206688 kb
Host smart-36d9df92-a532-44cb-aa1d-d520615b3bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750652496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3750652496
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1071762578
Short name T490
Test name
Test status
Simulation time 1908771821 ps
CPU time 7.81 seconds
Started Jun 26 06:25:21 PM PDT 24
Finished Jun 26 06:25:29 PM PDT 24
Peak memory 225460 kb
Host smart-a5016628-72a6-4f83-97dd-be0900ce332a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071762578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1071762578
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1882153181
Short name T780
Test name
Test status
Simulation time 15207437 ps
CPU time 0.76 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:25:25 PM PDT 24
Peak memory 206580 kb
Host smart-7ea5594e-2567-479b-84a6-ce54ec662799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882153181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1882153181
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.349179711
Short name T221
Test name
Test status
Simulation time 9432085279 ps
CPU time 8.68 seconds
Started Jun 26 06:25:21 PM PDT 24
Finished Jun 26 06:25:31 PM PDT 24
Peak memory 225548 kb
Host smart-374a6b36-9cc2-4233-ad23-67d5c0b616d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349179711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.349179711
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2247280625
Short name T381
Test name
Test status
Simulation time 63375227 ps
CPU time 0.78 seconds
Started Jun 26 06:25:22 PM PDT 24
Finished Jun 26 06:25:25 PM PDT 24
Peak memory 206400 kb
Host smart-64e944c3-d8e0-44a2-adbe-2603bc5f8f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247280625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2247280625
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2802293802
Short name T456
Test name
Test status
Simulation time 25739799575 ps
CPU time 192.39 seconds
Started Jun 26 06:25:22 PM PDT 24
Finished Jun 26 06:28:37 PM PDT 24
Peak memory 250144 kb
Host smart-05622db0-069f-4e18-beee-bde9c8a40153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802293802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2802293802
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2409445923
Short name T718
Test name
Test status
Simulation time 36858033611 ps
CPU time 55.49 seconds
Started Jun 26 06:25:25 PM PDT 24
Finished Jun 26 06:26:23 PM PDT 24
Peak memory 257284 kb
Host smart-b168bd0c-8673-4da5-9b0e-abea2f3df74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409445923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2409445923
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.853809774
Short name T202
Test name
Test status
Simulation time 149550433849 ps
CPU time 243.35 seconds
Started Jun 26 06:25:25 PM PDT 24
Finished Jun 26 06:29:31 PM PDT 24
Peak memory 257848 kb
Host smart-c1635798-942a-4d5d-99a3-4e00bb75656d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853809774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.853809774
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2334103006
Short name T19
Test name
Test status
Simulation time 10543682630 ps
CPU time 21.01 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:25:46 PM PDT 24
Peak memory 243960 kb
Host smart-a51ae2ac-e05a-41eb-bb2f-4cf2d66bd1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334103006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2334103006
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1951199589
Short name T772
Test name
Test status
Simulation time 3446210060 ps
CPU time 14.67 seconds
Started Jun 26 06:25:22 PM PDT 24
Finished Jun 26 06:25:38 PM PDT 24
Peak memory 225496 kb
Host smart-464c5403-7e60-4abd-85ab-695690e03272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951199589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1951199589
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3526008427
Short name T634
Test name
Test status
Simulation time 32705498356 ps
CPU time 66.65 seconds
Started Jun 26 06:25:26 PM PDT 24
Finished Jun 26 06:26:35 PM PDT 24
Peak memory 238572 kb
Host smart-e5278884-08a1-433f-b154-38abc608a122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526008427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3526008427
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2447137593
Short name T788
Test name
Test status
Simulation time 8729860588 ps
CPU time 9.3 seconds
Started Jun 26 06:25:26 PM PDT 24
Finished Jun 26 06:25:37 PM PDT 24
Peak memory 225544 kb
Host smart-801da501-c202-419c-8e54-35fb6b658e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447137593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2447137593
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.212215265
Short name T833
Test name
Test status
Simulation time 660208101 ps
CPU time 5.2 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:25:30 PM PDT 24
Peak memory 233620 kb
Host smart-0ab4c84c-cb68-44b8-82bf-8a5c4ffc4c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212215265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.212215265
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2993050355
Short name T656
Test name
Test status
Simulation time 269837732 ps
CPU time 3.6 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:25:29 PM PDT 24
Peak memory 220092 kb
Host smart-c4d2e2c7-0573-4cc6-8dd7-af0fa28147ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2993050355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2993050355
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3872988280
Short name T174
Test name
Test status
Simulation time 3810959854 ps
CPU time 85.23 seconds
Started Jun 26 06:25:25 PM PDT 24
Finished Jun 26 06:26:53 PM PDT 24
Peak memory 250192 kb
Host smart-7447d564-66f2-42f4-a5a5-dab57d5792e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872988280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3872988280
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.104755484
Short name T741
Test name
Test status
Simulation time 2422189623 ps
CPU time 20.92 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:25:46 PM PDT 24
Peak memory 217312 kb
Host smart-e6bcd3ff-8422-42a7-9ef4-f0a2162b67ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104755484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.104755484
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1457433665
Short name T590
Test name
Test status
Simulation time 406924804 ps
CPU time 1.95 seconds
Started Jun 26 06:25:25 PM PDT 24
Finished Jun 26 06:25:29 PM PDT 24
Peak memory 208616 kb
Host smart-4754c179-65c1-4354-b7e9-a8e356ac05f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457433665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1457433665
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3025300406
Short name T936
Test name
Test status
Simulation time 150868342 ps
CPU time 1.16 seconds
Started Jun 26 06:25:22 PM PDT 24
Finished Jun 26 06:25:24 PM PDT 24
Peak memory 208716 kb
Host smart-eab6b6eb-c600-4874-ba8c-03b3e2f462d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025300406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3025300406
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1813221844
Short name T869
Test name
Test status
Simulation time 37128372 ps
CPU time 0.7 seconds
Started Jun 26 06:25:21 PM PDT 24
Finished Jun 26 06:25:23 PM PDT 24
Peak memory 206424 kb
Host smart-75151863-13c7-4e93-af4c-dcc70792fcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813221844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1813221844
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.115227111
Short name T801
Test name
Test status
Simulation time 7282810264 ps
CPU time 22.86 seconds
Started Jun 26 06:25:22 PM PDT 24
Finished Jun 26 06:25:46 PM PDT 24
Peak memory 233748 kb
Host smart-88008be7-5cd9-4c2a-8e87-c61c26e82c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115227111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.115227111
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2247696044
Short name T856
Test name
Test status
Simulation time 23522554 ps
CPU time 0.74 seconds
Started Jun 26 06:25:31 PM PDT 24
Finished Jun 26 06:25:33 PM PDT 24
Peak memory 206684 kb
Host smart-9b542349-4d75-42d4-bd74-a57d935c8de4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247696044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2247696044
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.567370775
Short name T212
Test name
Test status
Simulation time 158707392 ps
CPU time 2.56 seconds
Started Jun 26 06:25:31 PM PDT 24
Finished Jun 26 06:25:35 PM PDT 24
Peak memory 233636 kb
Host smart-527e93ef-5732-4aa1-9829-b979d040e9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567370775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.567370775
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.273086197
Short name T73
Test name
Test status
Simulation time 52294847 ps
CPU time 0.79 seconds
Started Jun 26 06:25:24 PM PDT 24
Finished Jun 26 06:25:27 PM PDT 24
Peak memory 207716 kb
Host smart-1252ca25-f09a-4e83-8915-420da798b90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273086197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.273086197
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.861415799
Short name T347
Test name
Test status
Simulation time 57039643020 ps
CPU time 64.89 seconds
Started Jun 26 06:25:29 PM PDT 24
Finished Jun 26 06:26:36 PM PDT 24
Peak memory 250164 kb
Host smart-c0b0ea48-0605-462c-8e99-e8e8a5a0f8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861415799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.861415799
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1982541188
Short name T8
Test name
Test status
Simulation time 31631710753 ps
CPU time 257.66 seconds
Started Jun 26 06:25:30 PM PDT 24
Finished Jun 26 06:29:49 PM PDT 24
Peak memory 250204 kb
Host smart-b0528819-b89a-4fc8-8280-038220696751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982541188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1982541188
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2513946560
Short name T266
Test name
Test status
Simulation time 25994189503 ps
CPU time 151.52 seconds
Started Jun 26 06:25:29 PM PDT 24
Finished Jun 26 06:28:02 PM PDT 24
Peak memory 254516 kb
Host smart-02f9a8c8-7227-4b2e-834a-b00c5e773238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513946560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2513946560
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1671614459
Short name T274
Test name
Test status
Simulation time 2365386215 ps
CPU time 21.86 seconds
Started Jun 26 06:25:30 PM PDT 24
Finished Jun 26 06:25:54 PM PDT 24
Peak memory 235372 kb
Host smart-c7cd8795-38bf-4186-a68b-5499260e66b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671614459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1671614459
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4235421364
Short name T416
Test name
Test status
Simulation time 244360005 ps
CPU time 5.11 seconds
Started Jun 26 06:25:22 PM PDT 24
Finished Jun 26 06:25:28 PM PDT 24
Peak memory 225412 kb
Host smart-3dd48580-57ee-4806-89f7-993d7c601218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235421364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4235421364
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3307641488
Short name T332
Test name
Test status
Simulation time 13059479554 ps
CPU time 48.57 seconds
Started Jun 26 06:25:29 PM PDT 24
Finished Jun 26 06:26:19 PM PDT 24
Peak memory 249820 kb
Host smart-8b0743cd-599b-48ef-8674-d58440e18e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307641488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3307641488
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3576481870
Short name T418
Test name
Test status
Simulation time 58302853537 ps
CPU time 25.49 seconds
Started Jun 26 06:25:25 PM PDT 24
Finished Jun 26 06:25:53 PM PDT 24
Peak memory 233736 kb
Host smart-29807822-ada0-4320-b7f7-dfb8824dfa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576481870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3576481870
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2112924164
Short name T701
Test name
Test status
Simulation time 7528025811 ps
CPU time 22.47 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:25:48 PM PDT 24
Peak memory 241504 kb
Host smart-93aafb45-1ed1-4278-97f5-33fa99c69c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112924164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2112924164
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.762993560
Short name T540
Test name
Test status
Simulation time 4446234639 ps
CPU time 11.8 seconds
Started Jun 26 06:25:28 PM PDT 24
Finished Jun 26 06:25:42 PM PDT 24
Peak memory 221956 kb
Host smart-920678a3-0b0d-465c-b35d-ac8c93b737f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=762993560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.762993560
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4015145653
Short name T566
Test name
Test status
Simulation time 1264833942 ps
CPU time 14.67 seconds
Started Jun 26 06:25:29 PM PDT 24
Finished Jun 26 06:25:46 PM PDT 24
Peak memory 217468 kb
Host smart-3393d3c7-7c39-4d69-8ce6-ea834039e8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015145653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4015145653
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2793164265
Short name T529
Test name
Test status
Simulation time 902328551 ps
CPU time 5.82 seconds
Started Jun 26 06:25:23 PM PDT 24
Finished Jun 26 06:25:30 PM PDT 24
Peak memory 217120 kb
Host smart-0efe9a66-b90c-40b7-b511-b2115339d18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793164265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2793164265
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.4182597676
Short name T547
Test name
Test status
Simulation time 175594146 ps
CPU time 7.95 seconds
Started Jun 26 06:25:21 PM PDT 24
Finished Jun 26 06:25:31 PM PDT 24
Peak memory 217188 kb
Host smart-140ce473-b677-4f89-bc7d-4031becdd8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182597676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4182597676
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1309691449
Short name T666
Test name
Test status
Simulation time 116979715 ps
CPU time 0.93 seconds
Started Jun 26 06:25:24 PM PDT 24
Finished Jun 26 06:25:27 PM PDT 24
Peak memory 206776 kb
Host smart-25a962ad-1222-4885-9daf-8158bb200039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309691449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1309691449
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2380484024
Short name T463
Test name
Test status
Simulation time 1617623805 ps
CPU time 11.86 seconds
Started Jun 26 06:25:24 PM PDT 24
Finished Jun 26 06:25:38 PM PDT 24
Peak memory 225440 kb
Host smart-d75b6005-abc4-40b6-b06e-67624fe903e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380484024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2380484024
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3792414333
Short name T589
Test name
Test status
Simulation time 15430340 ps
CPU time 0.73 seconds
Started Jun 26 06:23:36 PM PDT 24
Finished Jun 26 06:23:39 PM PDT 24
Peak memory 206688 kb
Host smart-1eef1742-bf1c-4faf-8bb2-be3beffac6b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792414333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
792414333
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.4088775782
Short name T244
Test name
Test status
Simulation time 574919536 ps
CPU time 2.46 seconds
Started Jun 26 06:23:34 PM PDT 24
Finished Jun 26 06:23:37 PM PDT 24
Peak memory 225408 kb
Host smart-30f918f4-db87-4924-b4cb-3f06c6dec32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088775782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4088775782
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.649998952
Short name T355
Test name
Test status
Simulation time 19138099 ps
CPU time 0.77 seconds
Started Jun 26 06:23:36 PM PDT 24
Finished Jun 26 06:23:38 PM PDT 24
Peak memory 206368 kb
Host smart-0476df46-0820-48c6-be81-5c62652735ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649998952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.649998952
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.4076794058
Short name T945
Test name
Test status
Simulation time 54182320193 ps
CPU time 139.59 seconds
Started Jun 26 06:23:34 PM PDT 24
Finished Jun 26 06:25:55 PM PDT 24
Peak memory 253376 kb
Host smart-373c7d9c-1583-4051-b82e-77f1cacf59aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076794058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.4076794058
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3849192785
Short name T198
Test name
Test status
Simulation time 3406497161 ps
CPU time 17.63 seconds
Started Jun 26 06:23:34 PM PDT 24
Finished Jun 26 06:23:53 PM PDT 24
Peak memory 233812 kb
Host smart-39a3b27b-c9b8-4a20-8381-b531f7a2c303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849192785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3849192785
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1181316577
Short name T887
Test name
Test status
Simulation time 96447219 ps
CPU time 3.08 seconds
Started Jun 26 06:23:36 PM PDT 24
Finished Jun 26 06:23:41 PM PDT 24
Peak memory 234176 kb
Host smart-b98ef86b-5392-4408-a4cc-af3000ae4f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181316577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1181316577
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3354762914
Short name T33
Test name
Test status
Simulation time 1490281023 ps
CPU time 12.11 seconds
Started Jun 26 06:23:35 PM PDT 24
Finished Jun 26 06:23:48 PM PDT 24
Peak memory 225324 kb
Host smart-bf21330a-ef63-45b7-86ab-7f0f1e558d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354762914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3354762914
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2236405076
Short name T12
Test name
Test status
Simulation time 14866224439 ps
CPU time 26.29 seconds
Started Jun 26 06:23:36 PM PDT 24
Finished Jun 26 06:24:05 PM PDT 24
Peak memory 225552 kb
Host smart-a3c48218-c33d-455b-8e67-80018a0efb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236405076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2236405076
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2148126119
Short name T904
Test name
Test status
Simulation time 15183130098 ps
CPU time 44.44 seconds
Started Jun 26 06:23:33 PM PDT 24
Finished Jun 26 06:24:18 PM PDT 24
Peak memory 249924 kb
Host smart-e794227d-ccd9-48de-9d66-ab70b8cce12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148126119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2148126119
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.463584584
Short name T398
Test name
Test status
Simulation time 726429632 ps
CPU time 6.13 seconds
Started Jun 26 06:23:35 PM PDT 24
Finished Jun 26 06:23:43 PM PDT 24
Peak memory 235032 kb
Host smart-9d6b579f-7ca6-437d-a9ab-987d16d6283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463584584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.463584584
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.349320009
Short name T779
Test name
Test status
Simulation time 361182823 ps
CPU time 3.93 seconds
Started Jun 26 06:23:33 PM PDT 24
Finished Jun 26 06:23:38 PM PDT 24
Peak memory 224180 kb
Host smart-49de8d0d-10c6-4810-bff7-f17cc04c5c8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=349320009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.349320009
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1281891671
Short name T69
Test name
Test status
Simulation time 238266574 ps
CPU time 1.18 seconds
Started Jun 26 06:23:40 PM PDT 24
Finished Jun 26 06:23:42 PM PDT 24
Peak memory 237096 kb
Host smart-81bcb75c-c428-4f2a-9ee1-fe5032ffc051
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281891671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1281891671
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3274131135
Short name T21
Test name
Test status
Simulation time 20904124697 ps
CPU time 186.15 seconds
Started Jun 26 06:23:34 PM PDT 24
Finished Jun 26 06:26:42 PM PDT 24
Peak memory 252176 kb
Host smart-e4c18856-c244-4200-a12e-df326ed59ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274131135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3274131135
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2992063139
Short name T710
Test name
Test status
Simulation time 1818970611 ps
CPU time 9.01 seconds
Started Jun 26 06:23:38 PM PDT 24
Finished Jun 26 06:23:49 PM PDT 24
Peak memory 217076 kb
Host smart-27a0156c-491a-4562-b47a-d5778228b9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992063139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2992063139
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1443025558
Short name T86
Test name
Test status
Simulation time 1420179691 ps
CPU time 2.96 seconds
Started Jun 26 06:23:36 PM PDT 24
Finished Jun 26 06:23:42 PM PDT 24
Peak memory 216872 kb
Host smart-ec9f06e5-6589-4ed8-b683-afc5f264a58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443025558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1443025558
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1660058459
Short name T10
Test name
Test status
Simulation time 268703346 ps
CPU time 3.24 seconds
Started Jun 26 06:23:35 PM PDT 24
Finished Jun 26 06:23:41 PM PDT 24
Peak memory 217160 kb
Host smart-370b9ce3-e651-402d-b66c-829d37661cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660058459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1660058459
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1010994030
Short name T488
Test name
Test status
Simulation time 28450919 ps
CPU time 0.88 seconds
Started Jun 26 06:23:32 PM PDT 24
Finished Jun 26 06:23:33 PM PDT 24
Peak memory 206936 kb
Host smart-5f6586e4-167e-424c-b1ab-8462524e555c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010994030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1010994030
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3570215968
Short name T719
Test name
Test status
Simulation time 10877662218 ps
CPU time 12.64 seconds
Started Jun 26 06:23:34 PM PDT 24
Finished Jun 26 06:23:48 PM PDT 24
Peak memory 233772 kb
Host smart-42e51c63-d7fc-47cc-b97e-0d911490031a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570215968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3570215968
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4280350367
Short name T828
Test name
Test status
Simulation time 21193842 ps
CPU time 0.77 seconds
Started Jun 26 06:25:29 PM PDT 24
Finished Jun 26 06:25:32 PM PDT 24
Peak memory 206328 kb
Host smart-3896eb7e-268c-4d77-a665-d6fc6beca39b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280350367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4280350367
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1257440138
Short name T917
Test name
Test status
Simulation time 47821381 ps
CPU time 0.82 seconds
Started Jun 26 06:25:28 PM PDT 24
Finished Jun 26 06:25:31 PM PDT 24
Peak memory 206392 kb
Host smart-ec076128-48cc-44d5-9158-e2008a1418cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257440138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1257440138
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3232674477
Short name T52
Test name
Test status
Simulation time 14310625195 ps
CPU time 74.35 seconds
Started Jun 26 06:25:30 PM PDT 24
Finished Jun 26 06:26:46 PM PDT 24
Peak memory 257504 kb
Host smart-9545c4d0-0fb5-41ad-bb61-070bf5667ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232674477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3232674477
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1953661491
Short name T841
Test name
Test status
Simulation time 2327220306 ps
CPU time 4.91 seconds
Started Jun 26 06:25:29 PM PDT 24
Finished Jun 26 06:25:36 PM PDT 24
Peak memory 218968 kb
Host smart-945378c8-2abc-4636-91d3-78513c6a1dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953661491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1953661491
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2522562038
Short name T916
Test name
Test status
Simulation time 5976619001 ps
CPU time 34.9 seconds
Started Jun 26 06:25:27 PM PDT 24
Finished Jun 26 06:26:04 PM PDT 24
Peak memory 239864 kb
Host smart-e6021801-9239-4698-b1e5-792d2a6dab38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522562038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2522562038
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2333109257
Short name T602
Test name
Test status
Simulation time 10479722194 ps
CPU time 20.84 seconds
Started Jun 26 06:25:28 PM PDT 24
Finished Jun 26 06:25:51 PM PDT 24
Peak memory 233796 kb
Host smart-8ccf4131-fee1-4f4a-97d6-880c9f13e87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333109257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2333109257
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3714338319
Short name T609
Test name
Test status
Simulation time 1564105036 ps
CPU time 14.67 seconds
Started Jun 26 06:25:34 PM PDT 24
Finished Jun 26 06:25:49 PM PDT 24
Peak memory 225408 kb
Host smart-1f9727d0-89f7-4f70-b2f3-cdec49a0fe6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714338319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3714338319
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.174056166
Short name T740
Test name
Test status
Simulation time 284134769 ps
CPU time 4.29 seconds
Started Jun 26 06:25:30 PM PDT 24
Finished Jun 26 06:25:36 PM PDT 24
Peak memory 233668 kb
Host smart-a87fb23d-591b-4dcb-835c-db900ace1348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174056166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.174056166
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3234832556
Short name T524
Test name
Test status
Simulation time 1510438918 ps
CPU time 6.78 seconds
Started Jun 26 06:25:28 PM PDT 24
Finished Jun 26 06:25:36 PM PDT 24
Peak memory 233632 kb
Host smart-1329411d-3225-481a-a394-01fcc19ea4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234832556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3234832556
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4182660312
Short name T854
Test name
Test status
Simulation time 9617896671 ps
CPU time 9.6 seconds
Started Jun 26 06:25:29 PM PDT 24
Finished Jun 26 06:25:41 PM PDT 24
Peak memory 224376 kb
Host smart-6cc49135-145f-4ef6-a64e-34b2bbe3290f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4182660312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4182660312
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4155664408
Short name T151
Test name
Test status
Simulation time 65214087701 ps
CPU time 307.99 seconds
Started Jun 26 06:25:33 PM PDT 24
Finished Jun 26 06:30:42 PM PDT 24
Peak memory 265880 kb
Host smart-8ed60dc1-9c48-4564-beae-cb3c352382e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155664408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4155664408
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.822937459
Short name T414
Test name
Test status
Simulation time 3866826124 ps
CPU time 11.53 seconds
Started Jun 26 06:25:29 PM PDT 24
Finished Jun 26 06:25:43 PM PDT 24
Peak memory 217200 kb
Host smart-7eb074f4-f08b-416e-ba1f-8dd6fcd70657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822937459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.822937459
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1711146332
Short name T625
Test name
Test status
Simulation time 14228859204 ps
CPU time 11.38 seconds
Started Jun 26 06:25:29 PM PDT 24
Finished Jun 26 06:25:42 PM PDT 24
Peak memory 218192 kb
Host smart-76004cf3-0f78-4896-9746-7f582a60a56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711146332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1711146332
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4062668915
Short name T3
Test name
Test status
Simulation time 61829761 ps
CPU time 1.58 seconds
Started Jun 26 06:25:30 PM PDT 24
Finished Jun 26 06:25:34 PM PDT 24
Peak memory 208844 kb
Host smart-dcde2e19-5dff-4638-9446-196523946846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062668915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4062668915
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3286576688
Short name T451
Test name
Test status
Simulation time 501210875 ps
CPU time 0.85 seconds
Started Jun 26 06:25:28 PM PDT 24
Finished Jun 26 06:25:31 PM PDT 24
Peak memory 206740 kb
Host smart-a94bafdd-aba3-4471-8f4e-2e26daf3ba4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286576688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3286576688
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1019035103
Short name T789
Test name
Test status
Simulation time 1174005252 ps
CPU time 6.4 seconds
Started Jun 26 06:25:30 PM PDT 24
Finished Jun 26 06:25:38 PM PDT 24
Peak memory 225480 kb
Host smart-ab31d7ec-179f-4014-b33f-cc31fee36485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019035103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1019035103
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.520708546
Short name T913
Test name
Test status
Simulation time 13224161 ps
CPU time 0.74 seconds
Started Jun 26 06:25:36 PM PDT 24
Finished Jun 26 06:25:37 PM PDT 24
Peak memory 206344 kb
Host smart-0e2460d5-7b97-411b-903d-df88002c93ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520708546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.520708546
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3375426742
Short name T222
Test name
Test status
Simulation time 788987689 ps
CPU time 8.61 seconds
Started Jun 26 06:25:36 PM PDT 24
Finished Jun 26 06:25:45 PM PDT 24
Peak memory 233524 kb
Host smart-38db77e3-e738-48d3-a13d-e3f5efafe2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375426742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3375426742
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1399918622
Short name T912
Test name
Test status
Simulation time 42586498 ps
CPU time 0.79 seconds
Started Jun 26 06:25:27 PM PDT 24
Finished Jun 26 06:25:30 PM PDT 24
Peak memory 207308 kb
Host smart-b1cc582f-2d28-47f2-a63b-e55c4a4a1f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399918622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1399918622
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4002500934
Short name T255
Test name
Test status
Simulation time 63746064083 ps
CPU time 242.32 seconds
Started Jun 26 06:25:38 PM PDT 24
Finished Jun 26 06:29:41 PM PDT 24
Peak memory 265756 kb
Host smart-dc7e7729-e089-42c5-92e5-36cd2ee33a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002500934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4002500934
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.654900145
Short name T126
Test name
Test status
Simulation time 34462479806 ps
CPU time 327.79 seconds
Started Jun 26 06:25:40 PM PDT 24
Finished Jun 26 06:31:09 PM PDT 24
Peak memory 250404 kb
Host smart-e0bc2afd-0152-44df-bfdc-ebf67cf9a632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654900145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.654900145
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.4260315235
Short name T211
Test name
Test status
Simulation time 626845314554 ps
CPU time 588.43 seconds
Started Jun 26 06:25:37 PM PDT 24
Finished Jun 26 06:35:27 PM PDT 24
Peak memory 263868 kb
Host smart-00748b38-7e5c-4294-9225-718e945d0650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260315235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.4260315235
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.418536590
Short name T677
Test name
Test status
Simulation time 448448571 ps
CPU time 7.41 seconds
Started Jun 26 06:25:39 PM PDT 24
Finished Jun 26 06:25:48 PM PDT 24
Peak memory 233676 kb
Host smart-3fe921c6-4275-44f4-a6d6-5f923b76f789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418536590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.418536590
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1179247219
Short name T513
Test name
Test status
Simulation time 2569598195 ps
CPU time 10.88 seconds
Started Jun 26 06:25:29 PM PDT 24
Finished Jun 26 06:25:42 PM PDT 24
Peak memory 233684 kb
Host smart-08505b18-5100-4444-b12a-e5dd35f6a0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179247219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1179247219
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2760710629
Short name T382
Test name
Test status
Simulation time 7099577992 ps
CPU time 16.97 seconds
Started Jun 26 06:25:37 PM PDT 24
Finished Jun 26 06:25:55 PM PDT 24
Peak memory 250008 kb
Host smart-b9efd82e-e854-4e7d-9304-ce3ba61b9b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760710629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2760710629
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.385680650
Short name T331
Test name
Test status
Simulation time 1198309447 ps
CPU time 4.74 seconds
Started Jun 26 06:25:33 PM PDT 24
Finished Jun 26 06:25:39 PM PDT 24
Peak memory 233616 kb
Host smart-ff1ebf3d-c04e-441c-b605-6773b1ef4058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385680650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.385680650
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.340617127
Short name T903
Test name
Test status
Simulation time 17992954708 ps
CPU time 15.85 seconds
Started Jun 26 06:25:28 PM PDT 24
Finished Jun 26 06:25:46 PM PDT 24
Peak memory 233736 kb
Host smart-3448d244-ac79-48b8-8bc2-c17400f43a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340617127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.340617127
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3604642857
Short name T630
Test name
Test status
Simulation time 857680413 ps
CPU time 6.98 seconds
Started Jun 26 06:25:37 PM PDT 24
Finished Jun 26 06:25:45 PM PDT 24
Peak memory 219824 kb
Host smart-8a449f19-e34f-4a9a-807d-2a352fbf39e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3604642857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3604642857
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.934241719
Short name T673
Test name
Test status
Simulation time 15933195016 ps
CPU time 194.28 seconds
Started Jun 26 06:25:40 PM PDT 24
Finished Jun 26 06:28:55 PM PDT 24
Peak memory 256720 kb
Host smart-f926a9c9-e62d-41e2-950c-e6bb30f4602c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934241719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.934241719
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1741024194
Short name T943
Test name
Test status
Simulation time 42909052 ps
CPU time 0.73 seconds
Started Jun 26 06:25:29 PM PDT 24
Finished Jun 26 06:25:32 PM PDT 24
Peak memory 206524 kb
Host smart-4c79d836-119e-4684-87ce-b5338c9120f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741024194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1741024194
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3550136347
Short name T651
Test name
Test status
Simulation time 1166941174 ps
CPU time 3.98 seconds
Started Jun 26 06:25:28 PM PDT 24
Finished Jun 26 06:25:34 PM PDT 24
Peak memory 217116 kb
Host smart-eb907fc3-c8fa-41de-ae5b-a2e5393004cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550136347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3550136347
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1651006396
Short name T458
Test name
Test status
Simulation time 913170742 ps
CPU time 2.68 seconds
Started Jun 26 06:25:27 PM PDT 24
Finished Jun 26 06:25:32 PM PDT 24
Peak memory 217128 kb
Host smart-4ad72876-61e7-41de-b7ce-e7c441bd2c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651006396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1651006396
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3366057649
Short name T686
Test name
Test status
Simulation time 47274647 ps
CPU time 0.76 seconds
Started Jun 26 06:25:29 PM PDT 24
Finished Jun 26 06:25:32 PM PDT 24
Peak memory 206740 kb
Host smart-5de7a79f-b128-4ed3-a711-6bb2eddb4215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366057649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3366057649
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.4151254562
Short name T864
Test name
Test status
Simulation time 8810772528 ps
CPU time 10.01 seconds
Started Jun 26 06:25:35 PM PDT 24
Finished Jun 26 06:25:45 PM PDT 24
Peak memory 233788 kb
Host smart-8acb47ad-4c5c-4ee7-8077-45df745fff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151254562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4151254562
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2500890578
Short name T707
Test name
Test status
Simulation time 12284267 ps
CPU time 0.71 seconds
Started Jun 26 06:25:36 PM PDT 24
Finished Jun 26 06:25:38 PM PDT 24
Peak memory 206688 kb
Host smart-6459a1d9-029d-4b14-8722-66df114354a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500890578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2500890578
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4237102147
Short name T478
Test name
Test status
Simulation time 307732351 ps
CPU time 2.25 seconds
Started Jun 26 06:25:37 PM PDT 24
Finished Jun 26 06:25:41 PM PDT 24
Peak memory 225364 kb
Host smart-6f334dca-28b5-435a-96e1-403daf5cf287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237102147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4237102147
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3200249337
Short name T559
Test name
Test status
Simulation time 34619387 ps
CPU time 0.85 seconds
Started Jun 26 06:25:38 PM PDT 24
Finished Jun 26 06:25:40 PM PDT 24
Peak memory 207480 kb
Host smart-61b39b21-6b4d-4bf4-98cc-68b9d8a5a45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200249337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3200249337
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2218136333
Short name T821
Test name
Test status
Simulation time 2502446352 ps
CPU time 42.72 seconds
Started Jun 26 06:25:38 PM PDT 24
Finished Jun 26 06:26:22 PM PDT 24
Peak memory 250068 kb
Host smart-a54dc8ac-62e4-4c3d-91f7-5ad87ae6ad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218136333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2218136333
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2855710231
Short name T497
Test name
Test status
Simulation time 60555631312 ps
CPU time 84.74 seconds
Started Jun 26 06:25:36 PM PDT 24
Finished Jun 26 06:27:01 PM PDT 24
Peak memory 250236 kb
Host smart-7fb055ee-7a54-4ae3-9f3d-770671a65c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855710231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2855710231
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.209556124
Short name T358
Test name
Test status
Simulation time 284394135 ps
CPU time 3.88 seconds
Started Jun 26 06:25:39 PM PDT 24
Finished Jun 26 06:25:44 PM PDT 24
Peak memory 237456 kb
Host smart-991e4daf-9086-4f2a-b884-e4d6a7dab821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209556124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.209556124
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1257041210
Short name T572
Test name
Test status
Simulation time 2411494927 ps
CPU time 5.21 seconds
Started Jun 26 06:25:34 PM PDT 24
Finished Jun 26 06:25:40 PM PDT 24
Peak memory 225500 kb
Host smart-281e4fd0-43ca-42e5-9c0c-ce850d70213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257041210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1257041210
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.265695945
Short name T865
Test name
Test status
Simulation time 182093897 ps
CPU time 5.29 seconds
Started Jun 26 06:25:36 PM PDT 24
Finished Jun 26 06:25:42 PM PDT 24
Peak memory 241420 kb
Host smart-e7e35b0b-27be-41c7-8986-3459c82d2574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265695945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.265695945
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.35560229
Short name T836
Test name
Test status
Simulation time 268383702 ps
CPU time 3.48 seconds
Started Jun 26 06:25:39 PM PDT 24
Finished Jun 26 06:25:43 PM PDT 24
Peak memory 225352 kb
Host smart-8d25af6f-0c5f-4792-bf57-e91c50836c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35560229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.35560229
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2909125184
Short name T603
Test name
Test status
Simulation time 370052602 ps
CPU time 3.18 seconds
Started Jun 26 06:25:37 PM PDT 24
Finished Jun 26 06:25:41 PM PDT 24
Peak memory 225400 kb
Host smart-a552c0ed-cdae-4627-a0e2-daff62dadb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909125184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2909125184
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2319006479
Short name T395
Test name
Test status
Simulation time 6409217411 ps
CPU time 11.77 seconds
Started Jun 26 06:25:40 PM PDT 24
Finished Jun 26 06:25:53 PM PDT 24
Peak memory 221472 kb
Host smart-37f3aaa0-e1f7-4e58-b3f5-4dfc9ac3b654
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2319006479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2319006479
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3385671926
Short name T834
Test name
Test status
Simulation time 7454203994 ps
CPU time 26.02 seconds
Started Jun 26 06:25:38 PM PDT 24
Finished Jun 26 06:26:05 PM PDT 24
Peak memory 217348 kb
Host smart-31e2ee3e-1aab-4645-87f5-583a2e5c36bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385671926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3385671926
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2964418222
Short name T646
Test name
Test status
Simulation time 6422987093 ps
CPU time 4.15 seconds
Started Jun 26 06:25:40 PM PDT 24
Finished Jun 26 06:25:45 PM PDT 24
Peak memory 217308 kb
Host smart-2ca681d5-d2bd-44a3-9c40-d89c75c2ff25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964418222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2964418222
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2390093357
Short name T438
Test name
Test status
Simulation time 24640428 ps
CPU time 0.71 seconds
Started Jun 26 06:25:38 PM PDT 24
Finished Jun 26 06:25:40 PM PDT 24
Peak memory 206460 kb
Host smart-4378d308-3fbc-4221-ab20-9322ae8f35f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390093357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2390093357
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.4253209205
Short name T88
Test name
Test status
Simulation time 41424382 ps
CPU time 0.82 seconds
Started Jun 26 06:25:39 PM PDT 24
Finished Jun 26 06:25:42 PM PDT 24
Peak memory 206684 kb
Host smart-8b76c052-981f-4728-b46d-d17d9bffdd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253209205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.4253209205
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3801410278
Short name T737
Test name
Test status
Simulation time 620507115 ps
CPU time 3.16 seconds
Started Jun 26 06:25:36 PM PDT 24
Finished Jun 26 06:25:40 PM PDT 24
Peak memory 233628 kb
Host smart-837be7a8-bb04-440f-80b8-8cfc7b2de249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801410278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3801410278
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1270405341
Short name T40
Test name
Test status
Simulation time 69510326 ps
CPU time 0.75 seconds
Started Jun 26 06:25:45 PM PDT 24
Finished Jun 26 06:25:48 PM PDT 24
Peak memory 206356 kb
Host smart-eb11a464-e8aa-4027-9ec5-52183e54cd3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270405341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1270405341
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1851524828
Short name T932
Test name
Test status
Simulation time 1419257348 ps
CPU time 8.6 seconds
Started Jun 26 06:25:47 PM PDT 24
Finished Jun 26 06:25:57 PM PDT 24
Peak memory 233584 kb
Host smart-6c638d17-7893-4615-86d2-149211ac9cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851524828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1851524828
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4064179949
Short name T699
Test name
Test status
Simulation time 75834561 ps
CPU time 0.84 seconds
Started Jun 26 06:25:38 PM PDT 24
Finished Jun 26 06:25:40 PM PDT 24
Peak memory 207396 kb
Host smart-217c0158-22a4-4522-80df-a6a2e354f02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064179949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4064179949
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3352946477
Short name T168
Test name
Test status
Simulation time 3199662992 ps
CPU time 44.42 seconds
Started Jun 26 06:25:45 PM PDT 24
Finished Jun 26 06:26:31 PM PDT 24
Peak memory 250836 kb
Host smart-a9cf87d5-00dc-45d9-9ec2-4b2d100cef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352946477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3352946477
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1757366510
Short name T554
Test name
Test status
Simulation time 6166963051 ps
CPU time 88.86 seconds
Started Jun 26 06:25:43 PM PDT 24
Finished Jun 26 06:27:13 PM PDT 24
Peak memory 251360 kb
Host smart-9d5ce3b4-6e32-4306-adb2-ad6edfd43823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757366510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1757366510
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2754614467
Short name T688
Test name
Test status
Simulation time 8605900124 ps
CPU time 74.68 seconds
Started Jun 26 06:25:44 PM PDT 24
Finished Jun 26 06:26:59 PM PDT 24
Peak memory 258412 kb
Host smart-7005a73c-64de-4620-9232-294fcda508a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754614467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2754614467
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.213014140
Short name T361
Test name
Test status
Simulation time 2470089417 ps
CPU time 46.29 seconds
Started Jun 26 06:25:43 PM PDT 24
Finished Jun 26 06:26:30 PM PDT 24
Peak memory 233724 kb
Host smart-3f603988-899a-407b-98a4-9bb549f04d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213014140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.213014140
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3766851681
Short name T235
Test name
Test status
Simulation time 62961802 ps
CPU time 3.03 seconds
Started Jun 26 06:25:46 PM PDT 24
Finished Jun 26 06:25:51 PM PDT 24
Peak memory 233656 kb
Host smart-e13c668a-79fb-468b-a70f-544edaf89bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766851681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3766851681
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2344934031
Short name T774
Test name
Test status
Simulation time 1262104820 ps
CPU time 18.96 seconds
Started Jun 26 06:25:46 PM PDT 24
Finished Jun 26 06:26:07 PM PDT 24
Peak memory 233524 kb
Host smart-d45d8e32-1f97-44ef-88b5-5e092a269f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344934031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2344934031
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1810604138
Short name T227
Test name
Test status
Simulation time 1019553024 ps
CPU time 7.87 seconds
Started Jun 26 06:25:37 PM PDT 24
Finished Jun 26 06:25:46 PM PDT 24
Peak memory 233548 kb
Host smart-b3f1b756-6f59-4c6d-8a23-f2c235f2943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810604138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1810604138
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3770642169
Short name T384
Test name
Test status
Simulation time 16309041168 ps
CPU time 41.04 seconds
Started Jun 26 06:25:37 PM PDT 24
Finished Jun 26 06:26:19 PM PDT 24
Peak memory 241300 kb
Host smart-97fb0d75-7575-4bfa-ae5e-63314425f9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770642169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3770642169
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.355935451
Short name T753
Test name
Test status
Simulation time 839864671 ps
CPU time 3.92 seconds
Started Jun 26 06:25:48 PM PDT 24
Finished Jun 26 06:25:53 PM PDT 24
Peak memory 220344 kb
Host smart-947c7637-e274-4dd9-8938-be6aebcae9ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=355935451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.355935451
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4133320968
Short name T891
Test name
Test status
Simulation time 75285236 ps
CPU time 1.09 seconds
Started Jun 26 06:25:44 PM PDT 24
Finished Jun 26 06:25:46 PM PDT 24
Peak memory 207844 kb
Host smart-0915dd99-91bb-4505-95a6-84a6f8fa7969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133320968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4133320968
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2068458493
Short name T563
Test name
Test status
Simulation time 5323453579 ps
CPU time 14.15 seconds
Started Jun 26 06:25:37 PM PDT 24
Finished Jun 26 06:25:52 PM PDT 24
Peak memory 217216 kb
Host smart-7afe78cf-9667-4cbe-9b18-9d0305ce5854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068458493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2068458493
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1049372091
Short name T682
Test name
Test status
Simulation time 2216797720 ps
CPU time 5.58 seconds
Started Jun 26 06:25:37 PM PDT 24
Finished Jun 26 06:25:44 PM PDT 24
Peak memory 217156 kb
Host smart-9a379307-8d3d-493b-86ac-e5336da7e77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049372091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1049372091
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.609260331
Short name T947
Test name
Test status
Simulation time 61157024 ps
CPU time 1.28 seconds
Started Jun 26 06:25:37 PM PDT 24
Finished Jun 26 06:25:40 PM PDT 24
Peak memory 217096 kb
Host smart-ba885e4a-c1b0-4588-9f87-7610f5df1c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609260331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.609260331
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.153439943
Short name T123
Test name
Test status
Simulation time 285382717 ps
CPU time 0.96 seconds
Started Jun 26 06:25:37 PM PDT 24
Finished Jun 26 06:25:39 PM PDT 24
Peak memory 206924 kb
Host smart-e095037f-f5a5-468c-87db-551e60dbdaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153439943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.153439943
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3900628628
Short name T791
Test name
Test status
Simulation time 1275109382 ps
CPU time 4.01 seconds
Started Jun 26 06:25:45 PM PDT 24
Finished Jun 26 06:25:51 PM PDT 24
Peak memory 225464 kb
Host smart-2f7ac960-4ba5-4629-a14f-9308f6cdc072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900628628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3900628628
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.44881789
Short name T510
Test name
Test status
Simulation time 12290956 ps
CPU time 0.71 seconds
Started Jun 26 06:25:46 PM PDT 24
Finished Jun 26 06:25:49 PM PDT 24
Peak memory 206284 kb
Host smart-5012ed19-cec1-4c16-8880-f3cdba2c4e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44881789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.44881789
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1650984060
Short name T89
Test name
Test status
Simulation time 379921915 ps
CPU time 2.67 seconds
Started Jun 26 06:25:48 PM PDT 24
Finished Jun 26 06:25:51 PM PDT 24
Peak memory 225376 kb
Host smart-9714d46a-05da-4772-b1f6-2589f7061a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650984060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1650984060
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.426735056
Short name T862
Test name
Test status
Simulation time 74450686 ps
CPU time 0.82 seconds
Started Jun 26 06:25:44 PM PDT 24
Finished Jun 26 06:25:46 PM PDT 24
Peak memory 207768 kb
Host smart-6212a00b-e02a-4561-bb8c-b5cf93503bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426735056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.426735056
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2028819799
Short name T256
Test name
Test status
Simulation time 2649093955 ps
CPU time 67.66 seconds
Started Jun 26 06:25:45 PM PDT 24
Finished Jun 26 06:26:54 PM PDT 24
Peak memory 266060 kb
Host smart-806ce8db-0d45-450d-af5e-6a1594df8273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028819799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2028819799
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.496967983
Short name T624
Test name
Test status
Simulation time 108701916195 ps
CPU time 118.27 seconds
Started Jun 26 06:25:46 PM PDT 24
Finished Jun 26 06:27:46 PM PDT 24
Peak memory 257672 kb
Host smart-cb9d245f-1a9b-4dc2-b32b-0d5685f391c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496967983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.496967983
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2581341118
Short name T669
Test name
Test status
Simulation time 50924211300 ps
CPU time 123.04 seconds
Started Jun 26 06:25:45 PM PDT 24
Finished Jun 26 06:27:50 PM PDT 24
Peak memory 241932 kb
Host smart-65889ca7-5e61-4bc7-bb2d-f4bb50e56eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581341118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2581341118
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3961937027
Short name T482
Test name
Test status
Simulation time 143778549 ps
CPU time 4.58 seconds
Started Jun 26 06:25:43 PM PDT 24
Finished Jun 26 06:25:49 PM PDT 24
Peak memory 225396 kb
Host smart-1458f171-9085-470a-81f9-e7654e6570bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961937027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3961937027
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3195470414
Short name T756
Test name
Test status
Simulation time 117017618 ps
CPU time 3.85 seconds
Started Jun 26 06:25:44 PM PDT 24
Finished Jun 26 06:25:49 PM PDT 24
Peak memory 219688 kb
Host smart-32768f50-b382-4355-8e1a-cb88492f017a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195470414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3195470414
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3900575143
Short name T786
Test name
Test status
Simulation time 371209223 ps
CPU time 10.55 seconds
Started Jun 26 06:25:44 PM PDT 24
Finished Jun 26 06:25:56 PM PDT 24
Peak memory 233624 kb
Host smart-fcac3902-cd49-4701-a78a-e9dbda5a5e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900575143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3900575143
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3152777986
Short name T949
Test name
Test status
Simulation time 6754918083 ps
CPU time 17.32 seconds
Started Jun 26 06:25:45 PM PDT 24
Finished Jun 26 06:26:04 PM PDT 24
Peak memory 225528 kb
Host smart-f5dbdfa1-f3c0-404a-9090-7b770a66efa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152777986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3152777986
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.847761374
Short name T539
Test name
Test status
Simulation time 3110713723 ps
CPU time 13.26 seconds
Started Jun 26 06:25:45 PM PDT 24
Finished Jun 26 06:26:01 PM PDT 24
Peak memory 241884 kb
Host smart-92217daf-c139-44b9-841d-53fc3fdba68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847761374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.847761374
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1765978032
Short name T534
Test name
Test status
Simulation time 1630239038 ps
CPU time 9.44 seconds
Started Jun 26 06:25:48 PM PDT 24
Finished Jun 26 06:25:58 PM PDT 24
Peak memory 224004 kb
Host smart-111a0d4b-f2a2-42bb-8ce4-5d9002d898c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1765978032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1765978032
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2258136402
Short name T278
Test name
Test status
Simulation time 4050343267 ps
CPU time 6.23 seconds
Started Jun 26 06:25:45 PM PDT 24
Finished Jun 26 06:25:52 PM PDT 24
Peak memory 217144 kb
Host smart-2b0823f9-bc75-4a8e-baf1-2a8e30a0ce12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258136402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2258136402
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3154030882
Short name T473
Test name
Test status
Simulation time 9628668448 ps
CPU time 12.63 seconds
Started Jun 26 06:25:44 PM PDT 24
Finished Jun 26 06:25:58 PM PDT 24
Peak memory 217208 kb
Host smart-4d656a49-58de-497e-8a4a-40b3441530b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154030882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3154030882
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.667725481
Short name T595
Test name
Test status
Simulation time 53108472 ps
CPU time 0.69 seconds
Started Jun 26 06:25:44 PM PDT 24
Finished Jun 26 06:25:46 PM PDT 24
Peak memory 206668 kb
Host smart-40e9c1eb-b7cd-4f08-bc23-b3c5bbd39a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667725481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.667725481
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3294676441
Short name T763
Test name
Test status
Simulation time 43435082 ps
CPU time 0.79 seconds
Started Jun 26 06:25:43 PM PDT 24
Finished Jun 26 06:25:45 PM PDT 24
Peak memory 206684 kb
Host smart-c3d7655a-ed2b-4449-a5f9-0e41f048e05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294676441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3294676441
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2364520380
Short name T457
Test name
Test status
Simulation time 526032090 ps
CPU time 2.33 seconds
Started Jun 26 06:25:46 PM PDT 24
Finished Jun 26 06:25:50 PM PDT 24
Peak memory 223708 kb
Host smart-7f3d897d-ed54-46dc-8737-58d9d095694b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364520380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2364520380
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3464721414
Short name T867
Test name
Test status
Simulation time 40611324 ps
CPU time 0.75 seconds
Started Jun 26 06:25:56 PM PDT 24
Finished Jun 26 06:25:58 PM PDT 24
Peak memory 206296 kb
Host smart-9b71b294-f15e-4c60-b218-144092a5ed7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464721414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3464721414
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1762796937
Short name T461
Test name
Test status
Simulation time 418316376 ps
CPU time 3.83 seconds
Started Jun 26 06:25:45 PM PDT 24
Finished Jun 26 06:25:51 PM PDT 24
Peak memory 233648 kb
Host smart-36adf781-c2b9-4ecc-a9d1-950f2f3f48b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762796937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1762796937
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.393326180
Short name T644
Test name
Test status
Simulation time 66165146 ps
CPU time 0.77 seconds
Started Jun 26 06:25:46 PM PDT 24
Finished Jun 26 06:25:48 PM PDT 24
Peak memory 206420 kb
Host smart-9d71cab8-6e47-4b64-b483-a3d9cb796b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393326180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.393326180
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.361303268
Short name T594
Test name
Test status
Simulation time 109751451128 ps
CPU time 179.19 seconds
Started Jun 26 06:25:49 PM PDT 24
Finished Jun 26 06:28:49 PM PDT 24
Peak memory 241932 kb
Host smart-f8f5ec80-1f14-4b38-a9c0-328fcc913e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361303268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.361303268
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1771527454
Short name T204
Test name
Test status
Simulation time 272628089130 ps
CPU time 470.07 seconds
Started Jun 26 06:25:52 PM PDT 24
Finished Jun 26 06:33:43 PM PDT 24
Peak memory 256972 kb
Host smart-2aaad90c-448c-4749-803b-16f0faf97576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771527454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1771527454
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1784366279
Short name T751
Test name
Test status
Simulation time 11768959272 ps
CPU time 41.88 seconds
Started Jun 26 06:25:55 PM PDT 24
Finished Jun 26 06:26:38 PM PDT 24
Peak memory 233788 kb
Host smart-b2fe5948-334b-4205-a492-95a68776689f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784366279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1784366279
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.222947751
Short name T652
Test name
Test status
Simulation time 409184633 ps
CPU time 2.45 seconds
Started Jun 26 06:25:44 PM PDT 24
Finished Jun 26 06:25:49 PM PDT 24
Peak memory 224112 kb
Host smart-bd6837b0-5d2a-413f-a267-f820e1fb07e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222947751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.222947751
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.436038233
Short name T808
Test name
Test status
Simulation time 6473625908 ps
CPU time 15.84 seconds
Started Jun 26 06:25:44 PM PDT 24
Finished Jun 26 06:26:00 PM PDT 24
Peak memory 233800 kb
Host smart-4b74d7c8-d0c8-44ee-a6b4-06306525a561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436038233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.436038233
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.756067336
Short name T472
Test name
Test status
Simulation time 140487082 ps
CPU time 2.34 seconds
Started Jun 26 06:25:46 PM PDT 24
Finished Jun 26 06:25:50 PM PDT 24
Peak memory 224096 kb
Host smart-b35cee45-49a0-4c74-82c4-36b477eff5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756067336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.756067336
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.4046119752
Short name T620
Test name
Test status
Simulation time 63142295 ps
CPU time 2.44 seconds
Started Jun 26 06:25:46 PM PDT 24
Finished Jun 26 06:25:50 PM PDT 24
Peak memory 233304 kb
Host smart-d2124093-50f1-4398-bba3-d9c533edaea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046119752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.4046119752
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.4183853662
Short name T498
Test name
Test status
Simulation time 2429157435 ps
CPU time 10.15 seconds
Started Jun 26 06:25:56 PM PDT 24
Finished Jun 26 06:26:08 PM PDT 24
Peak memory 220524 kb
Host smart-d70a00e0-03d4-483c-8085-35c288cc14e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4183853662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.4183853662
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1153077246
Short name T265
Test name
Test status
Simulation time 106313822485 ps
CPU time 221.63 seconds
Started Jun 26 06:25:54 PM PDT 24
Finished Jun 26 06:29:36 PM PDT 24
Peak memory 252672 kb
Host smart-879e9e97-7683-4448-8224-21685e55e8e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153077246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1153077246
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.858434436
Short name T807
Test name
Test status
Simulation time 22528016339 ps
CPU time 30.19 seconds
Started Jun 26 06:25:46 PM PDT 24
Finished Jun 26 06:26:18 PM PDT 24
Peak memory 217288 kb
Host smart-1d7b3940-5db7-4a7f-889b-cc9cb9f52124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858434436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.858434436
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1374452653
Short name T431
Test name
Test status
Simulation time 3429964226 ps
CPU time 12.68 seconds
Started Jun 26 06:25:45 PM PDT 24
Finished Jun 26 06:26:00 PM PDT 24
Peak memory 217436 kb
Host smart-94a82acc-07ad-43c9-ab47-06a76e541714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374452653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1374452653
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3234600731
Short name T493
Test name
Test status
Simulation time 27890702 ps
CPU time 0.98 seconds
Started Jun 26 06:25:47 PM PDT 24
Finished Jun 26 06:25:49 PM PDT 24
Peak memory 207796 kb
Host smart-b8ae8044-95ef-441f-8f0c-6ec7ca132710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234600731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3234600731
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.4010222713
Short name T657
Test name
Test status
Simulation time 47835146 ps
CPU time 0.74 seconds
Started Jun 26 06:25:45 PM PDT 24
Finished Jun 26 06:25:47 PM PDT 24
Peak memory 206720 kb
Host smart-546e7dd2-d31a-481f-8e9b-7f09b2e04d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010222713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.4010222713
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3825396059
Short name T717
Test name
Test status
Simulation time 9552232677 ps
CPU time 9.18 seconds
Started Jun 26 06:25:46 PM PDT 24
Finished Jun 26 06:25:57 PM PDT 24
Peak memory 241952 kb
Host smart-520ea35f-2574-4949-973a-0e493e553035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825396059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3825396059
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3244642996
Short name T555
Test name
Test status
Simulation time 97092572 ps
CPU time 0.78 seconds
Started Jun 26 06:25:52 PM PDT 24
Finished Jun 26 06:25:53 PM PDT 24
Peak memory 206652 kb
Host smart-05d45096-e74e-4f56-aa77-dada479cb178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244642996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3244642996
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.147261913
Short name T920
Test name
Test status
Simulation time 63789918 ps
CPU time 2.45 seconds
Started Jun 26 06:25:54 PM PDT 24
Finished Jun 26 06:25:58 PM PDT 24
Peak memory 233336 kb
Host smart-df2c8120-c2bd-4faa-b307-92dda0c500a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147261913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.147261913
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1407881519
Short name T412
Test name
Test status
Simulation time 31441799 ps
CPU time 0.76 seconds
Started Jun 26 06:25:54 PM PDT 24
Finished Jun 26 06:25:56 PM PDT 24
Peak memory 207656 kb
Host smart-bc827067-dc46-4222-aea9-c12dbf8ad307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407881519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1407881519
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3610990972
Short name T367
Test name
Test status
Simulation time 943858649 ps
CPU time 8.29 seconds
Started Jun 26 06:25:56 PM PDT 24
Finished Jun 26 06:26:06 PM PDT 24
Peak memory 225404 kb
Host smart-93e8ad06-a3a3-4fc7-ac52-8210bac56235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610990972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3610990972
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3886963679
Short name T662
Test name
Test status
Simulation time 11315220100 ps
CPU time 29.56 seconds
Started Jun 26 06:25:56 PM PDT 24
Finished Jun 26 06:26:27 PM PDT 24
Peak memory 250164 kb
Host smart-5ce4e3d9-8945-4469-be15-e931e8ac8c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886963679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3886963679
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3186411022
Short name T314
Test name
Test status
Simulation time 92210925190 ps
CPU time 201.57 seconds
Started Jun 26 06:25:57 PM PDT 24
Finished Jun 26 06:29:20 PM PDT 24
Peak memory 250108 kb
Host smart-7006119f-33a2-474c-bf00-58357c7d58d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186411022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3186411022
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2915986469
Short name T859
Test name
Test status
Simulation time 1323816382 ps
CPU time 9.14 seconds
Started Jun 26 06:25:53 PM PDT 24
Finished Jun 26 06:26:03 PM PDT 24
Peak memory 241848 kb
Host smart-a00a85cf-7bc5-44cd-8c3e-904309c9c7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915986469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2915986469
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.611665214
Short name T641
Test name
Test status
Simulation time 390024832 ps
CPU time 7.06 seconds
Started Jun 26 06:25:55 PM PDT 24
Finished Jun 26 06:26:04 PM PDT 24
Peak memory 225332 kb
Host smart-7cc24abb-55d8-4311-aa31-4a7fea66c523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611665214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.611665214
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1859271665
Short name T215
Test name
Test status
Simulation time 1469881835 ps
CPU time 7.74 seconds
Started Jun 26 06:25:53 PM PDT 24
Finished Jun 26 06:26:02 PM PDT 24
Peak memory 233660 kb
Host smart-44cfa722-5bf9-4718-9126-bab41e93d488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859271665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1859271665
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.231377112
Short name T447
Test name
Test status
Simulation time 58370314 ps
CPU time 2.23 seconds
Started Jun 26 06:25:56 PM PDT 24
Finished Jun 26 06:25:59 PM PDT 24
Peak memory 224648 kb
Host smart-806f3f58-16bc-49a9-beca-ffeb4ea75d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231377112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.231377112
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2204191162
Short name T612
Test name
Test status
Simulation time 6341418225 ps
CPU time 9.05 seconds
Started Jun 26 06:25:51 PM PDT 24
Finished Jun 26 06:26:01 PM PDT 24
Peak memory 233728 kb
Host smart-3b4c4306-cabe-4338-9f8d-471a593a9029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204191162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2204191162
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.116456787
Short name T922
Test name
Test status
Simulation time 490694132 ps
CPU time 8.51 seconds
Started Jun 26 06:25:53 PM PDT 24
Finished Jun 26 06:26:03 PM PDT 24
Peak memory 221116 kb
Host smart-bfc0d853-1e22-4456-9cb7-cc95c8ac2cf8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=116456787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.116456787
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2002190890
Short name T712
Test name
Test status
Simulation time 5316903807 ps
CPU time 102.76 seconds
Started Jun 26 06:25:52 PM PDT 24
Finished Jun 26 06:27:36 PM PDT 24
Peak memory 264572 kb
Host smart-b44e82ea-786e-42f8-aefa-3040a4ade33a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002190890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2002190890
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.460521569
Short name T784
Test name
Test status
Simulation time 2095087115 ps
CPU time 17.14 seconds
Started Jun 26 06:25:54 PM PDT 24
Finished Jun 26 06:26:12 PM PDT 24
Peak memory 218820 kb
Host smart-b76bee3d-3e6d-4ec2-a5de-c000d29d8141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460521569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.460521569
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1965961156
Short name T615
Test name
Test status
Simulation time 911827592 ps
CPU time 2.67 seconds
Started Jun 26 06:25:53 PM PDT 24
Finished Jun 26 06:25:57 PM PDT 24
Peak memory 217084 kb
Host smart-af365cf5-d39b-4a97-9c29-847abdf7c325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965961156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1965961156
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2597115353
Short name T507
Test name
Test status
Simulation time 72451158 ps
CPU time 1.28 seconds
Started Jun 26 06:25:53 PM PDT 24
Finished Jun 26 06:25:55 PM PDT 24
Peak memory 217112 kb
Host smart-ef397008-3cc7-4c82-8491-9ecf45e3603a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597115353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2597115353
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3697623558
Short name T363
Test name
Test status
Simulation time 18759605 ps
CPU time 0.75 seconds
Started Jun 26 06:25:55 PM PDT 24
Finished Jun 26 06:25:57 PM PDT 24
Peak memory 206640 kb
Host smart-f2c30c73-72b7-4229-a692-1cf9e20d984e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697623558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3697623558
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.978169282
Short name T659
Test name
Test status
Simulation time 11610581413 ps
CPU time 20.11 seconds
Started Jun 26 06:25:52 PM PDT 24
Finished Jun 26 06:26:13 PM PDT 24
Peak memory 241152 kb
Host smart-6794291b-2ffa-4743-a632-baf53f6ee6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978169282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.978169282
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3833103718
Short name T353
Test name
Test status
Simulation time 13163666 ps
CPU time 0.74 seconds
Started Jun 26 06:25:54 PM PDT 24
Finished Jun 26 06:25:55 PM PDT 24
Peak memory 206676 kb
Host smart-fceb0954-9c20-4a90-8921-034a218dfb8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833103718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3833103718
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.90980342
Short name T323
Test name
Test status
Simulation time 476427519 ps
CPU time 4.91 seconds
Started Jun 26 06:25:56 PM PDT 24
Finished Jun 26 06:26:03 PM PDT 24
Peak memory 233508 kb
Host smart-48b54607-5e26-4a95-b289-a0b720ad72a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90980342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.90980342
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1565535804
Short name T545
Test name
Test status
Simulation time 60125046 ps
CPU time 0.78 seconds
Started Jun 26 06:25:53 PM PDT 24
Finished Jun 26 06:25:55 PM PDT 24
Peak memory 207640 kb
Host smart-eb23dc02-f886-47c8-bc71-5f284db5d629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565535804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1565535804
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.569124306
Short name T45
Test name
Test status
Simulation time 3212191409 ps
CPU time 17.88 seconds
Started Jun 26 06:25:52 PM PDT 24
Finished Jun 26 06:26:11 PM PDT 24
Peak memory 225500 kb
Host smart-dfea5a2c-5772-4beb-9b07-171cf83a8482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569124306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.569124306
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3660915735
Short name T549
Test name
Test status
Simulation time 6177126660 ps
CPU time 92.77 seconds
Started Jun 26 06:25:57 PM PDT 24
Finished Jun 26 06:27:31 PM PDT 24
Peak memory 257520 kb
Host smart-88402f80-78fc-4076-bf0a-b7cd595d7151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660915735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3660915735
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1614236182
Short name T208
Test name
Test status
Simulation time 29635105696 ps
CPU time 259.05 seconds
Started Jun 26 06:25:55 PM PDT 24
Finished Jun 26 06:30:16 PM PDT 24
Peak memory 250140 kb
Host smart-fc2de763-7a92-4d66-8e7a-db5653092613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614236182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1614236182
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.475699399
Short name T371
Test name
Test status
Simulation time 639004958 ps
CPU time 15.04 seconds
Started Jun 26 06:25:53 PM PDT 24
Finished Jun 26 06:26:09 PM PDT 24
Peak memory 233580 kb
Host smart-be062f16-58fc-44a5-9626-4778d95345f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475699399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.475699399
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4157179892
Short name T179
Test name
Test status
Simulation time 943654725 ps
CPU time 5.05 seconds
Started Jun 26 06:25:52 PM PDT 24
Finished Jun 26 06:25:59 PM PDT 24
Peak memory 225504 kb
Host smart-acc3c440-ac46-4392-8f5e-11fd880fd5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157179892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4157179892
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.220580943
Short name T176
Test name
Test status
Simulation time 1032044518 ps
CPU time 8.66 seconds
Started Jun 26 06:25:54 PM PDT 24
Finished Jun 26 06:26:04 PM PDT 24
Peak memory 233692 kb
Host smart-62ab0431-4aef-4ac6-81cc-1dabdbb4d1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220580943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.220580943
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.616447633
Short name T259
Test name
Test status
Simulation time 59291039476 ps
CPU time 22.52 seconds
Started Jun 26 06:25:56 PM PDT 24
Finished Jun 26 06:26:20 PM PDT 24
Peak memory 233688 kb
Host smart-99a12c31-de36-4cf8-86ab-345a3b846581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616447633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.616447633
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3725320135
Short name T525
Test name
Test status
Simulation time 19483640516 ps
CPU time 15.66 seconds
Started Jun 26 06:25:56 PM PDT 24
Finished Jun 26 06:26:13 PM PDT 24
Peak memory 233684 kb
Host smart-49f56a0f-ea6d-423d-b64e-81383e5213dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725320135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3725320135
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1020966445
Short name T60
Test name
Test status
Simulation time 915355495 ps
CPU time 10.72 seconds
Started Jun 26 06:25:53 PM PDT 24
Finished Jun 26 06:26:05 PM PDT 24
Peak memory 221020 kb
Host smart-38692569-545b-4b3d-9765-2060ad121620
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1020966445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1020966445
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.195047232
Short name T714
Test name
Test status
Simulation time 3653073246 ps
CPU time 49.27 seconds
Started Jun 26 06:25:56 PM PDT 24
Finished Jun 26 06:26:47 PM PDT 24
Peak memory 255424 kb
Host smart-2d08abce-4327-4610-bea4-00cc27a8538b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195047232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.195047232
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2376745186
Short name T393
Test name
Test status
Simulation time 21113943328 ps
CPU time 29.31 seconds
Started Jun 26 06:25:53 PM PDT 24
Finished Jun 26 06:26:23 PM PDT 24
Peak memory 217208 kb
Host smart-5adfd06a-b4b2-4a6c-9e5a-a62df2776555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376745186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2376745186
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3811811514
Short name T9
Test name
Test status
Simulation time 9483431874 ps
CPU time 14.13 seconds
Started Jun 26 06:25:52 PM PDT 24
Finished Jun 26 06:26:07 PM PDT 24
Peak memory 217216 kb
Host smart-a722291e-e22f-497b-bfa4-d5ee40cd96ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811811514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3811811514
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.996780410
Short name T957
Test name
Test status
Simulation time 586692458 ps
CPU time 3.35 seconds
Started Jun 26 06:25:55 PM PDT 24
Finished Jun 26 06:25:59 PM PDT 24
Peak memory 217148 kb
Host smart-c1adec3e-dbf6-4fc9-8418-ee3fd07fdaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996780410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.996780410
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1719587738
Short name T951
Test name
Test status
Simulation time 61356082 ps
CPU time 0.76 seconds
Started Jun 26 06:25:53 PM PDT 24
Finished Jun 26 06:25:55 PM PDT 24
Peak memory 206720 kb
Host smart-704c63ea-df59-427f-995c-acd0d2f334f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719587738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1719587738
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3067400435
Short name T850
Test name
Test status
Simulation time 12610823540 ps
CPU time 39.61 seconds
Started Jun 26 06:25:55 PM PDT 24
Finished Jun 26 06:26:36 PM PDT 24
Peak memory 239464 kb
Host smart-fca1eb68-2437-4564-87df-59a3510cb8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067400435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3067400435
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.736624799
Short name T637
Test name
Test status
Simulation time 17826431 ps
CPU time 0.77 seconds
Started Jun 26 06:26:00 PM PDT 24
Finished Jun 26 06:26:03 PM PDT 24
Peak memory 206284 kb
Host smart-ab33830e-6ec3-4e61-9b64-9a9bc9153ba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736624799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.736624799
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3255262429
Short name T894
Test name
Test status
Simulation time 660107357 ps
CPU time 4.1 seconds
Started Jun 26 06:25:58 PM PDT 24
Finished Jun 26 06:26:03 PM PDT 24
Peak memory 233644 kb
Host smart-b7d556c1-bef1-4afd-9855-e7548f23cc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255262429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3255262429
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.912035518
Short name T730
Test name
Test status
Simulation time 17449718 ps
CPU time 0.75 seconds
Started Jun 26 06:25:51 PM PDT 24
Finished Jun 26 06:25:53 PM PDT 24
Peak memory 206432 kb
Host smart-a413897f-3ece-4fb7-83a0-523cfdf590b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912035518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.912035518
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2158781985
Short name T732
Test name
Test status
Simulation time 309716644808 ps
CPU time 144.84 seconds
Started Jun 26 06:26:00 PM PDT 24
Finished Jun 26 06:28:26 PM PDT 24
Peak memory 250164 kb
Host smart-7521b5ba-4d56-4f5c-a6df-8f10a5c7ad17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158781985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2158781985
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3477918763
Short name T263
Test name
Test status
Simulation time 40064133778 ps
CPU time 126.47 seconds
Started Jun 26 06:25:59 PM PDT 24
Finished Jun 26 06:28:07 PM PDT 24
Peak memory 252568 kb
Host smart-8b5b06c3-6428-4c22-85af-fc6d1b83760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477918763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3477918763
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.809718087
Short name T228
Test name
Test status
Simulation time 1763470681 ps
CPU time 41.23 seconds
Started Jun 26 06:26:00 PM PDT 24
Finished Jun 26 06:26:43 PM PDT 24
Peak memory 268780 kb
Host smart-e43c1d2c-3105-4ef6-a3c4-779544106e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809718087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.809718087
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.868988728
Short name T520
Test name
Test status
Simulation time 1503174005 ps
CPU time 6.8 seconds
Started Jun 26 06:26:01 PM PDT 24
Finished Jun 26 06:26:09 PM PDT 24
Peak memory 225416 kb
Host smart-207dfa8d-9b93-4c11-a118-41cbf6b924af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868988728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.868988728
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3067053440
Short name T173
Test name
Test status
Simulation time 1369636249 ps
CPU time 6.43 seconds
Started Jun 26 06:26:00 PM PDT 24
Finished Jun 26 06:26:08 PM PDT 24
Peak memory 233652 kb
Host smart-f3e8140c-cfff-4f69-bbd3-0a0aed9e4b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067053440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3067053440
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1385679087
Short name T170
Test name
Test status
Simulation time 25032367949 ps
CPU time 67.96 seconds
Started Jun 26 06:25:59 PM PDT 24
Finished Jun 26 06:27:09 PM PDT 24
Peak memory 249732 kb
Host smart-07d0a525-6e73-4ddc-a7f8-fe0a3923144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385679087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1385679087
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2888469052
Short name T748
Test name
Test status
Simulation time 2940505596 ps
CPU time 13.07 seconds
Started Jun 26 06:26:00 PM PDT 24
Finished Jun 26 06:26:15 PM PDT 24
Peak memory 233752 kb
Host smart-f08c61b8-5c72-4172-8192-97abdb9f08b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888469052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2888469052
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2300722220
Short name T310
Test name
Test status
Simulation time 282489761 ps
CPU time 2.34 seconds
Started Jun 26 06:26:00 PM PDT 24
Finished Jun 26 06:26:04 PM PDT 24
Peak memory 225432 kb
Host smart-29358afa-fb26-44a7-99bb-5d035d478aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300722220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2300722220
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4114331257
Short name T946
Test name
Test status
Simulation time 431211669 ps
CPU time 6.47 seconds
Started Jun 26 06:25:59 PM PDT 24
Finished Jun 26 06:26:06 PM PDT 24
Peak memory 224052 kb
Host smart-d8325859-7dd3-4a15-bc75-9257bfc756c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4114331257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4114331257
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2118254083
Short name T150
Test name
Test status
Simulation time 189321575 ps
CPU time 1.05 seconds
Started Jun 26 06:25:59 PM PDT 24
Finished Jun 26 06:26:00 PM PDT 24
Peak memory 207436 kb
Host smart-3e8b8556-1ef2-4a55-8e4a-d605573422c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118254083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2118254083
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3083254267
Short name T76
Test name
Test status
Simulation time 1559787584 ps
CPU time 6.08 seconds
Started Jun 26 06:25:55 PM PDT 24
Finished Jun 26 06:26:03 PM PDT 24
Peak memory 217192 kb
Host smart-7e1b31d5-5306-4dc8-acc1-7d41aaadc64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083254267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3083254267
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1828710896
Short name T495
Test name
Test status
Simulation time 504664261 ps
CPU time 2.84 seconds
Started Jun 26 06:25:52 PM PDT 24
Finished Jun 26 06:25:56 PM PDT 24
Peak memory 217052 kb
Host smart-f22651b2-85bb-42a1-becd-33057742283c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828710896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1828710896
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.4057502589
Short name T713
Test name
Test status
Simulation time 76375057 ps
CPU time 1.72 seconds
Started Jun 26 06:25:59 PM PDT 24
Finished Jun 26 06:26:02 PM PDT 24
Peak memory 217164 kb
Host smart-77f08fc6-7d99-4e11-9676-1087cc2f1aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057502589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.4057502589
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3788642298
Short name T341
Test name
Test status
Simulation time 185845757 ps
CPU time 0.87 seconds
Started Jun 26 06:25:51 PM PDT 24
Finished Jun 26 06:25:53 PM PDT 24
Peak memory 207784 kb
Host smart-0d718ccb-62a0-4413-80bc-a67d003be63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788642298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3788642298
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2173271688
Short name T57
Test name
Test status
Simulation time 15094897792 ps
CPU time 25.61 seconds
Started Jun 26 06:26:00 PM PDT 24
Finished Jun 26 06:26:27 PM PDT 24
Peak memory 233676 kb
Host smart-17cbac67-56b4-4476-bac3-f4336b40389d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173271688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2173271688
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.199509945
Short name T533
Test name
Test status
Simulation time 11382135 ps
CPU time 0.74 seconds
Started Jun 26 06:26:06 PM PDT 24
Finished Jun 26 06:26:07 PM PDT 24
Peak memory 205792 kb
Host smart-f79512cc-b658-4c7b-92c7-bf7f1c8b3436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199509945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.199509945
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.552002847
Short name T91
Test name
Test status
Simulation time 835361343 ps
CPU time 6.7 seconds
Started Jun 26 06:25:59 PM PDT 24
Finished Jun 26 06:26:08 PM PDT 24
Peak memory 225424 kb
Host smart-7d91f162-f69d-4d04-b92a-6ceee1cc20b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552002847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.552002847
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2944479630
Short name T286
Test name
Test status
Simulation time 16774452 ps
CPU time 0.75 seconds
Started Jun 26 06:25:59 PM PDT 24
Finished Jun 26 06:26:01 PM PDT 24
Peak memory 206380 kb
Host smart-145950d3-0fbf-405d-a6d3-2c2e9cec4f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944479630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2944479630
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.647254897
Short name T80
Test name
Test status
Simulation time 462659789 ps
CPU time 0.87 seconds
Started Jun 26 06:26:07 PM PDT 24
Finished Jun 26 06:26:09 PM PDT 24
Peak memory 217008 kb
Host smart-9f84122f-d001-4fd6-af17-6de6117b9d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647254897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.647254897
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.85542794
Short name T231
Test name
Test status
Simulation time 124548349305 ps
CPU time 869.55 seconds
Started Jun 26 06:26:10 PM PDT 24
Finished Jun 26 06:40:41 PM PDT 24
Peak memory 274504 kb
Host smart-671a8115-e595-4607-b81e-142f0c10dfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85542794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.85542794
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4277380126
Short name T803
Test name
Test status
Simulation time 16655690060 ps
CPU time 45.45 seconds
Started Jun 26 06:26:07 PM PDT 24
Finished Jun 26 06:26:54 PM PDT 24
Peak memory 242072 kb
Host smart-83a9c9b6-50d9-492f-800c-b6eaab5c5090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277380126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4277380126
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3153193893
Short name T766
Test name
Test status
Simulation time 352576622 ps
CPU time 5.15 seconds
Started Jun 26 06:26:01 PM PDT 24
Finished Jun 26 06:26:08 PM PDT 24
Peak memory 233688 kb
Host smart-2ef2a930-a33b-4fdb-a163-91ced69375d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153193893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3153193893
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3984178663
Short name T18
Test name
Test status
Simulation time 1635485172 ps
CPU time 2.45 seconds
Started Jun 26 06:26:00 PM PDT 24
Finished Jun 26 06:26:04 PM PDT 24
Peak memory 225356 kb
Host smart-e3b54112-ae08-44dd-aaf1-dcb79ca0ed7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984178663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3984178663
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2424771507
Short name T745
Test name
Test status
Simulation time 3648208912 ps
CPU time 25.73 seconds
Started Jun 26 06:25:59 PM PDT 24
Finished Jun 26 06:26:25 PM PDT 24
Peak memory 233780 kb
Host smart-088533d2-6fed-4f7b-b2fe-e6a86c40d308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424771507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2424771507
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3746935038
Short name T960
Test name
Test status
Simulation time 1903467829 ps
CPU time 5.1 seconds
Started Jun 26 06:26:00 PM PDT 24
Finished Jun 26 06:26:07 PM PDT 24
Peak memory 233572 kb
Host smart-f595980d-5dbf-4971-9425-5acb46c78460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746935038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3746935038
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1415700709
Short name T360
Test name
Test status
Simulation time 1676436692 ps
CPU time 5.21 seconds
Started Jun 26 06:26:00 PM PDT 24
Finished Jun 26 06:26:07 PM PDT 24
Peak memory 225440 kb
Host smart-c59ff550-93bc-4c54-8c7e-184d4b3363fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415700709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1415700709
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1502602805
Short name T366
Test name
Test status
Simulation time 871203057 ps
CPU time 4.05 seconds
Started Jun 26 06:26:08 PM PDT 24
Finished Jun 26 06:26:14 PM PDT 24
Peak memory 220252 kb
Host smart-f6a0e52f-4d43-4324-b3a9-fd2b2b9b6968
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1502602805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1502602805
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2781796077
Short name T148
Test name
Test status
Simulation time 56476492036 ps
CPU time 146.96 seconds
Started Jun 26 06:26:07 PM PDT 24
Finished Jun 26 06:28:36 PM PDT 24
Peak memory 251260 kb
Host smart-602a8df1-68b8-450d-96c8-2d073d33544e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781796077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2781796077
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1351170895
Short name T489
Test name
Test status
Simulation time 9097168320 ps
CPU time 20.54 seconds
Started Jun 26 06:25:59 PM PDT 24
Finished Jun 26 06:26:21 PM PDT 24
Peak memory 219016 kb
Host smart-63c6e318-a39b-43fd-ba7e-d640818863b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351170895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1351170895
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.965889607
Short name T742
Test name
Test status
Simulation time 1561173212 ps
CPU time 6.92 seconds
Started Jun 26 06:26:00 PM PDT 24
Finished Jun 26 06:26:09 PM PDT 24
Peak memory 217104 kb
Host smart-bd539bb4-8524-400f-a43e-e79f65157a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965889607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.965889607
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3796375851
Short name T280
Test name
Test status
Simulation time 35294499 ps
CPU time 0.87 seconds
Started Jun 26 06:26:02 PM PDT 24
Finished Jun 26 06:26:04 PM PDT 24
Peak memory 207792 kb
Host smart-9b096d8f-ad07-4950-bda4-c940e4a6f2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796375851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3796375851
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3717115972
Short name T373
Test name
Test status
Simulation time 17345663 ps
CPU time 0.76 seconds
Started Jun 26 06:25:59 PM PDT 24
Finished Jun 26 06:26:02 PM PDT 24
Peak memory 206740 kb
Host smart-b69e51c1-8788-4601-b947-36266d4e2de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717115972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3717115972
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1949632889
Short name T302
Test name
Test status
Simulation time 675753885 ps
CPU time 4.7 seconds
Started Jun 26 06:26:00 PM PDT 24
Finished Jun 26 06:26:06 PM PDT 24
Peak memory 233668 kb
Host smart-9b115ee3-a6a2-4dfc-b963-1ddc2bc211a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949632889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1949632889
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.745020160
Short name T618
Test name
Test status
Simulation time 13939216 ps
CPU time 0.74 seconds
Started Jun 26 06:23:38 PM PDT 24
Finished Jun 26 06:23:40 PM PDT 24
Peak memory 206600 kb
Host smart-76af0521-8ad6-4431-9a3c-fca0679b8917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745020160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.745020160
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1329380574
Short name T459
Test name
Test status
Simulation time 61127407 ps
CPU time 2.57 seconds
Started Jun 26 06:23:33 PM PDT 24
Finished Jun 26 06:23:36 PM PDT 24
Peak memory 233380 kb
Host smart-54f1a398-ef6a-4be2-841a-5a8bb0d5d212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329380574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1329380574
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3485127827
Short name T752
Test name
Test status
Simulation time 27468303 ps
CPU time 0.8 seconds
Started Jun 26 06:23:35 PM PDT 24
Finished Jun 26 06:23:38 PM PDT 24
Peak memory 207472 kb
Host smart-b1e334b6-96f2-401e-85b9-c5d5f9c7a58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485127827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3485127827
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.4000111000
Short name T223
Test name
Test status
Simulation time 129934551692 ps
CPU time 227.65 seconds
Started Jun 26 06:23:37 PM PDT 24
Finished Jun 26 06:27:27 PM PDT 24
Peak memory 257560 kb
Host smart-d3b4154c-9d01-4db3-b9c7-349cb2dc3c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000111000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.4000111000
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3739684358
Short name T218
Test name
Test status
Simulation time 73491360900 ps
CPU time 261.84 seconds
Started Jun 26 06:23:38 PM PDT 24
Finished Jun 26 06:28:01 PM PDT 24
Peak memory 240124 kb
Host smart-7e7ff5f8-cc48-41e1-bd34-931900005cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739684358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3739684358
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2657301607
Short name T760
Test name
Test status
Simulation time 2749616678 ps
CPU time 41.42 seconds
Started Jun 26 06:23:34 PM PDT 24
Finished Jun 26 06:24:17 PM PDT 24
Peak memory 238972 kb
Host smart-498974e6-f75a-47ee-880c-c63f6d3549de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657301607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2657301607
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.685873656
Short name T90
Test name
Test status
Simulation time 208839941 ps
CPU time 3.92 seconds
Started Jun 26 06:23:35 PM PDT 24
Finished Jun 26 06:23:41 PM PDT 24
Peak memory 225332 kb
Host smart-3bcda56d-3972-479f-9e53-ad9ec6496b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685873656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.685873656
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1311007750
Short name T600
Test name
Test status
Simulation time 115301605 ps
CPU time 2.2 seconds
Started Jun 26 06:23:35 PM PDT 24
Finished Jun 26 06:23:39 PM PDT 24
Peak memory 224424 kb
Host smart-298ae588-d4a5-4ed8-9949-1ba287ddb385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311007750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1311007750
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2377555280
Short name T897
Test name
Test status
Simulation time 670004275 ps
CPU time 2.37 seconds
Started Jun 26 06:23:37 PM PDT 24
Finished Jun 26 06:23:41 PM PDT 24
Peak memory 225084 kb
Host smart-27e14836-9445-407f-a125-bb270b0d0815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377555280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2377555280
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3665898619
Short name T35
Test name
Test status
Simulation time 330014267 ps
CPU time 3.28 seconds
Started Jun 26 06:23:37 PM PDT 24
Finished Jun 26 06:23:43 PM PDT 24
Peak memory 233616 kb
Host smart-c846271a-6d40-4d0d-98ab-a37b2950786c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665898619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3665898619
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2760375568
Short name T629
Test name
Test status
Simulation time 810118410 ps
CPU time 4.96 seconds
Started Jun 26 06:23:35 PM PDT 24
Finished Jun 26 06:23:41 PM PDT 24
Peak memory 224092 kb
Host smart-76740eb1-0875-4370-ac14-62421c0c30ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2760375568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2760375568
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1730735037
Short name T279
Test name
Test status
Simulation time 6231212134 ps
CPU time 26.33 seconds
Started Jun 26 06:23:37 PM PDT 24
Finished Jun 26 06:24:06 PM PDT 24
Peak memory 217404 kb
Host smart-63423eb0-d3d3-4ec0-8ada-fc924bce2922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730735037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1730735037
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1143561195
Short name T325
Test name
Test status
Simulation time 4088567496 ps
CPU time 11.71 seconds
Started Jun 26 06:23:37 PM PDT 24
Finished Jun 26 06:23:50 PM PDT 24
Peak memory 217228 kb
Host smart-9da388cb-555c-4e9a-9412-1765121fbb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143561195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1143561195
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3389656347
Short name T401
Test name
Test status
Simulation time 21147945 ps
CPU time 0.82 seconds
Started Jun 26 06:23:36 PM PDT 24
Finished Jun 26 06:23:39 PM PDT 24
Peak memory 206692 kb
Host smart-6a047152-58ce-4b2a-a0e2-818218fc335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389656347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3389656347
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1878700794
Short name T481
Test name
Test status
Simulation time 182318955 ps
CPU time 0.91 seconds
Started Jun 26 06:23:34 PM PDT 24
Finished Jun 26 06:23:36 PM PDT 24
Peak memory 206664 kb
Host smart-ab07c369-c1b9-47aa-bd75-a497f8f3e859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878700794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1878700794
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.457679855
Short name T817
Test name
Test status
Simulation time 18265475466 ps
CPU time 15.37 seconds
Started Jun 26 06:23:37 PM PDT 24
Finished Jun 26 06:23:54 PM PDT 24
Peak memory 225540 kb
Host smart-9de8cfb6-9190-456d-876d-134603c1ec48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457679855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.457679855
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.322758357
Short name T443
Test name
Test status
Simulation time 35932580 ps
CPU time 0.71 seconds
Started Jun 26 06:23:43 PM PDT 24
Finished Jun 26 06:23:45 PM PDT 24
Peak memory 205796 kb
Host smart-7769e66d-0431-427c-a131-b8d9d4975f9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322758357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.322758357
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3665597834
Short name T919
Test name
Test status
Simulation time 692765520 ps
CPU time 3.25 seconds
Started Jun 26 06:23:44 PM PDT 24
Finished Jun 26 06:23:50 PM PDT 24
Peak memory 233656 kb
Host smart-254a387f-abd0-4238-8bd6-61e2557ded29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665597834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3665597834
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1440401714
Short name T883
Test name
Test status
Simulation time 72321477 ps
CPU time 0.81 seconds
Started Jun 26 06:23:36 PM PDT 24
Finished Jun 26 06:23:39 PM PDT 24
Peak memory 207456 kb
Host smart-b425a8b6-677d-450f-808d-423e3b428f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440401714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1440401714
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.4013702410
Short name T262
Test name
Test status
Simulation time 38225548653 ps
CPU time 112.4 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:25:44 PM PDT 24
Peak memory 258020 kb
Host smart-7a360085-53e9-4f42-b70d-ade19b8e4b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013702410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.4013702410
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2264561328
Short name T927
Test name
Test status
Simulation time 7830435206 ps
CPU time 113.34 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:25:42 PM PDT 24
Peak memory 257704 kb
Host smart-f6948e58-a924-4703-8635-b08c6ec52714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264561328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2264561328
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3562374218
Short name T246
Test name
Test status
Simulation time 6248030198 ps
CPU time 96.46 seconds
Started Jun 26 06:23:44 PM PDT 24
Finished Jun 26 06:25:23 PM PDT 24
Peak memory 266840 kb
Host smart-3a91d961-0656-48c6-8b30-77feff1156c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562374218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3562374218
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3757713523
Short name T134
Test name
Test status
Simulation time 283302544 ps
CPU time 9.71 seconds
Started Jun 26 06:23:45 PM PDT 24
Finished Jun 26 06:23:57 PM PDT 24
Peak memory 241796 kb
Host smart-aa6dfb16-0507-4458-9498-c53e28c8ecfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757713523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3757713523
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1998301951
Short name T239
Test name
Test status
Simulation time 1880590275 ps
CPU time 6.07 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:23:54 PM PDT 24
Peak memory 225388 kb
Host smart-f8e664fa-6e79-4616-a321-4306ba13823b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998301951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1998301951
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3672216488
Short name T757
Test name
Test status
Simulation time 845370876 ps
CPU time 15.08 seconds
Started Jun 26 06:23:42 PM PDT 24
Finished Jun 26 06:23:59 PM PDT 24
Peak memory 233680 kb
Host smart-618a725e-6dbc-4a2f-8535-a7a86467be5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672216488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3672216488
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.994884834
Short name T848
Test name
Test status
Simulation time 1671313568 ps
CPU time 4.63 seconds
Started Jun 26 06:23:43 PM PDT 24
Finished Jun 26 06:23:50 PM PDT 24
Peak memory 233588 kb
Host smart-4f57467c-9c5c-45dc-9f2a-a67f1b4a4230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994884834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
994884834
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.815356959
Short name T492
Test name
Test status
Simulation time 1365166067 ps
CPU time 10.3 seconds
Started Jun 26 06:23:42 PM PDT 24
Finished Jun 26 06:23:54 PM PDT 24
Peak memory 233684 kb
Host smart-8253cbf1-0e00-4a5f-a09d-363ff802dcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815356959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.815356959
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3851479351
Short name T328
Test name
Test status
Simulation time 1053475590 ps
CPU time 6.99 seconds
Started Jun 26 06:23:44 PM PDT 24
Finished Jun 26 06:23:53 PM PDT 24
Peak memory 223632 kb
Host smart-c471c191-9c13-4edd-9b64-a229583705b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3851479351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3851479351
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2526015413
Short name T27
Test name
Test status
Simulation time 34545589071 ps
CPU time 158 seconds
Started Jun 26 06:23:40 PM PDT 24
Finished Jun 26 06:26:19 PM PDT 24
Peak memory 261976 kb
Host smart-13a44dd2-6127-49eb-989e-91ab40568101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526015413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2526015413
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1274874163
Short name T307
Test name
Test status
Simulation time 2261493466 ps
CPU time 22.62 seconds
Started Jun 26 06:23:32 PM PDT 24
Finished Jun 26 06:23:56 PM PDT 24
Peak memory 217436 kb
Host smart-072a6170-cc93-4146-b9f8-1dc41b535587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274874163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1274874163
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3710283753
Short name T837
Test name
Test status
Simulation time 696948995 ps
CPU time 2.62 seconds
Started Jun 26 06:23:37 PM PDT 24
Finished Jun 26 06:23:41 PM PDT 24
Peak memory 217116 kb
Host smart-1c4ede3c-1c71-401d-a800-7ebc7c7f35cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710283753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3710283753
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.4151362296
Short name T610
Test name
Test status
Simulation time 31441451 ps
CPU time 0.76 seconds
Started Jun 26 06:23:38 PM PDT 24
Finished Jun 26 06:23:40 PM PDT 24
Peak memory 206672 kb
Host smart-ee0b1f9d-061f-41ad-bf23-729906588bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151362296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.4151362296
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2770448851
Short name T831
Test name
Test status
Simulation time 39921619 ps
CPU time 0.74 seconds
Started Jun 26 06:23:38 PM PDT 24
Finished Jun 26 06:23:40 PM PDT 24
Peak memory 206484 kb
Host smart-9c057d6d-dd99-4572-b152-21eee6fd5191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770448851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2770448851
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3573124882
Short name T950
Test name
Test status
Simulation time 1527078728 ps
CPU time 6.32 seconds
Started Jun 26 06:23:44 PM PDT 24
Finished Jun 26 06:23:52 PM PDT 24
Peak memory 233604 kb
Host smart-51af4bf0-0318-48bd-be80-a4954e1aa432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573124882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3573124882
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2383823828
Short name T908
Test name
Test status
Simulation time 48447370 ps
CPU time 0.76 seconds
Started Jun 26 06:23:43 PM PDT 24
Finished Jun 26 06:23:45 PM PDT 24
Peak memory 205788 kb
Host smart-5b1d99fd-4039-471a-ab1c-64744176a2d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383823828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
383823828
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1314250109
Short name T124
Test name
Test status
Simulation time 1182642413 ps
CPU time 10.86 seconds
Started Jun 26 06:23:41 PM PDT 24
Finished Jun 26 06:23:53 PM PDT 24
Peak memory 225412 kb
Host smart-281b787b-5082-40ce-99ab-0f9f8e9ceb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314250109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1314250109
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.411705750
Short name T1
Test name
Test status
Simulation time 76638912 ps
CPU time 0.8 seconds
Started Jun 26 06:23:40 PM PDT 24
Finished Jun 26 06:23:42 PM PDT 24
Peak memory 207460 kb
Host smart-892d78c6-3264-4220-9311-f0dd76abfa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411705750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.411705750
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1980747161
Short name T875
Test name
Test status
Simulation time 929087674 ps
CPU time 6.08 seconds
Started Jun 26 06:23:45 PM PDT 24
Finished Jun 26 06:23:53 PM PDT 24
Peak memory 225420 kb
Host smart-fb425075-0a59-4f9e-8903-d0d532379e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980747161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1980747161
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1347308716
Short name T178
Test name
Test status
Simulation time 44017823125 ps
CPU time 133.41 seconds
Started Jun 26 06:23:42 PM PDT 24
Finished Jun 26 06:25:57 PM PDT 24
Peak memory 250304 kb
Host smart-1b489e5e-2fdc-4885-bd27-bd7ab12898a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347308716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1347308716
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1410023172
Short name T333
Test name
Test status
Simulation time 6614604595 ps
CPU time 52.17 seconds
Started Jun 26 06:23:43 PM PDT 24
Finished Jun 26 06:24:37 PM PDT 24
Peak memory 241292 kb
Host smart-2deb510c-fe96-4cee-8fbb-9fca9b8d6a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410023172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1410023172
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2043636705
Short name T285
Test name
Test status
Simulation time 1330729854 ps
CPU time 8.52 seconds
Started Jun 26 06:23:40 PM PDT 24
Finished Jun 26 06:23:50 PM PDT 24
Peak memory 241764 kb
Host smart-a97bc875-6cc0-49cd-92ad-e56a9954390b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043636705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2043636705
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1268946413
Short name T724
Test name
Test status
Simulation time 286562033 ps
CPU time 5.11 seconds
Started Jun 26 06:23:41 PM PDT 24
Finished Jun 26 06:23:48 PM PDT 24
Peak memory 225432 kb
Host smart-e7a4fbaf-e47b-4d28-9d02-f6f69b0c0d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268946413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1268946413
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2237425864
Short name T238
Test name
Test status
Simulation time 862923314 ps
CPU time 4.8 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:23:53 PM PDT 24
Peak memory 225276 kb
Host smart-0cef13b3-fc95-4e72-bd9a-2c6c89005151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237425864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2237425864
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2516115398
Short name T578
Test name
Test status
Simulation time 1730041222 ps
CPU time 2.36 seconds
Started Jun 26 06:23:41 PM PDT 24
Finished Jun 26 06:23:45 PM PDT 24
Peak memory 225436 kb
Host smart-bece062f-c018-4f4c-ac93-aa941079e382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516115398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2516115398
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2699254864
Short name T424
Test name
Test status
Simulation time 28345668938 ps
CPU time 17.8 seconds
Started Jun 26 06:23:40 PM PDT 24
Finished Jun 26 06:23:59 PM PDT 24
Peak memory 233724 kb
Host smart-15fe1aeb-09c3-4632-85bd-08bb46a72fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699254864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2699254864
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3136156275
Short name T429
Test name
Test status
Simulation time 919857372 ps
CPU time 13.35 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:24:02 PM PDT 24
Peak memory 223992 kb
Host smart-496299bb-59fb-4d89-a4c0-3c2530c1b2e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3136156275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3136156275
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.33403346
Short name T166
Test name
Test status
Simulation time 35412952143 ps
CPU time 351.62 seconds
Started Jun 26 06:23:40 PM PDT 24
Finished Jun 26 06:29:33 PM PDT 24
Peak memory 274424 kb
Host smart-5015838d-a760-4b3e-8532-57099a200cda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33403346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_
all.33403346
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.762894487
Short name T734
Test name
Test status
Simulation time 1897599096 ps
CPU time 22.25 seconds
Started Jun 26 06:23:42 PM PDT 24
Finished Jun 26 06:24:06 PM PDT 24
Peak memory 220344 kb
Host smart-9feadff4-9ea0-411a-9f97-bbd97dd91a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762894487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.762894487
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2856506432
Short name T514
Test name
Test status
Simulation time 9342167768 ps
CPU time 22.55 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:24:10 PM PDT 24
Peak memory 217276 kb
Host smart-09dfaa5d-8bb9-4f34-a72a-d77dcd773dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856506432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2856506432
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3551284407
Short name T700
Test name
Test status
Simulation time 64749521 ps
CPU time 1.42 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:23:50 PM PDT 24
Peak memory 208832 kb
Host smart-9e99d33c-2a05-42e5-8f27-220f20364d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551284407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3551284407
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3059434066
Short name T868
Test name
Test status
Simulation time 144624204 ps
CPU time 0.85 seconds
Started Jun 26 06:23:43 PM PDT 24
Finished Jun 26 06:23:45 PM PDT 24
Peak memory 206708 kb
Host smart-5da7af00-b77c-4383-a14b-face19dab59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059434066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3059434066
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.299783023
Short name T184
Test name
Test status
Simulation time 2989254945 ps
CPU time 4.86 seconds
Started Jun 26 06:23:41 PM PDT 24
Finished Jun 26 06:23:47 PM PDT 24
Peak memory 233788 kb
Host smart-cc9c3d9b-f779-457a-a3ac-d87b6d683eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299783023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.299783023
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.643861067
Short name T621
Test name
Test status
Simulation time 31533472 ps
CPU time 0.73 seconds
Started Jun 26 06:23:45 PM PDT 24
Finished Jun 26 06:23:48 PM PDT 24
Peak memory 205788 kb
Host smart-d1d1ab61-460d-42a3-9fe1-90cd94f8fb6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643861067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.643861067
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.98960987
Short name T660
Test name
Test status
Simulation time 159510631 ps
CPU time 5.15 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:23:53 PM PDT 24
Peak memory 233616 kb
Host smart-70c08f51-f4e5-4836-9ba8-81255f5b2782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98960987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.98960987
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.353539853
Short name T13
Test name
Test status
Simulation time 58383487 ps
CPU time 0.81 seconds
Started Jun 26 06:23:43 PM PDT 24
Finished Jun 26 06:23:45 PM PDT 24
Peak memory 207380 kb
Host smart-ac421ebf-ce8e-4eb5-a2ca-410442e52875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353539853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.353539853
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.969702500
Short name T805
Test name
Test status
Simulation time 13608823028 ps
CPU time 28.92 seconds
Started Jun 26 06:23:43 PM PDT 24
Finished Jun 26 06:24:13 PM PDT 24
Peak memory 252888 kb
Host smart-4caba9ac-5223-423f-85bf-c57a91ca696c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969702500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.969702500
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3623006305
Short name T502
Test name
Test status
Simulation time 21353919683 ps
CPU time 60.85 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:24:49 PM PDT 24
Peak memory 258220 kb
Host smart-46de5445-2281-43fc-9185-445ff625b56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623006305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3623006305
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.4172287551
Short name T505
Test name
Test status
Simulation time 116432753963 ps
CPU time 280.33 seconds
Started Jun 26 06:23:41 PM PDT 24
Finished Jun 26 06:28:23 PM PDT 24
Peak memory 241472 kb
Host smart-4fb72b49-2f00-4445-ba9c-6dc5359c4d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172287551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.4172287551
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.385787039
Short name T759
Test name
Test status
Simulation time 44953655 ps
CPU time 2.77 seconds
Started Jun 26 06:23:45 PM PDT 24
Finished Jun 26 06:23:50 PM PDT 24
Peak memory 233508 kb
Host smart-fc6601eb-8d16-4460-8b07-27709623b945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385787039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.385787039
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.190311993
Short name T930
Test name
Test status
Simulation time 165940719 ps
CPU time 4.93 seconds
Started Jun 26 06:23:43 PM PDT 24
Finished Jun 26 06:23:50 PM PDT 24
Peak memory 233648 kb
Host smart-b980cd42-8242-4231-85fb-9d23a83419a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190311993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.190311993
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3812613589
Short name T574
Test name
Test status
Simulation time 898092611 ps
CPU time 14.44 seconds
Started Jun 26 06:23:44 PM PDT 24
Finished Jun 26 06:24:01 PM PDT 24
Peak memory 241512 kb
Host smart-c0e96d1a-ba09-4250-b0a0-adecda30766d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812613589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3812613589
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.231716632
Short name T835
Test name
Test status
Simulation time 1282401891 ps
CPU time 5.12 seconds
Started Jun 26 06:23:44 PM PDT 24
Finished Jun 26 06:23:52 PM PDT 24
Peak memory 225372 kb
Host smart-8bfc802e-6b76-43ef-8499-ce2aa3442683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231716632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
231716632
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.756811597
Short name T649
Test name
Test status
Simulation time 1732602807 ps
CPU time 11.98 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:24:00 PM PDT 24
Peak memory 233648 kb
Host smart-669a75f0-c1ac-4d5a-8046-4770cca34d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756811597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.756811597
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3217756921
Short name T537
Test name
Test status
Simulation time 888807946 ps
CPU time 12.38 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:24:01 PM PDT 24
Peak memory 221276 kb
Host smart-a229dd6d-e7aa-40b3-9260-84b66d537f9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3217756921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3217756921
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.503056274
Short name T154
Test name
Test status
Simulation time 15023578552 ps
CPU time 159.06 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:26:31 PM PDT 24
Peak memory 250240 kb
Host smart-20fe4fba-e691-46a6-9809-95ce2e45d832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503056274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.503056274
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1934272844
Short name T849
Test name
Test status
Simulation time 1311308086 ps
CPU time 11.64 seconds
Started Jun 26 06:23:42 PM PDT 24
Finished Jun 26 06:23:55 PM PDT 24
Peak memory 217116 kb
Host smart-e4b9364b-5577-4ca7-bee8-18a6489dcc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934272844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1934272844
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3935022161
Short name T665
Test name
Test status
Simulation time 3057331374 ps
CPU time 6.34 seconds
Started Jun 26 06:23:44 PM PDT 24
Finished Jun 26 06:23:52 PM PDT 24
Peak memory 217224 kb
Host smart-b8abb155-ef46-427f-a2b1-aab5b3b31250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935022161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3935022161
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2748964742
Short name T291
Test name
Test status
Simulation time 100141498 ps
CPU time 1.87 seconds
Started Jun 26 06:23:44 PM PDT 24
Finished Jun 26 06:23:49 PM PDT 24
Peak memory 217068 kb
Host smart-64ddd8ea-a72b-492e-9dab-76eacb7b67d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748964742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2748964742
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4142253648
Short name T399
Test name
Test status
Simulation time 124221276 ps
CPU time 0.83 seconds
Started Jun 26 06:23:43 PM PDT 24
Finished Jun 26 06:23:46 PM PDT 24
Peak memory 206740 kb
Host smart-07f10b09-2bb5-42dc-81b1-bbedadee83c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142253648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4142253648
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2085399622
Short name T632
Test name
Test status
Simulation time 288370507 ps
CPU time 2.87 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:23:52 PM PDT 24
Peak memory 233284 kb
Host smart-40c2cf21-e8de-403c-bf8a-f73ca572b71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085399622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2085399622
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1074435280
Short name T408
Test name
Test status
Simulation time 25499060 ps
CPU time 0.78 seconds
Started Jun 26 06:23:52 PM PDT 24
Finished Jun 26 06:23:56 PM PDT 24
Peak memory 206296 kb
Host smart-3db570a9-a326-439a-a9a1-a5591044c276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074435280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
074435280
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1110351097
Short name T870
Test name
Test status
Simulation time 953164883 ps
CPU time 9.9 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:23:58 PM PDT 24
Peak memory 233592 kb
Host smart-d624c3d6-04b1-41ae-844d-4939854b6b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110351097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1110351097
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2770978487
Short name T453
Test name
Test status
Simulation time 17751034 ps
CPU time 0.79 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:23:49 PM PDT 24
Peak memory 206460 kb
Host smart-af7a3b6c-e832-45e5-85fb-98f14a255dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770978487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2770978487
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2852054735
Short name T195
Test name
Test status
Simulation time 1346365599 ps
CPU time 27.85 seconds
Started Jun 26 06:23:52 PM PDT 24
Finished Jun 26 06:24:23 PM PDT 24
Peak memory 238320 kb
Host smart-8071a791-30e6-4713-b2c4-b52151419626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852054735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2852054735
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1135320089
Short name T940
Test name
Test status
Simulation time 11527450406 ps
CPU time 98.5 seconds
Started Jun 26 06:23:48 PM PDT 24
Finished Jun 26 06:25:29 PM PDT 24
Peak memory 250228 kb
Host smart-ca528888-76d9-48db-9a35-bcbb1f3eee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135320089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1135320089
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4012778446
Short name T272
Test name
Test status
Simulation time 740791339 ps
CPU time 8.69 seconds
Started Jun 26 06:23:46 PM PDT 24
Finished Jun 26 06:23:56 PM PDT 24
Peak memory 225420 kb
Host smart-fb0c0fd0-ce1d-41c6-98f7-46fa5b2ac2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012778446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4012778446
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.162427122
Short name T914
Test name
Test status
Simulation time 75378161 ps
CPU time 2.04 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:23:54 PM PDT 24
Peak memory 219388 kb
Host smart-42f3afc5-fc6a-445b-a6f9-ceccc410b0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162427122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.162427122
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2671356105
Short name T770
Test name
Test status
Simulation time 19814022707 ps
CPU time 73.01 seconds
Started Jun 26 06:23:42 PM PDT 24
Finished Jun 26 06:24:57 PM PDT 24
Peak memory 225540 kb
Host smart-d293798c-3fb3-4fc0-bd4d-26d621669b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671356105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2671356105
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.356408863
Short name T233
Test name
Test status
Simulation time 1109932737 ps
CPU time 9.03 seconds
Started Jun 26 06:23:42 PM PDT 24
Finished Jun 26 06:23:53 PM PDT 24
Peak memory 241336 kb
Host smart-6418aa84-75bd-477f-993c-28b25b4ed80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356408863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
356408863
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.177215524
Short name T375
Test name
Test status
Simulation time 2204708231 ps
CPU time 10.63 seconds
Started Jun 26 06:23:43 PM PDT 24
Finished Jun 26 06:23:55 PM PDT 24
Peak memory 233796 kb
Host smart-99face9c-7582-46bd-8882-15e4763dbcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177215524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.177215524
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2955207170
Short name T941
Test name
Test status
Simulation time 3067899786 ps
CPU time 11.35 seconds
Started Jun 26 06:23:49 PM PDT 24
Finished Jun 26 06:24:03 PM PDT 24
Peak memory 224100 kb
Host smart-ef7a931a-342c-40ac-8f0a-d66be5ab43f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2955207170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2955207170
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1451216805
Short name T153
Test name
Test status
Simulation time 258581188 ps
CPU time 1.26 seconds
Started Jun 26 06:23:48 PM PDT 24
Finished Jun 26 06:23:52 PM PDT 24
Peak memory 216148 kb
Host smart-5328b509-a75c-46e6-96b3-b4bfedbc98b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451216805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1451216805
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2335512267
Short name T475
Test name
Test status
Simulation time 4654412858 ps
CPU time 22.33 seconds
Started Jun 26 06:23:43 PM PDT 24
Finished Jun 26 06:24:08 PM PDT 24
Peak memory 220824 kb
Host smart-4cbf7616-9703-4df8-ac6a-bdf5c1cdfa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335512267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2335512267
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2164935505
Short name T379
Test name
Test status
Simulation time 4428700979 ps
CPU time 5.99 seconds
Started Jun 26 06:23:39 PM PDT 24
Finished Jun 26 06:23:46 PM PDT 24
Peak memory 217212 kb
Host smart-edf29f01-50a7-4d33-8aa9-a5dd424152bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164935505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2164935505
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2471934567
Short name T295
Test name
Test status
Simulation time 14754817 ps
CPU time 0.76 seconds
Started Jun 26 06:23:48 PM PDT 24
Finished Jun 26 06:23:51 PM PDT 24
Peak memory 206732 kb
Host smart-ebcce5e5-296f-4b2e-b199-d1afb17d77c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471934567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2471934567
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2002454810
Short name T823
Test name
Test status
Simulation time 38855920 ps
CPU time 0.72 seconds
Started Jun 26 06:23:43 PM PDT 24
Finished Jun 26 06:23:45 PM PDT 24
Peak memory 206724 kb
Host smart-87e8173d-c70f-4715-a82a-2eef33a376b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002454810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2002454810
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2618025224
Short name T526
Test name
Test status
Simulation time 2912696735 ps
CPU time 9 seconds
Started Jun 26 06:23:42 PM PDT 24
Finished Jun 26 06:23:53 PM PDT 24
Peak memory 233700 kb
Host smart-327f892e-e8f5-454a-8c27-6582e966b55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618025224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2618025224
Directory /workspace/9.spi_device_upload/latest
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