Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2502946	1			T1	1		T2	1		T3	50
all_values[1]	2502946	1			T1	1		T2	1		T3	50
all_values[2]	2502946	1			T1	1		T2	1		T3	50
all_values[3]	2502946	1			T1	1		T2	1		T3	50
all_values[4]	2502946	1			T1	1		T2	1		T3	50
all_values[5]	2502946	1			T1	1		T2	1		T3	50
all_values[6]	2502946	1			T1	1		T2	1		T3	50
all_values[7]	2502946	1			T1	1		T2	1		T3	50

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19410539

1

T1

8

T2

8

T3

400

auto[1]

613029

1

T8

82563

T10

79

T16

74

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19997195

1

T1

8

T2

8

T3

400

auto[1]

26373

1

T8

453

T9

81

T10

59

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2424775	1			T1	1		T2	1		T3	50
all_values[0]	auto[0]	auto[1]	12094	1			T9	27		T10	3		T22	11
all_values[0]	auto[1]	auto[0]	65496	1			T8	27274		T10	7		T16	2
all_values[0]	auto[1]	auto[1]	581	1			T8	239		T10	7		T16	4
all_values[1]	auto[0]	auto[0]	2437679	1			T1	1		T2	1		T3	50
all_values[1]	auto[0]	auto[1]	7580	1			T8	169		T9	27		T10	3
all_values[1]	auto[1]	auto[0]	57297	1			T8	4		T10	2		T16	4
all_values[1]	auto[1]	auto[1]	390	1			T8	3		T10	4		T16	6
all_values[2]	auto[0]	auto[0]	2411818	1			T1	1		T2	1		T3	50
all_values[2]	auto[0]	auto[1]	3380	1			T8	1		T9	27		T10	3
all_values[2]	auto[1]	auto[0]	87412	1			T8	27488		T10	11		T16	6
all_values[2]	auto[1]	auto[1]	336	1			T8	24		T10	4		T16	9
all_values[3]	auto[0]	auto[0]	2401267	1			T1	1		T2	1		T3	50
all_values[3]	auto[0]	auto[1]	214	1			T10	1		T16	6		T17	2
all_values[3]	auto[1]	auto[0]	101285	1			T8	2		T10	6		T16	3
all_values[3]	auto[1]	auto[1]	180	1			T8	1		T10	3		T16	3
all_values[4]	auto[0]	auto[0]	2376221	1			T1	1		T2	1		T3	50
all_values[4]	auto[0]	auto[1]	205	1			T10	2		T16	3		T17	1
all_values[4]	auto[1]	auto[0]	126316	1			T8	27512		T10	6		T16	9
all_values[4]	auto[1]	auto[1]	204	1			T8	5		T10	2		T16	3
all_values[5]	auto[0]	auto[0]	2439696	1			T1	1		T2	1		T3	50
all_values[5]	auto[0]	auto[1]	187	1			T8	3		T10	3		T16	5
all_values[5]	auto[1]	auto[0]	62882	1			T8	3		T10	4		T16	3
all_values[5]	auto[1]	auto[1]	181	1			T8	1		T10	4		T16	3
all_values[6]	auto[0]	auto[0]	2444696	1			T1	1		T2	1		T3	50
all_values[6]	auto[0]	auto[1]	209	1			T8	3		T10	5		T16	7
all_values[6]	auto[1]	auto[0]	57832	1			T8	1		T10	3		T16	5
all_values[6]	auto[1]	auto[1]	209	1			T8	1		T10	4		T16	2
all_values[7]	auto[0]	auto[0]	2450310	1			T1	1		T2	1		T3	50
all_values[7]	auto[0]	auto[1]	208	1			T10	6		T16	2		T17	2
all_values[7]	auto[1]	auto[0]	52213	1			T8	2		T10	7		T16	8
all_values[7]	auto[1]	auto[1]	215	1			T8	3		T10	5		T16	4