Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	31784	1			T2	4		T3	6		T7	2
auto[SpiFlashAddrCfg]	7042	1			T2	4		T3	2		T7	2
auto[SpiFlashAddr3b]	8605	1			T2	2		T3	2		T7	4
auto[SpiFlashAddr4b]	7128	1			T3	2		T8	89		T9	14

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30476

1

T2

10

T3

12

T7

8

auto[1]

24083

1

T8

253

T9

43

T14

38

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28572

1

T2

10

T7

8

T8

352

auto[1]

25987

1

T3

12

T8

233

T9

44

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	36159	1			T2	4		T3	6		T7	6
values[1]	1091	1			T8	13		T9	4		T14	4
values[2]	1291	1			T3	2		T8	12		T14	2
values[3]	1380	1			T3	2		T8	13		T9	3
values[4]	1367	1			T7	2		T8	15		T9	2
values[5]	1360	1			T8	10		T14	3		T22	4
values[6]	1386	1			T8	10		T9	1		T22	4
values[7]	1292	1			T3	2		T8	11		T11	2
values[8]	9233	1			T2	6		T8	103		T9	18

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24086

1

T2

10

T3

12

T7

8

auto[1]

30473

1

T8

585

T9

69

T14

80

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

51615

1

T2

10

T3

12

T7

8

write

2944

1

T8

34

T9

5

T14

13

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17941

1

T2

4

T3

2

T8

191

valids[0x1]

36618

1

T2

6

T3

10

T7

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1482	1			T3	2		T8	16		T9	1
internal_process_ops[0x5a]	1503	1			T7	4		T8	16		T9	3
internal_process_ops[0x05]	18630	1			T2	4		T3	2		T7	2
internal_process_ops[0x35]	1504	1			T3	2		T8	20		T9	2
internal_process_ops[0x15]	1530	1			T8	21		T9	2		T14	3
internal_process_ops[0x03]	976	1			T7	2		T8	8		T14	1
internal_process_ops[0x0b]	947	1			T3	2		T8	8		T9	2
internal_process_ops[0x3b]	999	1			T8	5		T9	1		T14	2
internal_process_ops[0x6b]	902	1			T8	5		T14	1		T22	3
internal_process_ops[0xbb]	923	1			T2	4		T8	3		T9	1
internal_process_ops[0xeb]	895	1			T3	2		T8	6		T9	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53048

1

T2

10

T3

12

T7

8

auto[1]

1511

1

T8

18

T9

1

T14

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52387

1

T2

10

T3

12

T7

8

auto[1]

2172

1

T8

22

T9

2

T14

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7600

1

T2

4

T3

6

T7

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4438

1

T22

4

T39

1

T25

125

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1857

1

T2

4

T3

2

T7

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1542

1

T22

9

T39

7

T25

17

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2145

1

T2

2

T3

2

T7

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1845

1

T22

6

T39

14

T25

15

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1839

1

T3

2

T11

2

T22

7

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1539

1

T22

10

T39

4

T25

24

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

106

1

T25

1

T57

2

T18

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

77

1

T21

1

T48

4

T51

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

48

1

T164

1

T165

3

T166

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

71

1

T25

1

T43

1

T46

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

102

1

T25

3

T38

1

T45

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

95

1

T43

2

T47

2

T50

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

68

1

T22

1

T38

1

T48

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

75

1

T25

4

T43

1

T21

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

93

1

T167

2

T21

4

T46

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

80

1

T25

6

T47

4

T50

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

62

1

T39

2

T21

3

T46

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

85

1

T50

1

T168

2

T51

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

106

1

T39

1

T25

1

T46

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

79

1

T25

2

T46

1

T47

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

68

1

T39

1

T25

1

T21

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

66

1

T25

1

T38

2

T169

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10635

1

T8

205

T9

15

T14

20

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8432

1

T8

131

T9

15

T14

11

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1478

1

T8

31

T14

6

T27

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1413

1

T8

37

T9

6

T14

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1951

1

T8

40

T9

7

T14

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1884

1

T8

30

T9

10

T14

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1447

1

T8

39

T9

2

T14

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1570

1

T8

38

T9

9

T14

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

91

1

T8

2

T84

3

T41

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

86

1

T8

3

T40

2

T84

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

82

1

T8

3

T27

1

T40

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

118

1

T85

1

T41

6

T93

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

80

1

T14

3

T40

2

T85

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

121

1

T8

3

T9

1

T40

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

99

1

T8

1

T85

3

T170

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

112

1

T8

4

T40

2

T29

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

103

1

T8

1

T9

1

T27

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

122

1

T8

2

T14

2

T27

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

111

1

T27

1

T85

1

T84

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

124

1

T8

3

T14

3

T27

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

97

1

T8

4

T27

1

T40

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

86

1

T8

2

T14

2

T85

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

117

1

T8

5

T9

3

T14

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

114

1

T8

1

T14

1

T27

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3239	1			T22	18		T44	24		T39	17
auto[0]	values[0]	valids[0x1]	11179	1			T2	4		T3	6		T7	6
auto[0]	values[1]	valids[0x1]	520	1			T22	3		T39	1		T25	4
auto[0]	values[2]	valids[0x0]	436	1			T22	4		T39	4		T25	13
auto[0]	values[2]	valids[0x1]	263	1			T3	2		T39	1		T25	2
auto[0]	values[3]	valids[0x0]	444	1			T3	2		T22	1		T25	5
auto[0]	values[3]	valids[0x1]	258	1			T39	3		T25	2		T38	1
auto[0]	values[4]	valids[0x0]	479	1			T22	3		T39	1		T25	3
auto[0]	values[4]	valids[0x1]	240	1			T7	2		T39	5		T25	3
auto[0]	values[5]	valids[0x0]	455	1			T22	4		T39	4		T25	13
auto[0]	values[5]	valids[0x1]	260	1			T39	2		T25	1		T38	2
auto[0]	values[6]	valids[0x0]	472	1			T22	3		T25	10		T54	4
auto[0]	values[6]	valids[0x1]	239	1			T22	1		T25	3		T38	4
auto[0]	values[7]	valids[0x0]	429	1			T11	2		T22	3		T39	2
auto[0]	values[7]	valids[0x1]	290	1			T3	2		T22	3		T25	9
auto[0]	values[8]	valids[0x0]	3012	1			T2	4		T22	10		T39	16
auto[0]	values[8]	valids[0x1]	1871	1			T2	2		T22	5		T39	4
auto[1]	values[0]	valids[0x0]	4105	1			T8	80		T9	10		T14	14
auto[1]	values[0]	valids[0x1]	17636	1			T8	318		T9	31		T14	32
auto[1]	values[1]	valids[0x1]	571	1			T8	13		T9	4		T14	4
auto[1]	values[2]	valids[0x0]	361	1			T8	12		T14	2		T27	4
auto[1]	values[2]	valids[0x1]	231	1			T27	3		T40	2		T85	4
auto[1]	values[3]	valids[0x0]	421	1			T8	11		T9	1		T14	2
auto[1]	values[3]	valids[0x1]	257	1			T8	2		T9	2		T27	2
auto[1]	values[4]	valids[0x0]	406	1			T8	12		T27	3		T40	2
auto[1]	values[4]	valids[0x1]	242	1			T8	3		T9	2		T14	1
auto[1]	values[5]	valids[0x0]	363	1			T8	3		T14	2		T27	1
auto[1]	values[5]	valids[0x1]	282	1			T8	7		T14	1		T27	6
auto[1]	values[6]	valids[0x0]	399	1			T8	6		T40	2		T29	4
auto[1]	values[6]	valids[0x1]	276	1			T8	4		T9	1		T27	4
auto[1]	values[7]	valids[0x0]	367	1			T8	8		T14	2		T27	7
auto[1]	values[7]	valids[0x1]	206	1			T8	3		T27	5		T40	5
auto[1]	values[8]	valids[0x0]	2553	1			T8	59		T9	15		T14	11
auto[1]	values[8]	valids[0x1]	1797	1			T8	44		T9	3		T14	9