Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3408740

1

T2

1

T3

1033

T6

7

auto[1]

24629

1

T8

166

T9

9

T14

53

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1103043

1

T2

1

T3

1

T6

7

auto[1]

2330326

1

T3

1032

T7

256

T8

22522

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	648758	1			T2	1		T3	1033		T7	257
auto[524288:1048575]	424220	1			T8	4078		T9	514		T14	10
auto[1048576:1572863]	422385	1			T8	4128		T14	16		T22	6
auto[1572864:2097151]	362501	1			T8	1472		T14	9		T22	3
auto[2097152:2621439]	404509	1			T8	1381		T11	3		T14	560
auto[2621440:3145727]	383830	1			T8	7545		T11	577		T14	2329
auto[3145728:3670015]	429096	1			T8	559		T9	907		T11	406
auto[3670016:4194303]	358070	1			T6	7		T8	1103		T9	1660

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2362235

1

T2

1

T3

1033

T6

2

auto[1]

1071134

1

T6

5

T8

1

T11

662

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3034488

1

T2

1

T3

1033

T6

7

auto[1]

398881

1

T8

2937

T9

1925

T14

537

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	257670	1			T2	1		T3	1		T7	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	333831	1			T3	1032		T7	256		T8	2358
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	104059	1			T8	4		T9	1		T14	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	257071	1			T8	3229		T9	256		T22	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	133588	1			T8	10		T14	7		T22	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	234410	1			T8	2113		T22	5		T25	4109
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	105448	1			T8	7		T14	9		T39	39
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	209363	1			T8	1372		T22	3		T39	1439
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	142107	1			T11	2		T14	18		T44	225
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	213822	1			T8	1379		T11	1		T14	256
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	118046	1			T8	13		T11	314		T14	24
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	216762	1			T8	7497		T11	263		T14	2275
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	120322	1			T8	12		T9	4		T11	276
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	265682	1			T8	516		T9	894		T11	130
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	104607	1			T6	7		T8	24		T14	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	196097	1			T8	1038		T22	290		T25	384
auto[0]	auto[1]	auto[0:524287]	auto[0]	1684	1			T9	3		T14	12		T22	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	51350	1			T9	3		T14	229		T22	4
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	663	1			T8	2		T14	2		T22	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	58930	1			T8	840		T9	257		T22	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1610	1			T8	3		T14	6		T39	9
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	50047	1			T8	1946		T39	343		T25	261
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1406	1			T39	27		T27	3		T40	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	43913	1			T8	90		T39	1708		T27	11
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1758	1			T8	1		T14	15		T39	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	43850	1			T14	256		T39	512		T40	22
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2816	1			T14	2		T44	7		T39	11
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	42961	1			T27	256		T18	2353		T20	914
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1876	1			T8	2		T9	2		T14	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	38467	1			T22	3036		T25	2		T84	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1901	1			T8	1		T9	3		T14	8
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	52623	1			T8	1		T9	1657		T40	4
auto[1]	auto[0]	auto[0:524287]	auto[0]	456	1			T9	1		T14	2		T25	5
auto[1]	auto[0]	auto[0:524287]	auto[1]	3425	1			T9	1		T25	49		T40	130
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	382	1			T8	1		T14	3		T25	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2715	1			T8	2		T25	1		T192	13
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	345	1			T8	3		T14	3		T39	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1828	1			T8	3		T38	15		T27	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	330	1			T8	1		T40	1		T85	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1704	1			T8	2		T40	2		T85	36
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	355	1			T8	1		T14	12		T27	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2181	1			T40	19		T85	170		T170	29
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	357	1			T8	4		T14	9		T25	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2559	1			T8	31		T14	19		T25	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	383	1			T8	3		T9	1		T38	13
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1995	1			T8	26		T9	6		T38	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	362	1			T8	6		T27	2		T29	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2226	1			T8	32		T27	1		T29	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	58	1			T22	1		T27	1		T18	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	284	1			T22	4		T86	25		T235	41
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	68	1			T14	2		T20	2		T132	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	332	1			T51	1		T153	2		T87	14
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	52	1			T8	3		T39	3		T25	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	505	1			T8	47		T39	174		T25	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	91	1			T39	8		T27	2		T41	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	246	1			T39	28		T27	3		T41	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	59	1			T14	3		T41	1		T51	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	377	1			T41	3		T51	1		T164	40
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	64	1			T84	5		T20	3		T168	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	265	1			T20	5		T168	76		T164	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	59	1			T25	2		T84	5		T192	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	312	1			T25	36		T21	1		T168	19
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	61	1			T8	1		T43	2		T46	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	193	1			T43	7		T236	19		T49	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1951144	1			T2	1		T3	1033		T6	2
auto[0]	auto[0]	auto[1]	1061741	1			T6	5		T11	662		T44	477
auto[0]	auto[1]	auto[0]	387088	1			T8	2886		T9	1925		T14	532
auto[0]	auto[1]	auto[1]	8767	1			T44	396		T237	1		T235	3
auto[1]	auto[0]	auto[0]	21067	1			T8	114		T9	9		T14	43
auto[1]	auto[0]	auto[1]	536	1			T8	1		T14	5		T39	1
auto[1]	auto[1]	auto[0]	2936	1			T8	51		T14	4		T22	5
auto[1]	auto[1]	auto[1]	90	1			T14	1		T39	2		T25	1