Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2502946	1			T1	1		T2	1		T3	50
all_pins[1]	2502946	1			T1	1		T2	1		T3	50
all_pins[2]	2502946	1			T1	1		T2	1		T3	50
all_pins[3]	2502946	1			T1	1		T2	1		T3	50
all_pins[4]	2502946	1			T1	1		T2	1		T3	50
all_pins[5]	2502946	1			T1	1		T2	1		T3	50
all_pins[6]	2502946	1			T1	1		T2	1		T3	50
all_pins[7]	2502946	1			T1	1		T2	1		T3	50

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19962761	1			T1	8		T2	8		T3	400
values[0x1]	60807	1			T8	303		T10	33		T16	34
transitions[0x0=>0x1]	59548	1			T8	299		T10	24		T16	29
transitions[0x1=>0x0]	59567	1			T8	299		T10	24		T16	29

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2502332	1			T1	1		T2	1		T3	50
all_pins[0]	values[0x1]	614	1			T8	261		T10	7		T16	4
all_pins[0]	transitions[0x0=>0x1]	558	1			T8	259		T10	7		T16	3
all_pins[0]	transitions[0x1=>0x0]	356	1			T8	1		T10	4		T16	5
all_pins[1]	values[0x0]	2502534	1			T1	1		T2	1		T3	50
all_pins[1]	values[0x1]	412	1			T8	3		T10	4		T16	6
all_pins[1]	transitions[0x0=>0x1]	303	1			T8	2		T10	3		T16	4
all_pins[1]	transitions[0x1=>0x0]	236	1			T8	27		T10	3		T16	7
all_pins[2]	values[0x0]	2502601	1			T1	1		T2	1		T3	50
all_pins[2]	values[0x1]	345	1			T8	28		T10	4		T16	9
all_pins[2]	transitions[0x0=>0x1]	298	1			T8	28		T10	4		T16	8
all_pins[2]	transitions[0x1=>0x0]	133	1			T8	1		T10	3		T16	2
all_pins[3]	values[0x0]	2502766	1			T1	1		T2	1		T3	50
all_pins[3]	values[0x1]	180	1			T8	1		T10	3		T16	3
all_pins[3]	transitions[0x0=>0x1]	122	1			T8	1		T10	1		T16	3
all_pins[3]	transitions[0x1=>0x0]	146	1			T8	5		T16	3		T17	1
all_pins[4]	values[0x0]	2502742	1			T1	1		T2	1		T3	50
all_pins[4]	values[0x1]	204	1			T8	5		T10	2		T16	3
all_pins[4]	transitions[0x0=>0x1]	166	1			T8	5		T10	2		T16	3
all_pins[4]	transitions[0x1=>0x0]	1167	1			T8	1		T10	4		T16	3
all_pins[5]	values[0x0]	2501741	1			T1	1		T2	1		T3	50
all_pins[5]	values[0x1]	1205	1			T8	1		T10	4		T16	3
all_pins[5]	transitions[0x0=>0x1]	378	1			T8	1		T10	2		T16	3
all_pins[5]	transitions[0x1=>0x0]	56805	1			T8	1		T10	2		T16	2
all_pins[6]	values[0x0]	2445314	1			T1	1		T2	1		T3	50
all_pins[6]	values[0x1]	57632	1			T8	1		T10	4		T16	2
all_pins[6]	transitions[0x0=>0x1]	57569	1			T8	1		T10	2		T16	1
all_pins[6]	transitions[0x1=>0x0]	152	1			T8	3		T10	3		T16	3
all_pins[7]	values[0x0]	2502731	1			T1	1		T2	1		T3	50
all_pins[7]	values[0x1]	215	1			T8	3		T10	5		T16	4
all_pins[7]	transitions[0x0=>0x1]	154	1			T8	2		T10	3		T16	4
all_pins[7]	transitions[0x1=>0x0]	572	1			T8	260		T10	5		T16	4