Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14179

1

T2

10

T3

12

T7

8

auto[1]

9907

1

T22

30

T39

29

T25

188

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2755	1			T22	45		T44	24		T92	4
values[1]	3271	1			T2	10		T25	71		T53	14
values[2]	2927	1			T39	20		T25	111		T38	20
values[3]	3221	1			T7	8		T22	40		T39	60
values[4]	3050	1			T25	58		T54	8		T38	20
values[5]	3288	1			T38	20		T239	6		T237	20
values[6]	2536	1			T3	12		T25	42		T38	20
values[7]	3038	1			T11	6		T231	26		T240	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2849	1			T22	20		T25	42		T55	14
values[1]	3105	1			T3	12		T53	14		T38	20
values[2]	2947	1			T22	20		T92	4		T25	98
values[3]	3200	1			T2	10		T11	6		T22	20
values[4]	2670	1			T39	20		T45	14		T241	2
values[5]	3164	1			T44	24		T25	40		T38	20
values[6]	3318	1			T22	25		T39	20		T25	100
values[7]	2833	1			T7	8		T39	20		T25	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	81	1			T55	14		T165	13		T77	15
auto[0]	values[0]	values[1]	179	1			T43	15		T184	18		T225	13
auto[0]	values[0]	values[2]	160	1			T92	4		T242	10		T46	13
auto[0]	values[0]	values[3]	221	1			T22	13		T21	18		T165	16
auto[0]	values[0]	values[4]	158	1			T52	11		T243	2		T82	12
auto[0]	values[0]	values[5]	351	1			T44	24		T25	17		T21	17
auto[0]	values[0]	values[6]	307	1			T22	19		T128	16		T197	16
auto[0]	values[0]	values[7]	291	1			T21	11		T183	13		T165	15
auto[0]	values[1]	values[0]	284	1			T168	17		T51	14		T211	7
auto[0]	values[1]	values[1]	386	1			T53	14		T168	17		T51	8
auto[0]	values[1]	values[2]	257	1			T209	12		T165	14		T244	2
auto[0]	values[1]	values[3]	215	1			T2	10		T25	14		T167	12
auto[0]	values[1]	values[4]	239	1			T241	2		T47	12		T206	23
auto[0]	values[1]	values[5]	117	1			T25	9		T51	6		T52	7
auto[0]	values[1]	values[6]	283	1			T25	11		T58	9		T220	2
auto[0]	values[1]	values[7]	236	1			T95	22		T52	13		T245	20
auto[0]	values[2]	values[0]	181	1			T25	12		T46	3		T168	35
auto[0]	values[2]	values[1]	302	1			T38	8		T246	14		T50	12
auto[0]	values[2]	values[2]	136	1			T18	13		T43	13		T130	2
auto[0]	values[2]	values[3]	151	1			T25	7		T49	5		T247	4
auto[0]	values[2]	values[4]	335	1			T39	11		T50	8		T164	14
auto[0]	values[2]	values[5]	175	1			T46	22		T50	13		T51	12
auto[0]	values[2]	values[6]	201	1			T25	15		T94	10		T248	12
auto[0]	values[2]	values[7]	189	1			T249	6		T183	17		T227	13
auto[0]	values[3]	values[0]	236	1			T22	10		T161	2		T168	35
auto[0]	values[3]	values[1]	241	1			T18	19		T48	13		T232	12
auto[0]	values[3]	values[2]	175	1			T22	13		T25	29		T164	9
auto[0]	values[3]	values[3]	271	1			T39	13		T250	16		T168	13
auto[0]	values[3]	values[4]	257	1			T45	14		T96	8		T48	8
auto[0]	values[3]	values[5]	177	1			T38	8		T50	24		T164	12
auto[0]	values[3]	values[6]	108	1			T39	11		T46	14		T251	6
auto[0]	values[3]	values[7]	256	1			T7	8		T39	16		T46	10
auto[0]	values[4]	values[0]	186	1			T225	9		T82	23		T200	11
auto[0]	values[4]	values[1]	157	1			T101	8		T154	10		T252	15
auto[0]	values[4]	values[2]	207	1			T25	11		T191	12		T164	12
auto[0]	values[4]	values[3]	292	1			T46	16		T50	30		T168	10
auto[0]	values[4]	values[4]	155	1			T214	12		T253	14		T254	11
auto[0]	values[4]	values[5]	235	1			T57	8		T166	9		T59	40
auto[0]	values[4]	values[6]	339	1			T38	12		T255	2		T164	12
auto[0]	values[4]	values[7]	202	1			T54	8		T256	6		T257	15
auto[0]	values[5]	values[0]	239	1			T201	22		T206	16		T258	18
auto[0]	values[5]	values[1]	236	1			T43	28		T21	14		T46	7
auto[0]	values[5]	values[2]	326	1			T21	15		T51	23		T212	12
auto[0]	values[5]	values[3]	327	1			T38	12		T206	15		T200	15
auto[0]	values[5]	values[4]	207	1			T21	11		T168	30		T52	26
auto[0]	values[5]	values[5]	243	1			T237	20		T43	16		T50	12
auto[0]	values[5]	values[6]	220	1			T239	6		T169	17		T48	24
auto[0]	values[5]	values[7]	146	1			T21	22		T169	13		T212	11
auto[0]	values[6]	values[0]	170	1			T25	17		T227	13		T225	13
auto[0]	values[6]	values[1]	240	1			T3	12		T21	16		T196	20
auto[0]	values[6]	values[2]	196	1			T216	2		T21	13		T34	11
auto[0]	values[6]	values[3]	231	1			T38	7		T259	12		T165	10
auto[0]	values[6]	values[4]	88	1			T260	18		T261	9		T195	11
auto[0]	values[6]	values[5]	146	1			T212	12		T77	12		T186	11
auto[0]	values[6]	values[6]	195	1			T21	13		T50	11		T197	9
auto[0]	values[6]	values[7]	161	1			T25	12		T46	15		T199	22
auto[0]	values[7]	values[0]	234	1			T164	14		T212	11		T262	8
auto[0]	values[7]	values[1]	166	1			T231	26		T263	8		T51	33
auto[0]	values[7]	values[2]	243	1			T47	35		T51	28		T200	9
auto[0]	values[7]	values[3]	221	1			T11	6		T264	22		T206	12
auto[0]	values[7]	values[4]	249	1			T164	14		T180	12		T185	15
auto[0]	values[7]	values[5]	313	1			T265	8		T50	8		T183	11
auto[0]	values[7]	values[6]	246	1			T266	8		T207	28		T185	13
auto[0]	values[7]	values[7]	207	1			T21	19		T51	15		T190	10
auto[1]	values[0]	values[0]	42	1			T165	10		T77	11		T267	8
auto[1]	values[0]	values[1]	117	1			T43	30		T225	7		T211	3
auto[1]	values[0]	values[2]	80	1			T46	7		T51	4		T165	22
auto[1]	values[0]	values[3]	128	1			T22	7		T21	6		T165	4
auto[1]	values[0]	values[4]	129	1			T52	9		T82	20		T207	8
auto[1]	values[0]	values[5]	120	1			T25	3		T21	7		T46	11
auto[1]	values[0]	values[6]	180	1			T22	6		T197	4		T166	23
auto[1]	values[0]	values[7]	211	1			T21	9		T183	24		T165	7
auto[1]	values[1]	values[0]	82	1			T168	3		T51	9		T211	13
auto[1]	values[1]	values[1]	158	1			T134	4		T168	8		T51	16
auto[1]	values[1]	values[2]	74	1			T165	6		T210	8		T268	14
auto[1]	values[1]	values[3]	118	1			T25	6		T232	12		T154	6
auto[1]	values[1]	values[4]	155	1			T47	8		T269	4		T206	8
auto[1]	values[1]	values[5]	211	1			T25	11		T51	14		T52	27
auto[1]	values[1]	values[6]	298	1			T25	20		T58	11		T50	17
auto[1]	values[1]	values[7]	158	1			T52	7		T165	8		T207	10
auto[1]	values[2]	values[0]	179	1			T25	8		T46	17		T168	9
auto[1]	values[2]	values[1]	190	1			T38	12		T50	29		T225	44
auto[1]	values[2]	values[2]	193	1			T18	7		T43	7		T48	5
auto[1]	values[2]	values[3]	136	1			T25	15		T49	20		T183	19
auto[1]	values[2]	values[4]	175	1			T39	9		T50	12		T164	7
auto[1]	values[2]	values[5]	124	1			T46	18		T50	7		T51	10
auto[1]	values[2]	values[6]	177	1			T25	54		T94	10		T51	9
auto[1]	values[2]	values[7]	83	1			T183	7		T227	7		T186	9
auto[1]	values[3]	values[0]	365	1			T22	10		T168	5		T186	12
auto[1]	values[3]	values[1]	170	1			T18	12		T48	7		T270	16
auto[1]	values[3]	values[2]	136	1			T22	7		T25	11		T164	11
auto[1]	values[3]	values[3]	299	1			T39	7		T168	88		T197	10
auto[1]	values[3]	values[4]	74	1			T48	12		T227	8		T271	8
auto[1]	values[3]	values[5]	163	1			T38	12		T50	47		T164	49
auto[1]	values[3]	values[6]	93	1			T39	9		T46	6		T208	19
auto[1]	values[3]	values[7]	200	1			T39	4		T46	10		T227	12
auto[1]	values[4]	values[0]	86	1			T225	11		T82	9		T200	9
auto[1]	values[4]	values[1]	127	1			T154	10		T252	5		T223	3
auto[1]	values[4]	values[2]	248	1			T25	47		T164	8		T183	7
auto[1]	values[4]	values[3]	260	1			T46	24		T50	8		T168	10
auto[1]	values[4]	values[4]	74	1			T254	13		T185	13		T272	4
auto[1]	values[4]	values[5]	137	1			T166	11		T59	14		T207	5
auto[1]	values[4]	values[6]	158	1			T38	8		T164	8		T34	8
auto[1]	values[4]	values[7]	187	1			T257	5		T222	10		T157	9
auto[1]	values[5]	values[0]	107	1			T206	4		T210	3		T273	6
auto[1]	values[5]	values[1]	167	1			T43	11		T21	6		T46	13
auto[1]	values[5]	values[2]	180	1			T21	5		T51	8		T212	8
auto[1]	values[5]	values[3]	99	1			T38	8		T206	7		T200	5
auto[1]	values[5]	values[4]	167	1			T21	11		T168	6		T52	8
auto[1]	values[5]	values[5]	303	1			T43	4		T50	112		T51	9
auto[1]	values[5]	values[6]	222	1			T169	8		T48	16		T225	10
auto[1]	values[5]	values[7]	99	1			T21	7		T169	7		T212	9
auto[1]	values[6]	values[0]	209	1			T25	5		T227	7		T225	15
auto[1]	values[6]	values[1]	149	1			T21	6		T165	14		T77	8
auto[1]	values[6]	values[2]	152	1			T21	10		T34	9		T166	8
auto[1]	values[6]	values[3]	109	1			T38	13		T165	10		T59	4
auto[1]	values[6]	values[4]	57	1			T274	4		T261	17		T195	9
auto[1]	values[6]	values[5]	160	1			T212	8		T77	8		T186	9
auto[1]	values[6]	values[6]	158	1			T215	18		T21	7		T50	9
auto[1]	values[6]	values[7]	115	1			T25	8		T46	5		T185	7
auto[1]	values[7]	values[0]	168	1			T240	12		T164	6		T212	9
auto[1]	values[7]	values[1]	120	1			T51	28		T211	14		T226	7
auto[1]	values[7]	values[2]	184	1			T47	4		T51	21		T200	85
auto[1]	values[7]	values[3]	122	1			T206	11		T193	10		T273	4
auto[1]	values[7]	values[4]	151	1			T164	6		T185	11		T210	8
auto[1]	values[7]	values[5]	189	1			T50	12		T183	46		T190	11
auto[1]	values[7]	values[6]	133	1			T207	17		T185	10		T272	3
auto[1]	values[7]	values[7]	92	1			T21	5		T51	6		T190	10