Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	357	1			T39	2		T25	4		T54	4
auto[ReadAddrCrossIntoMailbox]	240	1			T22	1		T25	5		T38	2
auto[ReadAddrCrossOutOfMailbox]	287	1			T22	1		T39	1		T25	2
auto[ReadAddrCrossAllMailbox]	213	1			T22	1		T54	2		T38	1
auto[ReadAddrOutsideMailbox]	2976	1			T2	4		T3	4		T7	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2023

1

T2

2

T3

2

T7

1

auto[1]

2050

1

T2

2

T3

2

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	716	1			T7	2		T22	3		T39	6
read_ops[0x0b]	687	1			T3	2		T22	3		T39	2
read_ops[0x3b]	716	1			T39	4		T25	9		T54	4
read_ops[0x6b]	656	1			T22	3		T39	4		T25	5
read_ops[0xbb]	666	1			T2	4		T22	1		T39	6
read_ops[0xeb]	632	1			T3	2		T11	2		T22	5

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T25	2		T191	1		T46	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T191	1		T47	1		T169	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T46	1		T168	3		T51	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T47	1		T206	1		T203	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T46	1		T164	2		T183	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T46	3		T206	1		T257	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T46	1		T164	1		T59	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T22	1		T34	1		T227	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	254	1			T7	1		T22	2		T39	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T7	1		T39	3		T25	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T55	1		T52	1		T164	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T55	1		T46	1		T169	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T94	1		T165	1		T227	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T25	1		T43	1		T50	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T21	2		T168	1		T164	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T22	1		T46	1		T47	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T46	1		T169	1		T164	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T46	1		T51	1		T212	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	239	1			T3	1		T22	1		T39	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	253	1			T3	1		T22	1		T25	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T54	1		T50	1		T51	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T39	1		T54	1		T51	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T265	1		T168	1		T212	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T265	1		T50	1		T183	3
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T164	1		T34	1		T212	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T51	1		T164	1		T212	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T21	1		T265	1		T47	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T265	1		T169	1		T189	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	255	1			T25	4		T54	1		T38	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	263	1			T39	3		T25	5		T54	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T38	1		T46	1		T169	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T50	1		T51	1		T184	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T25	1		T38	2		T206	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T51	1		T164	1		T183	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T34	1		T212	1		T165	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T169	1		T52	1		T212	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T38	1		T55	1		T46	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T55	1		T43	1		T50	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	256	1			T22	1		T39	2		T25	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	236	1			T22	2		T39	2		T25	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T54	1		T55	1		T51	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T25	1		T54	1		T55	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T43	1		T183	1		T221	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T25	1		T46	1		T47	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T55	1		T46	1		T265	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T39	1		T25	1		T55	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T54	1		T221	1		T165	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T54	1		T212	1		T221	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	208	1			T2	2		T22	1		T39	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	261	1			T2	2		T39	3		T25	5
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T39	1		T55	1		T43	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T25	1		T55	1		T169	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T22	1		T25	1		T51	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T25	1		T46	1		T48	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T55	1		T43	1		T165	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T25	1		T55	1		T21	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T229	1		T212	1		T165	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T164	1		T229	1		T257	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	223	1			T3	1		T11	1		T22	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	245	1			T3	1		T11	1		T22	1