Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	868	1			T8	8		T10	14		T16	17
all_values[1]	868	1			T8	8		T10	14		T16	17
all_values[2]	868	1			T8	8		T10	14		T16	17
all_values[3]	868	1			T8	8		T10	14		T16	17
all_values[4]	868	1			T8	8		T10	14		T16	17
all_values[5]	868	1			T8	8		T10	14		T16	17
all_values[6]	868	1			T8	8		T10	14		T16	17
all_values[7]	868	1			T8	8		T10	14		T16	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3632

1

T8

33

T10

54

T16

79

auto[1]

3312

1

T8

31

T10

58

T16

57

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2795

1

T8

29

T10

40

T16

41

auto[1]

4149

1

T8

35

T10

72

T16

95

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3942

1

T8

39

T10

59

T16

62

auto[1]

3002

1

T8

25

T10

53

T16

74

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	171	1			T8	4		T16	3		T17	4
all_values[0]	auto[0]	auto[0]	auto[1]	88	1			T10	1		T16	2		T19	1
all_values[0]	auto[0]	auto[1]	auto[0]	172	1			T8	1		T10	3		T17	2
all_values[0]	auto[0]	auto[1]	auto[1]	73	1			T8	1		T10	4		T16	3
all_values[0]	auto[1]	auto[0]	auto[1]	195	1			T8	2		T10	1		T16	9
all_values[0]	auto[1]	auto[1]	auto[1]	169	1			T10	5		T19	1		T33	2
all_values[1]	auto[0]	auto[0]	auto[0]	171	1			T10	4		T16	2		T17	4
all_values[1]	auto[0]	auto[0]	auto[1]	84	1			T8	2		T16	1		T19	4
all_values[1]	auto[0]	auto[1]	auto[0]	147	1			T8	2		T10	2		T20	1
all_values[1]	auto[0]	auto[1]	auto[1]	87	1			T8	1		T10	1		T16	1
all_values[1]	auto[1]	auto[0]	auto[1]	195	1			T8	1		T10	4		T16	5
all_values[1]	auto[1]	auto[1]	auto[1]	184	1			T8	2		T10	3		T16	8
all_values[2]	auto[0]	auto[0]	auto[0]	154	1			T8	1		T16	2		T17	1
all_values[2]	auto[0]	auto[0]	auto[1]	98	1			T16	2		T17	1		T19	2
all_values[2]	auto[0]	auto[1]	auto[0]	148	1			T8	1		T10	6		T16	1
all_values[2]	auto[0]	auto[1]	auto[1]	82	1			T8	1		T10	2		T16	3
all_values[2]	auto[1]	auto[0]	auto[1]	205	1			T8	2		T10	4		T16	4
all_values[2]	auto[1]	auto[1]	auto[1]	181	1			T8	3		T10	2		T16	5
all_values[3]	auto[0]	auto[0]	auto[0]	184	1			T8	3		T10	7		T16	3
all_values[3]	auto[0]	auto[0]	auto[1]	79	1			T10	1		T16	1		T17	1
all_values[3]	auto[0]	auto[1]	auto[0]	166	1			T8	3		T10	1		T16	1
all_values[3]	auto[0]	auto[1]	auto[1]	66	1			T10	1		T17	1		T19	5
all_values[3]	auto[1]	auto[0]	auto[1]	205	1			T10	2		T16	8		T17	1
all_values[3]	auto[1]	auto[1]	auto[1]	168	1			T8	2		T10	2		T16	4
all_values[4]	auto[0]	auto[0]	auto[0]	175	1			T10	4		T16	5		T19	3
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T17	1		T19	1		T20	2
all_values[4]	auto[0]	auto[1]	auto[0]	169	1			T8	2		T10	2		T16	3
all_values[4]	auto[0]	auto[1]	auto[1]	84	1			T8	3		T10	1		T16	2
all_values[4]	auto[1]	auto[0]	auto[1]	192	1			T10	5		T16	4		T17	2
all_values[4]	auto[1]	auto[1]	auto[1]	174	1			T8	3		T10	2		T16	3
all_values[5]	auto[0]	auto[0]	auto[0]	264	1			T8	3		T10	3		T16	4
all_values[5]	auto[0]	auto[1]	auto[0]	236	1			T8	1		T10	4		T16	5
all_values[5]	auto[1]	auto[0]	auto[1]	195	1			T8	4		T10	3		T16	5
all_values[5]	auto[1]	auto[1]	auto[1]	173	1			T10	4		T16	3		T17	1
all_values[6]	auto[0]	auto[0]	auto[0]	169	1			T8	1		T10	2		T16	3
all_values[6]	auto[0]	auto[0]	auto[1]	79	1			T8	1		T10	4		T16	3
all_values[6]	auto[0]	auto[1]	auto[0]	153	1			T8	2		T10	1		T16	2
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T19	3		T20	2		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	206	1			T8	3		T10	3		T16	5
all_values[6]	auto[1]	auto[1]	auto[1]	179	1			T8	1		T10	4		T16	4
all_values[7]	auto[0]	auto[0]	auto[0]	176	1			T8	5		T16	4		T19	2
all_values[7]	auto[0]	auto[0]	auto[1]	89	1			T10	2		T16	2		T17	1
all_values[7]	auto[0]	auto[1]	auto[0]	140	1			T10	1		T16	3		T17	2
all_values[7]	auto[0]	auto[1]	auto[1]	82	1			T8	1		T10	2		T16	1
all_values[7]	auto[1]	auto[0]	auto[1]	184	1			T8	1		T10	4		T16	2
all_values[7]	auto[1]	auto[1]	auto[1]	197	1			T8	1		T10	5		T16	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal