Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1694

1

T4

6

T8

27

T9

4

auto[1]

1742

1

T4

7

T8

21

T9

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1827

1

T8

45

T9

12

T22

22

auto[1]

1609

1

T4

13

T8

3

T12

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2764

1

T4

13

T8

34

T9

9

auto[1]

672

1

T8

14

T9

3

T22

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	703	1			T4	2		T8	9		T9	1
valid[1]	648	1			T4	5		T8	11		T12	2
valid[2]	653	1			T4	2		T8	9		T9	4
valid[3]	714	1			T4	4		T8	11		T9	2
valid[4]	718	1			T8	8		T9	5		T22	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	97	1			T8	3		T22	1		T41	1
auto[0]	auto[0]	valid[0]	auto[1]	168	1			T4	1		T41	1		T332	1
auto[0]	auto[0]	valid[1]	auto[0]	110	1			T8	5		T22	3		T25	1
auto[0]	auto[0]	valid[1]	auto[1]	168	1			T4	2		T8	1		T28	1
auto[0]	auto[0]	valid[2]	auto[0]	118	1			T8	3		T9	1		T22	5
auto[0]	auto[0]	valid[2]	auto[1]	173	1			T4	1		T12	1		T27	1
auto[0]	auto[0]	valid[3]	auto[0]	119	1			T8	3		T9	1		T29	1
auto[0]	auto[0]	valid[3]	auto[1]	153	1			T4	2		T12	2		T58	1
auto[0]	auto[0]	valid[4]	auto[0]	121	1			T8	3		T9	2		T22	4
auto[0]	auto[0]	valid[4]	auto[1]	140	1			T41	1		T18	1		T333	5
auto[0]	auto[1]	valid[0]	auto[0]	132	1			T8	2		T22	2		T27	2
auto[0]	auto[1]	valid[0]	auto[1]	174	1			T4	1		T8	1		T12	2
auto[0]	auto[1]	valid[1]	auto[0]	109	1			T8	2		T22	1		T29	1
auto[0]	auto[1]	valid[1]	auto[1]	144	1			T4	3		T12	2		T18	2
auto[0]	auto[1]	valid[2]	auto[0]	106	1			T8	4		T9	2		T22	1
auto[0]	auto[1]	valid[2]	auto[1]	130	1			T4	1		T12	1		T41	1
auto[0]	auto[1]	valid[3]	auto[0]	125	1			T8	4		T9	1		T22	2
auto[0]	auto[1]	valid[3]	auto[1]	168	1			T4	2		T8	1		T12	1
auto[0]	auto[1]	valid[4]	auto[0]	118	1			T8	2		T9	2		T27	2
auto[0]	auto[1]	valid[4]	auto[1]	191	1			T28	1		T58	2		T18	3
auto[1]	auto[0]	valid[0]	auto[0]	56	1			T8	3		T29	2		T58	2
auto[1]	auto[0]	valid[1]	auto[0]	54	1			T8	1		T29	1		T18	3
auto[1]	auto[0]	valid[2]	auto[0]	70	1			T8	2		T29	2		T18	1
auto[1]	auto[0]	valid[3]	auto[0]	73	1			T8	2		T25	2		T27	1
auto[1]	auto[0]	valid[4]	auto[0]	74	1			T8	1		T25	1		T27	1
auto[1]	auto[1]	valid[0]	auto[0]	76	1			T9	1		T41	2		T18	1
auto[1]	auto[1]	valid[1]	auto[0]	63	1			T8	2		T41	1		T58	2
auto[1]	auto[1]	valid[2]	auto[0]	56	1			T9	1		T29	1		T41	1
auto[1]	auto[1]	valid[3]	auto[0]	76	1			T8	1		T22	2		T25	1
auto[1]	auto[1]	valid[4]	auto[0]	74	1			T8	2		T9	1		T22	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal