Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46565

1

T8

670

T9

332

T22

521

auto[1]

17456

1

T4

13

T8

37

T12

162

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46871

1

T4

13

T8

453

T9

231

auto[1]

17150

1

T8

254

T9

101

T22

165

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32725	1			T4	13		T8	364		T9	176
others[1]	5417	1			T8	71		T9	20		T12	15
others[2]	5288	1			T8	55		T9	32		T12	17
others[3]	6155	1			T8	63		T9	22		T12	12
interest[1]	3590	1			T8	42		T9	26		T12	7
interest[4]	21344	1			T4	13		T8	242		T9	106
interest[64]	10846	1			T8	112		T9	56		T12	22

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14959	1			T8	206		T9	123		T22	166
auto[0]	auto[0]	others[1]	2525	1			T8	46		T9	14		T22	41
auto[0]	auto[0]	others[2]	2415	1			T8	40		T9	24		T22	29
auto[0]	auto[0]	others[3]	2881	1			T8	35		T9	16		T22	36
auto[0]	auto[0]	interest[1]	1638	1			T8	28		T9	19		T22	18
auto[0]	auto[0]	interest[4]	9738	1			T8	138		T9	73		T22	111
auto[0]	auto[0]	interest[64]	4997	1			T8	61		T9	35		T22	66
auto[0]	auto[1]	others[0]	9085	1			T4	13		T8	17		T12	89
auto[0]	auto[1]	others[1]	1425	1			T8	4		T12	15		T25	2
auto[0]	auto[1]	others[2]	1433	1			T8	1		T12	17		T25	3
auto[0]	auto[1]	others[3]	1649	1			T8	6		T12	12		T27	3
auto[0]	auto[1]	interest[1]	972	1			T8	3		T12	7		T25	4
auto[0]	auto[1]	interest[4]	6027	1			T4	13		T8	11		T12	58
auto[0]	auto[1]	interest[64]	2892	1			T8	6		T12	22		T25	6
auto[1]	auto[0]	others[0]	8681	1			T8	141		T9	53		T22	88
auto[1]	auto[0]	others[1]	1467	1			T8	21		T9	6		T22	12
auto[1]	auto[0]	others[2]	1440	1			T8	14		T9	8		T22	8
auto[1]	auto[0]	others[3]	1625	1			T8	22		T9	6		T22	13
auto[1]	auto[0]	interest[1]	980	1			T8	11		T9	7		T22	8
auto[1]	auto[0]	interest[4]	5579	1			T8	93		T9	33		T22	60
auto[1]	auto[0]	interest[64]	2957	1			T8	45		T9	21		T22	36

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal