Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1029 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1137435487 Jun 27 06:19:19 PM PDT 24 Jun 27 06:19:27 PM PDT 24 779673886 ps
T110 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3588498595 Jun 27 06:19:39 PM PDT 24 Jun 27 06:19:47 PM PDT 24 260354446 ps
T1030 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.490549645 Jun 27 06:19:44 PM PDT 24 Jun 27 06:19:50 PM PDT 24 26049316 ps
T176 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2535866672 Jun 27 06:19:16 PM PDT 24 Jun 27 06:19:26 PM PDT 24 108931033 ps
T1031 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3279913050 Jun 27 06:19:25 PM PDT 24 Jun 27 06:19:29 PM PDT 24 56868181 ps
T1032 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3051172909 Jun 27 06:19:41 PM PDT 24 Jun 27 06:19:47 PM PDT 24 45361368 ps
T102 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3377377286 Jun 27 06:19:32 PM PDT 24 Jun 27 06:19:40 PM PDT 24 772789138 ps
T1033 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2471848769 Jun 27 06:19:39 PM PDT 24 Jun 27 06:19:43 PM PDT 24 32489263 ps
T118 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3995420604 Jun 27 06:19:16 PM PDT 24 Jun 27 06:19:22 PM PDT 24 198308068 ps
T171 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1283309155 Jun 27 06:19:31 PM PDT 24 Jun 27 06:19:42 PM PDT 24 2232379334 ps
T1034 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1908898662 Jun 27 06:19:12 PM PDT 24 Jun 27 06:19:17 PM PDT 24 63944619 ps
T1035 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1189234674 Jun 27 06:19:25 PM PDT 24 Jun 27 06:19:31 PM PDT 24 38089142 ps
T1036 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.992983173 Jun 27 06:19:43 PM PDT 24 Jun 27 06:19:49 PM PDT 24 22441443 ps
T150 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3103523567 Jun 27 06:19:16 PM PDT 24 Jun 27 06:19:21 PM PDT 24 119529387 ps
T103 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2318336962 Jun 27 06:19:19 PM PDT 24 Jun 27 06:19:25 PM PDT 24 88790516 ps
T119 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4222644687 Jun 27 06:19:29 PM PDT 24 Jun 27 06:19:33 PM PDT 24 100875042 ps
T1037 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4125646061 Jun 27 06:19:03 PM PDT 24 Jun 27 06:19:14 PM PDT 24 2066337180 ps
T1038 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2229518334 Jun 27 06:19:48 PM PDT 24 Jun 27 06:19:53 PM PDT 24 51125551 ps
T1039 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2014086112 Jun 27 06:19:24 PM PDT 24 Jun 27 06:19:30 PM PDT 24 39656552 ps
T151 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1916304271 Jun 27 06:19:23 PM PDT 24 Jun 27 06:19:49 PM PDT 24 3719586219 ps
T174 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3605452845 Jun 27 06:19:26 PM PDT 24 Jun 27 06:19:37 PM PDT 24 275584537 ps
T1040 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1586098440 Jun 27 06:19:33 PM PDT 24 Jun 27 06:19:37 PM PDT 24 31630993 ps
T120 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3068312961 Jun 27 06:19:26 PM PDT 24 Jun 27 06:19:53 PM PDT 24 11333238491 ps
T107 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1253389764 Jun 27 06:19:14 PM PDT 24 Jun 27 06:19:20 PM PDT 24 151649641 ps
T1041 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4150462271 Jun 27 06:19:20 PM PDT 24 Jun 27 06:19:26 PM PDT 24 89531293 ps
T1042 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3090581018 Jun 27 06:19:22 PM PDT 24 Jun 27 06:19:28 PM PDT 24 49138119 ps
T121 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2836881905 Jun 27 06:19:06 PM PDT 24 Jun 27 06:19:14 PM PDT 24 71535261 ps
T1043 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1334544530 Jun 27 06:19:31 PM PDT 24 Jun 27 06:19:36 PM PDT 24 178503014 ps
T1044 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3349413741 Jun 27 06:19:26 PM PDT 24 Jun 27 06:19:33 PM PDT 24 55178287 ps
T122 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1756538027 Jun 27 06:19:17 PM PDT 24 Jun 27 06:19:43 PM PDT 24 1204211762 ps
T1045 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2167854050 Jun 27 06:19:29 PM PDT 24 Jun 27 06:19:34 PM PDT 24 217265380 ps
T1046 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1176964607 Jun 27 06:19:28 PM PDT 24 Jun 27 06:19:32 PM PDT 24 10683869 ps
T108 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1482681069 Jun 27 06:19:40 PM PDT 24 Jun 27 06:19:50 PM PDT 24 176486683 ps
T177 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.850019334 Jun 27 06:19:16 PM PDT 24 Jun 27 06:19:28 PM PDT 24 290902881 ps
T1047 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.224814249 Jun 27 06:19:29 PM PDT 24 Jun 27 06:19:33 PM PDT 24 26220594 ps
T1048 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2188577224 Jun 27 06:19:05 PM PDT 24 Jun 27 06:19:12 PM PDT 24 81568788 ps
T1049 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2691501372 Jun 27 06:19:41 PM PDT 24 Jun 27 06:19:49 PM PDT 24 381611404 ps
T152 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2718404510 Jun 27 06:19:38 PM PDT 24 Jun 27 06:19:45 PM PDT 24 120490202 ps
T1050 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.285776837 Jun 27 06:19:44 PM PDT 24 Jun 27 06:19:50 PM PDT 24 12041479 ps
T175 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2309774157 Jun 27 06:19:35 PM PDT 24 Jun 27 06:20:00 PM PDT 24 1705227459 ps
T1051 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3782246071 Jun 27 06:19:19 PM PDT 24 Jun 27 06:19:25 PM PDT 24 23747976 ps
T123 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2339854227 Jun 27 06:19:11 PM PDT 24 Jun 27 06:19:17 PM PDT 24 660386025 ps
T1052 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2523247420 Jun 27 06:19:09 PM PDT 24 Jun 27 06:19:19 PM PDT 24 172814509 ps
T1053 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1251717277 Jun 27 06:19:32 PM PDT 24 Jun 27 06:19:36 PM PDT 24 15485092 ps
T1054 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3630704097 Jun 27 06:19:32 PM PDT 24 Jun 27 06:19:37 PM PDT 24 52693677 ps
T1055 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4060481025 Jun 27 06:19:34 PM PDT 24 Jun 27 06:19:38 PM PDT 24 39231988 ps
T124 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1503088091 Jun 27 06:19:05 PM PDT 24 Jun 27 06:19:50 PM PDT 24 7088425912 ps
T1056 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2655912959 Jun 27 06:19:18 PM PDT 24 Jun 27 06:19:30 PM PDT 24 307199399 ps
T1057 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2023597312 Jun 27 06:19:32 PM PDT 24 Jun 27 06:19:37 PM PDT 24 16363686 ps
T125 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2921496056 Jun 27 06:19:16 PM PDT 24 Jun 27 06:19:59 PM PDT 24 5893045149 ps
T1058 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3597058271 Jun 27 06:19:23 PM PDT 24 Jun 27 06:19:30 PM PDT 24 141645082 ps
T1059 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3417686173 Jun 27 06:19:16 PM PDT 24 Jun 27 06:19:20 PM PDT 24 19746831 ps
T126 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1085194995 Jun 27 06:19:02 PM PDT 24 Jun 27 06:19:10 PM PDT 24 41282507 ps
T1060 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4184412297 Jun 27 06:19:37 PM PDT 24 Jun 27 06:19:41 PM PDT 24 10915332 ps
T1061 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3183113941 Jun 27 06:19:02 PM PDT 24 Jun 27 06:19:12 PM PDT 24 483291607 ps
T1062 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.271391216 Jun 27 06:19:19 PM PDT 24 Jun 27 06:19:26 PM PDT 24 343134629 ps
T1063 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3405444521 Jun 27 06:19:30 PM PDT 24 Jun 27 06:19:33 PM PDT 24 33055626 ps
T127 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3579748903 Jun 27 06:19:10 PM PDT 24 Jun 27 06:19:38 PM PDT 24 353787946 ps
T1064 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1312753679 Jun 27 06:19:20 PM PDT 24 Jun 27 06:19:26 PM PDT 24 79058772 ps
T1065 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1886502872 Jun 27 06:19:02 PM PDT 24 Jun 27 06:19:10 PM PDT 24 252471095 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1531419951 Jun 27 06:19:05 PM PDT 24 Jun 27 06:19:13 PM PDT 24 13400733 ps
T89 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3522261573 Jun 27 06:19:05 PM PDT 24 Jun 27 06:19:12 PM PDT 24 14976538 ps
T1067 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3931474610 Jun 27 06:19:03 PM PDT 24 Jun 27 06:19:12 PM PDT 24 109394467 ps
T1068 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1469753233 Jun 27 06:19:06 PM PDT 24 Jun 27 06:19:14 PM PDT 24 144673532 ps
T1069 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2234912743 Jun 27 06:19:32 PM PDT 24 Jun 27 06:19:38 PM PDT 24 171861041 ps
T1070 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3300065471 Jun 27 06:19:21 PM PDT 24 Jun 27 06:19:27 PM PDT 24 354546534 ps
T1071 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2326654269 Jun 27 06:19:19 PM PDT 24 Jun 27 06:19:25 PM PDT 24 218912420 ps
T1072 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3277630425 Jun 27 06:19:31 PM PDT 24 Jun 27 06:19:36 PM PDT 24 14767827 ps
T1073 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4100876078 Jun 27 06:19:32 PM PDT 24 Jun 27 06:19:38 PM PDT 24 34289215 ps
T1074 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.382063284 Jun 27 06:19:27 PM PDT 24 Jun 27 06:19:32 PM PDT 24 15811589 ps
T1075 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.359965949 Jun 27 06:19:12 PM PDT 24 Jun 27 06:19:19 PM PDT 24 128319423 ps
T1076 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2467000096 Jun 27 06:19:38 PM PDT 24 Jun 27 06:19:42 PM PDT 24 24510934 ps
T1077 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3230412406 Jun 27 06:19:06 PM PDT 24 Jun 27 06:19:20 PM PDT 24 343298894 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1091722588 Jun 27 06:19:16 PM PDT 24 Jun 27 06:19:42 PM PDT 24 4255322871 ps
T1079 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3291001541 Jun 27 06:19:28 PM PDT 24 Jun 27 06:19:34 PM PDT 24 87808759 ps
T1080 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.557615176 Jun 27 06:19:16 PM PDT 24 Jun 27 06:19:22 PM PDT 24 34406323 ps
T1081 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3576415076 Jun 27 06:19:12 PM PDT 24 Jun 27 06:19:17 PM PDT 24 36625561 ps
T1082 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3807666078 Jun 27 06:19:03 PM PDT 24 Jun 27 06:19:45 PM PDT 24 36057078662 ps
T1083 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3617606246 Jun 27 06:19:18 PM PDT 24 Jun 27 06:19:25 PM PDT 24 149499633 ps
T1084 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1307581709 Jun 27 06:19:29 PM PDT 24 Jun 27 06:19:33 PM PDT 24 21758251 ps
T1085 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1491862319 Jun 27 06:19:31 PM PDT 24 Jun 27 06:19:36 PM PDT 24 16418368 ps
T1086 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3358481606 Jun 27 06:19:27 PM PDT 24 Jun 27 06:19:34 PM PDT 24 57444426 ps
T1087 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.968553014 Jun 27 06:19:43 PM PDT 24 Jun 27 06:19:49 PM PDT 24 14666622 ps
T1088 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4276722547 Jun 27 06:19:17 PM PDT 24 Jun 27 06:19:23 PM PDT 24 88995387 ps
T1089 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2492976079 Jun 27 06:19:03 PM PDT 24 Jun 27 06:19:10 PM PDT 24 38667285 ps
T1090 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2639877835 Jun 27 06:19:15 PM PDT 24 Jun 27 06:19:21 PM PDT 24 191653585 ps
T1091 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1932678740 Jun 27 06:19:34 PM PDT 24 Jun 27 06:19:41 PM PDT 24 237601006 ps
T1092 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1617853817 Jun 27 06:19:04 PM PDT 24 Jun 27 06:19:14 PM PDT 24 184902660 ps
T1093 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2547105579 Jun 27 06:19:45 PM PDT 24 Jun 27 06:19:51 PM PDT 24 66925058 ps
T172 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1272599229 Jun 27 06:19:14 PM PDT 24 Jun 27 06:19:31 PM PDT 24 396568764 ps
T1094 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4231097767 Jun 27 06:19:04 PM PDT 24 Jun 27 06:19:14 PM PDT 24 651185182 ps
T1095 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3402954002 Jun 27 06:19:12 PM PDT 24 Jun 27 06:19:18 PM PDT 24 111623515 ps
T1096 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.857369698 Jun 27 06:19:22 PM PDT 24 Jun 27 06:19:40 PM PDT 24 425028460 ps
T178 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3359665654 Jun 27 06:19:41 PM PDT 24 Jun 27 06:19:59 PM PDT 24 3416646319 ps
T1097 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.250768326 Jun 27 06:19:26 PM PDT 24 Jun 27 06:19:32 PM PDT 24 1119968891 ps
T1098 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3571663021 Jun 27 06:19:24 PM PDT 24 Jun 27 06:19:28 PM PDT 24 78920895 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4374667 Jun 27 06:19:20 PM PDT 24 Jun 27 06:19:31 PM PDT 24 476358970 ps
T1100 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3102428664 Jun 27 06:19:20 PM PDT 24 Jun 27 06:19:28 PM PDT 24 926201775 ps
T1101 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3535353097 Jun 27 06:19:26 PM PDT 24 Jun 27 06:19:30 PM PDT 24 11863861 ps
T1102 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3790752804 Jun 27 06:19:36 PM PDT 24 Jun 27 06:19:42 PM PDT 24 29576686 ps
T1103 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3191325173 Jun 27 06:19:18 PM PDT 24 Jun 27 06:19:25 PM PDT 24 110468674 ps
T1104 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1507045179 Jun 27 06:19:18 PM PDT 24 Jun 27 06:19:23 PM PDT 24 51285802 ps
T1105 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.870404858 Jun 27 06:19:40 PM PDT 24 Jun 27 06:19:50 PM PDT 24 223282926 ps
T1106 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.334233703 Jun 27 06:19:03 PM PDT 24 Jun 27 06:19:10 PM PDT 24 13530380 ps
T1107 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4102167199 Jun 27 06:19:39 PM PDT 24 Jun 27 06:19:44 PM PDT 24 48370649 ps
T1108 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2110109175 Jun 27 06:19:12 PM PDT 24 Jun 27 06:19:23 PM PDT 24 456006344 ps
T1109 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1953938401 Jun 27 06:19:40 PM PDT 24 Jun 27 06:19:54 PM PDT 24 4060435789 ps
T1110 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2129554814 Jun 27 06:19:10 PM PDT 24 Jun 27 06:19:38 PM PDT 24 1303233421 ps
T1111 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4202611658 Jun 27 06:19:17 PM PDT 24 Jun 27 06:19:30 PM PDT 24 361353761 ps
T1112 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2017551855 Jun 27 06:19:39 PM PDT 24 Jun 27 06:19:44 PM PDT 24 30196884 ps
T1113 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2500502453 Jun 27 06:19:06 PM PDT 24 Jun 27 06:19:37 PM PDT 24 1265151526 ps
T1114 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1717840687 Jun 27 06:19:17 PM PDT 24 Jun 27 06:19:25 PM PDT 24 56865386 ps
T1115 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2120125145 Jun 27 06:19:26 PM PDT 24 Jun 27 06:19:30 PM PDT 24 13224057 ps
T90 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3735593505 Jun 27 06:19:20 PM PDT 24 Jun 27 06:19:25 PM PDT 24 122304452 ps
T1116 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.339068173 Jun 27 06:19:29 PM PDT 24 Jun 27 06:19:33 PM PDT 24 30019644 ps
T1117 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.742773750 Jun 27 06:19:05 PM PDT 24 Jun 27 06:19:12 PM PDT 24 12722207 ps
T1118 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4100989155 Jun 27 06:19:32 PM PDT 24 Jun 27 06:19:37 PM PDT 24 62162233 ps
T1119 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.497334957 Jun 27 06:19:35 PM PDT 24 Jun 27 06:19:40 PM PDT 24 52367647 ps
T1120 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.655480449 Jun 27 06:19:02 PM PDT 24 Jun 27 06:19:09 PM PDT 24 177381262 ps
T1121 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.787728296 Jun 27 06:19:12 PM PDT 24 Jun 27 06:19:19 PM PDT 24 215888800 ps
T1122 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2704997963 Jun 27 06:19:31 PM PDT 24 Jun 27 06:19:36 PM PDT 24 24211166 ps
T1123 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.998685990 Jun 27 06:19:22 PM PDT 24 Jun 27 06:19:26 PM PDT 24 40010890 ps
T1124 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1077810695 Jun 27 06:19:12 PM PDT 24 Jun 27 06:19:19 PM PDT 24 68776587 ps
T1125 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.322872354 Jun 27 06:19:31 PM PDT 24 Jun 27 06:19:35 PM PDT 24 17479027 ps
T1126 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3249070847 Jun 27 06:19:18 PM PDT 24 Jun 27 06:19:24 PM PDT 24 72850873 ps
T173 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.302067699 Jun 27 06:19:15 PM PDT 24 Jun 27 06:19:32 PM PDT 24 772884376 ps
T1127 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3368306802 Jun 27 06:19:12 PM PDT 24 Jun 27 06:19:17 PM PDT 24 34895346 ps
T1128 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2002704567 Jun 27 06:19:32 PM PDT 24 Jun 27 06:19:36 PM PDT 24 51339361 ps
T1129 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3556207678 Jun 27 06:19:17 PM PDT 24 Jun 27 06:19:23 PM PDT 24 129373115 ps
T1130 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3822094647 Jun 27 06:19:17 PM PDT 24 Jun 27 06:19:22 PM PDT 24 18199362 ps

Test location /workspace/coverage/default/11.spi_device_stress_all.2644577188
Short name T8
Test name
Test status
Simulation time 31586391397 ps
CPU time 335.15 seconds
Started Jun 27 06:23:44 PM PDT 24
Finished Jun 27 06:29:23 PM PDT 24
Peak memory 274608 kb
Host smart-6711f1d7-8479-49d7-9b59-edde9b12232c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644577188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2644577188
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.542611590
Short name T38
Test name
Test status
Simulation time 94722648572 ps
CPU time 174.75 seconds
Started Jun 27 06:24:19 PM PDT 24
Finished Jun 27 06:27:22 PM PDT 24
Peak memory 253352 kb
Host smart-7e08abd5-6ce1-447f-8b2a-875beb31e831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542611590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.542611590
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2673091848
Short name T25
Test name
Test status
Simulation time 126100307691 ps
CPU time 304.09 seconds
Started Jun 27 06:23:02 PM PDT 24
Finished Jun 27 06:28:15 PM PDT 24
Peak memory 266764 kb
Host smart-c4fabec3-95ed-4c17-971b-87627c79c915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673091848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2673091848
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2899158660
Short name T66
Test name
Test status
Simulation time 2131655038 ps
CPU time 23.65 seconds
Started Jun 27 06:19:18 PM PDT 24
Finished Jun 27 06:19:46 PM PDT 24
Peak memory 215404 kb
Host smart-87603396-31b2-48b1-b896-5159e0edff82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899158660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2899158660
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.495360723
Short name T164
Test name
Test status
Simulation time 23853475374 ps
CPU time 192.25 seconds
Started Jun 27 06:24:12 PM PDT 24
Finished Jun 27 06:27:31 PM PDT 24
Peak memory 274352 kb
Host smart-412c492d-91be-4f52-aedb-0447a42baa16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495360723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.495360723
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.4004718606
Short name T69
Test name
Test status
Simulation time 15627679 ps
CPU time 0.76 seconds
Started Jun 27 06:22:49 PM PDT 24
Finished Jun 27 06:22:55 PM PDT 24
Peak memory 216584 kb
Host smart-85b35399-39f1-4f92-8723-d6892f8b6d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004718606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4004718606
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.902573097
Short name T165
Test name
Test status
Simulation time 149594728444 ps
CPU time 701.11 seconds
Started Jun 27 06:24:45 PM PDT 24
Finished Jun 27 06:36:33 PM PDT 24
Peak memory 266420 kb
Host smart-468d0d92-d053-4d26-9dd7-f472d45b6788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902573097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.902573097
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3270470407
Short name T203
Test name
Test status
Simulation time 476464449266 ps
CPU time 968.78 seconds
Started Jun 27 06:23:30 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 289060 kb
Host smart-6a3b6fc0-c001-437d-8c74-a19409abe066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270470407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3270470407
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2294829462
Short name T18
Test name
Test status
Simulation time 184166978530 ps
CPU time 369.39 seconds
Started Jun 27 06:25:02 PM PDT 24
Finished Jun 27 06:31:15 PM PDT 24
Peak memory 252748 kb
Host smart-6e65e00e-44a7-4de6-a6fc-1501757bbcf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294829462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2294829462
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.421101038
Short name T59
Test name
Test status
Simulation time 40656308215 ps
CPU time 160.49 seconds
Started Jun 27 06:25:34 PM PDT 24
Finished Jun 27 06:28:20 PM PDT 24
Peak memory 269684 kb
Host smart-5304d140-7f6c-4c09-a996-60d8ed817ed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421101038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.421101038
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2465838236
Short name T68
Test name
Test status
Simulation time 118342466 ps
CPU time 3.59 seconds
Started Jun 27 06:19:18 PM PDT 24
Finished Jun 27 06:19:25 PM PDT 24
Peak memory 215528 kb
Host smart-c602845a-c99f-45db-a28c-4a81687bd798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465838236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
465838236
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.719571278
Short name T46
Test name
Test status
Simulation time 53766831813 ps
CPU time 245.18 seconds
Started Jun 27 06:24:25 PM PDT 24
Finished Jun 27 06:28:40 PM PDT 24
Peak memory 256244 kb
Host smart-3b452f8e-7f6f-4dbd-ada6-8d33676d43fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719571278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.719571278
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.408650142
Short name T63
Test name
Test status
Simulation time 25658464 ps
CPU time 0.72 seconds
Started Jun 27 06:23:55 PM PDT 24
Finished Jun 27 06:24:01 PM PDT 24
Peak memory 205932 kb
Host smart-992acaf9-b5e2-4b3d-bf2d-e2f31af82630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408650142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.408650142
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3681689041
Short name T144
Test name
Test status
Simulation time 442743623 ps
CPU time 9.47 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:35 PM PDT 24
Peak memory 236352 kb
Host smart-1656b486-b06d-44f7-896a-00d98db32b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681689041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3681689041
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1705391211
Short name T135
Test name
Test status
Simulation time 321764711472 ps
CPU time 475.13 seconds
Started Jun 27 06:24:10 PM PDT 24
Finished Jun 27 06:32:10 PM PDT 24
Peak memory 272516 kb
Host smart-ac531d20-43be-4539-91fe-241340ce36bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705391211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1705391211
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1723063005
Short name T117
Test name
Test status
Simulation time 44256737 ps
CPU time 1.5 seconds
Started Jun 27 06:19:29 PM PDT 24
Finished Jun 27 06:19:33 PM PDT 24
Peak memory 215268 kb
Host smart-8434e310-b9ba-49bd-a540-d18836b8b34c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723063005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1723063005
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.424485994
Short name T185
Test name
Test status
Simulation time 11508310244 ps
CPU time 170.41 seconds
Started Jun 27 06:24:26 PM PDT 24
Finished Jun 27 06:27:26 PM PDT 24
Peak memory 266476 kb
Host smart-bce9991f-6ab1-408a-bc8a-e956a3379e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424485994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.424485994
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2412821272
Short name T211
Test name
Test status
Simulation time 1123529454311 ps
CPU time 655.85 seconds
Started Jun 27 06:24:33 PM PDT 24
Finished Jun 27 06:35:38 PM PDT 24
Peak memory 282020 kb
Host smart-e62876ee-b4f6-46e5-9863-cf8815011dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412821272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2412821272
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.867503337
Short name T87
Test name
Test status
Simulation time 24466803557 ps
CPU time 198.33 seconds
Started Jun 27 06:24:25 PM PDT 24
Finished Jun 27 06:27:53 PM PDT 24
Peak memory 254732 kb
Host smart-7549380d-9d1e-4aad-b86a-ed9ee6515002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867503337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.867503337
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2498764366
Short name T295
Test name
Test status
Simulation time 13842950612 ps
CPU time 199.31 seconds
Started Jun 27 06:23:13 PM PDT 24
Finished Jun 27 06:26:41 PM PDT 24
Peak memory 274448 kb
Host smart-6275f620-b91c-4edf-a076-be41bb289067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498764366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2498764366
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.4202381676
Short name T74
Test name
Test status
Simulation time 132927333 ps
CPU time 0.97 seconds
Started Jun 27 06:23:02 PM PDT 24
Finished Jun 27 06:23:17 PM PDT 24
Peak memory 236972 kb
Host smart-0aae4db0-906b-4d4d-890e-beed88f91e9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202381676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.4202381676
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3113534603
Short name T39
Test name
Test status
Simulation time 32729406382 ps
CPU time 48.68 seconds
Started Jun 27 06:24:24 PM PDT 24
Finished Jun 27 06:25:22 PM PDT 24
Peak memory 241532 kb
Host smart-32239896-1e4d-47d4-9da7-083d022a8f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113534603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3113534603
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3741468080
Short name T261
Test name
Test status
Simulation time 10362644318 ps
CPU time 78.43 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:26:54 PM PDT 24
Peak memory 256328 kb
Host smart-12ae6335-78fe-4725-b33f-217b0119a982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741468080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3741468080
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2224544879
Short name T311
Test name
Test status
Simulation time 113313801786 ps
CPU time 192.31 seconds
Started Jun 27 06:23:39 PM PDT 24
Finished Jun 27 06:26:55 PM PDT 24
Peak memory 270076 kb
Host smart-bfbeaaa6-4149-4ea9-a1b2-1b1a0105eb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224544879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2224544879
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2544470650
Short name T41
Test name
Test status
Simulation time 13199988726 ps
CPU time 160.26 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:27:50 PM PDT 24
Peak memory 251628 kb
Host smart-1a2ca0f2-eb26-44c2-a230-8180fc2b0262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544470650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2544470650
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3914231344
Short name T200
Test name
Test status
Simulation time 13254863581 ps
CPU time 56.09 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:24:29 PM PDT 24
Peak memory 268036 kb
Host smart-bcaf95db-41ca-47a8-8209-e48766cd3c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914231344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3914231344
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.760603120
Short name T208
Test name
Test status
Simulation time 88733408726 ps
CPU time 228.97 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:29:14 PM PDT 24
Peak memory 249864 kb
Host smart-c683d681-0295-4680-933c-0f7716c1f1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760603120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.760603120
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.4188411360
Short name T153
Test name
Test status
Simulation time 2279883974 ps
CPU time 47.63 seconds
Started Jun 27 06:24:06 PM PDT 24
Finished Jun 27 06:24:55 PM PDT 24
Peak memory 249828 kb
Host smart-f25c8e37-d865-4237-922a-baabcf9f02e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188411360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.4188411360
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.813033826
Short name T193
Test name
Test status
Simulation time 305356892210 ps
CPU time 124.54 seconds
Started Jun 27 06:25:10 PM PDT 24
Finished Jun 27 06:27:21 PM PDT 24
Peak memory 224600 kb
Host smart-067db342-b875-43f8-954b-08236c7757c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813033826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.813033826
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1482681069
Short name T108
Test name
Test status
Simulation time 176486683 ps
CPU time 4.98 seconds
Started Jun 27 06:19:40 PM PDT 24
Finished Jun 27 06:19:50 PM PDT 24
Peak memory 215604 kb
Host smart-1101afae-a5c2-448d-8f29-e632f8b52213
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482681069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
482681069
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.822360128
Short name T56
Test name
Test status
Simulation time 877532324 ps
CPU time 16.61 seconds
Started Jun 27 06:24:48 PM PDT 24
Finished Jun 27 06:25:12 PM PDT 24
Peak memory 225048 kb
Host smart-e7f0accb-2df4-4740-95d8-560929acab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822360128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.822360128
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.4236792347
Short name T42
Test name
Test status
Simulation time 19861565147 ps
CPU time 75.74 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:26:25 PM PDT 24
Peak memory 250724 kb
Host smart-548e99ad-fc98-4ad2-97c7-52d18438fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236792347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.4236792347
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3359665654
Short name T178
Test name
Test status
Simulation time 3416646319 ps
CPU time 13.11 seconds
Started Jun 27 06:19:41 PM PDT 24
Finished Jun 27 06:19:59 PM PDT 24
Peak memory 215396 kb
Host smart-8d0b236e-dc96-475e-9343-575865ca2b5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359665654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3359665654
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.655415343
Short name T52
Test name
Test status
Simulation time 63954614549 ps
CPU time 123.15 seconds
Started Jun 27 06:23:20 PM PDT 24
Finished Jun 27 06:25:29 PM PDT 24
Peak memory 249728 kb
Host smart-4752ac31-1251-4eac-bdef-21430446b43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655415343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.655415343
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.529647128
Short name T268
Test name
Test status
Simulation time 12416938958 ps
CPU time 78.52 seconds
Started Jun 27 06:23:32 PM PDT 24
Finished Jun 27 06:24:54 PM PDT 24
Peak memory 267816 kb
Host smart-9ecf38c4-5f02-4b84-80e1-40c6df5f93c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529647128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.529647128
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.637374
Short name T51
Test name
Test status
Simulation time 391675887527 ps
CPU time 878.23 seconds
Started Jun 27 06:25:22 PM PDT 24
Finished Jun 27 06:40:06 PM PDT 24
Peak memory 274272 kb
Host smart-06a89fb4-f68c-42c7-b47f-943afc734bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.637374
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1639545755
Short name T195
Test name
Test status
Simulation time 18336778810 ps
CPU time 87.99 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:26:54 PM PDT 24
Peak memory 250584 kb
Host smart-0ab4a094-309f-4020-99d4-59b855cdd0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639545755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1639545755
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1272599229
Short name T172
Test name
Test status
Simulation time 396568764 ps
CPU time 12.91 seconds
Started Jun 27 06:19:14 PM PDT 24
Finished Jun 27 06:19:31 PM PDT 24
Peak memory 215784 kb
Host smart-c47cc6f4-e364-4d51-b531-544f5463e2dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272599229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1272599229
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1863604034
Short name T305
Test name
Test status
Simulation time 27653963531 ps
CPU time 120.91 seconds
Started Jun 27 06:23:56 PM PDT 24
Finished Jun 27 06:26:02 PM PDT 24
Peak memory 265324 kb
Host smart-6cf7c61e-3bd5-4be0-8e0a-d3b8968ff420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863604034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1863604034
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1585967214
Short name T30
Test name
Test status
Simulation time 9879061472 ps
CPU time 23.99 seconds
Started Jun 27 06:24:17 PM PDT 24
Finished Jun 27 06:24:49 PM PDT 24
Peak memory 225272 kb
Host smart-50555844-2478-4380-a08c-5386dd68e8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585967214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1585967214
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3678324715
Short name T313
Test name
Test status
Simulation time 493343785 ps
CPU time 11.28 seconds
Started Jun 27 06:24:23 PM PDT 24
Finished Jun 27 06:24:43 PM PDT 24
Peak memory 225020 kb
Host smart-f050cdbe-dbb7-4432-b4f0-276b10f31ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678324715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3678324715
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2257287595
Short name T12
Test name
Test status
Simulation time 675762946 ps
CPU time 3.94 seconds
Started Jun 27 06:24:29 PM PDT 24
Finished Jun 27 06:24:43 PM PDT 24
Peak memory 216808 kb
Host smart-802cfded-e574-4851-acab-57b34b3d7d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257287595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2257287595
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1658954078
Short name T233
Test name
Test status
Simulation time 295758105 ps
CPU time 9.17 seconds
Started Jun 27 06:24:44 PM PDT 24
Finished Jun 27 06:25:01 PM PDT 24
Peak memory 241404 kb
Host smart-39e3a933-7bc3-4ed8-a1b5-e4bd7af3510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658954078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1658954078
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3057698574
Short name T67
Test name
Test status
Simulation time 3296049414 ps
CPU time 4.77 seconds
Started Jun 27 06:19:37 PM PDT 24
Finished Jun 27 06:19:45 PM PDT 24
Peak memory 215752 kb
Host smart-b3bcf62f-437a-4cbf-9f8a-4a382ac9aa7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057698574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3057698574
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2992706174
Short name T113
Test name
Test status
Simulation time 3467575270 ps
CPU time 7.95 seconds
Started Jun 27 06:19:27 PM PDT 24
Finished Jun 27 06:19:38 PM PDT 24
Peak memory 215656 kb
Host smart-5b194a5c-3ba2-42e4-94f8-a4be4d89c5a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992706174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2992706174
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.850019334
Short name T177
Test name
Test status
Simulation time 290902881 ps
CPU time 7.65 seconds
Started Jun 27 06:19:16 PM PDT 24
Finished Jun 27 06:19:28 PM PDT 24
Peak memory 215352 kb
Host smart-408419b1-2039-4c00-ab36-2d996631619e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850019334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.850019334
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1923713467
Short name T321
Test name
Test status
Simulation time 4911707622 ps
CPU time 22.81 seconds
Started Jun 27 06:23:56 PM PDT 24
Finished Jun 27 06:24:24 PM PDT 24
Peak memory 216916 kb
Host smart-b264e4a9-e95b-4d7a-8469-ada66b7a2d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923713467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1923713467
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_intercept.287492075
Short name T447
Test name
Test status
Simulation time 6316848650 ps
CPU time 4.25 seconds
Started Jun 27 06:24:14 PM PDT 24
Finished Jun 27 06:24:26 PM PDT 24
Peak memory 225000 kb
Host smart-d5f0f841-9b2f-42bb-94ec-ccb8465fba1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287492075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.287492075
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.357669133
Short name T304
Test name
Test status
Simulation time 73025278806 ps
CPU time 390.91 seconds
Started Jun 27 06:24:20 PM PDT 24
Finished Jun 27 06:30:59 PM PDT 24
Peak memory 267576 kb
Host smart-70a67b8e-b8a3-40ec-ad4c-6c99a229fefe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357669133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.357669133
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2996544390
Short name T1006
Test name
Test status
Simulation time 406796340296 ps
CPU time 383.92 seconds
Started Jun 27 06:24:34 PM PDT 24
Finished Jun 27 06:31:07 PM PDT 24
Peak memory 252440 kb
Host smart-666fae4e-78d2-4a05-8aa4-053d41f3dde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996544390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2996544390
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2774576416
Short name T334
Test name
Test status
Simulation time 3820431329 ps
CPU time 18.68 seconds
Started Jun 27 06:23:13 PM PDT 24
Finished Jun 27 06:23:40 PM PDT 24
Peak memory 220700 kb
Host smart-f9b90d20-9f6a-4199-96aa-b041fbc002d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774576416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2774576416
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1989975416
Short name T23
Test name
Test status
Simulation time 317940952 ps
CPU time 3.45 seconds
Started Jun 27 06:23:30 PM PDT 24
Finished Jun 27 06:23:37 PM PDT 24
Peak memory 220736 kb
Host smart-8bf72acb-35d8-422c-8e7b-a115471ac39c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1989975416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1989975416
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2097743242
Short name T184
Test name
Test status
Simulation time 20175631594 ps
CPU time 37.35 seconds
Started Jun 27 06:23:42 PM PDT 24
Finished Jun 27 06:24:22 PM PDT 24
Peak memory 225176 kb
Host smart-e90599d7-9485-4a58-85c5-28cf65999fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097743242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2097743242
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3735593505
Short name T90
Test name
Test status
Simulation time 122304452 ps
CPU time 1.23 seconds
Started Jun 27 06:19:20 PM PDT 24
Finished Jun 27 06:19:25 PM PDT 24
Peak memory 216436 kb
Host smart-2cbecf18-67dd-45b1-b5a1-04b96bbd01eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735593505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3735593505
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2409724369
Short name T36
Test name
Test status
Simulation time 36504958353 ps
CPU time 409.46 seconds
Started Jun 27 06:22:58 PM PDT 24
Finished Jun 27 06:29:57 PM PDT 24
Peak memory 282628 kb
Host smart-8044f1b4-be79-40cb-b258-7d345ef29176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409724369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2409724369
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.857369698
Short name T1096
Test name
Test status
Simulation time 425028460 ps
CPU time 14.57 seconds
Started Jun 27 06:19:22 PM PDT 24
Finished Jun 27 06:19:40 PM PDT 24
Peak memory 215272 kb
Host smart-dd560732-be71-4af9-908a-11e974737cca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857369698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.857369698
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2500502453
Short name T1113
Test name
Test status
Simulation time 1265151526 ps
CPU time 24.89 seconds
Started Jun 27 06:19:06 PM PDT 24
Finished Jun 27 06:19:37 PM PDT 24
Peak memory 207096 kb
Host smart-245fd530-3fa7-4c32-9b4d-8f3340d4276a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500502453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2500502453
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2014086112
Short name T1039
Test name
Test status
Simulation time 39656552 ps
CPU time 2.82 seconds
Started Jun 27 06:19:24 PM PDT 24
Finished Jun 27 06:19:30 PM PDT 24
Peak memory 216376 kb
Host smart-96089681-2fbf-40e2-8f48-289fcea1f703
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014086112 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2014086112
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3931474610
Short name T1067
Test name
Test status
Simulation time 109394467 ps
CPU time 1.88 seconds
Started Jun 27 06:19:03 PM PDT 24
Finished Jun 27 06:19:12 PM PDT 24
Peak memory 207224 kb
Host smart-f0125ec3-9d22-4a76-bfef-70d32ca787a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931474610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
931474610
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2188577224
Short name T1048
Test name
Test status
Simulation time 81568788 ps
CPU time 0.66 seconds
Started Jun 27 06:19:05 PM PDT 24
Finished Jun 27 06:19:12 PM PDT 24
Peak memory 203864 kb
Host smart-8462caf1-7f40-4b2a-ab83-b1d34d80015d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188577224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
188577224
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2836881905
Short name T121
Test name
Test status
Simulation time 71535261 ps
CPU time 1.66 seconds
Started Jun 27 06:19:06 PM PDT 24
Finished Jun 27 06:19:14 PM PDT 24
Peak memory 215368 kb
Host smart-a61f756c-9e22-486c-8fdf-96d66fa6b4dc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836881905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2836881905
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.334233703
Short name T1106
Test name
Test status
Simulation time 13530380 ps
CPU time 0.67 seconds
Started Jun 27 06:19:03 PM PDT 24
Finished Jun 27 06:19:10 PM PDT 24
Peak memory 203792 kb
Host smart-b8db6734-a50c-4e02-9461-e12fd04c3abb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334233703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.334233703
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3090581018
Short name T1042
Test name
Test status
Simulation time 49138119 ps
CPU time 2.84 seconds
Started Jun 27 06:19:22 PM PDT 24
Finished Jun 27 06:19:28 PM PDT 24
Peak memory 215408 kb
Host smart-be4596c4-669e-4183-9942-ac22ef8b3ad0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090581018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3090581018
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3230412406
Short name T1077
Test name
Test status
Simulation time 343298894 ps
CPU time 7.95 seconds
Started Jun 27 06:19:06 PM PDT 24
Finished Jun 27 06:19:20 PM PDT 24
Peak memory 216528 kb
Host smart-721ce3d2-87f7-48de-91fc-9c2e1df130a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230412406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3230412406
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3068312961
Short name T120
Test name
Test status
Simulation time 11333238491 ps
CPU time 23.87 seconds
Started Jun 27 06:19:26 PM PDT 24
Finished Jun 27 06:19:53 PM PDT 24
Peak memory 215404 kb
Host smart-65dc555d-acc5-4e78-be25-0a7a4612e4de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068312961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3068312961
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3807666078
Short name T1082
Test name
Test status
Simulation time 36057078662 ps
CPU time 35.33 seconds
Started Jun 27 06:19:03 PM PDT 24
Finished Jun 27 06:19:45 PM PDT 24
Peak memory 215392 kb
Host smart-5172add8-19cc-45c3-8976-a1cd9e1264ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807666078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3807666078
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.257057199
Short name T88
Test name
Test status
Simulation time 42053352 ps
CPU time 1.28 seconds
Started Jun 27 06:19:03 PM PDT 24
Finished Jun 27 06:19:10 PM PDT 24
Peak memory 216240 kb
Host smart-630807a7-de1a-4326-b0c8-c6bb32edc93b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257057199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.257057199
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1077810695
Short name T1124
Test name
Test status
Simulation time 68776587 ps
CPU time 2.54 seconds
Started Jun 27 06:19:12 PM PDT 24
Finished Jun 27 06:19:19 PM PDT 24
Peak memory 217276 kb
Host smart-068c3df1-0d7d-44e8-9b24-cceb2c0746e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077810695 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1077810695
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3291001541
Short name T1079
Test name
Test status
Simulation time 87808759 ps
CPU time 2.63 seconds
Started Jun 27 06:19:28 PM PDT 24
Finished Jun 27 06:19:34 PM PDT 24
Peak memory 215308 kb
Host smart-db211fde-fe5c-4cda-886b-76c50b8a3ee8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291001541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
291001541
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3279913050
Short name T1031
Test name
Test status
Simulation time 56868181 ps
CPU time 0.73 seconds
Started Jun 27 06:19:25 PM PDT 24
Finished Jun 27 06:19:29 PM PDT 24
Peak memory 204108 kb
Host smart-b46906ae-9135-42ed-baa8-4b6c3836f444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279913050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
279913050
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3191325173
Short name T1103
Test name
Test status
Simulation time 110468674 ps
CPU time 1.78 seconds
Started Jun 27 06:19:18 PM PDT 24
Finished Jun 27 06:19:25 PM PDT 24
Peak memory 215404 kb
Host smart-a193da44-6465-4a47-b6bb-7dcd89f57089
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191325173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3191325173
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1176964607
Short name T1046
Test name
Test status
Simulation time 10683869 ps
CPU time 0.66 seconds
Started Jun 27 06:19:28 PM PDT 24
Finished Jun 27 06:19:32 PM PDT 24
Peak memory 204076 kb
Host smart-92a10918-7582-41f2-94af-3bf66ac0c1b8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176964607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1176964607
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1617853817
Short name T1092
Test name
Test status
Simulation time 184902660 ps
CPU time 2.76 seconds
Started Jun 27 06:19:04 PM PDT 24
Finished Jun 27 06:19:14 PM PDT 24
Peak memory 215372 kb
Host smart-cf6167a1-1381-460a-9c67-627dec011945
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617853817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1617853817
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.359965949
Short name T1075
Test name
Test status
Simulation time 128319423 ps
CPU time 3.09 seconds
Started Jun 27 06:19:12 PM PDT 24
Finished Jun 27 06:19:19 PM PDT 24
Peak memory 215552 kb
Host smart-ac14c084-d531-41e9-a693-8af0210c71eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359965949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.359965949
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.271391216
Short name T1062
Test name
Test status
Simulation time 343134629 ps
CPU time 2.83 seconds
Started Jun 27 06:19:19 PM PDT 24
Finished Jun 27 06:19:26 PM PDT 24
Peak memory 216632 kb
Host smart-d0faea4c-47ef-47b4-8565-af2a54a6cd8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271391216 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.271391216
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3782246071
Short name T1051
Test name
Test status
Simulation time 23747976 ps
CPU time 1.36 seconds
Started Jun 27 06:19:19 PM PDT 24
Finished Jun 27 06:19:25 PM PDT 24
Peak memory 207080 kb
Host smart-b4c6d77e-569a-4fc0-8f61-d1e2800f9c49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782246071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3782246071
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2704997963
Short name T1122
Test name
Test status
Simulation time 24211166 ps
CPU time 0.75 seconds
Started Jun 27 06:19:31 PM PDT 24
Finished Jun 27 06:19:36 PM PDT 24
Peak memory 203852 kb
Host smart-fceeaef7-287c-4c2c-a4c1-cd1f95aadff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704997963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2704997963
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4276722547
Short name T1088
Test name
Test status
Simulation time 88995387 ps
CPU time 1.71 seconds
Started Jun 27 06:19:17 PM PDT 24
Finished Jun 27 06:19:23 PM PDT 24
Peak memory 207068 kb
Host smart-f64166fc-9598-4d18-a298-b26c5b8fc78a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276722547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4276722547
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2318336962
Short name T103
Test name
Test status
Simulation time 88790516 ps
CPU time 1.68 seconds
Started Jun 27 06:19:19 PM PDT 24
Finished Jun 27 06:19:25 PM PDT 24
Peak memory 215564 kb
Host smart-b3b3c9a8-7ac0-4ee7-bee0-c3142de9102e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318336962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2318336962
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3103523567
Short name T150
Test name
Test status
Simulation time 119529387 ps
CPU time 1.82 seconds
Started Jun 27 06:19:16 PM PDT 24
Finished Jun 27 06:19:21 PM PDT 24
Peak memory 215468 kb
Host smart-f2dc9328-da52-49cd-a18e-d08186225525
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103523567 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3103523567
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2904447481
Short name T1014
Test name
Test status
Simulation time 17308396 ps
CPU time 0.75 seconds
Started Jun 27 06:19:29 PM PDT 24
Finished Jun 27 06:19:32 PM PDT 24
Peak memory 203864 kb
Host smart-c6ca7553-8e06-424e-a8d8-86641febd14b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904447481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2904447481
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3617606246
Short name T1083
Test name
Test status
Simulation time 149499633 ps
CPU time 2.54 seconds
Started Jun 27 06:19:18 PM PDT 24
Finished Jun 27 06:19:25 PM PDT 24
Peak memory 215400 kb
Host smart-de3871c1-ecd8-405b-b3ae-2f6aedb3776c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617606246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3617606246
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2234912743
Short name T1069
Test name
Test status
Simulation time 171861041 ps
CPU time 1.92 seconds
Started Jun 27 06:19:32 PM PDT 24
Finished Jun 27 06:19:38 PM PDT 24
Peak memory 215428 kb
Host smart-72823582-1710-4b46-8ce7-ac3d1b85d1f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234912743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2234912743
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1527274071
Short name T1024
Test name
Test status
Simulation time 87586367 ps
CPU time 2.57 seconds
Started Jun 27 06:19:20 PM PDT 24
Finished Jun 27 06:19:27 PM PDT 24
Peak memory 216456 kb
Host smart-a9f20834-4f66-4e18-872e-5a6c27724f86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527274071 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1527274071
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3790752804
Short name T1102
Test name
Test status
Simulation time 29576686 ps
CPU time 1.97 seconds
Started Jun 27 06:19:36 PM PDT 24
Finished Jun 27 06:19:42 PM PDT 24
Peak memory 215408 kb
Host smart-010e53e5-c7bd-4d51-ab36-60129f58d192
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790752804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3790752804
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3368306802
Short name T1127
Test name
Test status
Simulation time 34895346 ps
CPU time 0.73 seconds
Started Jun 27 06:19:12 PM PDT 24
Finished Jun 27 06:19:17 PM PDT 24
Peak memory 203792 kb
Host smart-c4d46619-e8c3-4202-af54-c7462948ce2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368306802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3368306802
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1932678740
Short name T1091
Test name
Test status
Simulation time 237601006 ps
CPU time 3.82 seconds
Started Jun 27 06:19:34 PM PDT 24
Finished Jun 27 06:19:41 PM PDT 24
Peak memory 215404 kb
Host smart-5bf810e4-16ff-43bd-bb82-a7ff4890d565
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932678740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1932678740
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1253389764
Short name T107
Test name
Test status
Simulation time 151649641 ps
CPU time 2.71 seconds
Started Jun 27 06:19:14 PM PDT 24
Finished Jun 27 06:19:20 PM PDT 24
Peak memory 215548 kb
Host smart-891f875d-3213-457a-a2bc-5d9a0ef3d609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253389764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1253389764
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.302067699
Short name T173
Test name
Test status
Simulation time 772884376 ps
CPU time 12.86 seconds
Started Jun 27 06:19:15 PM PDT 24
Finished Jun 27 06:19:32 PM PDT 24
Peak memory 215704 kb
Host smart-77240f3a-159f-43db-93b4-f60c36bd89e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302067699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.302067699
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2167854050
Short name T1045
Test name
Test status
Simulation time 217265380 ps
CPU time 1.82 seconds
Started Jun 27 06:19:29 PM PDT 24
Finished Jun 27 06:19:34 PM PDT 24
Peak memory 216472 kb
Host smart-34f523b8-97e2-4642-9c9c-64e9283a84e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167854050 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2167854050
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1898124763
Short name T115
Test name
Test status
Simulation time 149386708 ps
CPU time 1.84 seconds
Started Jun 27 06:19:24 PM PDT 24
Finished Jun 27 06:19:30 PM PDT 24
Peak memory 215628 kb
Host smart-0487b6a0-4030-4fd3-8402-148fd7b58726
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898124763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1898124763
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2120125145
Short name T1115
Test name
Test status
Simulation time 13224057 ps
CPU time 0.74 seconds
Started Jun 27 06:19:26 PM PDT 24
Finished Jun 27 06:19:30 PM PDT 24
Peak memory 204348 kb
Host smart-65974225-b47c-475f-8cda-24dadb80f944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120125145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2120125145
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1137435487
Short name T1029
Test name
Test status
Simulation time 779673886 ps
CPU time 3.29 seconds
Started Jun 27 06:19:19 PM PDT 24
Finished Jun 27 06:19:27 PM PDT 24
Peak memory 215308 kb
Host smart-d0f22eb3-32f3-4370-a382-f0bf5a5bb179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137435487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1137435487
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4125058711
Short name T100
Test name
Test status
Simulation time 138386095 ps
CPU time 5.25 seconds
Started Jun 27 06:19:19 PM PDT 24
Finished Jun 27 06:19:29 PM PDT 24
Peak memory 215560 kb
Host smart-7a123fb5-bc10-4816-b1be-0d9cb39e1ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125058711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
4125058711
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2238394363
Short name T1021
Test name
Test status
Simulation time 92029292 ps
CPU time 1.7 seconds
Started Jun 27 06:19:27 PM PDT 24
Finished Jun 27 06:19:32 PM PDT 24
Peak memory 216688 kb
Host smart-15641f23-509b-4f63-b96f-9a2a5665e3c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238394363 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2238394363
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4222644687
Short name T119
Test name
Test status
Simulation time 100875042 ps
CPU time 1.8 seconds
Started Jun 27 06:19:29 PM PDT 24
Finished Jun 27 06:19:33 PM PDT 24
Peak memory 215388 kb
Host smart-69712597-9684-4628-8ab4-86a40406adde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222644687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4222644687
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.998685990
Short name T1123
Test name
Test status
Simulation time 40010890 ps
CPU time 0.74 seconds
Started Jun 27 06:19:22 PM PDT 24
Finished Jun 27 06:19:26 PM PDT 24
Peak memory 203860 kb
Host smart-48ac53ac-95e8-4f88-ab34-630d062206a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998685990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.998685990
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1189234674
Short name T1035
Test name
Test status
Simulation time 38089142 ps
CPU time 2.52 seconds
Started Jun 27 06:19:25 PM PDT 24
Finished Jun 27 06:19:31 PM PDT 24
Peak memory 215624 kb
Host smart-e0ebb0fe-45f8-4fce-bf55-b733803f2b51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189234674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1189234674
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2718404510
Short name T152
Test name
Test status
Simulation time 120490202 ps
CPU time 2.93 seconds
Started Jun 27 06:19:38 PM PDT 24
Finished Jun 27 06:19:45 PM PDT 24
Peak memory 215640 kb
Host smart-8f7ab3da-2f7b-42e0-8072-44d06fdddd85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718404510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2718404510
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1334544530
Short name T1043
Test name
Test status
Simulation time 178503014 ps
CPU time 1.71 seconds
Started Jun 27 06:19:31 PM PDT 24
Finished Jun 27 06:19:36 PM PDT 24
Peak memory 215436 kb
Host smart-2a1cd603-bf72-4cb4-b6e4-eeef247b67f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334544530 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1334544530
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4100876078
Short name T1073
Test name
Test status
Simulation time 34289215 ps
CPU time 2.34 seconds
Started Jun 27 06:19:32 PM PDT 24
Finished Jun 27 06:19:38 PM PDT 24
Peak memory 215528 kb
Host smart-65321ae4-fe73-43bf-8027-14767287f336
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100876078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4100876078
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1976990901
Short name T1028
Test name
Test status
Simulation time 13981670 ps
CPU time 0.72 seconds
Started Jun 27 06:19:39 PM PDT 24
Finished Jun 27 06:19:44 PM PDT 24
Peak memory 203844 kb
Host smart-04087dda-2ab4-4890-a7e9-71c41846fa5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976990901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1976990901
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2615928621
Short name T140
Test name
Test status
Simulation time 600416945 ps
CPU time 3.88 seconds
Started Jun 27 06:19:26 PM PDT 24
Finished Jun 27 06:19:33 PM PDT 24
Peak memory 215372 kb
Host smart-c0504181-426c-4bc4-bd99-6ba837d32c57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615928621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2615928621
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.658266448
Short name T106
Test name
Test status
Simulation time 294766069 ps
CPU time 4 seconds
Started Jun 27 06:19:33 PM PDT 24
Finished Jun 27 06:19:41 PM PDT 24
Peak memory 215708 kb
Host smart-00184e06-7bea-4f3e-b8cd-fd282f932b70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658266448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.658266448
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.550779880
Short name T111
Test name
Test status
Simulation time 1405121796 ps
CPU time 16.48 seconds
Started Jun 27 06:19:21 PM PDT 24
Finished Jun 27 06:19:41 PM PDT 24
Peak memory 215496 kb
Host smart-7c9554b5-681b-45fa-985a-c5e1253d32a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550779880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.550779880
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.870404858
Short name T1105
Test name
Test status
Simulation time 223282926 ps
CPU time 3.84 seconds
Started Jun 27 06:19:40 PM PDT 24
Finished Jun 27 06:19:50 PM PDT 24
Peak memory 218788 kb
Host smart-6ce62d83-aa61-402a-9453-93ae49b473c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870404858 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.870404858
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2992728905
Short name T136
Test name
Test status
Simulation time 159780260 ps
CPU time 1.48 seconds
Started Jun 27 06:19:41 PM PDT 24
Finished Jun 27 06:19:48 PM PDT 24
Peak memory 215584 kb
Host smart-19dcbd20-d836-479b-a2d2-92b524847e51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992728905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2992728905
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1944168086
Short name T1020
Test name
Test status
Simulation time 49207434 ps
CPU time 0.82 seconds
Started Jun 27 06:19:24 PM PDT 24
Finished Jun 27 06:19:28 PM PDT 24
Peak memory 203880 kb
Host smart-f80d2f64-a16b-4cc6-9e68-fb02c98794e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944168086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1944168086
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2691501372
Short name T1049
Test name
Test status
Simulation time 381611404 ps
CPU time 2.87 seconds
Started Jun 27 06:19:41 PM PDT 24
Finished Jun 27 06:19:49 PM PDT 24
Peak memory 215404 kb
Host smart-090a90df-e816-435d-8fb4-66035b5e162a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691501372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2691501372
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1953938401
Short name T1109
Test name
Test status
Simulation time 4060435789 ps
CPU time 8.5 seconds
Started Jun 27 06:19:40 PM PDT 24
Finished Jun 27 06:19:54 PM PDT 24
Peak memory 215364 kb
Host smart-12430b40-82a1-4f03-b3f7-1eb4d01efa5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953938401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1953938401
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3135527689
Short name T109
Test name
Test status
Simulation time 54739987 ps
CPU time 3.54 seconds
Started Jun 27 06:19:19 PM PDT 24
Finished Jun 27 06:19:27 PM PDT 24
Peak memory 217844 kb
Host smart-eed46027-e837-4f65-a054-f8b849527a8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135527689 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3135527689
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3995420604
Short name T118
Test name
Test status
Simulation time 198308068 ps
CPU time 2.54 seconds
Started Jun 27 06:19:16 PM PDT 24
Finished Jun 27 06:19:22 PM PDT 24
Peak memory 215400 kb
Host smart-bbd9bde8-8ff0-460e-bf00-1e16cb4f8217
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995420604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3995420604
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1773426911
Short name T1019
Test name
Test status
Simulation time 21167347 ps
CPU time 0.82 seconds
Started Jun 27 06:19:34 PM PDT 24
Finished Jun 27 06:19:39 PM PDT 24
Peak memory 203856 kb
Host smart-8d720603-2dda-41b4-b724-0b4ab0f216de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773426911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1773426911
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3597058271
Short name T1058
Test name
Test status
Simulation time 141645082 ps
CPU time 3.47 seconds
Started Jun 27 06:19:23 PM PDT 24
Finished Jun 27 06:19:30 PM PDT 24
Peak memory 215808 kb
Host smart-1bb79bd7-bdf3-428d-8f67-407b9a1917b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597058271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3597058271
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3377377286
Short name T102
Test name
Test status
Simulation time 772789138 ps
CPU time 4.35 seconds
Started Jun 27 06:19:32 PM PDT 24
Finished Jun 27 06:19:40 PM PDT 24
Peak memory 215556 kb
Host smart-8105b4b1-fd1f-4480-91ce-777d3e012f97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377377286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3377377286
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1916304271
Short name T151
Test name
Test status
Simulation time 3719586219 ps
CPU time 23.44 seconds
Started Jun 27 06:19:23 PM PDT 24
Finished Jun 27 06:19:49 PM PDT 24
Peak memory 215400 kb
Host smart-26a36413-4c33-4a27-b515-8af0fd56ab8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916304271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1916304271
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.250768326
Short name T1097
Test name
Test status
Simulation time 1119968891 ps
CPU time 2.64 seconds
Started Jun 27 06:19:26 PM PDT 24
Finished Jun 27 06:19:32 PM PDT 24
Peak memory 216516 kb
Host smart-e1be7f3c-3d97-441a-a3f6-6f903b0cf17d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250768326 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.250768326
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.787728296
Short name T1121
Test name
Test status
Simulation time 215888800 ps
CPU time 2.66 seconds
Started Jun 27 06:19:12 PM PDT 24
Finished Jun 27 06:19:19 PM PDT 24
Peak memory 215368 kb
Host smart-7e6afd70-4186-4b74-9662-4f9aa78ebe8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787728296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.787728296
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3630704097
Short name T1054
Test name
Test status
Simulation time 52693677 ps
CPU time 0.77 seconds
Started Jun 27 06:19:32 PM PDT 24
Finished Jun 27 06:19:37 PM PDT 24
Peak memory 204184 kb
Host smart-c013b96b-c942-4a82-a6f2-bd5eace2c30f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630704097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3630704097
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2326654269
Short name T1071
Test name
Test status
Simulation time 218912420 ps
CPU time 1.96 seconds
Started Jun 27 06:19:19 PM PDT 24
Finished Jun 27 06:19:25 PM PDT 24
Peak memory 215376 kb
Host smart-7eff5fc3-76bd-4fc4-a912-89779891f276
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326654269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2326654269
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3897344502
Short name T105
Test name
Test status
Simulation time 249260221 ps
CPU time 2.16 seconds
Started Jun 27 06:19:37 PM PDT 24
Finished Jun 27 06:19:43 PM PDT 24
Peak memory 215548 kb
Host smart-f179c219-c43b-4c5f-bff0-f4f254d8a529
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897344502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3897344502
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2309774157
Short name T175
Test name
Test status
Simulation time 1705227459 ps
CPU time 21.1 seconds
Started Jun 27 06:19:35 PM PDT 24
Finished Jun 27 06:20:00 PM PDT 24
Peak memory 215832 kb
Host smart-e7c93a12-7869-47b4-b3c7-a246be5156aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309774157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2309774157
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3588498595
Short name T110
Test name
Test status
Simulation time 260354446 ps
CPU time 3.7 seconds
Started Jun 27 06:19:39 PM PDT 24
Finished Jun 27 06:19:47 PM PDT 24
Peak memory 216992 kb
Host smart-2d979257-b04c-40af-a874-d34997b19653
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588498595 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3588498595
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4100989155
Short name T1118
Test name
Test status
Simulation time 62162233 ps
CPU time 1.98 seconds
Started Jun 27 06:19:32 PM PDT 24
Finished Jun 27 06:19:37 PM PDT 24
Peak memory 215404 kb
Host smart-58eb1e9c-1b97-460b-b2b7-8ca88081115f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100989155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4100989155
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.382063284
Short name T1074
Test name
Test status
Simulation time 15811589 ps
CPU time 0.77 seconds
Started Jun 27 06:19:27 PM PDT 24
Finished Jun 27 06:19:32 PM PDT 24
Peak memory 203880 kb
Host smart-07a5a3cd-beed-4814-ab3a-82a670b575a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382063284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.382063284
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2511495050
Short name T1025
Test name
Test status
Simulation time 233615515 ps
CPU time 1.83 seconds
Started Jun 27 06:19:42 PM PDT 24
Finished Jun 27 06:19:50 PM PDT 24
Peak memory 215396 kb
Host smart-93cca33a-98b1-491b-8ad6-ece09caee6a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511495050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2511495050
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3102428664
Short name T1100
Test name
Test status
Simulation time 926201775 ps
CPU time 3.56 seconds
Started Jun 27 06:19:20 PM PDT 24
Finished Jun 27 06:19:28 PM PDT 24
Peak memory 215760 kb
Host smart-e512e163-dcd0-4fa8-8791-d877045dcb97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102428664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3102428664
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3605452845
Short name T174
Test name
Test status
Simulation time 275584537 ps
CPU time 7.09 seconds
Started Jun 27 06:19:26 PM PDT 24
Finished Jun 27 06:19:37 PM PDT 24
Peak memory 223556 kb
Host smart-4ea81e8c-7f42-4918-9c8b-cf524e1941db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605452845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3605452845
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1756538027
Short name T122
Test name
Test status
Simulation time 1204211762 ps
CPU time 22.19 seconds
Started Jun 27 06:19:17 PM PDT 24
Finished Jun 27 06:19:43 PM PDT 24
Peak memory 215596 kb
Host smart-fafd83ff-ccd5-459d-9425-1fa014d58d5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756538027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1756538027
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1503088091
Short name T124
Test name
Test status
Simulation time 7088425912 ps
CPU time 38.79 seconds
Started Jun 27 06:19:05 PM PDT 24
Finished Jun 27 06:19:50 PM PDT 24
Peak memory 207280 kb
Host smart-4b04b16c-e363-4a9c-ac3f-022649de1d83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503088091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1503088091
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3522261573
Short name T89
Test name
Test status
Simulation time 14976538 ps
CPU time 0.99 seconds
Started Jun 27 06:19:05 PM PDT 24
Finished Jun 27 06:19:12 PM PDT 24
Peak memory 206972 kb
Host smart-eb540281-6f0c-46f4-8446-bff138cffe96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522261573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3522261573
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.799562000
Short name T97
Test name
Test status
Simulation time 54509825 ps
CPU time 3.64 seconds
Started Jun 27 06:19:03 PM PDT 24
Finished Jun 27 06:19:13 PM PDT 24
Peak memory 217540 kb
Host smart-ce10d482-b19c-4c11-bab1-f203af242002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799562000 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.799562000
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1886502872
Short name T1065
Test name
Test status
Simulation time 252471095 ps
CPU time 1.43 seconds
Started Jun 27 06:19:02 PM PDT 24
Finished Jun 27 06:19:10 PM PDT 24
Peak memory 215320 kb
Host smart-9347ff95-f0ce-4443-95b3-5240e9f99cea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886502872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
886502872
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1531419951
Short name T1066
Test name
Test status
Simulation time 13400733 ps
CPU time 0.73 seconds
Started Jun 27 06:19:05 PM PDT 24
Finished Jun 27 06:19:13 PM PDT 24
Peak memory 203840 kb
Host smart-7b73db8f-3682-4c88-b290-61aa64bda2c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531419951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
531419951
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1085194995
Short name T126
Test name
Test status
Simulation time 41282507 ps
CPU time 2.02 seconds
Started Jun 27 06:19:02 PM PDT 24
Finished Jun 27 06:19:10 PM PDT 24
Peak memory 215396 kb
Host smart-ae82fe51-cef1-45a0-bdf7-9f588a8e1ce2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085194995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1085194995
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2680578199
Short name T1027
Test name
Test status
Simulation time 13897772 ps
CPU time 0.69 seconds
Started Jun 27 06:19:04 PM PDT 24
Finished Jun 27 06:19:11 PM PDT 24
Peak memory 203780 kb
Host smart-20c13b9a-b89b-422f-b7e1-19218c01bc2d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680578199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2680578199
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.301033438
Short name T1026
Test name
Test status
Simulation time 47027635 ps
CPU time 2.73 seconds
Started Jun 27 06:19:01 PM PDT 24
Finished Jun 27 06:19:10 PM PDT 24
Peak memory 215300 kb
Host smart-cfe310b8-f534-4f22-876c-cd7ff7189b3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301033438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.301033438
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3183113941
Short name T1061
Test name
Test status
Simulation time 483291607 ps
CPU time 3.08 seconds
Started Jun 27 06:19:02 PM PDT 24
Finished Jun 27 06:19:12 PM PDT 24
Peak memory 215360 kb
Host smart-693104af-524f-4ebe-84c7-04591900e616
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183113941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
183113941
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2655912959
Short name T1056
Test name
Test status
Simulation time 307199399 ps
CPU time 7.82 seconds
Started Jun 27 06:19:18 PM PDT 24
Finished Jun 27 06:19:30 PM PDT 24
Peak memory 215636 kb
Host smart-4f1cc999-b656-43d0-94eb-e0348459f242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655912959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2655912959
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1251717277
Short name T1053
Test name
Test status
Simulation time 15485092 ps
CPU time 0.74 seconds
Started Jun 27 06:19:32 PM PDT 24
Finished Jun 27 06:19:36 PM PDT 24
Peak memory 203856 kb
Host smart-3dfd0e83-0005-4322-8b0c-7ddbfa3fcdee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251717277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1251717277
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4102167199
Short name T1107
Test name
Test status
Simulation time 48370649 ps
CPU time 0.68 seconds
Started Jun 27 06:19:39 PM PDT 24
Finished Jun 27 06:19:44 PM PDT 24
Peak memory 203832 kb
Host smart-d46c8b78-5420-4d6c-a2a0-39977139e769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102167199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4102167199
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1307581709
Short name T1084
Test name
Test status
Simulation time 21758251 ps
CPU time 0.69 seconds
Started Jun 27 06:19:29 PM PDT 24
Finished Jun 27 06:19:33 PM PDT 24
Peak memory 203800 kb
Host smart-45adbc85-4f46-47e9-ada1-0eee5419c25d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307581709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1307581709
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3405444521
Short name T1063
Test name
Test status
Simulation time 33055626 ps
CPU time 0.67 seconds
Started Jun 27 06:19:30 PM PDT 24
Finished Jun 27 06:19:33 PM PDT 24
Peak memory 203852 kb
Host smart-309d094e-0d94-49a7-840a-33df814f8fa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405444521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3405444521
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2002704567
Short name T1128
Test name
Test status
Simulation time 51339361 ps
CPU time 0.75 seconds
Started Jun 27 06:19:32 PM PDT 24
Finished Jun 27 06:19:36 PM PDT 24
Peak memory 203852 kb
Host smart-0920779d-8731-4a60-9129-c035f2daeef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002704567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2002704567
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.224814249
Short name T1047
Test name
Test status
Simulation time 26220594 ps
CPU time 0.76 seconds
Started Jun 27 06:19:29 PM PDT 24
Finished Jun 27 06:19:33 PM PDT 24
Peak memory 204116 kb
Host smart-11948131-e1ba-4cc5-9040-4eb88870df17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224814249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.224814249
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3571663021
Short name T1098
Test name
Test status
Simulation time 78920895 ps
CPU time 0.73 seconds
Started Jun 27 06:19:24 PM PDT 24
Finished Jun 27 06:19:28 PM PDT 24
Peak memory 203860 kb
Host smart-b2fca1b7-9478-4f94-8588-ea57d308b368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571663021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3571663021
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1586098440
Short name T1040
Test name
Test status
Simulation time 31630993 ps
CPU time 0.74 seconds
Started Jun 27 06:19:33 PM PDT 24
Finished Jun 27 06:19:37 PM PDT 24
Peak memory 203848 kb
Host smart-0fea0946-e65b-4872-be52-3fa0d176ac97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586098440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1586098440
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3535353097
Short name T1101
Test name
Test status
Simulation time 11863861 ps
CPU time 0.71 seconds
Started Jun 27 06:19:26 PM PDT 24
Finished Jun 27 06:19:30 PM PDT 24
Peak memory 204164 kb
Host smart-3bfd677a-03d4-4f23-8651-805496aed124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535353097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3535353097
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2023597312
Short name T1057
Test name
Test status
Simulation time 16363686 ps
CPU time 0.75 seconds
Started Jun 27 06:19:32 PM PDT 24
Finished Jun 27 06:19:37 PM PDT 24
Peak memory 204172 kb
Host smart-43ac64c0-05c7-46e5-aa85-4fec3ab06060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023597312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2023597312
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1091722588
Short name T1078
Test name
Test status
Simulation time 4255322871 ps
CPU time 22.16 seconds
Started Jun 27 06:19:16 PM PDT 24
Finished Jun 27 06:19:42 PM PDT 24
Peak memory 215332 kb
Host smart-c7a5a28d-a68a-427d-bcee-3ee8098c6478
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091722588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1091722588
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2129554814
Short name T1110
Test name
Test status
Simulation time 1303233421 ps
CPU time 22.64 seconds
Started Jun 27 06:19:10 PM PDT 24
Finished Jun 27 06:19:38 PM PDT 24
Peak memory 215336 kb
Host smart-d687a543-1c60-4841-ada3-8f315aacc819
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129554814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2129554814
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1159188127
Short name T116
Test name
Test status
Simulation time 41453762 ps
CPU time 0.96 seconds
Started Jun 27 06:19:12 PM PDT 24
Finished Jun 27 06:19:17 PM PDT 24
Peak memory 206904 kb
Host smart-e3bd5737-a1c4-4692-b59d-e6c9c5ab5c50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159188127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1159188127
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2639877835
Short name T1090
Test name
Test status
Simulation time 191653585 ps
CPU time 2.59 seconds
Started Jun 27 06:19:15 PM PDT 24
Finished Jun 27 06:19:21 PM PDT 24
Peak memory 217156 kb
Host smart-8a96bef4-d21a-4d98-9c2a-d34f971d41e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639877835 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2639877835
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3402954002
Short name T1095
Test name
Test status
Simulation time 111623515 ps
CPU time 1.9 seconds
Started Jun 27 06:19:12 PM PDT 24
Finished Jun 27 06:19:18 PM PDT 24
Peak memory 215348 kb
Host smart-a5fd0e07-590c-4cd9-af5f-55c474a861e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402954002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
402954002
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.742773750
Short name T1117
Test name
Test status
Simulation time 12722207 ps
CPU time 0.7 seconds
Started Jun 27 06:19:05 PM PDT 24
Finished Jun 27 06:19:12 PM PDT 24
Peak memory 203828 kb
Host smart-a53f0c9f-72b6-473c-acae-cc0b268fdb40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742773750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.742773750
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.655480449
Short name T1120
Test name
Test status
Simulation time 177381262 ps
CPU time 1.29 seconds
Started Jun 27 06:19:02 PM PDT 24
Finished Jun 27 06:19:09 PM PDT 24
Peak memory 215332 kb
Host smart-478afc71-ecba-4c31-8676-dccf5090d146
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655480449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.655480449
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2492976079
Short name T1089
Test name
Test status
Simulation time 38667285 ps
CPU time 0.68 seconds
Started Jun 27 06:19:03 PM PDT 24
Finished Jun 27 06:19:10 PM PDT 24
Peak memory 203768 kb
Host smart-f6c75317-866a-4ffc-8297-5811537645d1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492976079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2492976079
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3306272753
Short name T142
Test name
Test status
Simulation time 174718147 ps
CPU time 4.13 seconds
Started Jun 27 06:19:03 PM PDT 24
Finished Jun 27 06:19:14 PM PDT 24
Peak memory 215336 kb
Host smart-79f98e54-8e1f-4fe9-a219-c4a6ecd537ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306272753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3306272753
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4231097767
Short name T1094
Test name
Test status
Simulation time 651185182 ps
CPU time 4.61 seconds
Started Jun 27 06:19:04 PM PDT 24
Finished Jun 27 06:19:14 PM PDT 24
Peak memory 215448 kb
Host smart-7fb970bb-c670-4771-b914-e03f182f723e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231097767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.4
231097767
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4374667
Short name T1099
Test name
Test status
Simulation time 476358970 ps
CPU time 6.43 seconds
Started Jun 27 06:19:20 PM PDT 24
Finished Jun 27 06:19:31 PM PDT 24
Peak memory 215480 kb
Host smart-2a601ef8-6f4a-49f3-8c21-f341bfcd630e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4374667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl
_intg_err.4374667
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2471848769
Short name T1033
Test name
Test status
Simulation time 32489263 ps
CPU time 0.69 seconds
Started Jun 27 06:19:39 PM PDT 24
Finished Jun 27 06:19:43 PM PDT 24
Peak memory 203796 kb
Host smart-234bffff-2edb-415c-88a3-7919d9bc755e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471848769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2471848769
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.497334957
Short name T1119
Test name
Test status
Simulation time 52367647 ps
CPU time 0.8 seconds
Started Jun 27 06:19:35 PM PDT 24
Finished Jun 27 06:19:40 PM PDT 24
Peak memory 204112 kb
Host smart-9de5cccb-1b2a-4343-8d34-a6734fcb0c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497334957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.497334957
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4060481025
Short name T1055
Test name
Test status
Simulation time 39231988 ps
CPU time 0.78 seconds
Started Jun 27 06:19:34 PM PDT 24
Finished Jun 27 06:19:38 PM PDT 24
Peak memory 204168 kb
Host smart-86b46e88-539e-40e3-8de7-d7c84440f7ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060481025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
4060481025
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2547105579
Short name T1093
Test name
Test status
Simulation time 66925058 ps
CPU time 0.74 seconds
Started Jun 27 06:19:45 PM PDT 24
Finished Jun 27 06:19:51 PM PDT 24
Peak memory 204184 kb
Host smart-54088bb3-c3e0-40ba-b9fb-b38964ddd5fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547105579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2547105579
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.490549645
Short name T1030
Test name
Test status
Simulation time 26049316 ps
CPU time 0.76 seconds
Started Jun 27 06:19:44 PM PDT 24
Finished Jun 27 06:19:50 PM PDT 24
Peak memory 203780 kb
Host smart-b2061c45-7e49-46a5-a7f1-b5e41761eafd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490549645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.490549645
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2811429693
Short name T1017
Test name
Test status
Simulation time 20164756 ps
CPU time 0.66 seconds
Started Jun 27 06:19:39 PM PDT 24
Finished Jun 27 06:19:45 PM PDT 24
Peak memory 203864 kb
Host smart-1649357c-d897-4de6-a58f-73782bdddb2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811429693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2811429693
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.760606278
Short name T1013
Test name
Test status
Simulation time 101108211 ps
CPU time 0.74 seconds
Started Jun 27 06:19:40 PM PDT 24
Finished Jun 27 06:19:46 PM PDT 24
Peak memory 203864 kb
Host smart-0f37eb9f-1902-4c6a-a99d-5da4f6b1534d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760606278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.760606278
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4184412297
Short name T1060
Test name
Test status
Simulation time 10915332 ps
CPU time 0.78 seconds
Started Jun 27 06:19:37 PM PDT 24
Finished Jun 27 06:19:41 PM PDT 24
Peak memory 203856 kb
Host smart-7163c309-13b9-4b14-81c7-fab53b5217e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184412297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4184412297
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2467000096
Short name T1076
Test name
Test status
Simulation time 24510934 ps
CPU time 0.72 seconds
Started Jun 27 06:19:38 PM PDT 24
Finished Jun 27 06:19:42 PM PDT 24
Peak memory 204144 kb
Host smart-d3cbcfb2-517b-4eb0-ae51-85fed6d54196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467000096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2467000096
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.968553014
Short name T1087
Test name
Test status
Simulation time 14666622 ps
CPU time 0.73 seconds
Started Jun 27 06:19:43 PM PDT 24
Finished Jun 27 06:19:49 PM PDT 24
Peak memory 203788 kb
Host smart-bf8a55a9-d4ee-4302-8be5-42bbfbc679e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968553014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.968553014
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3579748903
Short name T127
Test name
Test status
Simulation time 353787946 ps
CPU time 22.54 seconds
Started Jun 27 06:19:10 PM PDT 24
Finished Jun 27 06:19:38 PM PDT 24
Peak memory 215292 kb
Host smart-ba4f35dd-58d3-4928-bb18-8a9bc127cb4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579748903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3579748903
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2921496056
Short name T125
Test name
Test status
Simulation time 5893045149 ps
CPU time 38.81 seconds
Started Jun 27 06:19:16 PM PDT 24
Finished Jun 27 06:19:59 PM PDT 24
Peak memory 207100 kb
Host smart-378ad0e2-2c67-465d-a313-bc638c8fbb2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921496056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2921496056
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.339068173
Short name T1116
Test name
Test status
Simulation time 30019644 ps
CPU time 0.97 seconds
Started Jun 27 06:19:29 PM PDT 24
Finished Jun 27 06:19:33 PM PDT 24
Peak memory 206916 kb
Host smart-4d7c5890-cc13-430a-8b78-da105793d4c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339068173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.339068173
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1312753679
Short name T1064
Test name
Test status
Simulation time 79058772 ps
CPU time 1.65 seconds
Started Jun 27 06:19:20 PM PDT 24
Finished Jun 27 06:19:26 PM PDT 24
Peak memory 216572 kb
Host smart-8e61452a-aa82-4dfd-8933-7cf385c7201b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312753679 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1312753679
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1845163041
Short name T149
Test name
Test status
Simulation time 781240815 ps
CPU time 2.13 seconds
Started Jun 27 06:19:12 PM PDT 24
Finished Jun 27 06:19:18 PM PDT 24
Peak memory 215396 kb
Host smart-beca5334-0364-4b9f-b249-cca945f9cdfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845163041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
845163041
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3576415076
Short name T1081
Test name
Test status
Simulation time 36625561 ps
CPU time 0.74 seconds
Started Jun 27 06:19:12 PM PDT 24
Finished Jun 27 06:19:17 PM PDT 24
Peak memory 204168 kb
Host smart-2f01ea59-b0b7-4bf9-a977-b6a457588497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576415076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
576415076
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1469753233
Short name T1068
Test name
Test status
Simulation time 144673532 ps
CPU time 2.22 seconds
Started Jun 27 06:19:06 PM PDT 24
Finished Jun 27 06:19:14 PM PDT 24
Peak memory 215404 kb
Host smart-813a7f68-a628-498d-89af-64dfbf8e920c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469753233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1469753233
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1908898662
Short name T1034
Test name
Test status
Simulation time 63944619 ps
CPU time 0.64 seconds
Started Jun 27 06:19:12 PM PDT 24
Finished Jun 27 06:19:17 PM PDT 24
Peak memory 203776 kb
Host smart-077fbc53-3f57-4665-ad7d-69d4a55ea150
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908898662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1908898662
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4125646061
Short name T1037
Test name
Test status
Simulation time 2066337180 ps
CPU time 4.1 seconds
Started Jun 27 06:19:03 PM PDT 24
Finished Jun 27 06:19:14 PM PDT 24
Peak memory 215404 kb
Host smart-4d2bc13b-c337-4842-b87c-6e324eefdac8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125646061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.4125646061
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2523247420
Short name T1052
Test name
Test status
Simulation time 172814509 ps
CPU time 4.7 seconds
Started Jun 27 06:19:09 PM PDT 24
Finished Jun 27 06:19:19 PM PDT 24
Peak memory 215544 kb
Host smart-4c081701-574b-4c07-9c2f-186272a8b207
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523247420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
523247420
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2110109175
Short name T1108
Test name
Test status
Simulation time 456006344 ps
CPU time 6.65 seconds
Started Jun 27 06:19:12 PM PDT 24
Finished Jun 27 06:19:23 PM PDT 24
Peak memory 215388 kb
Host smart-90c5bf95-aaa6-4bad-be62-d64bde15fa2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110109175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2110109175
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3277630425
Short name T1072
Test name
Test status
Simulation time 14767827 ps
CPU time 0.76 seconds
Started Jun 27 06:19:31 PM PDT 24
Finished Jun 27 06:19:36 PM PDT 24
Peak memory 203872 kb
Host smart-b54ba52c-5878-40a7-8436-d1ac7e22da75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277630425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3277630425
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.285776837
Short name T1050
Test name
Test status
Simulation time 12041479 ps
CPU time 0.78 seconds
Started Jun 27 06:19:44 PM PDT 24
Finished Jun 27 06:19:50 PM PDT 24
Peak memory 203836 kb
Host smart-4008a626-7bb1-4291-a822-ee50d036d35e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285776837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.285776837
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3271940066
Short name T1023
Test name
Test status
Simulation time 14352847 ps
CPU time 0.73 seconds
Started Jun 27 06:19:40 PM PDT 24
Finished Jun 27 06:19:46 PM PDT 24
Peak memory 203864 kb
Host smart-8c71b1e8-a459-4757-9095-10be4317230d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271940066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3271940066
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3202266563
Short name T1018
Test name
Test status
Simulation time 44396620 ps
CPU time 0.71 seconds
Started Jun 27 06:19:41 PM PDT 24
Finished Jun 27 06:19:47 PM PDT 24
Peak memory 203772 kb
Host smart-6f7cb860-3102-4df7-8704-eec3badd8de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202266563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3202266563
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2017551855
Short name T1112
Test name
Test status
Simulation time 30196884 ps
CPU time 0.77 seconds
Started Jun 27 06:19:39 PM PDT 24
Finished Jun 27 06:19:44 PM PDT 24
Peak memory 204136 kb
Host smart-96ff4958-9017-4773-a068-02f61b65b366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017551855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2017551855
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1429278255
Short name T1016
Test name
Test status
Simulation time 17975954 ps
CPU time 0.71 seconds
Started Jun 27 06:19:40 PM PDT 24
Finished Jun 27 06:19:45 PM PDT 24
Peak memory 203844 kb
Host smart-1dcc75c0-d42c-4a11-af73-85f78b0a4768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429278255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1429278255
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2229518334
Short name T1038
Test name
Test status
Simulation time 51125551 ps
CPU time 0.73 seconds
Started Jun 27 06:19:48 PM PDT 24
Finished Jun 27 06:19:53 PM PDT 24
Peak memory 203868 kb
Host smart-5862b0e6-5787-4451-b229-d27c3c6431f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229518334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2229518334
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3051172909
Short name T1032
Test name
Test status
Simulation time 45361368 ps
CPU time 0.78 seconds
Started Jun 27 06:19:41 PM PDT 24
Finished Jun 27 06:19:47 PM PDT 24
Peak memory 204144 kb
Host smart-006c8643-c228-4723-901f-fb6fa82cb03d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051172909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3051172909
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.992983173
Short name T1036
Test name
Test status
Simulation time 22441443 ps
CPU time 0.66 seconds
Started Jun 27 06:19:43 PM PDT 24
Finished Jun 27 06:19:49 PM PDT 24
Peak memory 204136 kb
Host smart-1387f192-cb03-4399-94a3-9242cd01b026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992983173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.992983173
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2576623422
Short name T1012
Test name
Test status
Simulation time 51313749 ps
CPU time 0.77 seconds
Started Jun 27 06:19:33 PM PDT 24
Finished Jun 27 06:19:38 PM PDT 24
Peak memory 203812 kb
Host smart-7cf1e28e-964d-4f53-9d25-e6e39e539b3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576623422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2576623422
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1717840687
Short name T1114
Test name
Test status
Simulation time 56865386 ps
CPU time 3.63 seconds
Started Jun 27 06:19:17 PM PDT 24
Finished Jun 27 06:19:25 PM PDT 24
Peak memory 217132 kb
Host smart-490abb1f-59db-4592-8798-10a298e131d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717840687 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1717840687
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.863824779
Short name T138
Test name
Test status
Simulation time 31904196 ps
CPU time 1.92 seconds
Started Jun 27 06:19:29 PM PDT 24
Finished Jun 27 06:19:33 PM PDT 24
Peak memory 215348 kb
Host smart-258979b1-f069-4829-bc27-2ec514b728c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863824779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.863824779
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.613353578
Short name T1015
Test name
Test status
Simulation time 11105201 ps
CPU time 0.73 seconds
Started Jun 27 06:19:19 PM PDT 24
Finished Jun 27 06:19:23 PM PDT 24
Peak memory 203860 kb
Host smart-d0d59e1c-19c5-4045-ab86-bc5144b16e26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613353578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.613353578
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3358481606
Short name T1086
Test name
Test status
Simulation time 57444426 ps
CPU time 3.81 seconds
Started Jun 27 06:19:27 PM PDT 24
Finished Jun 27 06:19:34 PM PDT 24
Peak memory 215336 kb
Host smart-51e16b18-d853-49e9-a9eb-48a31271c56b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358481606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3358481606
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1402452837
Short name T98
Test name
Test status
Simulation time 441397613 ps
CPU time 6.72 seconds
Started Jun 27 06:19:32 PM PDT 24
Finished Jun 27 06:19:43 PM PDT 24
Peak memory 215444 kb
Host smart-184ac256-91c7-4e98-b042-ddf5850efe42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402452837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1402452837
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4150462271
Short name T1041
Test name
Test status
Simulation time 89531293 ps
CPU time 2.53 seconds
Started Jun 27 06:19:20 PM PDT 24
Finished Jun 27 06:19:26 PM PDT 24
Peak memory 217024 kb
Host smart-5ab8f1b0-5cb3-47dc-9049-6189a156cd06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150462271 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4150462271
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2339854227
Short name T123
Test name
Test status
Simulation time 660386025 ps
CPU time 1.97 seconds
Started Jun 27 06:19:11 PM PDT 24
Finished Jun 27 06:19:17 PM PDT 24
Peak memory 215288 kb
Host smart-04ac6de6-9195-4845-8967-00c95b1ddd13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339854227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
339854227
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3417686173
Short name T1059
Test name
Test status
Simulation time 19746831 ps
CPU time 0.68 seconds
Started Jun 27 06:19:16 PM PDT 24
Finished Jun 27 06:19:20 PM PDT 24
Peak memory 203792 kb
Host smart-f361f820-2a52-4662-b142-9c981625d010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417686173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
417686173
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3707495511
Short name T148
Test name
Test status
Simulation time 895961026 ps
CPU time 3.94 seconds
Started Jun 27 06:19:13 PM PDT 24
Finished Jun 27 06:19:20 PM PDT 24
Peak memory 215300 kb
Host smart-dfaf50ef-d125-4d88-85e8-6f10955840f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707495511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3707495511
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3349413741
Short name T1044
Test name
Test status
Simulation time 55178287 ps
CPU time 3.35 seconds
Started Jun 27 06:19:26 PM PDT 24
Finished Jun 27 06:19:33 PM PDT 24
Peak memory 215624 kb
Host smart-d4573409-c7d0-4d1a-a321-f28895775503
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349413741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
349413741
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4202611658
Short name T1111
Test name
Test status
Simulation time 361353761 ps
CPU time 8.23 seconds
Started Jun 27 06:19:17 PM PDT 24
Finished Jun 27 06:19:30 PM PDT 24
Peak memory 215392 kb
Host smart-e006b348-f3af-4797-9519-104a077f2bfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202611658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.4202611658
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1833787529
Short name T112
Test name
Test status
Simulation time 129453869 ps
CPU time 3.56 seconds
Started Jun 27 06:19:40 PM PDT 24
Finished Jun 27 06:19:49 PM PDT 24
Peak memory 217428 kb
Host smart-6eebafe0-0635-4e0a-9d40-e4e5d53cdff2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833787529 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1833787529
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1045484891
Short name T1022
Test name
Test status
Simulation time 160054169 ps
CPU time 1.81 seconds
Started Jun 27 06:19:11 PM PDT 24
Finished Jun 27 06:19:17 PM PDT 24
Peak memory 215416 kb
Host smart-607980da-3103-41f3-9fbb-580428853f88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045484891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
045484891
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3822094647
Short name T1130
Test name
Test status
Simulation time 18199362 ps
CPU time 0.71 seconds
Started Jun 27 06:19:17 PM PDT 24
Finished Jun 27 06:19:22 PM PDT 24
Peak memory 203824 kb
Host smart-30f1dd2e-3a43-4532-8a4d-c0eb7e7a8283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822094647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
822094647
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.697105751
Short name T139
Test name
Test status
Simulation time 122753180 ps
CPU time 1.83 seconds
Started Jun 27 06:19:34 PM PDT 24
Finished Jun 27 06:19:40 PM PDT 24
Peak memory 215340 kb
Host smart-a803246f-9307-4a66-a2f6-536add599cf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697105751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.697105751
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3249070847
Short name T1126
Test name
Test status
Simulation time 72850873 ps
CPU time 2.16 seconds
Started Jun 27 06:19:18 PM PDT 24
Finished Jun 27 06:19:24 PM PDT 24
Peak memory 215688 kb
Host smart-3191d82d-644a-4e27-889a-1f04eef5d90f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249070847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
249070847
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2470013099
Short name T99
Test name
Test status
Simulation time 1325148590 ps
CPU time 14.91 seconds
Started Jun 27 06:19:16 PM PDT 24
Finished Jun 27 06:19:34 PM PDT 24
Peak memory 215580 kb
Host smart-fb87059b-dd00-4a74-9aca-827de4b47b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470013099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2470013099
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.309921821
Short name T114
Test name
Test status
Simulation time 165727652 ps
CPU time 2.69 seconds
Started Jun 27 06:19:20 PM PDT 24
Finished Jun 27 06:19:27 PM PDT 24
Peak memory 218260 kb
Host smart-743b4867-9297-4ace-95f3-7c15ecc4eeab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309921821 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.309921821
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1507045179
Short name T1104
Test name
Test status
Simulation time 51285802 ps
CPU time 1.45 seconds
Started Jun 27 06:19:18 PM PDT 24
Finished Jun 27 06:19:23 PM PDT 24
Peak memory 207224 kb
Host smart-79fda972-42b1-41fa-b660-836fda864c2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507045179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
507045179
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1491862319
Short name T1085
Test name
Test status
Simulation time 16418368 ps
CPU time 0.75 seconds
Started Jun 27 06:19:31 PM PDT 24
Finished Jun 27 06:19:36 PM PDT 24
Peak memory 203860 kb
Host smart-3f64e048-5a18-4dcb-bfb3-0e141f696e6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491862319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
491862319
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2670390564
Short name T137
Test name
Test status
Simulation time 1438219702 ps
CPU time 2.77 seconds
Started Jun 27 06:19:35 PM PDT 24
Finished Jun 27 06:19:42 PM PDT 24
Peak memory 215260 kb
Host smart-bf501849-d88d-4026-b81e-2b455eee1534
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670390564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2670390564
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3300065471
Short name T1070
Test name
Test status
Simulation time 354546534 ps
CPU time 1.64 seconds
Started Jun 27 06:19:21 PM PDT 24
Finished Jun 27 06:19:27 PM PDT 24
Peak memory 215708 kb
Host smart-4882e1ba-625d-4e1a-a252-d36b2582ee10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300065471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
300065471
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2535866672
Short name T176
Test name
Test status
Simulation time 108931033 ps
CPU time 7.32 seconds
Started Jun 27 06:19:16 PM PDT 24
Finished Jun 27 06:19:26 PM PDT 24
Peak memory 215340 kb
Host smart-f248ad74-08fc-4eee-9d58-ae4f4f2cc4e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535866672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2535866672
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3556207678
Short name T1129
Test name
Test status
Simulation time 129373115 ps
CPU time 2.5 seconds
Started Jun 27 06:19:17 PM PDT 24
Finished Jun 27 06:19:23 PM PDT 24
Peak memory 217068 kb
Host smart-b27e2c4d-c33f-4642-a1f0-352269a91042
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556207678 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3556207678
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.557615176
Short name T1080
Test name
Test status
Simulation time 34406323 ps
CPU time 2.23 seconds
Started Jun 27 06:19:16 PM PDT 24
Finished Jun 27 06:19:22 PM PDT 24
Peak memory 215328 kb
Host smart-8a10c9d6-32d5-4f19-ac82-6342794b01c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557615176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.557615176
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.322872354
Short name T1125
Test name
Test status
Simulation time 17479027 ps
CPU time 0.74 seconds
Started Jun 27 06:19:31 PM PDT 24
Finished Jun 27 06:19:35 PM PDT 24
Peak memory 203812 kb
Host smart-d850256c-7ec5-4af6-83b6-655460b06112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322872354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.322872354
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2168053830
Short name T141
Test name
Test status
Simulation time 212863240 ps
CPU time 3.05 seconds
Started Jun 27 06:19:34 PM PDT 24
Finished Jun 27 06:19:41 PM PDT 24
Peak memory 215328 kb
Host smart-a86311c6-b10f-4fac-bc47-1996b16d8a31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168053830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2168053830
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2027746246
Short name T104
Test name
Test status
Simulation time 62674714 ps
CPU time 1.93 seconds
Started Jun 27 06:19:13 PM PDT 24
Finished Jun 27 06:19:18 PM PDT 24
Peak memory 215652 kb
Host smart-a2b59957-d674-4769-862e-59c5a8dacba2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027746246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
027746246
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1283309155
Short name T171
Test name
Test status
Simulation time 2232379334 ps
CPU time 7.37 seconds
Started Jun 27 06:19:31 PM PDT 24
Finished Jun 27 06:19:42 PM PDT 24
Peak memory 215472 kb
Host smart-bc94983e-80da-4563-bae2-496eed54a201
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283309155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1283309155
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1851694678
Short name T596
Test name
Test status
Simulation time 20448622 ps
CPU time 0.75 seconds
Started Jun 27 06:23:08 PM PDT 24
Finished Jun 27 06:23:18 PM PDT 24
Peak memory 205968 kb
Host smart-9b6c5ef0-25aa-431f-81e0-47dcb3fd47bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851694678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
851694678
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1982371686
Short name T281
Test name
Test status
Simulation time 574087108 ps
CPU time 5.97 seconds
Started Jun 27 06:22:57 PM PDT 24
Finished Jun 27 06:23:12 PM PDT 24
Peak memory 225040 kb
Host smart-7055a0fe-bb8c-4ed1-ba94-9f7d4a813a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982371686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1982371686
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1173099234
Short name T455
Test name
Test status
Simulation time 52024268 ps
CPU time 0.75 seconds
Started Jun 27 06:22:57 PM PDT 24
Finished Jun 27 06:23:06 PM PDT 24
Peak memory 207388 kb
Host smart-69f9a632-03eb-45c3-ae43-3ffd4ea53395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173099234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1173099234
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2772270537
Short name T197
Test name
Test status
Simulation time 18020167485 ps
CPU time 132.66 seconds
Started Jun 27 06:22:50 PM PDT 24
Finished Jun 27 06:25:08 PM PDT 24
Peak memory 241500 kb
Host smart-e9683d2e-83d1-40e5-8d10-1e89937c3592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772270537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2772270537
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2529125542
Short name T62
Test name
Test status
Simulation time 17275025505 ps
CPU time 90.9 seconds
Started Jun 27 06:22:51 PM PDT 24
Finished Jun 27 06:24:28 PM PDT 24
Peak memory 257720 kb
Host smart-bfa57693-87ac-4a7f-aa5a-676c3ebaeec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529125542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2529125542
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1121540989
Short name T312
Test name
Test status
Simulation time 2348636667 ps
CPU time 29.44 seconds
Started Jun 27 06:22:49 PM PDT 24
Finished Jun 27 06:23:23 PM PDT 24
Peak memory 234668 kb
Host smart-99fdda73-4c8e-45df-86bb-0b7c03158084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121540989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1121540989
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3183742718
Short name T876
Test name
Test status
Simulation time 160647917548 ps
CPU time 323.6 seconds
Started Jun 27 06:22:51 PM PDT 24
Finished Jun 27 06:28:20 PM PDT 24
Peak memory 257732 kb
Host smart-2b1bbd2a-f407-4dd7-8a0b-26290026b685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183742718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3183742718
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2755907416
Short name T671
Test name
Test status
Simulation time 52540808 ps
CPU time 2.67 seconds
Started Jun 27 06:22:51 PM PDT 24
Finished Jun 27 06:22:59 PM PDT 24
Peak memory 219428 kb
Host smart-7b83fa6e-3236-4022-8279-5fa9b7dec1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755907416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2755907416
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1122356446
Short name T736
Test name
Test status
Simulation time 2924359983 ps
CPU time 11.81 seconds
Started Jun 27 06:23:04 PM PDT 24
Finished Jun 27 06:23:24 PM PDT 24
Peak memory 233264 kb
Host smart-95a51866-72b6-4740-bdc2-0c8d33119d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122356446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1122356446
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.313126384
Short name T679
Test name
Test status
Simulation time 5924634740 ps
CPU time 8.09 seconds
Started Jun 27 06:22:59 PM PDT 24
Finished Jun 27 06:23:17 PM PDT 24
Peak memory 233312 kb
Host smart-841deac0-8b67-4c68-a542-1e094005d299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313126384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
313126384
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2383628148
Short name T491
Test name
Test status
Simulation time 590920965 ps
CPU time 6.77 seconds
Started Jun 27 06:22:56 PM PDT 24
Finished Jun 27 06:23:11 PM PDT 24
Peak memory 225008 kb
Host smart-a31318ce-6247-4192-8e18-ef42068086d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383628148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2383628148
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3144581559
Short name T921
Test name
Test status
Simulation time 10105955827 ps
CPU time 14.17 seconds
Started Jun 27 06:22:57 PM PDT 24
Finished Jun 27 06:23:19 PM PDT 24
Peak memory 219844 kb
Host smart-33bfbc53-f87c-4c6a-93a3-4c8233ab5f2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3144581559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3144581559
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.442387288
Short name T957
Test name
Test status
Simulation time 52799161 ps
CPU time 0.89 seconds
Started Jun 27 06:22:56 PM PDT 24
Finished Jun 27 06:23:05 PM PDT 24
Peak memory 207148 kb
Host smart-8847351b-a072-4473-ac12-3fee77297a90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442387288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.442387288
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.15505562
Short name T950
Test name
Test status
Simulation time 25008238199 ps
CPU time 27.71 seconds
Started Jun 27 06:23:04 PM PDT 24
Finished Jun 27 06:23:40 PM PDT 24
Peak memory 216888 kb
Host smart-8ea670ab-f8ca-45d7-8c8d-c8f8aad13991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15505562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.15505562
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1578567695
Short name T901
Test name
Test status
Simulation time 34923091 ps
CPU time 0.94 seconds
Started Jun 27 06:23:08 PM PDT 24
Finished Jun 27 06:23:18 PM PDT 24
Peak memory 206556 kb
Host smart-48766385-5614-4981-86d7-39b2ce8243bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578567695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1578567695
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.962891084
Short name T718
Test name
Test status
Simulation time 102205222 ps
CPU time 3.88 seconds
Started Jun 27 06:23:05 PM PDT 24
Finished Jun 27 06:23:18 PM PDT 24
Peak memory 216816 kb
Host smart-ec0eb879-8d32-42d7-9353-b790156678f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962891084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.962891084
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.628157361
Short name T332
Test name
Test status
Simulation time 129760578 ps
CPU time 1.03 seconds
Started Jun 27 06:23:08 PM PDT 24
Finished Jun 27 06:23:18 PM PDT 24
Peak memory 207484 kb
Host smart-2d344b30-97b2-412b-b8c8-3e7cecb5df75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628157361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.628157361
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.717674457
Short name T264
Test name
Test status
Simulation time 30824298262 ps
CPU time 22.66 seconds
Started Jun 27 06:22:56 PM PDT 24
Finished Jun 27 06:23:27 PM PDT 24
Peak memory 233252 kb
Host smart-8c4c7d90-5f41-4153-b91a-39802e3ae4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717674457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.717674457
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3484262219
Short name T533
Test name
Test status
Simulation time 48736350 ps
CPU time 0.73 seconds
Started Jun 27 06:23:01 PM PDT 24
Finished Jun 27 06:23:10 PM PDT 24
Peak memory 205348 kb
Host smart-1cf6fce0-e085-410f-9698-7c20daf36cd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484262219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
484262219
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2803510360
Short name T251
Test name
Test status
Simulation time 5353638770 ps
CPU time 27.43 seconds
Started Jun 27 06:23:03 PM PDT 24
Finished Jun 27 06:23:39 PM PDT 24
Peak memory 225060 kb
Host smart-53d1c233-3f57-4dbb-99bd-6200befad496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803510360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2803510360
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.60109819
Short name T724
Test name
Test status
Simulation time 16675455 ps
CPU time 0.77 seconds
Started Jun 27 06:23:01 PM PDT 24
Finished Jun 27 06:23:10 PM PDT 24
Peak memory 207352 kb
Host smart-f3c7d250-ad88-414d-bc53-4fb64410c789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60109819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.60109819
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2782110817
Short name T647
Test name
Test status
Simulation time 4449233900 ps
CPU time 78.88 seconds
Started Jun 27 06:23:23 PM PDT 24
Finished Jun 27 06:24:47 PM PDT 24
Peak memory 250484 kb
Host smart-78b7cdd7-61d9-40d4-aaba-00de903eff23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782110817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2782110817
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.708820725
Short name T433
Test name
Test status
Simulation time 940055892 ps
CPU time 5.87 seconds
Started Jun 27 06:23:01 PM PDT 24
Finished Jun 27 06:23:15 PM PDT 24
Peak memory 218100 kb
Host smart-632b9388-9fae-4d4c-b3a8-cfe411fe3de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708820725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
708820725
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.863357879
Short name T523
Test name
Test status
Simulation time 3579869491 ps
CPU time 11.78 seconds
Started Jun 27 06:23:17 PM PDT 24
Finished Jun 27 06:23:35 PM PDT 24
Peak memory 223312 kb
Host smart-78faafae-66fa-4954-99c0-6d7aeb6a1c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863357879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.863357879
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.710282162
Short name T288
Test name
Test status
Simulation time 8942114834 ps
CPU time 85.3 seconds
Started Jun 27 06:22:57 PM PDT 24
Finished Jun 27 06:24:30 PM PDT 24
Peak memory 254512 kb
Host smart-7a6fb225-f1a7-4fa7-9c72-8c47d8e1f3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710282162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
710282162
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.607663958
Short name T462
Test name
Test status
Simulation time 95798498 ps
CPU time 2.16 seconds
Started Jun 27 06:23:09 PM PDT 24
Finished Jun 27 06:23:20 PM PDT 24
Peak memory 225044 kb
Host smart-add26c3e-3bd9-43e2-84aa-a380f685ad6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607663958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.607663958
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3339504400
Short name T979
Test name
Test status
Simulation time 29815505 ps
CPU time 2.28 seconds
Started Jun 27 06:22:58 PM PDT 24
Finished Jun 27 06:23:10 PM PDT 24
Peak memory 232996 kb
Host smart-7b402847-49f0-43ba-8810-b5c59f0b4f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339504400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3339504400
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.934762357
Short name T998
Test name
Test status
Simulation time 1620485189 ps
CPU time 4.52 seconds
Started Jun 27 06:23:09 PM PDT 24
Finished Jun 27 06:23:22 PM PDT 24
Peak memory 233196 kb
Host smart-2f123757-01cb-4ee0-9837-01018075a0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934762357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
934762357
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3789591835
Short name T821
Test name
Test status
Simulation time 1634081762 ps
CPU time 11.2 seconds
Started Jun 27 06:23:08 PM PDT 24
Finished Jun 27 06:23:28 PM PDT 24
Peak memory 241124 kb
Host smart-cb80a3b9-31e2-43e6-889d-ec0f57b4fc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789591835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3789591835
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1297842234
Short name T516
Test name
Test status
Simulation time 239136450 ps
CPU time 3.97 seconds
Started Jun 27 06:22:59 PM PDT 24
Finished Jun 27 06:23:13 PM PDT 24
Peak memory 223520 kb
Host smart-c87e22a4-1225-49a6-b5de-6e33a4249b9b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1297842234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1297842234
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2683640472
Short name T72
Test name
Test status
Simulation time 124454127 ps
CPU time 1.07 seconds
Started Jun 27 06:23:08 PM PDT 24
Finished Jun 27 06:23:18 PM PDT 24
Peak memory 236372 kb
Host smart-f0aaa51e-5282-4085-b5f3-f85f43a7d4c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683640472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2683640472
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2169923528
Short name T381
Test name
Test status
Simulation time 48888823 ps
CPU time 0.9 seconds
Started Jun 27 06:23:03 PM PDT 24
Finished Jun 27 06:23:13 PM PDT 24
Peak memory 206496 kb
Host smart-ef771386-3c44-4b13-999f-d95786a21cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169923528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2169923528
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.954430462
Short name T546
Test name
Test status
Simulation time 696304100 ps
CPU time 4.39 seconds
Started Jun 27 06:23:01 PM PDT 24
Finished Jun 27 06:23:14 PM PDT 24
Peak memory 216780 kb
Host smart-987c141c-072d-4267-be74-97fdfacc0d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954430462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.954430462
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3931336836
Short name T416
Test name
Test status
Simulation time 2492451759 ps
CPU time 2.42 seconds
Started Jun 27 06:23:01 PM PDT 24
Finished Jun 27 06:23:12 PM PDT 24
Peak memory 208056 kb
Host smart-a492882a-459b-4622-91c0-f3192592351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931336836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3931336836
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2889013404
Short name T807
Test name
Test status
Simulation time 1662464556 ps
CPU time 1.34 seconds
Started Jun 27 06:23:02 PM PDT 24
Finished Jun 27 06:23:13 PM PDT 24
Peak memory 216828 kb
Host smart-78c99905-1862-473c-a88b-7e1a9e01eaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889013404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2889013404
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.891957904
Short name T451
Test name
Test status
Simulation time 25269909 ps
CPU time 0.74 seconds
Started Jun 27 06:22:58 PM PDT 24
Finished Jun 27 06:23:08 PM PDT 24
Peak memory 206476 kb
Host smart-d5818e30-7255-41d3-9e7c-a3864f6c68f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891957904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.891957904
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.820389874
Short name T794
Test name
Test status
Simulation time 1212437140 ps
CPU time 6.7 seconds
Started Jun 27 06:22:58 PM PDT 24
Finished Jun 27 06:23:14 PM PDT 24
Peak memory 235636 kb
Host smart-5ca9ef71-046c-4744-accd-83f6ef77d4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820389874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.820389874
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2813556111
Short name T943
Test name
Test status
Simulation time 50919257 ps
CPU time 0.73 seconds
Started Jun 27 06:23:48 PM PDT 24
Finished Jun 27 06:23:54 PM PDT 24
Peak memory 205928 kb
Host smart-920f4bfc-7109-437b-beeb-f16234b67979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813556111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2813556111
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.277033445
Short name T602
Test name
Test status
Simulation time 2638002174 ps
CPU time 4.92 seconds
Started Jun 27 06:23:31 PM PDT 24
Finished Jun 27 06:23:40 PM PDT 24
Peak memory 233288 kb
Host smart-8f9d98a7-582e-4a1b-8501-749be5dba453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277033445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.277033445
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3395516434
Short name T695
Test name
Test status
Simulation time 17187451 ps
CPU time 0.81 seconds
Started Jun 27 06:23:17 PM PDT 24
Finished Jun 27 06:23:25 PM PDT 24
Peak memory 207052 kb
Host smart-bd332fef-fb77-4595-af27-3b1b97c6e38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395516434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3395516434
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2461835358
Short name T515
Test name
Test status
Simulation time 5394175433 ps
CPU time 20.04 seconds
Started Jun 27 06:23:47 PM PDT 24
Finished Jun 27 06:24:11 PM PDT 24
Peak memory 241496 kb
Host smart-6335b8db-053a-4dcf-bd79-ac6be36ce6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461835358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2461835358
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.4107238672
Short name T889
Test name
Test status
Simulation time 87610846720 ps
CPU time 246.32 seconds
Started Jun 27 06:23:44 PM PDT 24
Finished Jun 27 06:27:54 PM PDT 24
Peak memory 267864 kb
Host smart-bdb1eab5-c770-4773-b003-1559fc7ec0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107238672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.4107238672
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3997780815
Short name T169
Test name
Test status
Simulation time 61671368559 ps
CPU time 136.57 seconds
Started Jun 27 06:23:36 PM PDT 24
Finished Jun 27 06:25:56 PM PDT 24
Peak memory 250164 kb
Host smart-0deecb83-188a-450c-9d6c-e9d6eff42338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997780815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3997780815
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1466419075
Short name T453
Test name
Test status
Simulation time 4691050722 ps
CPU time 19.59 seconds
Started Jun 27 06:23:30 PM PDT 24
Finished Jun 27 06:23:53 PM PDT 24
Peak memory 233284 kb
Host smart-4564981e-2155-4e66-921a-8e53e4f34099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466419075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1466419075
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.375452273
Short name T179
Test name
Test status
Simulation time 15231821823 ps
CPU time 32.06 seconds
Started Jun 27 06:23:47 PM PDT 24
Finished Jun 27 06:24:24 PM PDT 24
Peak memory 241552 kb
Host smart-d3567a91-7f64-459a-833e-bd31ee3a453e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375452273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.375452273
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.504860352
Short name T802
Test name
Test status
Simulation time 49798858 ps
CPU time 2.53 seconds
Started Jun 27 06:23:30 PM PDT 24
Finished Jun 27 06:23:36 PM PDT 24
Peak memory 233040 kb
Host smart-335bd33d-786d-40ce-9f80-53ba630b9254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504860352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.504860352
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4050973705
Short name T544
Test name
Test status
Simulation time 266496689 ps
CPU time 4.11 seconds
Started Jun 27 06:23:44 PM PDT 24
Finished Jun 27 06:23:53 PM PDT 24
Peak memory 233200 kb
Host smart-be26d1f0-9e73-486c-a72d-bfc19f4f122e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050973705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4050973705
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3304900869
Short name T473
Test name
Test status
Simulation time 1565203451 ps
CPU time 6.89 seconds
Started Jun 27 06:23:37 PM PDT 24
Finished Jun 27 06:23:47 PM PDT 24
Peak memory 225012 kb
Host smart-69c00e2e-330e-4ab9-bb61-182a513ac60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304900869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3304900869
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.791107545
Short name T648
Test name
Test status
Simulation time 2888356968 ps
CPU time 6.04 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:23:40 PM PDT 24
Peak memory 225152 kb
Host smart-35ec8b5f-e431-4d69-955b-e583339c0fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791107545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.791107545
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2107520917
Short name T963
Test name
Test status
Simulation time 12469299258 ps
CPU time 61.11 seconds
Started Jun 27 06:23:32 PM PDT 24
Finished Jun 27 06:24:38 PM PDT 24
Peak memory 241680 kb
Host smart-8324cff1-6430-4517-a66e-a60b189f61ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107520917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2107520917
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2369311419
Short name T454
Test name
Test status
Simulation time 1932902928 ps
CPU time 5.36 seconds
Started Jun 27 06:23:32 PM PDT 24
Finished Jun 27 06:23:41 PM PDT 24
Peak memory 216724 kb
Host smart-ea9e637d-8252-42d8-acb1-60ed54cd24dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369311419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2369311419
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.317485099
Short name T783
Test name
Test status
Simulation time 3770322405 ps
CPU time 6.17 seconds
Started Jun 27 06:23:45 PM PDT 24
Finished Jun 27 06:23:55 PM PDT 24
Peak memory 216920 kb
Host smart-77bd4428-a477-4eed-9e91-2a78a1d18147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317485099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.317485099
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2825527858
Short name T576
Test name
Test status
Simulation time 1592690743 ps
CPU time 2.95 seconds
Started Jun 27 06:23:41 PM PDT 24
Finished Jun 27 06:23:46 PM PDT 24
Peak memory 216824 kb
Host smart-0667696a-d5ab-4056-9d3a-19fc675dff07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825527858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2825527858
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2276500450
Short name T937
Test name
Test status
Simulation time 47657578 ps
CPU time 0.74 seconds
Started Jun 27 06:23:31 PM PDT 24
Finished Jun 27 06:23:36 PM PDT 24
Peak memory 206424 kb
Host smart-2fbfded7-b65d-4b3b-a32e-67715846145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276500450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2276500450
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1666876519
Short name T362
Test name
Test status
Simulation time 456256981 ps
CPU time 1.94 seconds
Started Jun 27 06:23:36 PM PDT 24
Finished Jun 27 06:23:41 PM PDT 24
Peak memory 224724 kb
Host smart-9bd45dc6-ef17-45b4-814f-489f8aefca8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666876519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1666876519
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2440548938
Short name T543
Test name
Test status
Simulation time 21934853 ps
CPU time 0.74 seconds
Started Jun 27 06:23:37 PM PDT 24
Finished Jun 27 06:23:41 PM PDT 24
Peak memory 205920 kb
Host smart-5cc16a5e-0b1d-46ed-8295-d1cb12f71547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440548938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2440548938
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.234696005
Short name T241
Test name
Test status
Simulation time 1913345817 ps
CPU time 9.18 seconds
Started Jun 27 06:23:44 PM PDT 24
Finished Jun 27 06:23:57 PM PDT 24
Peak memory 224976 kb
Host smart-86f3005b-c550-404a-a67f-6ac93d448c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234696005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.234696005
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1306531942
Short name T756
Test name
Test status
Simulation time 24584428 ps
CPU time 0.78 seconds
Started Jun 27 06:23:36 PM PDT 24
Finished Jun 27 06:23:40 PM PDT 24
Peak memory 207092 kb
Host smart-7601b281-ee98-4299-9c66-f8b88ad5f557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306531942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1306531942
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.292747413
Short name T696
Test name
Test status
Simulation time 13417238853 ps
CPU time 28.26 seconds
Started Jun 27 06:23:31 PM PDT 24
Finished Jun 27 06:24:03 PM PDT 24
Peak memory 240504 kb
Host smart-032ebc5a-8994-48e0-a5c3-4de0b67eb3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292747413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.292747413
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3722344454
Short name T935
Test name
Test status
Simulation time 2200268954 ps
CPU time 52.23 seconds
Started Jun 27 06:23:47 PM PDT 24
Finished Jun 27 06:24:44 PM PDT 24
Peak memory 255372 kb
Host smart-519ec2c9-79b6-46b9-9a19-614dc60aa851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722344454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3722344454
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2708431671
Short name T272
Test name
Test status
Simulation time 35223701423 ps
CPU time 348.76 seconds
Started Jun 27 06:23:34 PM PDT 24
Finished Jun 27 06:29:27 PM PDT 24
Peak memory 257996 kb
Host smart-cbcf2552-f428-424c-a076-95d9969e196f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708431671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2708431671
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3921476844
Short name T858
Test name
Test status
Simulation time 689318432 ps
CPU time 7.28 seconds
Started Jun 27 06:23:45 PM PDT 24
Finished Jun 27 06:23:57 PM PDT 24
Peak memory 224916 kb
Host smart-b9244cef-7896-42b2-b6fa-ef6ec83f5dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921476844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3921476844
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1876515183
Short name T847
Test name
Test status
Simulation time 66133313967 ps
CPU time 68.84 seconds
Started Jun 27 06:23:37 PM PDT 24
Finished Jun 27 06:24:49 PM PDT 24
Peak memory 233276 kb
Host smart-aec8a2b6-30df-48ef-822e-19c8c0482062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876515183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1876515183
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3584437203
Short name T161
Test name
Test status
Simulation time 60732629 ps
CPU time 2.62 seconds
Started Jun 27 06:23:45 PM PDT 24
Finished Jun 27 06:23:51 PM PDT 24
Peak memory 233168 kb
Host smart-17f0058a-3951-4192-aa3b-7c21a2d05cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584437203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3584437203
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.904179752
Short name T552
Test name
Test status
Simulation time 1559036954 ps
CPU time 2.97 seconds
Started Jun 27 06:23:43 PM PDT 24
Finished Jun 27 06:23:50 PM PDT 24
Peak memory 225164 kb
Host smart-28de9423-689c-45f8-ad10-fe4b04bf6338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904179752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.904179752
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3950588646
Short name T213
Test name
Test status
Simulation time 1801057536 ps
CPU time 2.8 seconds
Started Jun 27 06:23:43 PM PDT 24
Finished Jun 27 06:23:50 PM PDT 24
Peak memory 225008 kb
Host smart-2cb6ac31-50ce-436e-b9bb-2b72dd726ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950588646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3950588646
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3748857838
Short name T391
Test name
Test status
Simulation time 62966984 ps
CPU time 3.3 seconds
Started Jun 27 06:23:50 PM PDT 24
Finished Jun 27 06:23:59 PM PDT 24
Peak memory 223312 kb
Host smart-40fd9ed0-78aa-4b8d-bbe8-3367fd6d16ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3748857838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3748857838
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2672370647
Short name T76
Test name
Test status
Simulation time 814598458 ps
CPU time 8.55 seconds
Started Jun 27 06:23:45 PM PDT 24
Finished Jun 27 06:23:58 PM PDT 24
Peak memory 216752 kb
Host smart-70463049-bdde-4d15-ab0d-1c0e5ecb050e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672370647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2672370647
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4153073747
Short name T997
Test name
Test status
Simulation time 35794835729 ps
CPU time 20.43 seconds
Started Jun 27 06:23:40 PM PDT 24
Finished Jun 27 06:24:03 PM PDT 24
Peak memory 217112 kb
Host smart-091f16ab-3525-41da-8e3b-dd53e8aa7d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153073747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4153073747
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2227893885
Short name T924
Test name
Test status
Simulation time 82866908 ps
CPU time 1.6 seconds
Started Jun 27 06:23:35 PM PDT 24
Finished Jun 27 06:23:40 PM PDT 24
Peak memory 216780 kb
Host smart-98fe6d3e-d109-4a03-9df2-e844d6452d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227893885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2227893885
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2394341793
Short name T496
Test name
Test status
Simulation time 1554087205 ps
CPU time 1.05 seconds
Started Jun 27 06:23:43 PM PDT 24
Finished Jun 27 06:23:48 PM PDT 24
Peak memory 206408 kb
Host smart-e889e237-ed87-4083-9c23-b4bc4da6e695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394341793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2394341793
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.194361058
Short name T841
Test name
Test status
Simulation time 4560427342 ps
CPU time 8.55 seconds
Started Jun 27 06:23:45 PM PDT 24
Finished Jun 27 06:23:58 PM PDT 24
Peak memory 233244 kb
Host smart-ed2c6149-59dd-42c3-b1d7-a0b9a9013b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194361058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.194361058
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2862593829
Short name T828
Test name
Test status
Simulation time 50281814 ps
CPU time 0.7 seconds
Started Jun 27 06:23:41 PM PDT 24
Finished Jun 27 06:23:44 PM PDT 24
Peak memory 205944 kb
Host smart-dcbecb9a-6ddb-4612-8e9a-d51971ca7919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862593829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2862593829
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1887647923
Short name T877
Test name
Test status
Simulation time 26573074547 ps
CPU time 26.7 seconds
Started Jun 27 06:23:38 PM PDT 24
Finished Jun 27 06:24:08 PM PDT 24
Peak memory 225148 kb
Host smart-7640b480-0dcd-4071-b345-598493b31775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887647923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1887647923
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.143270671
Short name T690
Test name
Test status
Simulation time 24740988 ps
CPU time 0.78 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:23:59 PM PDT 24
Peak memory 206068 kb
Host smart-20016597-b106-4a96-bf46-ab0942fee876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143270671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.143270671
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.477972848
Short name T472
Test name
Test status
Simulation time 35456630980 ps
CPU time 251.28 seconds
Started Jun 27 06:23:33 PM PDT 24
Finished Jun 27 06:27:48 PM PDT 24
Peak memory 253656 kb
Host smart-65ec2cd5-3744-40dd-97da-e998fe885086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477972848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.477972848
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2228206446
Short name T35
Test name
Test status
Simulation time 43850670851 ps
CPU time 206.56 seconds
Started Jun 27 06:23:48 PM PDT 24
Finished Jun 27 06:27:20 PM PDT 24
Peak memory 249876 kb
Host smart-c64143c2-06b2-42a5-abd4-2f4cfabf467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228206446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2228206446
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3579057115
Short name T424
Test name
Test status
Simulation time 8881558729 ps
CPU time 51.13 seconds
Started Jun 27 06:23:38 PM PDT 24
Finished Jun 27 06:24:32 PM PDT 24
Peak memory 265520 kb
Host smart-3dd64e1c-b8ee-4f50-a4d5-0ad9c167096e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579057115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3579057115
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3724847483
Short name T888
Test name
Test status
Simulation time 506429333 ps
CPU time 6.43 seconds
Started Jun 27 06:23:49 PM PDT 24
Finished Jun 27 06:24:01 PM PDT 24
Peak memory 233244 kb
Host smart-b131c71e-512d-45fc-8774-de1fdc14bcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724847483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3724847483
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3246236855
Short name T273
Test name
Test status
Simulation time 47429386004 ps
CPU time 303.76 seconds
Started Jun 27 06:23:42 PM PDT 24
Finished Jun 27 06:28:49 PM PDT 24
Peak memory 240492 kb
Host smart-9ad0901b-846e-4036-aacc-ebe07cedc645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246236855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3246236855
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1953356589
Short name T559
Test name
Test status
Simulation time 573229202 ps
CPU time 3.7 seconds
Started Jun 27 06:23:42 PM PDT 24
Finished Jun 27 06:23:48 PM PDT 24
Peak memory 224928 kb
Host smart-84c935cf-47a7-4e2a-935e-cc61b33e12f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953356589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1953356589
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.819372764
Short name T867
Test name
Test status
Simulation time 1296407681 ps
CPU time 8.31 seconds
Started Jun 27 06:23:37 PM PDT 24
Finished Jun 27 06:23:49 PM PDT 24
Peak memory 233228 kb
Host smart-32486170-bd55-4b56-a967-2d1d90a5b43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819372764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.819372764
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.89792714
Short name T883
Test name
Test status
Simulation time 2732733206 ps
CPU time 4.57 seconds
Started Jun 27 06:23:36 PM PDT 24
Finished Jun 27 06:23:44 PM PDT 24
Peak memory 233344 kb
Host smart-858b1422-4f27-4eb7-99c4-4eefc1df34f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89792714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.89792714
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2143733897
Short name T594
Test name
Test status
Simulation time 222479582 ps
CPU time 2.82 seconds
Started Jun 27 06:23:35 PM PDT 24
Finished Jun 27 06:23:42 PM PDT 24
Peak memory 225072 kb
Host smart-e63484e8-1747-402b-acc5-3bcf0f71b370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143733897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2143733897
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3674566422
Short name T372
Test name
Test status
Simulation time 1253910883 ps
CPU time 4.01 seconds
Started Jun 27 06:23:34 PM PDT 24
Finished Jun 27 06:23:42 PM PDT 24
Peak memory 219556 kb
Host smart-660b18ae-08d7-4bce-9c35-b7801c0f7ceb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3674566422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3674566422
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1315186973
Short name T289
Test name
Test status
Simulation time 76450578770 ps
CPU time 243.8 seconds
Started Jun 27 06:23:37 PM PDT 24
Finished Jun 27 06:27:44 PM PDT 24
Peak memory 265112 kb
Host smart-94ea7d4a-6671-465e-8f35-9835cb2bcf70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315186973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1315186973
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3307255479
Short name T449
Test name
Test status
Simulation time 26668630 ps
CPU time 0.71 seconds
Started Jun 27 06:23:42 PM PDT 24
Finished Jun 27 06:23:46 PM PDT 24
Peak memory 206240 kb
Host smart-d3e313ee-983b-485d-a68b-9ecaf2fdbcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307255479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3307255479
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.851575300
Short name T574
Test name
Test status
Simulation time 522162758 ps
CPU time 4.19 seconds
Started Jun 27 06:23:37 PM PDT 24
Finished Jun 27 06:23:44 PM PDT 24
Peak memory 216728 kb
Host smart-e14004db-a947-4886-ab8a-bf3ff1b6bacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851575300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.851575300
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3536170416
Short name T32
Test name
Test status
Simulation time 16632776 ps
CPU time 0.77 seconds
Started Jun 27 06:23:45 PM PDT 24
Finished Jun 27 06:23:50 PM PDT 24
Peak memory 206432 kb
Host smart-897a123b-a0d9-4a47-8f4f-67f4d67ce933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536170416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3536170416
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1627409760
Short name T873
Test name
Test status
Simulation time 77851852 ps
CPU time 0.76 seconds
Started Jun 27 06:23:39 PM PDT 24
Finished Jun 27 06:23:43 PM PDT 24
Peak memory 206128 kb
Host smart-63ea0a01-b70f-4e62-945d-434ab44bc141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627409760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1627409760
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2773720397
Short name T539
Test name
Test status
Simulation time 127572775 ps
CPU time 2.63 seconds
Started Jun 27 06:23:32 PM PDT 24
Finished Jun 27 06:23:39 PM PDT 24
Peak memory 224736 kb
Host smart-8daeaa9b-70a5-4665-a91f-50ce0609bef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773720397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2773720397
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1440413979
Short name T823
Test name
Test status
Simulation time 12563932 ps
CPU time 0.71 seconds
Started Jun 27 06:23:38 PM PDT 24
Finished Jun 27 06:23:42 PM PDT 24
Peak memory 205968 kb
Host smart-0a62bdcc-0852-4342-819e-74f77f955604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440413979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1440413979
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1987429526
Short name T250
Test name
Test status
Simulation time 3310502475 ps
CPU time 11.23 seconds
Started Jun 27 06:23:35 PM PDT 24
Finished Jun 27 06:23:50 PM PDT 24
Peak memory 225072 kb
Host smart-098888bd-c775-4f15-8b87-d9a90e07d78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987429526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1987429526
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.88689299
Short name T531
Test name
Test status
Simulation time 119198134 ps
CPU time 0.83 seconds
Started Jun 27 06:23:30 PM PDT 24
Finished Jun 27 06:23:35 PM PDT 24
Peak memory 207292 kb
Host smart-eabb1982-723a-48ff-98ca-b78de9cd640e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88689299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.88689299
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.119085088
Short name T276
Test name
Test status
Simulation time 179621314768 ps
CPU time 287.63 seconds
Started Jun 27 06:23:42 PM PDT 24
Finished Jun 27 06:28:32 PM PDT 24
Peak memory 250720 kb
Host smart-125ba86b-b6bd-4c43-aa65-a86261fa056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119085088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.119085088
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1376526003
Short name T769
Test name
Test status
Simulation time 10923168906 ps
CPU time 49.65 seconds
Started Jun 27 06:23:38 PM PDT 24
Finished Jun 27 06:24:31 PM PDT 24
Peak memory 237600 kb
Host smart-03b7eaf2-ea01-4f44-9955-0abbe57cab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376526003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1376526003
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2987158593
Short name T22
Test name
Test status
Simulation time 5579774086 ps
CPU time 73.57 seconds
Started Jun 27 06:23:43 PM PDT 24
Finished Jun 27 06:24:59 PM PDT 24
Peak memory 250160 kb
Host smart-a914c655-9436-4bd5-b6c2-9f44bda88513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987158593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2987158593
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3139974643
Short name T369
Test name
Test status
Simulation time 2267052637 ps
CPU time 25.91 seconds
Started Jun 27 06:23:31 PM PDT 24
Finished Jun 27 06:24:01 PM PDT 24
Peak memory 241236 kb
Host smart-ffbc14ee-9747-45d8-ac6e-b6d4bfd86bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139974643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3139974643
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2255799226
Short name T282
Test name
Test status
Simulation time 3639795812 ps
CPU time 49.87 seconds
Started Jun 27 06:23:38 PM PDT 24
Finished Jun 27 06:24:31 PM PDT 24
Peak memory 249736 kb
Host smart-16c7034a-e232-47f8-bc1d-8ed019c6cf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255799226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2255799226
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3815430032
Short name T101
Test name
Test status
Simulation time 13586392666 ps
CPU time 10.72 seconds
Started Jun 27 06:23:39 PM PDT 24
Finished Jun 27 06:23:53 PM PDT 24
Peak memory 225108 kb
Host smart-9063f1c0-0e65-401f-83da-6c9485befac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815430032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3815430032
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3089401840
Short name T562
Test name
Test status
Simulation time 31928396150 ps
CPU time 99.24 seconds
Started Jun 27 06:23:31 PM PDT 24
Finished Jun 27 06:25:15 PM PDT 24
Peak memory 240648 kb
Host smart-7a7fc3bc-768e-4529-aae0-f3deb2babcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089401840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3089401840
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.540763443
Short name T271
Test name
Test status
Simulation time 1314606362 ps
CPU time 4.15 seconds
Started Jun 27 06:23:36 PM PDT 24
Finished Jun 27 06:23:44 PM PDT 24
Peak memory 233212 kb
Host smart-0a95ba75-64c1-419a-9672-8d89caba724f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540763443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.540763443
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3097959267
Short name T277
Test name
Test status
Simulation time 4302903441 ps
CPU time 13.54 seconds
Started Jun 27 06:23:42 PM PDT 24
Finished Jun 27 06:23:58 PM PDT 24
Peak memory 233312 kb
Host smart-a75e3b7c-9206-4585-b86d-55a823ce89f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097959267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3097959267
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.4088319621
Short name T993
Test name
Test status
Simulation time 388172253 ps
CPU time 4.64 seconds
Started Jun 27 06:23:38 PM PDT 24
Finished Jun 27 06:23:46 PM PDT 24
Peak memory 224584 kb
Host smart-340d6ecf-869f-4a11-a671-603be86263f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4088319621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.4088319621
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1100277648
Short name T894
Test name
Test status
Simulation time 176303736166 ps
CPU time 408.38 seconds
Started Jun 27 06:23:32 PM PDT 24
Finished Jun 27 06:30:25 PM PDT 24
Peak memory 250712 kb
Host smart-88a5aa62-8534-4113-9e51-b801455c184e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100277648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1100277648
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3556357140
Short name T793
Test name
Test status
Simulation time 40057133849 ps
CPU time 34.16 seconds
Started Jun 27 06:23:39 PM PDT 24
Finished Jun 27 06:24:16 PM PDT 24
Peak memory 216924 kb
Host smart-cfc33177-f423-4d85-8b01-039dd66d216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556357140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3556357140
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1368065490
Short name T778
Test name
Test status
Simulation time 300960404 ps
CPU time 3.05 seconds
Started Jun 27 06:23:34 PM PDT 24
Finished Jun 27 06:23:41 PM PDT 24
Peak memory 216840 kb
Host smart-2e97bbce-5706-42a1-bcb6-6e73d9cf11d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368065490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1368065490
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2915274206
Short name T608
Test name
Test status
Simulation time 367599088 ps
CPU time 6.28 seconds
Started Jun 27 06:23:33 PM PDT 24
Finished Jun 27 06:23:43 PM PDT 24
Peak memory 216756 kb
Host smart-e5c9fde9-3e85-4a41-9aab-0428f965c280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915274206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2915274206
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.731516022
Short name T392
Test name
Test status
Simulation time 41676422 ps
CPU time 0.88 seconds
Started Jun 27 06:23:44 PM PDT 24
Finished Jun 27 06:23:49 PM PDT 24
Peak memory 206476 kb
Host smart-5c5b6d33-05e1-41ea-bcab-563c4c8dcdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731516022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.731516022
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.4054204446
Short name T667
Test name
Test status
Simulation time 1214955514 ps
CPU time 7.58 seconds
Started Jun 27 06:23:44 PM PDT 24
Finished Jun 27 06:23:57 PM PDT 24
Peak memory 233128 kb
Host smart-5fb4c85d-48e4-44dc-9563-af0aab6a2f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054204446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4054204446
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.506885963
Short name T751
Test name
Test status
Simulation time 11614357 ps
CPU time 0.73 seconds
Started Jun 27 06:23:50 PM PDT 24
Finished Jun 27 06:23:56 PM PDT 24
Peak memory 206304 kb
Host smart-f9f2f2dd-fb69-4c6d-945a-e367cb3b98d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506885963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.506885963
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.4291109289
Short name T92
Test name
Test status
Simulation time 2013788801 ps
CPU time 18.34 seconds
Started Jun 27 06:23:48 PM PDT 24
Finished Jun 27 06:24:11 PM PDT 24
Peak memory 233124 kb
Host smart-9d78be3b-4118-499e-9fd9-09afa7b350d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291109289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4291109289
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3644350855
Short name T863
Test name
Test status
Simulation time 63322588 ps
CPU time 0.83 seconds
Started Jun 27 06:23:43 PM PDT 24
Finished Jun 27 06:23:47 PM PDT 24
Peak memory 207140 kb
Host smart-6b4dbe01-dfd9-42a6-96ed-e67499bb5ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644350855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3644350855
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1240810083
Short name T706
Test name
Test status
Simulation time 13235123560 ps
CPU time 50.96 seconds
Started Jun 27 06:23:45 PM PDT 24
Finished Jun 27 06:24:40 PM PDT 24
Peak memory 250612 kb
Host smart-4ebc1f8b-b5a1-4cf1-9d79-174e0f29fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240810083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1240810083
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4228290956
Short name T1000
Test name
Test status
Simulation time 9642076860 ps
CPU time 68.93 seconds
Started Jun 27 06:23:49 PM PDT 24
Finished Jun 27 06:25:03 PM PDT 24
Peak memory 253428 kb
Host smart-8fdcf0d2-13e7-46cb-bdc4-dac7defd343d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228290956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4228290956
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2310103468
Short name T824
Test name
Test status
Simulation time 10848679278 ps
CPU time 103.62 seconds
Started Jun 27 06:23:46 PM PDT 24
Finished Jun 27 06:25:35 PM PDT 24
Peak memory 249848 kb
Host smart-b9d033b9-01cc-43f1-9bc2-355dd28a3733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310103468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2310103468
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3209618842
Short name T373
Test name
Test status
Simulation time 4539427346 ps
CPU time 19.08 seconds
Started Jun 27 06:23:49 PM PDT 24
Finished Jun 27 06:24:13 PM PDT 24
Peak memory 241500 kb
Host smart-6d699536-9708-4a13-8dbd-5a39fd8b0fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209618842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3209618842
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.163470478
Short name T680
Test name
Test status
Simulation time 2343610290 ps
CPU time 40.77 seconds
Started Jun 27 06:23:47 PM PDT 24
Finished Jun 27 06:24:32 PM PDT 24
Peak memory 250612 kb
Host smart-62fc8c1c-c9bb-4a94-82dd-450d11589f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163470478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.163470478
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.326933851
Short name T930
Test name
Test status
Simulation time 5793459715 ps
CPU time 7.28 seconds
Started Jun 27 06:23:50 PM PDT 24
Finished Jun 27 06:24:03 PM PDT 24
Peak memory 224920 kb
Host smart-0183ce4d-2758-4810-9f8a-e30bba1732f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326933851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.326933851
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1560765889
Short name T609
Test name
Test status
Simulation time 895786382 ps
CPU time 15.28 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:24:14 PM PDT 24
Peak memory 240884 kb
Host smart-d8d791d6-568d-4029-a90e-9e077c384ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560765889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1560765889
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.556242686
Short name T240
Test name
Test status
Simulation time 2448871721 ps
CPU time 9.29 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:24:08 PM PDT 24
Peak memory 233292 kb
Host smart-baa386ba-00f0-4fc4-97f0-b1e822b23980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556242686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.556242686
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3964251639
Short name T545
Test name
Test status
Simulation time 2523361415 ps
CPU time 3.59 seconds
Started Jun 27 06:23:44 PM PDT 24
Finished Jun 27 06:23:53 PM PDT 24
Peak memory 225120 kb
Host smart-22d52b19-08e3-49c0-9ce4-842807874be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964251639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3964251639
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1309284819
Short name T5
Test name
Test status
Simulation time 736640618 ps
CPU time 4.17 seconds
Started Jun 27 06:23:54 PM PDT 24
Finished Jun 27 06:24:03 PM PDT 24
Peak memory 220940 kb
Host smart-bcebd2e7-32e5-4f89-861e-c46c360e210a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1309284819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1309284819
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.464142963
Short name T684
Test name
Test status
Simulation time 81180948 ps
CPU time 1.01 seconds
Started Jun 27 06:23:48 PM PDT 24
Finished Jun 27 06:23:54 PM PDT 24
Peak memory 207616 kb
Host smart-d1b9c23d-6c24-494a-8191-68bbb4262f39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464142963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.464142963
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3546260016
Short name T366
Test name
Test status
Simulation time 4899264466 ps
CPU time 8.25 seconds
Started Jun 27 06:23:45 PM PDT 24
Finished Jun 27 06:23:57 PM PDT 24
Peak memory 216972 kb
Host smart-2d632e69-76f4-456e-8f10-1e2199dea7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546260016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3546260016
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1346317180
Short name T837
Test name
Test status
Simulation time 13470483874 ps
CPU time 9.12 seconds
Started Jun 27 06:23:35 PM PDT 24
Finished Jun 27 06:23:48 PM PDT 24
Peak memory 216924 kb
Host smart-180715d0-f531-4b72-abac-483ca94732a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346317180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1346317180
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4252117167
Short name T436
Test name
Test status
Simulation time 284062580 ps
CPU time 2 seconds
Started Jun 27 06:23:36 PM PDT 24
Finished Jun 27 06:23:41 PM PDT 24
Peak memory 216740 kb
Host smart-86af238f-8624-48b7-9ec0-1d09be8780ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252117167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4252117167
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1951238613
Short name T91
Test name
Test status
Simulation time 59204160 ps
CPU time 0.9 seconds
Started Jun 27 06:23:40 PM PDT 24
Finished Jun 27 06:23:44 PM PDT 24
Peak memory 206780 kb
Host smart-114e8d22-9e1e-4e13-a11c-f53126bcb2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951238613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1951238613
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1125121840
Short name T959
Test name
Test status
Simulation time 22738980910 ps
CPU time 13.77 seconds
Started Jun 27 06:23:47 PM PDT 24
Finished Jun 27 06:24:05 PM PDT 24
Peak memory 249696 kb
Host smart-89cb1c13-cfd8-4afb-924c-4bb5a3d6ffd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125121840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1125121840
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3178193305
Short name T429
Test name
Test status
Simulation time 20921054 ps
CPU time 0.71 seconds
Started Jun 27 06:23:55 PM PDT 24
Finished Jun 27 06:24:01 PM PDT 24
Peak memory 205388 kb
Host smart-229003d9-208d-4851-ac04-14077098eab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178193305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3178193305
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3963136970
Short name T933
Test name
Test status
Simulation time 2280813113 ps
CPU time 10.7 seconds
Started Jun 27 06:23:48 PM PDT 24
Finished Jun 27 06:24:03 PM PDT 24
Peak memory 225328 kb
Host smart-3b482a0b-0a72-4a0c-bdf4-00d38912e358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963136970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3963136970
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3404597563
Short name T425
Test name
Test status
Simulation time 28529547 ps
CPU time 0.8 seconds
Started Jun 27 06:23:49 PM PDT 24
Finished Jun 27 06:23:55 PM PDT 24
Peak memory 207392 kb
Host smart-5d38925a-2608-4e65-9a85-ef3bb8184679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404597563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3404597563
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1793305945
Short name T290
Test name
Test status
Simulation time 34609480497 ps
CPU time 111.81 seconds
Started Jun 27 06:23:53 PM PDT 24
Finished Jun 27 06:25:51 PM PDT 24
Peak memory 271788 kb
Host smart-9451927d-10f0-4aaa-95c5-ad7d2ae6d556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793305945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1793305945
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.162938206
Short name T635
Test name
Test status
Simulation time 1917211051 ps
CPU time 49.77 seconds
Started Jun 27 06:23:54 PM PDT 24
Finished Jun 27 06:24:49 PM PDT 24
Peak memory 249764 kb
Host smart-e3b0e845-ddac-41aa-89ec-2092f2ffc8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162938206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.162938206
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2011034457
Short name T320
Test name
Test status
Simulation time 1062566668 ps
CPU time 13.59 seconds
Started Jun 27 06:23:45 PM PDT 24
Finished Jun 27 06:24:03 PM PDT 24
Peak memory 256160 kb
Host smart-f59d466e-9697-41cd-a0cc-a7da67c8648e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011034457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2011034457
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3896021561
Short name T48
Test name
Test status
Simulation time 11488553061 ps
CPU time 37.73 seconds
Started Jun 27 06:23:49 PM PDT 24
Finished Jun 27 06:24:31 PM PDT 24
Peak memory 249752 kb
Host smart-b924f01d-586f-4b3a-9674-374551d87482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896021561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3896021561
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.307997030
Short name T848
Test name
Test status
Simulation time 2385878315 ps
CPU time 5.29 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:24:04 PM PDT 24
Peak memory 225084 kb
Host smart-3d394909-cf97-4c05-9866-53ae05149424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307997030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.307997030
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3188715187
Short name T258
Test name
Test status
Simulation time 7407512485 ps
CPU time 73.28 seconds
Started Jun 27 06:23:50 PM PDT 24
Finished Jun 27 06:25:09 PM PDT 24
Peak memory 225148 kb
Host smart-1c321c6d-c464-4922-9ff4-b87269360936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188715187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3188715187
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.58529615
Short name T298
Test name
Test status
Simulation time 22699107141 ps
CPU time 15.27 seconds
Started Jun 27 06:23:49 PM PDT 24
Finished Jun 27 06:24:10 PM PDT 24
Peak memory 225032 kb
Host smart-1f3dc701-3f2e-4d8b-9245-7108464349f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58529615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.58529615
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.557645066
Short name T256
Test name
Test status
Simulation time 6759845339 ps
CPU time 12.5 seconds
Started Jun 27 06:23:51 PM PDT 24
Finished Jun 27 06:24:10 PM PDT 24
Peak memory 233360 kb
Host smart-933bf91d-74e1-4f4c-9fc9-5ddfa78c4de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557645066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.557645066
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.4225618062
Short name T687
Test name
Test status
Simulation time 355184866 ps
CPU time 3.73 seconds
Started Jun 27 06:23:47 PM PDT 24
Finished Jun 27 06:23:55 PM PDT 24
Peak memory 221048 kb
Host smart-86234c55-e4a7-4a89-89c3-9a3285905e41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4225618062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.4225618062
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2231065651
Short name T77
Test name
Test status
Simulation time 54476761849 ps
CPU time 342.87 seconds
Started Jun 27 06:23:51 PM PDT 24
Finished Jun 27 06:29:40 PM PDT 24
Peak memory 273908 kb
Host smart-adadc284-4bca-4729-afb5-6932de4e324f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231065651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2231065651
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3805160880
Short name T852
Test name
Test status
Simulation time 3805950017 ps
CPU time 3.7 seconds
Started Jun 27 06:23:48 PM PDT 24
Finished Jun 27 06:23:57 PM PDT 24
Peak memory 216920 kb
Host smart-5b0c4060-259a-4fef-98ea-91dc6e0ff48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805160880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3805160880
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2962383935
Short name T717
Test name
Test status
Simulation time 88657084 ps
CPU time 2.37 seconds
Started Jun 27 06:23:48 PM PDT 24
Finished Jun 27 06:23:54 PM PDT 24
Peak memory 217012 kb
Host smart-f3a16419-26b1-4065-a7ca-b412a97356b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962383935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2962383935
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2454913389
Short name T728
Test name
Test status
Simulation time 264903828 ps
CPU time 0.91 seconds
Started Jun 27 06:23:48 PM PDT 24
Finished Jun 27 06:23:54 PM PDT 24
Peak memory 206468 kb
Host smart-81ecf1f6-570d-4004-abb5-ad9a8386aeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454913389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2454913389
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1545764816
Short name T245
Test name
Test status
Simulation time 1497247694 ps
CPU time 6.24 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:24:05 PM PDT 24
Peak memory 225024 kb
Host smart-ba4ec4cd-8cbe-4ccb-86e5-4b3622ef775b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545764816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1545764816
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4243241866
Short name T638
Test name
Test status
Simulation time 82606655 ps
CPU time 2.47 seconds
Started Jun 27 06:23:50 PM PDT 24
Finished Jun 27 06:23:58 PM PDT 24
Peak memory 224756 kb
Host smart-cb227596-d921-43fb-81d2-2dffe404362c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243241866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4243241866
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.761353559
Short name T763
Test name
Test status
Simulation time 99521230 ps
CPU time 0.77 seconds
Started Jun 27 06:23:50 PM PDT 24
Finished Jun 27 06:23:57 PM PDT 24
Peak memory 206060 kb
Host smart-1d8c181d-0f90-4ca3-aea7-481601fe200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761353559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.761353559
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4239495635
Short name T280
Test name
Test status
Simulation time 30561993313 ps
CPU time 57.24 seconds
Started Jun 27 06:23:51 PM PDT 24
Finished Jun 27 06:24:55 PM PDT 24
Peak memory 236484 kb
Host smart-d7f1ff22-153f-4fc4-a775-f1002bd49187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239495635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4239495635
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.978381176
Short name T29
Test name
Test status
Simulation time 3726417293 ps
CPU time 43.68 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:24:42 PM PDT 24
Peak memory 241600 kb
Host smart-cb317b2b-4f7c-4742-b17e-fe45e4539048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978381176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.978381176
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3480506063
Short name T285
Test name
Test status
Simulation time 7884306056 ps
CPU time 126.19 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:26:05 PM PDT 24
Peak memory 265200 kb
Host smart-8edfbb5c-7e4a-4d22-ae03-634b7a9eeb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480506063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3480506063
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1719264212
Short name T920
Test name
Test status
Simulation time 835523660 ps
CPU time 5.56 seconds
Started Jun 27 06:23:53 PM PDT 24
Finished Jun 27 06:24:05 PM PDT 24
Peak memory 235328 kb
Host smart-73062ffe-48e8-43fc-b97f-a7d637cf70fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719264212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1719264212
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.746847733
Short name T914
Test name
Test status
Simulation time 18552932922 ps
CPU time 40.61 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:24:39 PM PDT 24
Peak memory 241448 kb
Host smart-2772c7b5-c55e-4c86-aefc-9ab30f5afd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746847733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.746847733
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.725486446
Short name T266
Test name
Test status
Simulation time 2223458482 ps
CPU time 20.8 seconds
Started Jun 27 06:23:51 PM PDT 24
Finished Jun 27 06:24:18 PM PDT 24
Peak memory 225080 kb
Host smart-428fb6a6-e18e-409f-9f13-a2a5fc8297b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725486446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.725486446
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.105459435
Short name T216
Test name
Test status
Simulation time 213039604 ps
CPU time 2.46 seconds
Started Jun 27 06:23:56 PM PDT 24
Finished Jun 27 06:24:04 PM PDT 24
Peak memory 224924 kb
Host smart-f7d3c8d4-f0e3-4cad-8752-cdc4e3e8d391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105459435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.105459435
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2828584976
Short name T308
Test name
Test status
Simulation time 7675986396 ps
CPU time 14.36 seconds
Started Jun 27 06:23:49 PM PDT 24
Finished Jun 27 06:24:09 PM PDT 24
Peak memory 237400 kb
Host smart-caaed50f-0dc6-4ee3-87dd-f660beb31a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828584976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2828584976
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.186627496
Short name T501
Test name
Test status
Simulation time 416059779 ps
CPU time 2.35 seconds
Started Jun 27 06:23:51 PM PDT 24
Finished Jun 27 06:23:59 PM PDT 24
Peak memory 233032 kb
Host smart-9bda1e9d-1cac-4d10-85d8-3163ff0267d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186627496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.186627496
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.125873085
Short name T354
Test name
Test status
Simulation time 123463216 ps
CPU time 3.5 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:24:01 PM PDT 24
Peak memory 219416 kb
Host smart-f0651661-4ffb-4a58-93e1-cefe4f326474
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=125873085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.125873085
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3359950569
Short name T1002
Test name
Test status
Simulation time 18874778196 ps
CPU time 77 seconds
Started Jun 27 06:23:54 PM PDT 24
Finished Jun 27 06:25:17 PM PDT 24
Peak memory 250996 kb
Host smart-eadc03e1-256e-4deb-b96f-d325d1514568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359950569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3359950569
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.150113905
Short name T388
Test name
Test status
Simulation time 2182053176 ps
CPU time 19.27 seconds
Started Jun 27 06:23:46 PM PDT 24
Finished Jun 27 06:24:10 PM PDT 24
Peak memory 216960 kb
Host smart-8666646e-f68a-4df5-b60c-13aa681f0607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150113905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.150113905
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3803678829
Short name T725
Test name
Test status
Simulation time 8474040237 ps
CPU time 14.05 seconds
Started Jun 27 06:23:49 PM PDT 24
Finished Jun 27 06:24:08 PM PDT 24
Peak memory 216932 kb
Host smart-97b89cb9-3312-4bff-a43f-27d374168ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803678829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3803678829
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.585092066
Short name T330
Test name
Test status
Simulation time 37203096 ps
CPU time 1.1 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:23:59 PM PDT 24
Peak memory 208044 kb
Host smart-6b9ad34a-a5b5-44c3-afa2-9e9fa7a46c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585092066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.585092066
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2124368116
Short name T685
Test name
Test status
Simulation time 83833182 ps
CPU time 0.8 seconds
Started Jun 27 06:23:55 PM PDT 24
Finished Jun 27 06:24:01 PM PDT 24
Peak memory 206472 kb
Host smart-537cf7ab-a8b6-4b5f-b7e8-74dc7412faa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124368116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2124368116
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2552961089
Short name T904
Test name
Test status
Simulation time 1265297311 ps
CPU time 9.04 seconds
Started Jun 27 06:23:56 PM PDT 24
Finished Jun 27 06:24:10 PM PDT 24
Peak memory 234148 kb
Host smart-943a905e-e4d1-4286-9ae9-84141fb2b3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552961089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2552961089
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3098881566
Short name T1005
Test name
Test status
Simulation time 44346072 ps
CPU time 0.7 seconds
Started Jun 27 06:23:57 PM PDT 24
Finished Jun 27 06:24:02 PM PDT 24
Peak memory 205380 kb
Host smart-731ff5ab-6215-4517-8608-ab086f9f89aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098881566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3098881566
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2701493761
Short name T910
Test name
Test status
Simulation time 283387156 ps
CPU time 5.42 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:24:04 PM PDT 24
Peak memory 233160 kb
Host smart-963c31ee-3797-4e1a-b298-93abd56cf649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701493761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2701493761
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.4160154336
Short name T26
Test name
Test status
Simulation time 81224737 ps
CPU time 0.74 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:23:59 PM PDT 24
Peak memory 206008 kb
Host smart-4bd7706e-7a40-4a49-9f5c-90ea70503161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160154336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4160154336
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.50416461
Short name T85
Test name
Test status
Simulation time 173158916706 ps
CPU time 110.56 seconds
Started Jun 27 06:23:51 PM PDT 24
Finished Jun 27 06:25:48 PM PDT 24
Peak memory 256468 kb
Host smart-1c30360c-88e0-4dfa-9059-85dc1dbf4172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50416461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.50416461
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.658281438
Short name T49
Test name
Test status
Simulation time 8032110256 ps
CPU time 70.23 seconds
Started Jun 27 06:23:51 PM PDT 24
Finished Jun 27 06:25:07 PM PDT 24
Peak memory 249836 kb
Host smart-83dd50d6-c976-410f-a549-adc77d3c53f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658281438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.658281438
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.647159323
Short name T535
Test name
Test status
Simulation time 1148844896 ps
CPU time 9.54 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:24:09 PM PDT 24
Peak memory 218348 kb
Host smart-35ea78fa-3fa9-4e67-9659-3f5418274469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647159323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.647159323
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3924581093
Short name T634
Test name
Test status
Simulation time 439876240 ps
CPU time 8.91 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:24:07 PM PDT 24
Peak memory 234288 kb
Host smart-3f7480fa-0161-428f-835e-a14f8d6c1711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924581093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3924581093
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2272808531
Short name T94
Test name
Test status
Simulation time 15096018728 ps
CPU time 52.96 seconds
Started Jun 27 06:23:48 PM PDT 24
Finished Jun 27 06:24:46 PM PDT 24
Peak memory 236000 kb
Host smart-8c03daa6-eef3-400f-9157-1dec286bf94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272808531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2272808531
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3797147915
Short name T955
Test name
Test status
Simulation time 7383271065 ps
CPU time 13.19 seconds
Started Jun 27 06:23:56 PM PDT 24
Finished Jun 27 06:24:15 PM PDT 24
Peak memory 225092 kb
Host smart-3118a077-eb6f-4c55-878c-0dfb3f71c338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797147915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3797147915
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1384282334
Short name T902
Test name
Test status
Simulation time 3621644307 ps
CPU time 37.73 seconds
Started Jun 27 06:23:48 PM PDT 24
Finished Jun 27 06:24:31 PM PDT 24
Peak memory 220600 kb
Host smart-596a5e09-affc-4ee3-b5c3-c25288326410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384282334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1384282334
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2157867526
Short name T588
Test name
Test status
Simulation time 2597612568 ps
CPU time 7.38 seconds
Started Jun 27 06:23:52 PM PDT 24
Finished Jun 27 06:24:06 PM PDT 24
Peak memory 233300 kb
Host smart-2e27d33a-9923-47ce-8567-5bff66b527b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157867526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2157867526
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2080837319
Short name T57
Test name
Test status
Simulation time 2437300489 ps
CPU time 9.08 seconds
Started Jun 27 06:23:50 PM PDT 24
Finished Jun 27 06:24:05 PM PDT 24
Peak memory 225140 kb
Host smart-a7de8128-2a21-4869-a701-2dd2c2f3bd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080837319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2080837319
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2556533531
Short name T80
Test name
Test status
Simulation time 1603459225 ps
CPU time 8.4 seconds
Started Jun 27 06:23:51 PM PDT 24
Finished Jun 27 06:24:06 PM PDT 24
Peak memory 222700 kb
Host smart-0d2da1b2-23d2-4094-8006-918295f77790
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2556533531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2556533531
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2884390109
Short name T158
Test name
Test status
Simulation time 19622689666 ps
CPU time 80.63 seconds
Started Jun 27 06:23:48 PM PDT 24
Finished Jun 27 06:25:13 PM PDT 24
Peak memory 252656 kb
Host smart-600b7632-b925-4c12-b17a-e5c228b65fa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884390109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2884390109
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.42398126
Short name T822
Test name
Test status
Simulation time 1132845049 ps
CPU time 6.2 seconds
Started Jun 27 06:23:54 PM PDT 24
Finished Jun 27 06:24:06 PM PDT 24
Peak memory 219620 kb
Host smart-a4d9cd78-fd9e-4765-828f-43f2cbc1381a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42398126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.42398126
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.999584083
Short name T378
Test name
Test status
Simulation time 1461531811 ps
CPU time 5.42 seconds
Started Jun 27 06:23:54 PM PDT 24
Finished Jun 27 06:24:05 PM PDT 24
Peak memory 216832 kb
Host smart-e54caa93-175d-4b61-9707-22040f635e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999584083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.999584083
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.247879507
Short name T860
Test name
Test status
Simulation time 78460680 ps
CPU time 0.87 seconds
Started Jun 27 06:23:47 PM PDT 24
Finished Jun 27 06:23:52 PM PDT 24
Peak memory 207044 kb
Host smart-c6598d28-be9e-4a79-8e02-f92b58b21ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247879507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.247879507
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3039094098
Short name T415
Test name
Test status
Simulation time 245069061 ps
CPU time 0.9 seconds
Started Jun 27 06:23:54 PM PDT 24
Finished Jun 27 06:24:01 PM PDT 24
Peak memory 206456 kb
Host smart-e186d49b-2142-4e4b-9aa0-4a79bafe60f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039094098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3039094098
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4255734297
Short name T663
Test name
Test status
Simulation time 2987232035 ps
CPU time 8.55 seconds
Started Jun 27 06:23:51 PM PDT 24
Finished Jun 27 06:24:06 PM PDT 24
Peak memory 225020 kb
Host smart-1b5a309c-cc7b-4e3c-9b95-e019dd7b05b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255734297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4255734297
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.98567719
Short name T484
Test name
Test status
Simulation time 18070444 ps
CPU time 0.69 seconds
Started Jun 27 06:24:08 PM PDT 24
Finished Jun 27 06:24:12 PM PDT 24
Peak memory 205872 kb
Host smart-e20d746b-7556-476e-86a3-5df4b26e2407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98567719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.98567719
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.794788810
Short name T500
Test name
Test status
Simulation time 71651120 ps
CPU time 2.8 seconds
Started Jun 27 06:24:10 PM PDT 24
Finished Jun 27 06:24:18 PM PDT 24
Peak memory 233200 kb
Host smart-c60603ec-d496-4e67-b06d-5d9702fb5871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794788810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.794788810
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2236679282
Short name T1008
Test name
Test status
Simulation time 52433112 ps
CPU time 0.75 seconds
Started Jun 27 06:23:49 PM PDT 24
Finished Jun 27 06:23:55 PM PDT 24
Peak memory 206388 kb
Host smart-33bc3a25-6009-47ca-a408-b0af3a968c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236679282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2236679282
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3107095135
Short name T723
Test name
Test status
Simulation time 111448382092 ps
CPU time 188.87 seconds
Started Jun 27 06:24:09 PM PDT 24
Finished Jun 27 06:27:21 PM PDT 24
Peak memory 266100 kb
Host smart-115ed275-932a-4da5-9028-4821fb8b02c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107095135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3107095135
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.274897865
Short name T267
Test name
Test status
Simulation time 16854436209 ps
CPU time 64.65 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:25:29 PM PDT 24
Peak memory 251432 kb
Host smart-db70062d-09f8-4784-bd06-846fef051a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274897865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.274897865
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3130769095
Short name T879
Test name
Test status
Simulation time 34095284474 ps
CPU time 144.92 seconds
Started Jun 27 06:24:11 PM PDT 24
Finished Jun 27 06:26:41 PM PDT 24
Peak memory 265804 kb
Host smart-0d4d41bc-8483-4a63-894e-7b9a1b0b118c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130769095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3130769095
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4097886945
Short name T314
Test name
Test status
Simulation time 6345164545 ps
CPU time 35.65 seconds
Started Jun 27 06:24:06 PM PDT 24
Finished Jun 27 06:24:44 PM PDT 24
Peak memory 233352 kb
Host smart-51727d03-0472-43d1-a4a2-54e3bba9f086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097886945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4097886945
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3247264295
Short name T607
Test name
Test status
Simulation time 3449956714 ps
CPU time 12.92 seconds
Started Jun 27 06:24:12 PM PDT 24
Finished Jun 27 06:24:31 PM PDT 24
Peak memory 224692 kb
Host smart-4f71d95f-b998-4bef-b0a0-ce2243a015a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247264295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3247264295
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3729896797
Short name T799
Test name
Test status
Simulation time 6739050284 ps
CPU time 15.7 seconds
Started Jun 27 06:23:54 PM PDT 24
Finished Jun 27 06:24:15 PM PDT 24
Peak memory 225056 kb
Host smart-c08f2328-8430-4aea-bc04-ad172df98090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729896797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3729896797
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.354586720
Short name T435
Test name
Test status
Simulation time 6907501417 ps
CPU time 35.15 seconds
Started Jun 27 06:23:50 PM PDT 24
Finished Jun 27 06:24:31 PM PDT 24
Peak memory 233284 kb
Host smart-04462517-d8df-4a70-b8b0-2de09d50afca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354586720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.354586720
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2082526692
Short name T215
Test name
Test status
Simulation time 27263336776 ps
CPU time 22.77 seconds
Started Jun 27 06:23:48 PM PDT 24
Finished Jun 27 06:24:14 PM PDT 24
Peak memory 225156 kb
Host smart-e8a638cc-5787-48f7-b9a8-f7a1145db3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082526692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2082526692
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1510008009
Short name T764
Test name
Test status
Simulation time 67582003 ps
CPU time 2.44 seconds
Started Jun 27 06:23:57 PM PDT 24
Finished Jun 27 06:24:04 PM PDT 24
Peak memory 233212 kb
Host smart-874026f4-0cbd-4591-aba6-088140e334fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510008009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1510008009
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2182672944
Short name T699
Test name
Test status
Simulation time 2087412151 ps
CPU time 7.04 seconds
Started Jun 27 06:24:05 PM PDT 24
Finished Jun 27 06:24:14 PM PDT 24
Peak memory 220540 kb
Host smart-08d38856-cc95-432b-a6fb-d6dcf4875dc0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2182672944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2182672944
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.4103005072
Short name T708
Test name
Test status
Simulation time 5703886449 ps
CPU time 9.42 seconds
Started Jun 27 06:23:55 PM PDT 24
Finished Jun 27 06:24:10 PM PDT 24
Peak memory 217140 kb
Host smart-307b1055-c6eb-4ec6-bbcc-73af7393f9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103005072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.4103005072
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2313813155
Short name T522
Test name
Test status
Simulation time 1787996681 ps
CPU time 3.31 seconds
Started Jun 27 06:23:58 PM PDT 24
Finished Jun 27 06:24:05 PM PDT 24
Peak memory 216772 kb
Host smart-303aae22-374d-4646-b635-bbdcf367359f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313813155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2313813155
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2648448507
Short name T760
Test name
Test status
Simulation time 73360378 ps
CPU time 2.07 seconds
Started Jun 27 06:23:55 PM PDT 24
Finished Jun 27 06:24:02 PM PDT 24
Peak memory 216836 kb
Host smart-8ea1fded-9988-4e1f-8739-c8d8fd185c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648448507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2648448507
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.47362866
Short name T511
Test name
Test status
Simulation time 145082275 ps
CPU time 0.81 seconds
Started Jun 27 06:23:56 PM PDT 24
Finished Jun 27 06:24:02 PM PDT 24
Peak memory 206472 kb
Host smart-44f1ae2c-af27-4edb-9cc2-aaf6fbf0cd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47362866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.47362866
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.615623858
Short name T978
Test name
Test status
Simulation time 108394678 ps
CPU time 2.48 seconds
Started Jun 27 06:24:04 PM PDT 24
Finished Jun 27 06:24:08 PM PDT 24
Peak memory 232980 kb
Host smart-3955a8a3-7305-4658-a79a-acda7cc91027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615623858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.615623858
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3059163300
Short name T874
Test name
Test status
Simulation time 11181511 ps
CPU time 0.69 seconds
Started Jun 27 06:24:10 PM PDT 24
Finished Jun 27 06:24:15 PM PDT 24
Peak memory 205984 kb
Host smart-bace521a-3273-4d55-ad93-a7411145649a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059163300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3059163300
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.377724998
Short name T988
Test name
Test status
Simulation time 81876008 ps
CPU time 2.82 seconds
Started Jun 27 06:24:10 PM PDT 24
Finished Jun 27 06:24:16 PM PDT 24
Peak memory 233248 kb
Host smart-12f73829-e105-4bb9-896c-254152c5f735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377724998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.377724998
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.899408115
Short name T439
Test name
Test status
Simulation time 23488161 ps
CPU time 0.82 seconds
Started Jun 27 06:24:04 PM PDT 24
Finished Jun 27 06:24:06 PM PDT 24
Peak memory 207108 kb
Host smart-278e7559-60af-468f-be29-7b8e916c390e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899408115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.899408115
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2997617909
Short name T218
Test name
Test status
Simulation time 5861935721 ps
CPU time 67.85 seconds
Started Jun 27 06:24:04 PM PDT 24
Finished Jun 27 06:25:13 PM PDT 24
Peak memory 253824 kb
Host smart-4d756e34-6416-41cd-9bb4-5ffe946c43af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997617909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2997617909
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2125564943
Short name T458
Test name
Test status
Simulation time 60713738863 ps
CPU time 153.72 seconds
Started Jun 27 06:24:11 PM PDT 24
Finished Jun 27 06:26:49 PM PDT 24
Peak memory 255104 kb
Host smart-ae3ae4c6-eb61-4e38-91bf-e83b198b3b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125564943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2125564943
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.6091916
Short name T734
Test name
Test status
Simulation time 220815857119 ps
CPU time 297.41 seconds
Started Jun 27 06:24:04 PM PDT 24
Finished Jun 27 06:29:03 PM PDT 24
Peak memory 252432 kb
Host smart-77af694e-eb4b-483c-8c33-6ca665dce7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6091916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.6091916
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2319845441
Short name T319
Test name
Test status
Simulation time 763236494 ps
CPU time 12.36 seconds
Started Jun 27 06:24:08 PM PDT 24
Finished Jun 27 06:24:23 PM PDT 24
Peak memory 233252 kb
Host smart-6bea48c4-839b-42fe-a8fa-75989c719c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319845441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2319845441
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2158856365
Short name T819
Test name
Test status
Simulation time 91342320393 ps
CPU time 195.1 seconds
Started Jun 27 06:24:08 PM PDT 24
Finished Jun 27 06:27:27 PM PDT 24
Peak memory 251740 kb
Host smart-2e0317f1-3810-47d7-9ab6-e510dc77e286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158856365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2158856365
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.257263468
Short name T931
Test name
Test status
Simulation time 533424446 ps
CPU time 9.27 seconds
Started Jun 27 06:24:08 PM PDT 24
Finished Jun 27 06:24:20 PM PDT 24
Peak memory 233188 kb
Host smart-e2785f64-fa2a-4e94-abb3-42aa4eea2c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257263468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.257263468
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3341270724
Short name T270
Test name
Test status
Simulation time 30705357356 ps
CPU time 17.62 seconds
Started Jun 27 06:24:08 PM PDT 24
Finished Jun 27 06:24:29 PM PDT 24
Peak memory 225072 kb
Host smart-f7b75fd5-c8ed-48ad-806b-d8e55d0e17f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341270724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3341270724
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2725183509
Short name T886
Test name
Test status
Simulation time 4211048453 ps
CPU time 12.59 seconds
Started Jun 27 06:24:03 PM PDT 24
Finished Jun 27 06:24:17 PM PDT 24
Peak memory 234372 kb
Host smart-ec333f22-4945-4d43-9c07-4baba7864d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725183509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2725183509
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1782481703
Short name T145
Test name
Test status
Simulation time 3759494284 ps
CPU time 7.89 seconds
Started Jun 27 06:24:10 PM PDT 24
Finished Jun 27 06:24:22 PM PDT 24
Peak memory 221484 kb
Host smart-57d50179-6d61-4340-b310-3c406d009915
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1782481703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1782481703
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3653451564
Short name T818
Test name
Test status
Simulation time 67381808599 ps
CPU time 37.53 seconds
Started Jun 27 06:24:08 PM PDT 24
Finished Jun 27 06:24:49 PM PDT 24
Peak memory 216892 kb
Host smart-bd5fce22-3fcb-45e4-9d76-03a1005855b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653451564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3653451564
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2041903574
Short name T487
Test name
Test status
Simulation time 2258975357 ps
CPU time 7.02 seconds
Started Jun 27 06:24:04 PM PDT 24
Finished Jun 27 06:24:13 PM PDT 24
Peak memory 216948 kb
Host smart-b9c8d4fb-cae3-4fd2-8c0b-1194001a8e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041903574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2041903574
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2499343876
Short name T31
Test name
Test status
Simulation time 33215635 ps
CPU time 0.77 seconds
Started Jun 27 06:24:09 PM PDT 24
Finished Jun 27 06:24:13 PM PDT 24
Peak memory 206512 kb
Host smart-393759a1-47e8-47fb-8e87-23de68b99e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499343876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2499343876
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1022474895
Short name T412
Test name
Test status
Simulation time 10866029 ps
CPU time 0.69 seconds
Started Jun 27 06:24:10 PM PDT 24
Finished Jun 27 06:24:16 PM PDT 24
Peak memory 206088 kb
Host smart-81015663-b902-45c5-a6f9-29df5e7ebda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022474895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1022474895
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2025113271
Short name T45
Test name
Test status
Simulation time 4206804060 ps
CPU time 14.49 seconds
Started Jun 27 06:24:09 PM PDT 24
Finished Jun 27 06:24:28 PM PDT 24
Peak memory 234264 kb
Host smart-1544d67f-04bb-4ef1-a153-c7994c4a633e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025113271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2025113271
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2882360284
Short name T64
Test name
Test status
Simulation time 94167756 ps
CPU time 0.72 seconds
Started Jun 27 06:23:13 PM PDT 24
Finished Jun 27 06:23:22 PM PDT 24
Peak memory 205956 kb
Host smart-d76d52ef-c046-4738-9146-bae198c402fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882360284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
882360284
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.73241784
Short name T907
Test name
Test status
Simulation time 113228068 ps
CPU time 2.61 seconds
Started Jun 27 06:23:12 PM PDT 24
Finished Jun 27 06:23:23 PM PDT 24
Peak memory 232988 kb
Host smart-732397e0-624c-421d-92a0-33e6e887f465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73241784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.73241784
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2243842176
Short name T488
Test name
Test status
Simulation time 24452890 ps
CPU time 0.87 seconds
Started Jun 27 06:22:56 PM PDT 24
Finished Jun 27 06:23:05 PM PDT 24
Peak memory 207084 kb
Host smart-96af36d5-6ce1-4063-bffb-58b6adc9f172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243842176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2243842176
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2149058734
Short name T965
Test name
Test status
Simulation time 17627292933 ps
CPU time 65.05 seconds
Started Jun 27 06:23:00 PM PDT 24
Finished Jun 27 06:24:15 PM PDT 24
Peak memory 257876 kb
Host smart-14bc3412-6a4f-46ae-9202-bd9b710ee21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149058734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2149058734
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2242953676
Short name T881
Test name
Test status
Simulation time 3417645517 ps
CPU time 15.15 seconds
Started Jun 27 06:23:04 PM PDT 24
Finished Jun 27 06:23:28 PM PDT 24
Peak memory 218356 kb
Host smart-b2dd5855-6ff8-4c5e-93f8-1d4b515b85f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242953676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2242953676
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3091807620
Short name T309
Test name
Test status
Simulation time 70871324655 ps
CPU time 362.8 seconds
Started Jun 27 06:23:05 PM PDT 24
Finished Jun 27 06:29:17 PM PDT 24
Peak memory 264080 kb
Host smart-60197650-6afb-42cd-a5a0-3bbfa6a5dc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091807620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3091807620
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3448981068
Short name T622
Test name
Test status
Simulation time 2507813625 ps
CPU time 38.93 seconds
Started Jun 27 06:23:13 PM PDT 24
Finished Jun 27 06:24:00 PM PDT 24
Peak memory 249708 kb
Host smart-af0a546c-2352-4b41-9c5b-9566737e0cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448981068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3448981068
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.159181580
Short name T987
Test name
Test status
Simulation time 7716550657 ps
CPU time 81.21 seconds
Started Jun 27 06:23:24 PM PDT 24
Finished Jun 27 06:24:50 PM PDT 24
Peak memory 257896 kb
Host smart-2c4c4a07-2ea0-4b4a-b3c0-c78a01a9cbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159181580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
159181580
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1500446839
Short name T560
Test name
Test status
Simulation time 315274816 ps
CPU time 3.21 seconds
Started Jun 27 06:23:20 PM PDT 24
Finished Jun 27 06:23:28 PM PDT 24
Peak memory 225004 kb
Host smart-861aef82-ce74-44a5-b08a-dced9f2ed47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500446839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1500446839
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1242803005
Short name T229
Test name
Test status
Simulation time 1746076783 ps
CPU time 9.8 seconds
Started Jun 27 06:23:10 PM PDT 24
Finished Jun 27 06:23:28 PM PDT 24
Peak memory 224968 kb
Host smart-b9d51e4d-c39b-46b4-ab3e-37cb5eefa659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242803005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1242803005
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1973968893
Short name T387
Test name
Test status
Simulation time 104828589 ps
CPU time 2.26 seconds
Started Jun 27 06:23:09 PM PDT 24
Finished Jun 27 06:23:20 PM PDT 24
Peak memory 224528 kb
Host smart-ad5e0ec5-84d0-4aab-ac0b-1d19ed242d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973968893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1973968893
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.690081373
Short name T780
Test name
Test status
Simulation time 17817172557 ps
CPU time 28.05 seconds
Started Jun 27 06:22:56 PM PDT 24
Finished Jun 27 06:23:33 PM PDT 24
Peak memory 233276 kb
Host smart-07630f2d-9deb-4b92-b357-ff87f2cd23a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690081373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.690081373
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3920222348
Short name T915
Test name
Test status
Simulation time 957990954 ps
CPU time 5.39 seconds
Started Jun 27 06:23:00 PM PDT 24
Finished Jun 27 06:23:15 PM PDT 24
Peak memory 223660 kb
Host smart-47a4319f-db2b-428b-ac6f-15bc514bc622
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3920222348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3920222348
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2385416105
Short name T70
Test name
Test status
Simulation time 120591131 ps
CPU time 1.06 seconds
Started Jun 27 06:23:13 PM PDT 24
Finished Jun 27 06:23:22 PM PDT 24
Peak memory 236912 kb
Host smart-a83f8588-3cb9-483f-be6f-4a2032c2ed2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385416105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2385416105
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2081390306
Short name T417
Test name
Test status
Simulation time 173057996 ps
CPU time 0.99 seconds
Started Jun 27 06:23:04 PM PDT 24
Finished Jun 27 06:23:14 PM PDT 24
Peak memory 207552 kb
Host smart-a8dd3c26-bf25-4267-b3fc-2dc373fd7927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081390306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2081390306
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1878360597
Short name T328
Test name
Test status
Simulation time 80726536 ps
CPU time 1.91 seconds
Started Jun 27 06:23:14 PM PDT 24
Finished Jun 27 06:23:24 PM PDT 24
Peak memory 216800 kb
Host smart-2ffe3530-3cee-4799-a779-b5f7b9ac8bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878360597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1878360597
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4079910006
Short name T78
Test name
Test status
Simulation time 3087820957 ps
CPU time 9.35 seconds
Started Jun 27 06:23:05 PM PDT 24
Finished Jun 27 06:23:24 PM PDT 24
Peak memory 216840 kb
Host smart-f7bc0a94-27be-4630-b47a-eb9ef2af9bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079910006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4079910006
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2964978883
Short name T79
Test name
Test status
Simulation time 120693645 ps
CPU time 1.33 seconds
Started Jun 27 06:23:00 PM PDT 24
Finished Jun 27 06:23:15 PM PDT 24
Peak memory 216740 kb
Host smart-3e164b96-4b41-4bb8-bb1a-1371957b4d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964978883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2964978883
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1333970275
Short name T521
Test name
Test status
Simulation time 205556185 ps
CPU time 0.78 seconds
Started Jun 27 06:23:11 PM PDT 24
Finished Jun 27 06:23:20 PM PDT 24
Peak memory 206424 kb
Host smart-24c25d5d-32f3-4a33-8051-cfc338f40f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333970275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1333970275
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3564111110
Short name T700
Test name
Test status
Simulation time 313815765 ps
CPU time 2.82 seconds
Started Jun 27 06:23:08 PM PDT 24
Finished Jun 27 06:23:19 PM PDT 24
Peak memory 225056 kb
Host smart-9be1a86b-e152-459f-9123-26244be5eca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564111110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3564111110
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.827877116
Short name T407
Test name
Test status
Simulation time 11112420 ps
CPU time 0.7 seconds
Started Jun 27 06:24:15 PM PDT 24
Finished Jun 27 06:24:23 PM PDT 24
Peak memory 205984 kb
Host smart-a68de3f2-484d-490c-ac16-dca3dfd0d572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827877116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.827877116
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.876415438
Short name T591
Test name
Test status
Simulation time 2406133154 ps
CPU time 4.55 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:29 PM PDT 24
Peak memory 225100 kb
Host smart-c1549ac3-1828-476d-b0a9-48b22ae6f11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876415438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.876415438
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.271217753
Short name T625
Test name
Test status
Simulation time 19280376 ps
CPU time 0.83 seconds
Started Jun 27 06:24:11 PM PDT 24
Finished Jun 27 06:24:18 PM PDT 24
Peak memory 207104 kb
Host smart-2bb2ce76-cc40-4d26-9349-31c8ed9ede22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271217753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.271217753
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.203682802
Short name T571
Test name
Test status
Simulation time 2569567355 ps
CPU time 23.57 seconds
Started Jun 27 06:24:10 PM PDT 24
Finished Jun 27 06:24:39 PM PDT 24
Peak memory 240216 kb
Host smart-c067f982-ae3c-4f7f-a722-2876dfacade1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203682802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.203682802
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3716852511
Short name T302
Test name
Test status
Simulation time 6854917846 ps
CPU time 76.74 seconds
Started Jun 27 06:24:12 PM PDT 24
Finished Jun 27 06:25:34 PM PDT 24
Peak memory 253648 kb
Host smart-24a8fbab-0842-4e64-98cd-4b59d163e4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716852511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3716852511
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3246813850
Short name T300
Test name
Test status
Simulation time 88078344120 ps
CPU time 261.06 seconds
Started Jun 27 06:24:08 PM PDT 24
Finished Jun 27 06:28:33 PM PDT 24
Peak memory 236276 kb
Host smart-4d75f2aa-f299-4526-aecc-235d83a9443b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246813850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3246813850
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3017148699
Short name T629
Test name
Test status
Simulation time 717739121 ps
CPU time 13.31 seconds
Started Jun 27 06:24:09 PM PDT 24
Finished Jun 27 06:24:27 PM PDT 24
Peak memory 225004 kb
Host smart-dba0458a-c2bc-4b71-8a3f-bc3fac2ede5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017148699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3017148699
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1923451070
Short name T954
Test name
Test status
Simulation time 6428262201 ps
CPU time 41.17 seconds
Started Jun 27 06:24:12 PM PDT 24
Finished Jun 27 06:24:58 PM PDT 24
Peak memory 249688 kb
Host smart-2e1e4dab-f7bb-4855-9114-7ac00d2ed172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923451070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1923451070
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.24020042
Short name T984
Test name
Test status
Simulation time 148936193 ps
CPU time 2.24 seconds
Started Jun 27 06:24:12 PM PDT 24
Finished Jun 27 06:24:20 PM PDT 24
Peak memory 224976 kb
Host smart-e2624382-24ea-4867-9aaf-a533a302cc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24020042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.24020042
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4188675116
Short name T857
Test name
Test status
Simulation time 2165436632 ps
CPU time 10.74 seconds
Started Jun 27 06:24:08 PM PDT 24
Finished Jun 27 06:24:22 PM PDT 24
Peak memory 249532 kb
Host smart-f3f41505-810d-4e28-9890-3d18d64d85d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188675116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4188675116
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3924716335
Short name T642
Test name
Test status
Simulation time 134960673 ps
CPU time 2.26 seconds
Started Jun 27 06:24:14 PM PDT 24
Finished Jun 27 06:24:24 PM PDT 24
Peak memory 232888 kb
Host smart-60323d52-72e9-4785-9838-7df1d1b3c7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924716335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3924716335
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2592706646
Short name T855
Test name
Test status
Simulation time 2462291256 ps
CPU time 7.4 seconds
Started Jun 27 06:24:06 PM PDT 24
Finished Jun 27 06:24:15 PM PDT 24
Peak memory 225116 kb
Host smart-4ded74c7-0ba9-4b20-9cb9-c7e8fffc6ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592706646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2592706646
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1080012699
Short name T646
Test name
Test status
Simulation time 322852657 ps
CPU time 3.74 seconds
Started Jun 27 06:24:09 PM PDT 24
Finished Jun 27 06:24:17 PM PDT 24
Peak memory 223644 kb
Host smart-326fe59e-0fd0-4b91-a320-0cb0ed860023
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1080012699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1080012699
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3131994878
Short name T15
Test name
Test status
Simulation time 291584418 ps
CPU time 1.14 seconds
Started Jun 27 06:24:11 PM PDT 24
Finished Jun 27 06:24:18 PM PDT 24
Peak memory 207484 kb
Host smart-fb9e277b-58c2-4be7-adf4-a678d602772d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131994878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3131994878
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2557286970
Short name T327
Test name
Test status
Simulation time 4962240119 ps
CPU time 26.79 seconds
Started Jun 27 06:24:04 PM PDT 24
Finished Jun 27 06:24:32 PM PDT 24
Peak memory 217084 kb
Host smart-706809a0-bf46-4869-b215-e0b634f5e320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557286970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2557286970
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4085897104
Short name T485
Test name
Test status
Simulation time 5433991719 ps
CPU time 12.33 seconds
Started Jun 27 06:24:08 PM PDT 24
Finished Jun 27 06:24:24 PM PDT 24
Peak memory 216896 kb
Host smart-cc7cb829-1e72-48c1-9d8d-18c79e07f3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085897104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4085897104
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.281784019
Short name T868
Test name
Test status
Simulation time 470939794 ps
CPU time 1.59 seconds
Started Jun 27 06:24:11 PM PDT 24
Finished Jun 27 06:24:17 PM PDT 24
Peak memory 217040 kb
Host smart-5c788038-0bc5-4fe8-86d0-b070f23803bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281784019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.281784019
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1526665703
Short name T375
Test name
Test status
Simulation time 29835511 ps
CPU time 0.81 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:24:20 PM PDT 24
Peak memory 206420 kb
Host smart-0dfc1f26-43de-426d-b6f0-6130827983b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526665703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1526665703
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.737888640
Short name T348
Test name
Test status
Simulation time 5290488634 ps
CPU time 19.46 seconds
Started Jun 27 06:24:11 PM PDT 24
Finished Jun 27 06:24:36 PM PDT 24
Peak memory 225272 kb
Host smart-de89b89f-6a51-4e40-9dab-3ef2ca44b1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737888640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.737888640
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4076333149
Short name T742
Test name
Test status
Simulation time 22970304 ps
CPU time 0.71 seconds
Started Jun 27 06:24:20 PM PDT 24
Finished Jun 27 06:24:30 PM PDT 24
Peak memory 205272 kb
Host smart-069b6f69-68b3-4402-bf6b-7086ce74e937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076333149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4076333149
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1868674155
Short name T262
Test name
Test status
Simulation time 101296146 ps
CPU time 3.6 seconds
Started Jun 27 06:24:15 PM PDT 24
Finished Jun 27 06:24:26 PM PDT 24
Peak memory 233176 kb
Host smart-343df2ca-44b7-4ede-9483-118713182147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868674155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1868674155
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1635072285
Short name T895
Test name
Test status
Simulation time 57874041 ps
CPU time 0.74 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:25 PM PDT 24
Peak memory 206344 kb
Host smart-1bac21d7-b68a-42d6-bef9-491e45b94054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635072285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1635072285
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.207980894
Short name T686
Test name
Test status
Simulation time 9536604463 ps
CPU time 99.41 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:25:59 PM PDT 24
Peak memory 255804 kb
Host smart-0c7f598c-b9ee-4c77-aa9f-c8ebc4aba2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207980894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.207980894
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.888039495
Short name T252
Test name
Test status
Simulation time 16541695616 ps
CPU time 86.89 seconds
Started Jun 27 06:24:12 PM PDT 24
Finished Jun 27 06:25:45 PM PDT 24
Peak memory 255296 kb
Host smart-eca2638d-62dc-458c-9a0b-f1f72b00d3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888039495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.888039495
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2588543240
Short name T956
Test name
Test status
Simulation time 496160269 ps
CPU time 7.51 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:24:27 PM PDT 24
Peak memory 233236 kb
Host smart-1fcc4dde-097e-43ca-b9f4-830edd000528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588543240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2588543240
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.4284076559
Short name T908
Test name
Test status
Simulation time 2125084288 ps
CPU time 10.05 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:34 PM PDT 24
Peak memory 239164 kb
Host smart-bc7d1268-4d6f-4f19-b1a7-d1500b24e25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284076559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.4284076559
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.550012036
Short name T770
Test name
Test status
Simulation time 4034863143 ps
CPU time 22.79 seconds
Started Jun 27 06:24:15 PM PDT 24
Finished Jun 27 06:24:45 PM PDT 24
Peak memory 225060 kb
Host smart-df7ba5d2-3cb3-4de6-a245-624c2bef1c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550012036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.550012036
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1052809282
Short name T444
Test name
Test status
Simulation time 1046432365 ps
CPU time 10.75 seconds
Started Jun 27 06:24:15 PM PDT 24
Finished Jun 27 06:24:33 PM PDT 24
Peak memory 237736 kb
Host smart-fdd77ce7-3505-4c52-bf13-30e9cfd9d1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052809282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1052809282
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3643791276
Short name T765
Test name
Test status
Simulation time 1561930800 ps
CPU time 9.02 seconds
Started Jun 27 06:24:15 PM PDT 24
Finished Jun 27 06:24:31 PM PDT 24
Peak memory 237072 kb
Host smart-0ac84d90-db4c-40f1-9585-130d92971d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643791276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3643791276
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.520133630
Short name T878
Test name
Test status
Simulation time 10137339851 ps
CPU time 10.28 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:34 PM PDT 24
Peak memory 241196 kb
Host smart-5c29b352-3c1a-4fe5-8dca-0d6e74c1918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520133630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.520133630
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3436795240
Short name T825
Test name
Test status
Simulation time 12632134129 ps
CPU time 19.1 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:24:39 PM PDT 24
Peak memory 220744 kb
Host smart-34adc9a5-0052-4459-8eb9-9dc93131c829
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3436795240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3436795240
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1594781440
Short name T469
Test name
Test status
Simulation time 7708596055 ps
CPU time 25.62 seconds
Started Jun 27 06:24:14 PM PDT 24
Finished Jun 27 06:24:47 PM PDT 24
Peak memory 216932 kb
Host smart-56d583ca-9609-4350-8144-97ac182636e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594781440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1594781440
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3912580848
Short name T788
Test name
Test status
Simulation time 12065960 ps
CPU time 0.7 seconds
Started Jun 27 06:24:11 PM PDT 24
Finished Jun 27 06:24:18 PM PDT 24
Peak memory 206368 kb
Host smart-7c624229-0293-421b-9477-f68ac76dad1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912580848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3912580848
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1868791724
Short name T831
Test name
Test status
Simulation time 87936634 ps
CPU time 1.09 seconds
Started Jun 27 06:24:15 PM PDT 24
Finished Jun 27 06:24:24 PM PDT 24
Peak memory 208344 kb
Host smart-fa084d48-0dc0-41fc-a83a-902b08228dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868791724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1868791724
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1313402330
Short name T803
Test name
Test status
Simulation time 22490754 ps
CPU time 0.73 seconds
Started Jun 27 06:24:15 PM PDT 24
Finished Jun 27 06:24:23 PM PDT 24
Peak memory 206424 kb
Host smart-3687dbec-1409-4734-aa47-bfe8da5b9874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313402330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1313402330
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4219761677
Short name T180
Test name
Test status
Simulation time 745967601 ps
CPU time 7.79 seconds
Started Jun 27 06:24:10 PM PDT 24
Finished Jun 27 06:24:21 PM PDT 24
Peak memory 233192 kb
Host smart-0d52c7f6-52a8-4f08-b435-8de98c0bd147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219761677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4219761677
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.947671052
Short name T785
Test name
Test status
Simulation time 137669809 ps
CPU time 0.67 seconds
Started Jun 27 06:24:17 PM PDT 24
Finished Jun 27 06:24:25 PM PDT 24
Peak memory 205984 kb
Host smart-14fec025-411a-42f9-b581-f418e527b7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947671052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.947671052
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1379797426
Short name T434
Test name
Test status
Simulation time 977910725 ps
CPU time 3.41 seconds
Started Jun 27 06:24:19 PM PDT 24
Finished Jun 27 06:24:31 PM PDT 24
Peak memory 224900 kb
Host smart-a3dc36a5-d9ce-4dcc-8aa0-c8638bb56911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379797426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1379797426
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3391649337
Short name T335
Test name
Test status
Simulation time 23711302 ps
CPU time 0.77 seconds
Started Jun 27 06:24:19 PM PDT 24
Finished Jun 27 06:24:28 PM PDT 24
Peak memory 207052 kb
Host smart-61803b63-2b5c-4f38-af48-4be3980c83a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391649337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3391649337
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2429468024
Short name T697
Test name
Test status
Simulation time 61660736888 ps
CPU time 117.5 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:26:24 PM PDT 24
Peak memory 256608 kb
Host smart-f0f993f8-9cba-452a-8429-ea52421e5d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429468024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2429468024
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4253532523
Short name T291
Test name
Test status
Simulation time 68504514669 ps
CPU time 652.94 seconds
Started Jun 27 06:24:14 PM PDT 24
Finished Jun 27 06:35:14 PM PDT 24
Peak memory 271228 kb
Host smart-ec9cbeef-0f65-4e3f-bd26-5a3264fa61b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253532523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4253532523
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2313194161
Short name T310
Test name
Test status
Simulation time 15674794703 ps
CPU time 84.2 seconds
Started Jun 27 06:24:11 PM PDT 24
Finished Jun 27 06:25:40 PM PDT 24
Peak memory 257144 kb
Host smart-d80d787d-05d8-4de4-9c3e-4d3bd52bb941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313194161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2313194161
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1780327735
Short name T315
Test name
Test status
Simulation time 1027335956 ps
CPU time 6.67 seconds
Started Jun 27 06:24:17 PM PDT 24
Finished Jun 27 06:24:32 PM PDT 24
Peak memory 225020 kb
Host smart-adc8d57b-540c-4972-bb8a-30e287206151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780327735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1780327735
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1809344547
Short name T962
Test name
Test status
Simulation time 25048899007 ps
CPU time 196.01 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:27:42 PM PDT 24
Peak memory 266336 kb
Host smart-9cadebf4-ab50-416c-a0ed-9e366ca59c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809344547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1809344547
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3874734992
Short name T536
Test name
Test status
Simulation time 288166892 ps
CPU time 2.95 seconds
Started Jun 27 06:24:10 PM PDT 24
Finished Jun 27 06:24:18 PM PDT 24
Peak memory 224924 kb
Host smart-e6c7b867-ee7f-43ef-83ba-2d0ec342f863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874734992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3874734992
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4054021407
Short name T1003
Test name
Test status
Simulation time 3825027197 ps
CPU time 11.66 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:38 PM PDT 24
Peak memory 225096 kb
Host smart-a3bbe60c-2467-4952-972d-48eb6891f858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054021407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4054021407
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4047942882
Short name T512
Test name
Test status
Simulation time 16925673632 ps
CPU time 13.14 seconds
Started Jun 27 06:24:15 PM PDT 24
Finished Jun 27 06:24:36 PM PDT 24
Peak memory 234308 kb
Host smart-4ff2ff74-b88a-432e-86b9-ed7c468cd716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047942882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4047942882
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.348103858
Short name T711
Test name
Test status
Simulation time 36439548 ps
CPU time 2.56 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:29 PM PDT 24
Peak memory 232988 kb
Host smart-a3d0ff28-5208-4701-b790-055447938c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348103858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.348103858
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4141111194
Short name T1004
Test name
Test status
Simulation time 1055046153 ps
CPU time 16.38 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:24:36 PM PDT 24
Peak memory 220864 kb
Host smart-42fb8c65-bb75-4061-99ca-9aeaacd5dce3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4141111194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4141111194
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.380327092
Short name T856
Test name
Test status
Simulation time 265421487 ps
CPU time 0.94 seconds
Started Jun 27 06:24:07 PM PDT 24
Finished Jun 27 06:24:11 PM PDT 24
Peak memory 207440 kb
Host smart-bc86a88c-c958-4583-816d-194cf012bd66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380327092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.380327092
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.631623951
Short name T593
Test name
Test status
Simulation time 2520676901 ps
CPU time 9.98 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:33 PM PDT 24
Peak memory 220716 kb
Host smart-5e79237e-c993-4cb0-bb09-4f8fa18e81ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631623951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.631623951
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1050325518
Short name T589
Test name
Test status
Simulation time 3889553381 ps
CPU time 11.09 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:34 PM PDT 24
Peak memory 216924 kb
Host smart-dacb90e8-8dc3-40ad-a6dc-f98ab7cef728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050325518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1050325518
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1412418031
Short name T899
Test name
Test status
Simulation time 45441938 ps
CPU time 0.88 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:27 PM PDT 24
Peak memory 207232 kb
Host smart-5d717f03-1ca6-4dd4-b8fe-8de39f7bd37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412418031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1412418031
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.4184196475
Short name T575
Test name
Test status
Simulation time 45368132 ps
CPU time 0.68 seconds
Started Jun 27 06:24:20 PM PDT 24
Finished Jun 27 06:24:29 PM PDT 24
Peak memory 206056 kb
Host smart-acc0c535-caa9-4068-9e5d-74aa81045103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184196475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.4184196475
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1558385893
Short name T199
Test name
Test status
Simulation time 868917579 ps
CPU time 8.62 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:35 PM PDT 24
Peak memory 225024 kb
Host smart-a8180be5-34ce-4e22-8765-a2578c99711e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558385893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1558385893
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.842949618
Short name T401
Test name
Test status
Simulation time 10141462 ps
CPU time 0.68 seconds
Started Jun 27 06:24:14 PM PDT 24
Finished Jun 27 06:24:22 PM PDT 24
Peak memory 205212 kb
Host smart-a566426b-17e5-42cd-b9ba-c26d83ddf2da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842949618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.842949618
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.681182525
Short name T390
Test name
Test status
Simulation time 9311668250 ps
CPU time 19.84 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:44 PM PDT 24
Peak memory 233364 kb
Host smart-0ccdb6bb-0588-4aca-a889-53cbfa96838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681182525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.681182525
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3039282841
Short name T853
Test name
Test status
Simulation time 20050990 ps
CPU time 0.76 seconds
Started Jun 27 06:24:07 PM PDT 24
Finished Jun 27 06:24:10 PM PDT 24
Peak memory 205592 kb
Host smart-b680a3a4-f78a-4dca-8f97-334f1424cd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039282841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3039282841
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.496882859
Short name T222
Test name
Test status
Simulation time 17582524073 ps
CPU time 120.78 seconds
Started Jun 27 06:24:10 PM PDT 24
Finished Jun 27 06:26:16 PM PDT 24
Peak memory 249696 kb
Host smart-911d3a5d-23fb-4611-8716-68dc0b9263ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496882859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.496882859
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3385682716
Short name T952
Test name
Test status
Simulation time 66602670092 ps
CPU time 111.88 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:26:11 PM PDT 24
Peak memory 254504 kb
Host smart-199d230a-008c-4389-a2d2-38ba6c699903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385682716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3385682716
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.533875650
Short name T985
Test name
Test status
Simulation time 104005399744 ps
CPU time 345.1 seconds
Started Jun 27 06:24:15 PM PDT 24
Finished Jun 27 06:30:07 PM PDT 24
Peak memory 274160 kb
Host smart-ef603368-f6fe-46c6-a95f-84c4c3cb5a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533875650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.533875650
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1200848125
Short name T958
Test name
Test status
Simulation time 5189541613 ps
CPU time 23.61 seconds
Started Jun 27 06:24:12 PM PDT 24
Finished Jun 27 06:24:42 PM PDT 24
Peak memory 233220 kb
Host smart-ad678f7e-5965-483c-a57e-e7c8dbdc4f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200848125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1200848125
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.679406309
Short name T190
Test name
Test status
Simulation time 10116982220 ps
CPU time 87.09 seconds
Started Jun 27 06:24:10 PM PDT 24
Finished Jun 27 06:25:41 PM PDT 24
Peak memory 255856 kb
Host smart-d3bb0a5e-0b25-4e4e-8258-3a48bf237613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679406309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.679406309
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2666654096
Short name T861
Test name
Test status
Simulation time 495078747 ps
CPU time 4.11 seconds
Started Jun 27 06:24:10 PM PDT 24
Finished Jun 27 06:24:19 PM PDT 24
Peak memory 233100 kb
Host smart-2d8a0be6-6d3d-4a26-8f2a-c7282ccae34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666654096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2666654096
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.99983233
Short name T441
Test name
Test status
Simulation time 333257011 ps
CPU time 5.33 seconds
Started Jun 27 06:24:07 PM PDT 24
Finished Jun 27 06:24:15 PM PDT 24
Peak memory 233168 kb
Host smart-d7ce99a6-5680-44aa-8d26-9d936b9ed7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99983233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.99983233
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1786528934
Short name T871
Test name
Test status
Simulation time 1634923943 ps
CPU time 7.43 seconds
Started Jun 27 06:24:07 PM PDT 24
Finished Jun 27 06:24:17 PM PDT 24
Peak memory 233228 kb
Host smart-3455a19f-0e82-4bc3-8ded-a4c33c021832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786528934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1786528934
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2619611432
Short name T714
Test name
Test status
Simulation time 45550629 ps
CPU time 2.41 seconds
Started Jun 27 06:24:07 PM PDT 24
Finished Jun 27 06:24:12 PM PDT 24
Peak memory 232792 kb
Host smart-8bae97d9-0b16-4c00-9d9a-c836584be027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619611432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2619611432
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.912605367
Short name T355
Test name
Test status
Simulation time 5398740748 ps
CPU time 13.31 seconds
Started Jun 27 06:24:12 PM PDT 24
Finished Jun 27 06:24:32 PM PDT 24
Peak memory 219484 kb
Host smart-a2827f31-466e-4098-93cb-088bb34b7bea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=912605367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.912605367
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2772250740
Short name T776
Test name
Test status
Simulation time 41080086466 ps
CPU time 188 seconds
Started Jun 27 06:24:12 PM PDT 24
Finished Jun 27 06:27:26 PM PDT 24
Peak memory 250836 kb
Host smart-daf107e6-7da7-460a-9a0b-34b6a2e83ac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772250740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2772250740
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2070509463
Short name T781
Test name
Test status
Simulation time 6289801125 ps
CPU time 21.32 seconds
Started Jun 27 06:24:07 PM PDT 24
Finished Jun 27 06:24:30 PM PDT 24
Peak memory 216908 kb
Host smart-78e5a89e-b5cd-448b-82d0-4f2c56b46de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070509463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2070509463
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1520649142
Short name T554
Test name
Test status
Simulation time 30058091426 ps
CPU time 9.83 seconds
Started Jun 27 06:24:07 PM PDT 24
Finished Jun 27 06:24:19 PM PDT 24
Peak memory 217980 kb
Host smart-167ccaff-75ad-476c-8cfc-e0e2a4e98bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520649142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1520649142
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2401873477
Short name T797
Test name
Test status
Simulation time 383525118 ps
CPU time 10.24 seconds
Started Jun 27 06:24:09 PM PDT 24
Finished Jun 27 06:24:23 PM PDT 24
Peak memory 216772 kb
Host smart-afa03ad4-b53d-4a23-a2ec-5dccf655baeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401873477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2401873477
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2528576598
Short name T494
Test name
Test status
Simulation time 143377497 ps
CPU time 0.78 seconds
Started Jun 27 06:24:07 PM PDT 24
Finished Jun 27 06:24:10 PM PDT 24
Peak memory 206468 kb
Host smart-178ce763-49ab-4adb-8827-ca95bd7b2e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528576598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2528576598
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.502724419
Short name T410
Test name
Test status
Simulation time 9469555566 ps
CPU time 19.75 seconds
Started Jun 27 06:24:10 PM PDT 24
Finished Jun 27 06:24:34 PM PDT 24
Peak memory 235568 kb
Host smart-ce6c8610-672c-4d27-9eff-22988cd0f640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502724419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.502724419
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3394616081
Short name T427
Test name
Test status
Simulation time 34889979 ps
CPU time 0.75 seconds
Started Jun 27 06:24:11 PM PDT 24
Finished Jun 27 06:24:17 PM PDT 24
Peak memory 205396 kb
Host smart-4899f539-42fd-48f7-84df-5a1fa05fc762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394616081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3394616081
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1183785424
Short name T850
Test name
Test status
Simulation time 721111449 ps
CPU time 2.5 seconds
Started Jun 27 06:24:15 PM PDT 24
Finished Jun 27 06:24:25 PM PDT 24
Peak memory 233116 kb
Host smart-9d0a8c5f-a0a0-4f98-a547-2984aeefd7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183785424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1183785424
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2264360933
Short name T753
Test name
Test status
Simulation time 13972313 ps
CPU time 0.74 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:24:20 PM PDT 24
Peak memory 207108 kb
Host smart-ae39e7b7-3af0-4319-bd99-3b93e675c9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264360933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2264360933
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.590686060
Short name T50
Test name
Test status
Simulation time 178470980931 ps
CPU time 335.68 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:29:56 PM PDT 24
Peak memory 253636 kb
Host smart-9fa9e4bf-cf24-4e6a-8bbe-cf975c6af4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590686060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.590686060
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.4166499198
Short name T132
Test name
Test status
Simulation time 6125897969 ps
CPU time 49.21 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:25:08 PM PDT 24
Peak memory 225228 kb
Host smart-8661964b-71a8-4700-9498-ec1f52f798f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166499198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4166499198
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.809097191
Short name T37
Test name
Test status
Simulation time 43328157295 ps
CPU time 182.56 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:27:27 PM PDT 24
Peak memory 274312 kb
Host smart-4c4d513a-65a6-4e0b-8bed-48a4bba61d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809097191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.809097191
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.192188390
Short name T633
Test name
Test status
Simulation time 3162422384 ps
CPU time 15.72 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:24:35 PM PDT 24
Peak memory 235024 kb
Host smart-128acd62-de33-4757-bdf8-6c7f0a716d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192188390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.192188390
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1719997854
Short name T14
Test name
Test status
Simulation time 1117696926 ps
CPU time 22.46 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:46 PM PDT 24
Peak memory 250824 kb
Host smart-772a0a88-c4e4-4308-803b-21f8b8cc1a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719997854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1719997854
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3956953030
Short name T253
Test name
Test status
Simulation time 891115900 ps
CPU time 6.08 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:24:26 PM PDT 24
Peak memory 219360 kb
Host smart-a06ee7f5-0bcf-4a3e-86dc-804d7077c6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956953030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3956953030
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2853558442
Short name T204
Test name
Test status
Simulation time 3376425394 ps
CPU time 12.97 seconds
Started Jun 27 06:24:15 PM PDT 24
Finished Jun 27 06:24:35 PM PDT 24
Peak memory 240740 kb
Host smart-5c687160-6b8b-4e7b-8355-2d2646d65223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853558442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2853558442
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4088221547
Short name T402
Test name
Test status
Simulation time 1519691495 ps
CPU time 3.47 seconds
Started Jun 27 06:24:14 PM PDT 24
Finished Jun 27 06:24:25 PM PDT 24
Peak memory 233116 kb
Host smart-0c6711f9-310e-4865-8006-a624fcb01787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088221547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4088221547
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2785506188
Short name T95
Test name
Test status
Simulation time 4889605680 ps
CPU time 16.88 seconds
Started Jun 27 06:24:11 PM PDT 24
Finished Jun 27 06:24:32 PM PDT 24
Peak memory 233272 kb
Host smart-0b9b59c6-b308-4dc0-a60c-f75c8de51cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785506188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2785506188
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1284676824
Short name T365
Test name
Test status
Simulation time 755267943 ps
CPU time 7.92 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:32 PM PDT 24
Peak memory 220440 kb
Host smart-e31a90e1-8e5f-4e6c-85a0-6ee3221fb329
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1284676824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1284676824
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3668682402
Short name T307
Test name
Test status
Simulation time 45497609752 ps
CPU time 379.59 seconds
Started Jun 27 06:24:15 PM PDT 24
Finished Jun 27 06:30:42 PM PDT 24
Peak memory 266276 kb
Host smart-2541a0a8-954e-4a83-81df-d7a363b1c8d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668682402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3668682402
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.548991866
Short name T572
Test name
Test status
Simulation time 4512546944 ps
CPU time 8.15 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:24:28 PM PDT 24
Peak memory 220448 kb
Host smart-a6fe0c3f-66a9-4c14-bc97-21741c5d0327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548991866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.548991866
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1723743771
Short name T773
Test name
Test status
Simulation time 9154822344 ps
CPU time 7.9 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:24:28 PM PDT 24
Peak memory 216868 kb
Host smart-2a459206-bfa2-4906-8145-3307a02fb990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723743771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1723743771
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1692545246
Short name T83
Test name
Test status
Simulation time 47182690 ps
CPU time 0.7 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:24:21 PM PDT 24
Peak memory 206148 kb
Host smart-32417756-894f-4a7c-8f66-8398e005d33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692545246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1692545246
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4062898339
Short name T564
Test name
Test status
Simulation time 157532488 ps
CPU time 0.79 seconds
Started Jun 27 06:24:14 PM PDT 24
Finished Jun 27 06:24:22 PM PDT 24
Peak memory 206444 kb
Host smart-5789e428-dc72-4fd0-9cac-646c3f29d733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062898339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4062898339
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1732213278
Short name T761
Test name
Test status
Simulation time 1102745816 ps
CPU time 8.35 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:24:29 PM PDT 24
Peak memory 241116 kb
Host smart-bd9869c8-aaef-4f25-beb4-87a34caa2776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732213278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1732213278
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1385136855
Short name T418
Test name
Test status
Simulation time 34767018 ps
CPU time 0.69 seconds
Started Jun 27 06:24:36 PM PDT 24
Finished Jun 27 06:24:46 PM PDT 24
Peak memory 205952 kb
Host smart-c9fdf338-e17e-4704-848a-32984c081554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385136855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1385136855
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2418463871
Short name T1009
Test name
Test status
Simulation time 291527130 ps
CPU time 3.97 seconds
Started Jun 27 06:24:25 PM PDT 24
Finished Jun 27 06:24:38 PM PDT 24
Peak memory 224960 kb
Host smart-d5828ee1-592c-4f00-8ac2-e761319d4bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418463871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2418463871
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4174386710
Short name T361
Test name
Test status
Simulation time 14806057 ps
CPU time 0.74 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:24:20 PM PDT 24
Peak memory 207044 kb
Host smart-1ba3facc-cd91-4aa6-973f-3aed0903b0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174386710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4174386710
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2502496569
Short name T869
Test name
Test status
Simulation time 29693404196 ps
CPU time 127.41 seconds
Started Jun 27 06:24:17 PM PDT 24
Finished Jun 27 06:26:32 PM PDT 24
Peak memory 255276 kb
Host smart-fb7aea15-c5dd-4b51-8534-578eb529a1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502496569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2502496569
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2703812465
Short name T735
Test name
Test status
Simulation time 13621153194 ps
CPU time 131.7 seconds
Started Jun 27 06:24:42 PM PDT 24
Finished Jun 27 06:27:02 PM PDT 24
Peak memory 249860 kb
Host smart-5891c7bb-3c73-4cdb-a0f7-4e26660ac7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703812465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2703812465
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.294460403
Short name T727
Test name
Test status
Simulation time 2087244640 ps
CPU time 6.4 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:31 PM PDT 24
Peak memory 249784 kb
Host smart-aac3dc19-995b-4e19-8db4-d7dc1aacc771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294460403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.294460403
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.140506240
Short name T960
Test name
Test status
Simulation time 183585864 ps
CPU time 2.38 seconds
Started Jun 27 06:24:19 PM PDT 24
Finished Jun 27 06:24:30 PM PDT 24
Peak memory 225036 kb
Host smart-6994535d-ba41-4003-93d1-7b2a0b04247d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140506240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.140506240
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2441367774
Short name T892
Test name
Test status
Simulation time 561543060 ps
CPU time 6.14 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:32 PM PDT 24
Peak memory 233080 kb
Host smart-74854a36-3f12-4a05-907e-cbfeefe2a862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441367774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2441367774
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.95794564
Short name T820
Test name
Test status
Simulation time 4164809818 ps
CPU time 6 seconds
Started Jun 27 06:24:23 PM PDT 24
Finished Jun 27 06:24:39 PM PDT 24
Peak memory 225084 kb
Host smart-9f49ad94-e091-42d5-bdbb-743c4b3e00ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95794564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.95794564
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1806707646
Short name T579
Test name
Test status
Simulation time 26244535406 ps
CPU time 20.3 seconds
Started Jun 27 06:24:17 PM PDT 24
Finished Jun 27 06:24:45 PM PDT 24
Peak memory 233252 kb
Host smart-c7b83230-05b8-4ae5-8e48-fb25d934987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806707646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1806707646
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.206148072
Short name T618
Test name
Test status
Simulation time 1912173476 ps
CPU time 19.74 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:45 PM PDT 24
Peak memory 219640 kb
Host smart-34eb23b1-ed3e-4e86-b55f-9e06b8d231ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=206148072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.206148072
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1031870464
Short name T159
Test name
Test status
Simulation time 293894861 ps
CPU time 1.26 seconds
Started Jun 27 06:24:39 PM PDT 24
Finished Jun 27 06:24:49 PM PDT 24
Peak memory 207680 kb
Host smart-4ebf94a3-8220-461f-b7c9-6b37cc6ca41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031870464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1031870464
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2839503480
Short name T973
Test name
Test status
Simulation time 3070719613 ps
CPU time 24.52 seconds
Started Jun 27 06:24:20 PM PDT 24
Finished Jun 27 06:24:54 PM PDT 24
Peak memory 220368 kb
Host smart-bf4f5df0-8f61-4242-b6f0-f4d722bc8bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839503480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2839503480
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.216902331
Short name T399
Test name
Test status
Simulation time 5910372015 ps
CPU time 9.48 seconds
Started Jun 27 06:24:19 PM PDT 24
Finished Jun 27 06:24:38 PM PDT 24
Peak memory 216840 kb
Host smart-98b53b6b-d1d0-44ce-aa77-8128a36487de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216902331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.216902331
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3371178422
Short name T786
Test name
Test status
Simulation time 104168897 ps
CPU time 1.22 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:24 PM PDT 24
Peak memory 216616 kb
Host smart-941aa201-692f-46d6-bfcb-d86dc698cf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371178422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3371178422
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3759090867
Short name T397
Test name
Test status
Simulation time 29907272 ps
CPU time 0.76 seconds
Started Jun 27 06:24:13 PM PDT 24
Finished Jun 27 06:24:20 PM PDT 24
Peak memory 206396 kb
Host smart-14eb3e3d-5e53-441f-bb7e-14b05fa7a307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759090867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3759090867
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.297470496
Short name T209
Test name
Test status
Simulation time 3148954744 ps
CPU time 4.58 seconds
Started Jun 27 06:24:19 PM PDT 24
Finished Jun 27 06:24:31 PM PDT 24
Peak memory 233352 kb
Host smart-18d8a3f7-626f-4729-8e54-8d1423b45f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297470496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.297470496
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4113750288
Short name T862
Test name
Test status
Simulation time 25368811 ps
CPU time 0.71 seconds
Started Jun 27 06:24:29 PM PDT 24
Finished Jun 27 06:24:40 PM PDT 24
Peak memory 206248 kb
Host smart-4a9b0fd6-16de-4dd5-93ac-5b2884cc05cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113750288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4113750288
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2405895423
Short name T1001
Test name
Test status
Simulation time 166455733 ps
CPU time 3.82 seconds
Started Jun 27 06:24:25 PM PDT 24
Finished Jun 27 06:24:39 PM PDT 24
Peak memory 233200 kb
Host smart-2ffeecec-4497-4913-895b-fb30e7597a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405895423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2405895423
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.679712814
Short name T383
Test name
Test status
Simulation time 17015469 ps
CPU time 0.76 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:28 PM PDT 24
Peak memory 207012 kb
Host smart-a3bedb87-de02-4f1a-ae56-0627c5bb166d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679712814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.679712814
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.891935681
Short name T747
Test name
Test status
Simulation time 1101183045 ps
CPU time 6.05 seconds
Started Jun 27 06:24:29 PM PDT 24
Finished Jun 27 06:24:44 PM PDT 24
Peak memory 224776 kb
Host smart-ae3c0344-988d-42ae-bf3f-7a7c44d4b5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891935681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.891935681
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3496823689
Short name T903
Test name
Test status
Simulation time 105727027707 ps
CPU time 173.44 seconds
Started Jun 27 06:24:39 PM PDT 24
Finished Jun 27 06:27:41 PM PDT 24
Peak memory 258012 kb
Host smart-aebf911c-0e3e-4ed9-88f2-3e130390586a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496823689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3496823689
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.944115000
Short name T738
Test name
Test status
Simulation time 556894239 ps
CPU time 7.18 seconds
Started Jun 27 06:24:22 PM PDT 24
Finished Jun 27 06:24:38 PM PDT 24
Peak memory 225016 kb
Host smart-d89279c5-89bc-4e98-a9dc-1caefc05b162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944115000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.944115000
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1274699654
Short name T53
Test name
Test status
Simulation time 139419663 ps
CPU time 4.77 seconds
Started Jun 27 06:24:25 PM PDT 24
Finished Jun 27 06:24:45 PM PDT 24
Peak memory 219376 kb
Host smart-41e5dc6a-9355-43cb-8612-80ab06481362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274699654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1274699654
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2166245328
Short name T422
Test name
Test status
Simulation time 3666164461 ps
CPU time 28.71 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:53 PM PDT 24
Peak memory 225072 kb
Host smart-19c40d16-7b16-4da8-beee-47f1661a04d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166245328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2166245328
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3028356121
Short name T532
Test name
Test status
Simulation time 389701189 ps
CPU time 3.76 seconds
Started Jun 27 06:24:26 PM PDT 24
Finished Jun 27 06:24:39 PM PDT 24
Peak memory 233148 kb
Host smart-93690c1e-259e-48fd-8459-16e621b4d9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028356121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3028356121
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.262438419
Short name T497
Test name
Test status
Simulation time 1002204068 ps
CPU time 7.4 seconds
Started Jun 27 06:24:29 PM PDT 24
Finished Jun 27 06:24:46 PM PDT 24
Peak memory 233204 kb
Host smart-f4f3856a-127b-48bd-a480-409e801bb8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262438419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.262438419
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1235672013
Short name T341
Test name
Test status
Simulation time 1980796965 ps
CPU time 13.41 seconds
Started Jun 27 06:24:20 PM PDT 24
Finished Jun 27 06:24:42 PM PDT 24
Peak memory 219788 kb
Host smart-8e62e34e-5a7d-47e3-9263-2fe3bab19543
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1235672013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1235672013
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.701574872
Short name T518
Test name
Test status
Simulation time 2870268484 ps
CPU time 16.25 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:43 PM PDT 24
Peak memory 225260 kb
Host smart-5ff7090f-6713-46b3-bbc7-41988027f544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701574872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.701574872
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1242111332
Short name T131
Test name
Test status
Simulation time 8971438532 ps
CPU time 16.2 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:43 PM PDT 24
Peak memory 216884 kb
Host smart-eb61087a-7b00-4b6b-b446-f0455f8cd03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242111332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1242111332
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2009893626
Short name T683
Test name
Test status
Simulation time 16486504459 ps
CPU time 10.76 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:36 PM PDT 24
Peak memory 216912 kb
Host smart-3a0ea843-a6b4-417f-854c-abcafeb50178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009893626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2009893626
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3412450374
Short name T358
Test name
Test status
Simulation time 57056085 ps
CPU time 0.86 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:25 PM PDT 24
Peak memory 206476 kb
Host smart-5ecc0525-a8c5-40d4-9718-70f6418e3d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412450374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3412450374
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1842681074
Short name T645
Test name
Test status
Simulation time 98704207 ps
CPU time 0.72 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:25 PM PDT 24
Peak memory 206480 kb
Host smart-927c82cc-02e2-40ad-88dc-bf0f6bbea981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842681074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1842681074
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3126583390
Short name T493
Test name
Test status
Simulation time 20071805392 ps
CPU time 22.52 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:49 PM PDT 24
Peak memory 249388 kb
Host smart-38d2ba1c-7b23-422a-9bd8-101c58cca4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126583390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3126583390
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3804797846
Short name T384
Test name
Test status
Simulation time 17152493 ps
CPU time 0.76 seconds
Started Jun 27 06:24:36 PM PDT 24
Finished Jun 27 06:24:46 PM PDT 24
Peak memory 205364 kb
Host smart-b31bf1ea-98b8-43c6-805d-a7e75a548080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804797846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3804797846
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3193598241
Short name T656
Test name
Test status
Simulation time 277970344 ps
CPU time 5.74 seconds
Started Jun 27 06:24:25 PM PDT 24
Finished Jun 27 06:24:40 PM PDT 24
Peak memory 225048 kb
Host smart-625599c6-38e3-43ce-bd49-90f590c18693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193598241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3193598241
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.512722986
Short name T445
Test name
Test status
Simulation time 47046857 ps
CPU time 0.72 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:27 PM PDT 24
Peak memory 205992 kb
Host smart-5a20fdff-ce63-4f05-ba5f-808f59c8aca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512722986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.512722986
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3752112814
Short name T851
Test name
Test status
Simulation time 39675586394 ps
CPU time 358.62 seconds
Started Jun 27 06:24:31 PM PDT 24
Finished Jun 27 06:30:39 PM PDT 24
Peak memory 257200 kb
Host smart-5b329b84-5d9b-4544-932f-3962041bce5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752112814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3752112814
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3583354843
Short name T839
Test name
Test status
Simulation time 14001931027 ps
CPU time 164.6 seconds
Started Jun 27 06:24:34 PM PDT 24
Finished Jun 27 06:27:27 PM PDT 24
Peak memory 250228 kb
Host smart-6a218215-637d-4e0e-9ac5-36dea7f7898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583354843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3583354843
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2937926162
Short name T220
Test name
Test status
Simulation time 339721385 ps
CPU time 3.75 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:28 PM PDT 24
Peak memory 233168 kb
Host smart-be013443-988d-4c2c-a06c-184454aa37f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937926162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2937926162
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2382356684
Short name T243
Test name
Test status
Simulation time 41881894719 ps
CPU time 62.04 seconds
Started Jun 27 06:24:25 PM PDT 24
Finished Jun 27 06:25:36 PM PDT 24
Peak memory 251124 kb
Host smart-ab00db7f-311b-4dc8-9f41-91869b132f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382356684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2382356684
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.45058298
Short name T949
Test name
Test status
Simulation time 870694489 ps
CPU time 4.6 seconds
Started Jun 27 06:24:25 PM PDT 24
Finished Jun 27 06:24:39 PM PDT 24
Peak memory 225020 kb
Host smart-2a2b4382-8351-4444-8cb5-ca26bfab38e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45058298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.45058298
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.891118091
Short name T981
Test name
Test status
Simulation time 624663764 ps
CPU time 3.94 seconds
Started Jun 27 06:24:16 PM PDT 24
Finished Jun 27 06:24:28 PM PDT 24
Peak memory 233164 kb
Host smart-89db7cb1-59b7-4bf4-9778-55aa44bca374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891118091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.891118091
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3026033097
Short name T446
Test name
Test status
Simulation time 681825682 ps
CPU time 5.4 seconds
Started Jun 27 06:24:34 PM PDT 24
Finished Jun 27 06:24:48 PM PDT 24
Peak memory 222592 kb
Host smart-0ac24e42-0de0-4073-a48a-6d491e48a150
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3026033097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3026033097
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3747888506
Short name T154
Test name
Test status
Simulation time 111949860961 ps
CPU time 226.02 seconds
Started Jun 27 06:24:29 PM PDT 24
Finished Jun 27 06:28:24 PM PDT 24
Peak memory 257820 kb
Host smart-0e7e60e8-ce3a-41c8-a6b2-4989cc87bbf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747888506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3747888506
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2545344891
Short name T534
Test name
Test status
Simulation time 6134055423 ps
CPU time 11.91 seconds
Started Jun 27 06:24:30 PM PDT 24
Finished Jun 27 06:24:52 PM PDT 24
Peak memory 216884 kb
Host smart-7f5fa117-9cdc-43c7-ae66-9978d5b56bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545344891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2545344891
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1227838822
Short name T413
Test name
Test status
Simulation time 6051253444 ps
CPU time 6.89 seconds
Started Jun 27 06:24:28 PM PDT 24
Finished Jun 27 06:24:45 PM PDT 24
Peak memory 216920 kb
Host smart-f6187939-e922-4ffa-9195-1c2b2a3c798e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227838822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1227838822
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1417809361
Short name T730
Test name
Test status
Simulation time 131341887 ps
CPU time 2.45 seconds
Started Jun 27 06:24:25 PM PDT 24
Finished Jun 27 06:24:37 PM PDT 24
Peak memory 216784 kb
Host smart-56bae5ec-45f6-4f73-88ad-800c9617277f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417809361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1417809361
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2041791514
Short name T784
Test name
Test status
Simulation time 46754487 ps
CPU time 0.75 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:27 PM PDT 24
Peak memory 206400 kb
Host smart-174568aa-7476-4fca-b75c-f23cfcbf9f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041791514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2041791514
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1268199511
Short name T247
Test name
Test status
Simulation time 3367754624 ps
CPU time 4.67 seconds
Started Jun 27 06:24:28 PM PDT 24
Finished Jun 27 06:24:42 PM PDT 24
Peak memory 224840 kb
Host smart-ebce24b8-337e-4f35-a1ab-62f5ec27b246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268199511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1268199511
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1236686944
Short name T509
Test name
Test status
Simulation time 29622818 ps
CPU time 0.7 seconds
Started Jun 27 06:24:20 PM PDT 24
Finished Jun 27 06:24:29 PM PDT 24
Peak memory 205956 kb
Host smart-c125a2e5-166b-4c85-9ce3-3ad72c870f29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236686944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1236686944
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.569327442
Short name T771
Test name
Test status
Simulation time 861278777 ps
CPU time 5.43 seconds
Started Jun 27 06:24:30 PM PDT 24
Finished Jun 27 06:24:45 PM PDT 24
Peak memory 232348 kb
Host smart-dfb4057a-3ef6-4801-8c2d-6e5cc154f9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569327442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.569327442
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3200827695
Short name T936
Test name
Test status
Simulation time 15916763 ps
CPU time 0.77 seconds
Started Jun 27 06:24:22 PM PDT 24
Finished Jun 27 06:24:31 PM PDT 24
Peak memory 207428 kb
Host smart-dbcf0270-c572-4163-86cc-71948e86ce1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200827695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3200827695
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1649398353
Short name T86
Test name
Test status
Simulation time 102644703533 ps
CPU time 211.32 seconds
Started Jun 27 06:24:38 PM PDT 24
Finished Jun 27 06:28:17 PM PDT 24
Peak memory 256100 kb
Host smart-68433cfb-2adc-4700-af9f-224320e4a92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649398353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1649398353
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4085251738
Short name T205
Test name
Test status
Simulation time 90006164040 ps
CPU time 270.4 seconds
Started Jun 27 06:24:19 PM PDT 24
Finished Jun 27 06:28:58 PM PDT 24
Peak memory 274136 kb
Host smart-558ea979-fda0-44b4-bbe5-1b59c4253fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085251738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4085251738
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1256127456
Short name T317
Test name
Test status
Simulation time 815552106 ps
CPU time 4.84 seconds
Started Jun 27 06:24:30 PM PDT 24
Finished Jun 27 06:24:44 PM PDT 24
Peak memory 233220 kb
Host smart-9c8a3f0e-2c44-451f-b9ea-ab9dc3d754bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256127456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1256127456
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.451246029
Short name T238
Test name
Test status
Simulation time 6037028285 ps
CPU time 24.54 seconds
Started Jun 27 06:24:39 PM PDT 24
Finished Jun 27 06:25:12 PM PDT 24
Peak memory 241508 kb
Host smart-8661787a-d6e2-437c-9d2b-9cc9b10559f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451246029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.451246029
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2951438543
Short name T228
Test name
Test status
Simulation time 386825481 ps
CPU time 6.04 seconds
Started Jun 27 06:24:30 PM PDT 24
Finished Jun 27 06:24:46 PM PDT 24
Peak memory 224988 kb
Host smart-10bdc72b-b584-4627-ba95-f2e4569cf179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951438543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2951438543
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3407040645
Short name T246
Test name
Test status
Simulation time 21086679300 ps
CPU time 152.45 seconds
Started Jun 27 06:24:35 PM PDT 24
Finished Jun 27 06:27:17 PM PDT 24
Peak memory 236056 kb
Host smart-d538c0aa-f473-4563-bd1f-ffa59a8d00aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407040645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3407040645
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3753426563
Short name T884
Test name
Test status
Simulation time 649386480 ps
CPU time 2.3 seconds
Started Jun 27 06:24:30 PM PDT 24
Finished Jun 27 06:24:42 PM PDT 24
Peak memory 224552 kb
Host smart-d26e768c-7a4a-4563-b4e5-44d85a51bfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753426563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3753426563
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.691349115
Short name T2
Test name
Test status
Simulation time 1044396940 ps
CPU time 6.07 seconds
Started Jun 27 06:24:32 PM PDT 24
Finished Jun 27 06:24:48 PM PDT 24
Peak memory 241376 kb
Host smart-a9cd896b-dc36-4a32-8b84-359916dc83c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691349115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.691349115
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2772360319
Short name T351
Test name
Test status
Simulation time 2525576462 ps
CPU time 7.74 seconds
Started Jun 27 06:24:32 PM PDT 24
Finished Jun 27 06:24:49 PM PDT 24
Peak memory 222964 kb
Host smart-3a838bbe-6c51-4e57-9874-c76338e63dcd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2772360319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2772360319
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1720149684
Short name T10
Test name
Test status
Simulation time 44030776 ps
CPU time 0.92 seconds
Started Jun 27 06:24:38 PM PDT 24
Finished Jun 27 06:24:47 PM PDT 24
Peak memory 207460 kb
Host smart-5818371a-b4f9-4795-9e03-4726d5badd2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720149684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1720149684
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1516495559
Short name T323
Test name
Test status
Simulation time 6291377577 ps
CPU time 7.75 seconds
Started Jun 27 06:24:34 PM PDT 24
Finished Jun 27 06:24:50 PM PDT 24
Peak memory 216936 kb
Host smart-9583c24b-e0c0-4d6a-be0a-435857898a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516495559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1516495559
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.272714712
Short name T845
Test name
Test status
Simulation time 11645656027 ps
CPU time 5.98 seconds
Started Jun 27 06:24:17 PM PDT 24
Finished Jun 27 06:24:31 PM PDT 24
Peak memory 216904 kb
Host smart-03d293be-5946-4242-81c8-0ffc274f4795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272714712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.272714712
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2189791710
Short name T376
Test name
Test status
Simulation time 49796960 ps
CPU time 0.87 seconds
Started Jun 27 06:24:34 PM PDT 24
Finished Jun 27 06:24:44 PM PDT 24
Peak memory 207124 kb
Host smart-4dcdaa9a-0874-42f3-bc28-56ec5572789c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189791710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2189791710
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.628998872
Short name T465
Test name
Test status
Simulation time 102887768 ps
CPU time 1.04 seconds
Started Jun 27 06:24:22 PM PDT 24
Finished Jun 27 06:24:32 PM PDT 24
Peak memory 207492 kb
Host smart-2f4c39fb-2e99-431a-99b0-5348c8dd9ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628998872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.628998872
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.4208162720
Short name T972
Test name
Test status
Simulation time 2619232974 ps
CPU time 11.67 seconds
Started Jun 27 06:24:32 PM PDT 24
Finished Jun 27 06:24:53 PM PDT 24
Peak memory 241060 kb
Host smart-c2d15459-ce8a-4e0c-ab00-8a735d81793c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208162720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4208162720
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.905473853
Short name T996
Test name
Test status
Simulation time 11909587 ps
CPU time 0.71 seconds
Started Jun 27 06:24:29 PM PDT 24
Finished Jun 27 06:24:39 PM PDT 24
Peak memory 205372 kb
Host smart-d848af75-c461-475b-a1dc-318921359143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905473853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.905473853
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.948079579
Short name T514
Test name
Test status
Simulation time 3767698113 ps
CPU time 32.17 seconds
Started Jun 27 06:24:33 PM PDT 24
Finished Jun 27 06:25:14 PM PDT 24
Peak memory 225112 kb
Host smart-23f42e6f-683b-4160-81c5-d9b37ff063ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948079579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.948079579
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.860049624
Short name T537
Test name
Test status
Simulation time 17031349 ps
CPU time 0.77 seconds
Started Jun 27 06:24:34 PM PDT 24
Finished Jun 27 06:24:44 PM PDT 24
Peak memory 207432 kb
Host smart-f109ad37-1c51-4005-9b16-37ff884eff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860049624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.860049624
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.894630178
Short name T746
Test name
Test status
Simulation time 5906123987 ps
CPU time 60.8 seconds
Started Jun 27 06:24:35 PM PDT 24
Finished Jun 27 06:25:45 PM PDT 24
Peak memory 257652 kb
Host smart-8929357b-e478-4eb9-a3fe-869bbb378ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894630178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.894630178
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1753506976
Short name T189
Test name
Test status
Simulation time 12200805386 ps
CPU time 150.21 seconds
Started Jun 27 06:24:33 PM PDT 24
Finished Jun 27 06:27:12 PM PDT 24
Peak memory 249820 kb
Host smart-d4dc6ab5-7937-448e-bac8-048bfca06e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753506976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1753506976
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2670213704
Short name T6
Test name
Test status
Simulation time 74972156 ps
CPU time 3.03 seconds
Started Jun 27 06:24:27 PM PDT 24
Finished Jun 27 06:24:40 PM PDT 24
Peak memory 233220 kb
Host smart-a147fd0c-30a8-465a-805c-122058590555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670213704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2670213704
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.102571609
Short name T471
Test name
Test status
Simulation time 1005613848 ps
CPU time 10.32 seconds
Started Jun 27 06:24:27 PM PDT 24
Finished Jun 27 06:24:47 PM PDT 24
Peak memory 234608 kb
Host smart-1a36a1ab-0953-46d6-b369-6c61be284d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102571609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.102571609
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3679449533
Short name T470
Test name
Test status
Simulation time 254793206 ps
CPU time 3.66 seconds
Started Jun 27 06:24:28 PM PDT 24
Finished Jun 27 06:24:41 PM PDT 24
Peak memory 233184 kb
Host smart-9107c507-b83e-4727-9bb9-84a15f14328b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679449533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3679449533
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3164097807
Short name T838
Test name
Test status
Simulation time 1408876081 ps
CPU time 4.99 seconds
Started Jun 27 06:24:33 PM PDT 24
Finished Jun 27 06:24:47 PM PDT 24
Peak memory 233168 kb
Host smart-f12f6cba-f729-463f-a919-2ede7a84438e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164097807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3164097807
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3986752957
Short name T893
Test name
Test status
Simulation time 5892985241 ps
CPU time 9.44 seconds
Started Jun 27 06:24:30 PM PDT 24
Finished Jun 27 06:24:49 PM PDT 24
Peak memory 225160 kb
Host smart-40513a0a-d7a1-4b50-907e-c2dd0e0da0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986752957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3986752957
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1204257162
Short name T966
Test name
Test status
Simulation time 716599452 ps
CPU time 4.7 seconds
Started Jun 27 06:24:39 PM PDT 24
Finished Jun 27 06:24:52 PM PDT 24
Peak memory 224964 kb
Host smart-7ab4ac36-4230-4f99-a9aa-725a2cb37464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204257162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1204257162
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.242981943
Short name T750
Test name
Test status
Simulation time 932504926 ps
CPU time 8.44 seconds
Started Jun 27 06:24:32 PM PDT 24
Finished Jun 27 06:24:50 PM PDT 24
Peak memory 222440 kb
Host smart-5f75a95a-8b8a-4763-b40a-bbb57066ecc1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=242981943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.242981943
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3201935903
Short name T688
Test name
Test status
Simulation time 30743591157 ps
CPU time 282.6 seconds
Started Jun 27 06:24:20 PM PDT 24
Finished Jun 27 06:29:11 PM PDT 24
Peak memory 258016 kb
Host smart-87c557fd-32e9-4574-b8ac-5ed3fce23b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201935903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3201935903
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1366380875
Short name T478
Test name
Test status
Simulation time 3129106961 ps
CPU time 16.52 seconds
Started Jun 27 06:24:30 PM PDT 24
Finished Jun 27 06:24:56 PM PDT 24
Peak memory 216940 kb
Host smart-01ac6da2-3a24-4e0e-a3de-ad1ae28307e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366380875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1366380875
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.284143293
Short name T729
Test name
Test status
Simulation time 1497478561 ps
CPU time 3.98 seconds
Started Jun 27 06:24:28 PM PDT 24
Finished Jun 27 06:24:41 PM PDT 24
Peak memory 216804 kb
Host smart-ab61e560-98ac-4748-85de-1bfa3cd7b472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284143293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.284143293
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2311309646
Short name T832
Test name
Test status
Simulation time 207454825 ps
CPU time 1.66 seconds
Started Jun 27 06:24:37 PM PDT 24
Finished Jun 27 06:24:47 PM PDT 24
Peak memory 216812 kb
Host smart-ac1a54c8-bb26-4b73-a5a2-02c2f5e205ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311309646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2311309646
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1257069067
Short name T440
Test name
Test status
Simulation time 119950343 ps
CPU time 0.76 seconds
Started Jun 27 06:24:21 PM PDT 24
Finished Jun 27 06:24:30 PM PDT 24
Peak memory 206464 kb
Host smart-bee61157-5488-4911-a3fb-ad935f5e2f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257069067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1257069067
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2211297039
Short name T658
Test name
Test status
Simulation time 20792064146 ps
CPU time 15.37 seconds
Started Jun 27 06:24:32 PM PDT 24
Finished Jun 27 06:24:57 PM PDT 24
Peak memory 225048 kb
Host smart-b0c44b8e-25d7-4507-9b33-bb2960b2045e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211297039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2211297039
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1611600180
Short name T670
Test name
Test status
Simulation time 19934779 ps
CPU time 0.73 seconds
Started Jun 27 06:22:59 PM PDT 24
Finished Jun 27 06:23:09 PM PDT 24
Peak memory 206212 kb
Host smart-6b4cbfb7-153c-4226-86f1-b28839435090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611600180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
611600180
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2006946566
Short name T237
Test name
Test status
Simulation time 119200243 ps
CPU time 2.56 seconds
Started Jun 27 06:23:14 PM PDT 24
Finished Jun 27 06:23:25 PM PDT 24
Peak memory 225000 kb
Host smart-8bc3fbae-76c7-4cee-981a-ebabe0569b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006946566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2006946566
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3608250517
Short name T603
Test name
Test status
Simulation time 22498904 ps
CPU time 0.79 seconds
Started Jun 27 06:22:58 PM PDT 24
Finished Jun 27 06:23:08 PM PDT 24
Peak memory 207436 kb
Host smart-2afd4c81-de9d-4ad9-b094-40f7028759df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608250517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3608250517
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2231627704
Short name T887
Test name
Test status
Simulation time 9967601646 ps
CPU time 81.14 seconds
Started Jun 27 06:23:15 PM PDT 24
Finished Jun 27 06:24:43 PM PDT 24
Peak memory 267072 kb
Host smart-d52ea994-f3f2-4875-b286-a148b6231512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231627704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2231627704
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3977628475
Short name T581
Test name
Test status
Simulation time 24177407171 ps
CPU time 122.01 seconds
Started Jun 27 06:23:14 PM PDT 24
Finished Jun 27 06:25:24 PM PDT 24
Peak memory 249864 kb
Host smart-1336b326-9c23-420b-8e25-a2d58487a63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977628475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3977628475
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.693669574
Short name T982
Test name
Test status
Simulation time 13519009429 ps
CPU time 19.49 seconds
Started Jun 27 06:23:13 PM PDT 24
Finished Jun 27 06:23:40 PM PDT 24
Peak memory 238004 kb
Host smart-85828155-52e3-4c79-8920-bfc6a8ccd8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693669574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.693669574
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3848026419
Short name T922
Test name
Test status
Simulation time 19564075672 ps
CPU time 72.38 seconds
Started Jun 27 06:23:11 PM PDT 24
Finished Jun 27 06:24:31 PM PDT 24
Peak memory 256788 kb
Host smart-ad8f13a9-d045-4f1a-8cb9-d4859a5d2da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848026419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3848026419
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.376656504
Short name T553
Test name
Test status
Simulation time 890583719 ps
CPU time 11.99 seconds
Started Jun 27 06:23:24 PM PDT 24
Finished Jun 27 06:23:40 PM PDT 24
Peak memory 225064 kb
Host smart-aed24a79-e9a5-40f1-b43d-d3e2ddeaf5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376656504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.376656504
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2342560965
Short name T360
Test name
Test status
Simulation time 3240608642 ps
CPU time 7.21 seconds
Started Jun 27 06:23:05 PM PDT 24
Finished Jun 27 06:23:21 PM PDT 24
Peak memory 233376 kb
Host smart-b697b3ab-d136-420d-9763-48be4ebf77f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342560965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2342560965
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.516640520
Short name T843
Test name
Test status
Simulation time 2285539770 ps
CPU time 4.98 seconds
Started Jun 27 06:22:58 PM PDT 24
Finished Jun 27 06:23:12 PM PDT 24
Peak memory 233292 kb
Host smart-64df7149-0778-447c-980a-7996eac14c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516640520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
516640520
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2843079171
Short name T682
Test name
Test status
Simulation time 11730816403 ps
CPU time 10.9 seconds
Started Jun 27 06:23:13 PM PDT 24
Finished Jun 27 06:23:32 PM PDT 24
Peak memory 225120 kb
Host smart-9cc8ad49-fb21-436c-a103-115bc51905af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843079171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2843079171
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.296267087
Short name T538
Test name
Test status
Simulation time 426190013 ps
CPU time 5.94 seconds
Started Jun 27 06:23:05 PM PDT 24
Finished Jun 27 06:23:20 PM PDT 24
Peak memory 220748 kb
Host smart-ec62d5ae-a9c2-4370-82c0-363ae0f187b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=296267087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.296267087
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1873621768
Short name T73
Test name
Test status
Simulation time 57074861 ps
CPU time 0.93 seconds
Started Jun 27 06:23:14 PM PDT 24
Finished Jun 27 06:23:23 PM PDT 24
Peak memory 234916 kb
Host smart-e704c868-afa0-4062-b98c-48013057314d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873621768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1873621768
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1182904037
Short name T498
Test name
Test status
Simulation time 50757223 ps
CPU time 1.01 seconds
Started Jun 27 06:23:13 PM PDT 24
Finished Jun 27 06:23:22 PM PDT 24
Peak memory 207416 kb
Host smart-6ca3e56d-8b9c-4990-bd75-b7a9c71cef8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182904037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1182904037
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.301324329
Short name T322
Test name
Test status
Simulation time 9873708300 ps
CPU time 24.92 seconds
Started Jun 27 06:22:58 PM PDT 24
Finished Jun 27 06:23:33 PM PDT 24
Peak memory 221460 kb
Host smart-ccb88f6b-6683-4816-8043-0dbeacb0d135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301324329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.301324329
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4042884295
Short name T651
Test name
Test status
Simulation time 1673113411 ps
CPU time 9.2 seconds
Started Jun 27 06:23:12 PM PDT 24
Finished Jun 27 06:23:29 PM PDT 24
Peak memory 216832 kb
Host smart-bf9957eb-5c69-44f1-a132-d74f0374bdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042884295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4042884295
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3246525907
Short name T891
Test name
Test status
Simulation time 151558092 ps
CPU time 1.22 seconds
Started Jun 27 06:23:13 PM PDT 24
Finished Jun 27 06:23:22 PM PDT 24
Peak memory 216800 kb
Host smart-d5ef6f13-2cd9-4323-9a3c-0ea434984217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246525907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3246525907
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.300058456
Short name T475
Test name
Test status
Simulation time 22075296 ps
CPU time 0.72 seconds
Started Jun 27 06:23:11 PM PDT 24
Finished Jun 27 06:23:20 PM PDT 24
Peak memory 206144 kb
Host smart-4c291efe-6690-4766-b053-8d7d5236313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300058456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.300058456
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.559796340
Short name T925
Test name
Test status
Simulation time 38318108173 ps
CPU time 26.66 seconds
Started Jun 27 06:23:26 PM PDT 24
Finished Jun 27 06:23:57 PM PDT 24
Peak memory 233236 kb
Host smart-a938c58d-e7c9-4fc0-8dfe-d3da93a46647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559796340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.559796340
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.282692984
Short name T640
Test name
Test status
Simulation time 38836402 ps
CPU time 0.75 seconds
Started Jun 27 06:24:46 PM PDT 24
Finished Jun 27 06:24:54 PM PDT 24
Peak memory 205964 kb
Host smart-74377d48-1fb1-400e-90ae-504dd286f1cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282692984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.282692984
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.410784967
Short name T130
Test name
Test status
Simulation time 108722172 ps
CPU time 3.62 seconds
Started Jun 27 06:24:29 PM PDT 24
Finished Jun 27 06:24:42 PM PDT 24
Peak memory 224904 kb
Host smart-f674e5e4-b4a7-4c83-a188-64179254f9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410784967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.410784967
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4019972950
Short name T866
Test name
Test status
Simulation time 94568556 ps
CPU time 0.81 seconds
Started Jun 27 06:24:33 PM PDT 24
Finished Jun 27 06:24:43 PM PDT 24
Peak memory 207080 kb
Host smart-c852b865-c7e6-46be-a539-487db12e731f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019972950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4019972950
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.521338150
Short name T477
Test name
Test status
Simulation time 15223104787 ps
CPU time 113.29 seconds
Started Jun 27 06:24:23 PM PDT 24
Finished Jun 27 06:26:25 PM PDT 24
Peak memory 253140 kb
Host smart-4546ebce-f5d7-4a6f-a699-5d63665e63a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521338150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.521338150
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.868772620
Short name T896
Test name
Test status
Simulation time 2445768385 ps
CPU time 19.47 seconds
Started Jun 27 06:24:29 PM PDT 24
Finished Jun 27 06:24:58 PM PDT 24
Peak memory 220124 kb
Host smart-aecc49c8-68ba-4a73-af25-206e0f77b2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868772620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.868772620
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.896489595
Short name T840
Test name
Test status
Simulation time 1536125083 ps
CPU time 19.21 seconds
Started Jun 27 06:24:47 PM PDT 24
Finished Jun 27 06:25:14 PM PDT 24
Peak memory 233348 kb
Host smart-7bd41d2d-73a9-4480-9587-2359ffdd486d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896489595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.896489595
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1625119998
Short name T459
Test name
Test status
Simulation time 769629236 ps
CPU time 17.24 seconds
Started Jun 27 06:24:20 PM PDT 24
Finished Jun 27 06:24:46 PM PDT 24
Peak memory 233204 kb
Host smart-596775dc-6416-46b6-87f0-be40f193fb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625119998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1625119998
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3452263236
Short name T624
Test name
Test status
Simulation time 24170097943 ps
CPU time 125.07 seconds
Started Jun 27 06:24:28 PM PDT 24
Finished Jun 27 06:26:42 PM PDT 24
Peak memory 241528 kb
Host smart-84fc5a8a-965b-4964-ab6e-50c2f6958949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452263236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3452263236
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3484417839
Short name T230
Test name
Test status
Simulation time 129664172 ps
CPU time 2.19 seconds
Started Jun 27 06:24:30 PM PDT 24
Finished Jun 27 06:24:42 PM PDT 24
Peak memory 224976 kb
Host smart-f48b5621-2be4-49c0-adc0-edf6df5916d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484417839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3484417839
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3283943210
Short name T590
Test name
Test status
Simulation time 1976768426 ps
CPU time 25.51 seconds
Started Jun 27 06:24:19 PM PDT 24
Finished Jun 27 06:24:53 PM PDT 24
Peak memory 249520 kb
Host smart-f42de850-621f-4ac9-b720-5885f4067420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283943210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3283943210
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.253608068
Short name T398
Test name
Test status
Simulation time 587118005 ps
CPU time 3.04 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:29 PM PDT 24
Peak memory 225020 kb
Host smart-c8971b17-3cdc-408e-8267-34abee4eb8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253608068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.253608068
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3992823429
Short name T464
Test name
Test status
Simulation time 25308172674 ps
CPU time 24.05 seconds
Started Jun 27 06:24:28 PM PDT 24
Finished Jun 27 06:25:02 PM PDT 24
Peak memory 249060 kb
Host smart-89e270ea-a61a-448d-b59b-6394fe846b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992823429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3992823429
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2633323595
Short name T703
Test name
Test status
Simulation time 680403003 ps
CPU time 7.36 seconds
Started Jun 27 06:24:23 PM PDT 24
Finished Jun 27 06:24:39 PM PDT 24
Peak memory 219624 kb
Host smart-d221601d-319d-4e0e-bd2f-a613bc985a76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2633323595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2633323595
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1148132583
Short name T33
Test name
Test status
Simulation time 173393550 ps
CPU time 0.95 seconds
Started Jun 27 06:24:48 PM PDT 24
Finished Jun 27 06:24:57 PM PDT 24
Peak memory 207104 kb
Host smart-887378a4-9238-4041-8f50-3ad15d7b0e80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148132583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1148132583
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4192247734
Short name T644
Test name
Test status
Simulation time 36542776 ps
CPU time 0.69 seconds
Started Jun 27 06:24:18 PM PDT 24
Finished Jun 27 06:24:28 PM PDT 24
Peak memory 206232 kb
Host smart-59a1c7bb-e46d-489c-a2bc-22cf31ae5522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192247734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4192247734
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3341693755
Short name T719
Test name
Test status
Simulation time 79521586 ps
CPU time 1.82 seconds
Started Jun 27 06:24:29 PM PDT 24
Finished Jun 27 06:24:41 PM PDT 24
Peak memory 216792 kb
Host smart-2e63b3bf-56e1-4308-9983-295ca0d4c80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341693755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3341693755
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2129791910
Short name T4
Test name
Test status
Simulation time 744888771 ps
CPU time 0.89 seconds
Started Jun 27 06:24:20 PM PDT 24
Finished Jun 27 06:24:29 PM PDT 24
Peak memory 206752 kb
Host smart-3c9822ef-678a-42ae-ae53-a520973ce06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129791910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2129791910
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.583895595
Short name T808
Test name
Test status
Simulation time 467532526 ps
CPU time 3.07 seconds
Started Jun 27 06:24:22 PM PDT 24
Finished Jun 27 06:24:34 PM PDT 24
Peak memory 224912 kb
Host smart-64e00100-3dad-46ca-b56e-920576a0bc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583895595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.583895595
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2204001472
Short name T414
Test name
Test status
Simulation time 22756715 ps
CPU time 0.72 seconds
Started Jun 27 06:24:44 PM PDT 24
Finished Jun 27 06:24:52 PM PDT 24
Peak memory 205944 kb
Host smart-d8da560f-36c0-48d5-acff-1b800edb357e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204001472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2204001472
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4488660
Short name T551
Test name
Test status
Simulation time 164537963 ps
CPU time 4.05 seconds
Started Jun 27 06:24:43 PM PDT 24
Finished Jun 27 06:24:55 PM PDT 24
Peak memory 225008 kb
Host smart-7b9c131a-41a8-4694-ab2a-a91e1e73fa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4488660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4488660
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.40741124
Short name T540
Test name
Test status
Simulation time 27449366 ps
CPU time 0.78 seconds
Started Jun 27 06:24:45 PM PDT 24
Finished Jun 27 06:24:53 PM PDT 24
Peak memory 206028 kb
Host smart-8ace958f-5c1e-487a-9c5d-690d338f3ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40741124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.40741124
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3432193752
Short name T287
Test name
Test status
Simulation time 3672005080 ps
CPU time 50.29 seconds
Started Jun 27 06:24:49 PM PDT 24
Finished Jun 27 06:25:48 PM PDT 24
Peak memory 257040 kb
Host smart-4cb7be25-297d-4328-b627-0d6a6d5365a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432193752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3432193752
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1693229030
Short name T905
Test name
Test status
Simulation time 3935925599 ps
CPU time 61.13 seconds
Started Jun 27 06:24:45 PM PDT 24
Finished Jun 27 06:25:54 PM PDT 24
Peak memory 251488 kb
Host smart-776cd1fe-0291-4d74-9213-36d7ec5ad6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693229030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1693229030
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2946559465
Short name T226
Test name
Test status
Simulation time 9595123625 ps
CPU time 56.51 seconds
Started Jun 27 06:24:45 PM PDT 24
Finished Jun 27 06:25:49 PM PDT 24
Peak memory 253892 kb
Host smart-1ac50c8a-8d08-4e0c-a53a-8385c1646e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946559465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2946559465
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.896534707
Short name T733
Test name
Test status
Simulation time 5879417021 ps
CPU time 43.29 seconds
Started Jun 27 06:24:46 PM PDT 24
Finished Jun 27 06:25:37 PM PDT 24
Peak memory 252792 kb
Host smart-cd924e42-c780-4295-a3e0-0fd53f37be6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896534707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.896534707
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.841844944
Short name T191
Test name
Test status
Simulation time 822150671 ps
CPU time 4.4 seconds
Started Jun 27 06:24:48 PM PDT 24
Finished Jun 27 06:25:00 PM PDT 24
Peak memory 219332 kb
Host smart-ba47b437-d295-448a-9645-393aa2f0b9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841844944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.841844944
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.993447523
Short name T128
Test name
Test status
Simulation time 7753911827 ps
CPU time 81.22 seconds
Started Jun 27 06:24:44 PM PDT 24
Finished Jun 27 06:26:13 PM PDT 24
Peak memory 225156 kb
Host smart-908d6466-a2a9-4cc0-98ee-dbaff0539c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993447523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.993447523
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.435189386
Short name T502
Test name
Test status
Simulation time 437779327 ps
CPU time 5.05 seconds
Started Jun 27 06:24:46 PM PDT 24
Finished Jun 27 06:24:58 PM PDT 24
Peak memory 240936 kb
Host smart-c0cf6549-288a-46f8-8632-9b0495935d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435189386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.435189386
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2747469453
Short name T577
Test name
Test status
Simulation time 795196730 ps
CPU time 4.4 seconds
Started Jun 27 06:24:47 PM PDT 24
Finished Jun 27 06:24:59 PM PDT 24
Peak memory 237896 kb
Host smart-d55f7327-74f3-457c-bf95-6d10f21810b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747469453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2747469453
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2917967575
Short name T675
Test name
Test status
Simulation time 382020430 ps
CPU time 6.16 seconds
Started Jun 27 06:24:49 PM PDT 24
Finished Jun 27 06:25:03 PM PDT 24
Peak memory 220880 kb
Host smart-0b64c10a-ffb6-40bb-96a2-e91adc18d654
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2917967575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2917967575
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.771385105
Short name T34
Test name
Test status
Simulation time 6326639155 ps
CPU time 33.13 seconds
Started Jun 27 06:24:45 PM PDT 24
Finished Jun 27 06:25:26 PM PDT 24
Peak memory 225244 kb
Host smart-a72062f4-eaef-41f1-9280-dcd0f6697279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771385105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.771385105
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2031603283
Short name T971
Test name
Test status
Simulation time 2306418011 ps
CPU time 6.01 seconds
Started Jun 27 06:24:47 PM PDT 24
Finished Jun 27 06:25:01 PM PDT 24
Peak memory 219832 kb
Host smart-8e9eb12c-3d30-4c99-b259-0191f25ff259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031603283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2031603283
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.951176927
Short name T431
Test name
Test status
Simulation time 1073406293 ps
CPU time 2.02 seconds
Started Jun 27 06:24:44 PM PDT 24
Finished Jun 27 06:24:53 PM PDT 24
Peak memory 208392 kb
Host smart-eba155d9-fcac-4579-b2fb-5d92fe59cb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951176927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.951176927
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.184689196
Short name T804
Test name
Test status
Simulation time 133358557 ps
CPU time 1.48 seconds
Started Jun 27 06:24:45 PM PDT 24
Finished Jun 27 06:24:54 PM PDT 24
Peak memory 216836 kb
Host smart-4b8de3fa-41db-4e21-a5dd-7451db66823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184689196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.184689196
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1227871007
Short name T712
Test name
Test status
Simulation time 36161017 ps
CPU time 0.84 seconds
Started Jun 27 06:24:41 PM PDT 24
Finished Jun 27 06:24:50 PM PDT 24
Peak memory 206396 kb
Host smart-574abdb9-069c-459d-9bff-83d212429a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227871007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1227871007
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3104140751
Short name T811
Test name
Test status
Simulation time 15056021504 ps
CPU time 9.76 seconds
Started Jun 27 06:24:45 PM PDT 24
Finished Jun 27 06:25:03 PM PDT 24
Peak memory 233316 kb
Host smart-55f6b4f6-66a8-4ae0-af95-7764a35b9103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104140751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3104140751
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3037225740
Short name T600
Test name
Test status
Simulation time 11787647 ps
CPU time 0.74 seconds
Started Jun 27 06:24:47 PM PDT 24
Finished Jun 27 06:24:55 PM PDT 24
Peak memory 205932 kb
Host smart-a76adf3e-d31d-4a77-8063-e5214c3e8178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037225740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3037225740
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2607962353
Short name T480
Test name
Test status
Simulation time 1888473487 ps
CPU time 10.2 seconds
Started Jun 27 06:24:49 PM PDT 24
Finished Jun 27 06:25:07 PM PDT 24
Peak memory 225036 kb
Host smart-3d67da03-dce2-4548-bc48-466228d04edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607962353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2607962353
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2563790078
Short name T768
Test name
Test status
Simulation time 59992469 ps
CPU time 0.8 seconds
Started Jun 27 06:24:48 PM PDT 24
Finished Jun 27 06:24:56 PM PDT 24
Peak memory 207452 kb
Host smart-38b3b0b7-70c2-4ef5-93d8-844eb29f343c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563790078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2563790078
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3199614483
Short name T827
Test name
Test status
Simulation time 1031055466 ps
CPU time 4.75 seconds
Started Jun 27 06:24:47 PM PDT 24
Finished Jun 27 06:25:00 PM PDT 24
Peak memory 225036 kb
Host smart-3f434ecb-9e6a-4999-9ae2-ba9c7cb9af40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199614483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3199614483
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1391744198
Short name T43
Test name
Test status
Simulation time 19204125431 ps
CPU time 45.66 seconds
Started Jun 27 06:24:50 PM PDT 24
Finished Jun 27 06:25:44 PM PDT 24
Peak memory 249848 kb
Host smart-a1daad83-de13-4a3c-8926-edcf587ec13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391744198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1391744198
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3258320440
Short name T598
Test name
Test status
Simulation time 1136981943 ps
CPU time 9.92 seconds
Started Jun 27 06:24:46 PM PDT 24
Finished Jun 27 06:25:04 PM PDT 24
Peak memory 233204 kb
Host smart-11dbd01c-a2eb-4277-9a07-ecf27fac928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258320440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3258320440
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3987059225
Short name T364
Test name
Test status
Simulation time 38697172 ps
CPU time 2.33 seconds
Started Jun 27 06:24:47 PM PDT 24
Finished Jun 27 06:24:57 PM PDT 24
Peak memory 225016 kb
Host smart-4c7a5b45-7719-4652-b5d9-eca40493e44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987059225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3987059225
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1225331587
Short name T93
Test name
Test status
Simulation time 5702933072 ps
CPU time 34.78 seconds
Started Jun 27 06:24:48 PM PDT 24
Finished Jun 27 06:25:31 PM PDT 24
Peak memory 249676 kb
Host smart-3c9f2e68-6390-4887-bc4e-89bd8efa728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225331587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1225331587
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1810303882
Short name T556
Test name
Test status
Simulation time 112453251 ps
CPU time 2.27 seconds
Started Jun 27 06:24:46 PM PDT 24
Finished Jun 27 06:24:56 PM PDT 24
Peak memory 224972 kb
Host smart-6d277601-7aae-46d6-b18c-e5aa9a4aea69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810303882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1810303882
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2438808682
Short name T187
Test name
Test status
Simulation time 9878931360 ps
CPU time 86.05 seconds
Started Jun 27 06:24:45 PM PDT 24
Finished Jun 27 06:26:19 PM PDT 24
Peak memory 233328 kb
Host smart-c81d6012-572e-459f-927b-567618b3d444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438808682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2438808682
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3068190706
Short name T692
Test name
Test status
Simulation time 1135891134 ps
CPU time 9.47 seconds
Started Jun 27 06:24:49 PM PDT 24
Finished Jun 27 06:25:07 PM PDT 24
Peak memory 237240 kb
Host smart-3a673528-fbac-4974-8c75-bd484eb4f5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068190706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3068190706
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.894011961
Short name T167
Test name
Test status
Simulation time 1708497936 ps
CPU time 8.63 seconds
Started Jun 27 06:24:43 PM PDT 24
Finished Jun 27 06:25:00 PM PDT 24
Peak memory 233152 kb
Host smart-cef8cdc5-646d-4b90-aa64-b095e58691f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894011961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.894011961
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3742893043
Short name T758
Test name
Test status
Simulation time 1031958253 ps
CPU time 9.3 seconds
Started Jun 27 06:24:49 PM PDT 24
Finished Jun 27 06:25:06 PM PDT 24
Peak memory 223564 kb
Host smart-c8f2724f-28ef-4d62-84d3-d97556a6cdd4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3742893043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3742893043
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2159592913
Short name T61
Test name
Test status
Simulation time 141553701410 ps
CPU time 221.86 seconds
Started Jun 27 06:24:50 PM PDT 24
Finished Jun 27 06:28:40 PM PDT 24
Peak memory 250676 kb
Host smart-161caf2a-6758-4e30-b3ac-06533a7a21aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159592913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2159592913
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3412834220
Short name T483
Test name
Test status
Simulation time 755580625 ps
CPU time 3.11 seconds
Started Jun 27 06:24:43 PM PDT 24
Finished Jun 27 06:24:54 PM PDT 24
Peak memory 216864 kb
Host smart-2716c953-6eab-403d-b8b9-dfcd501caa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412834220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3412834220
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1900661549
Short name T721
Test name
Test status
Simulation time 3053602941 ps
CPU time 5.06 seconds
Started Jun 27 06:24:42 PM PDT 24
Finished Jun 27 06:24:55 PM PDT 24
Peak memory 216912 kb
Host smart-6f6210db-d4b0-4d79-9dfe-bd3f1e151af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900661549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1900661549
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2603926804
Short name T380
Test name
Test status
Simulation time 80101558 ps
CPU time 0.9 seconds
Started Jun 27 06:24:45 PM PDT 24
Finished Jun 27 06:24:54 PM PDT 24
Peak memory 207664 kb
Host smart-d9016c77-85a3-4101-972b-f2159701e882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603926804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2603926804
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.659339357
Short name T28
Test name
Test status
Simulation time 170025782 ps
CPU time 0.84 seconds
Started Jun 27 06:24:47 PM PDT 24
Finished Jun 27 06:24:56 PM PDT 24
Peak memory 206472 kb
Host smart-3f8ef995-a9d6-4322-87ba-31143c2113f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659339357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.659339357
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.745881769
Short name T337
Test name
Test status
Simulation time 291244823 ps
CPU time 3.26 seconds
Started Jun 27 06:24:47 PM PDT 24
Finished Jun 27 06:24:58 PM PDT 24
Peak memory 228168 kb
Host smart-5189f9ad-1221-497b-aed4-d888cc7331fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745881769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.745881769
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.348763251
Short name T630
Test name
Test status
Simulation time 13975309 ps
CPU time 0.72 seconds
Started Jun 27 06:24:50 PM PDT 24
Finished Jun 27 06:24:59 PM PDT 24
Peak memory 206328 kb
Host smart-1f081156-2809-4e60-9dbd-afffb04adddf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348763251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.348763251
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1100051793
Short name T567
Test name
Test status
Simulation time 788820338 ps
CPU time 3.88 seconds
Started Jun 27 06:24:46 PM PDT 24
Finished Jun 27 06:24:57 PM PDT 24
Peak memory 225040 kb
Host smart-7336f2a9-cefd-46dd-a354-d78ee82b98a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100051793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1100051793
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4286615842
Short name T347
Test name
Test status
Simulation time 14934695 ps
CPU time 0.78 seconds
Started Jun 27 06:24:43 PM PDT 24
Finished Jun 27 06:24:52 PM PDT 24
Peak memory 207096 kb
Host smart-c4dcce6c-b21d-48f1-8d11-bf8a8c6f4822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286615842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4286615842
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1902489961
Short name T812
Test name
Test status
Simulation time 36621499913 ps
CPU time 259.42 seconds
Started Jun 27 06:24:47 PM PDT 24
Finished Jun 27 06:29:14 PM PDT 24
Peak memory 254592 kb
Host smart-d9939789-7d30-442d-a2e4-f8a6921e32b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902489961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1902489961
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.175337156
Short name T741
Test name
Test status
Simulation time 38398772607 ps
CPU time 110.69 seconds
Started Jun 27 06:24:51 PM PDT 24
Finished Jun 27 06:26:49 PM PDT 24
Peak memory 252088 kb
Host smart-d2afc6e6-863f-44e5-adce-d70a84398d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175337156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.175337156
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3007568319
Short name T691
Test name
Test status
Simulation time 191858168 ps
CPU time 2.68 seconds
Started Jun 27 06:24:44 PM PDT 24
Finished Jun 27 06:24:54 PM PDT 24
Peak memory 224896 kb
Host smart-c80848d9-2d53-4a22-9361-2a2daa0c15e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007568319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3007568319
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2267246249
Short name T257
Test name
Test status
Simulation time 103675084111 ps
CPU time 84.87 seconds
Started Jun 27 06:24:49 PM PDT 24
Finished Jun 27 06:26:22 PM PDT 24
Peak memory 241120 kb
Host smart-2efebbb3-9892-4981-9b3e-bc6d1e4f6178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267246249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2267246249
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2285191113
Short name T96
Test name
Test status
Simulation time 670661921 ps
CPU time 3.72 seconds
Started Jun 27 06:24:46 PM PDT 24
Finished Jun 27 06:24:58 PM PDT 24
Peak memory 224988 kb
Host smart-ab61cb68-c4dd-4977-a611-476a10c92fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285191113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2285191113
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2456266355
Short name T263
Test name
Test status
Simulation time 22453314403 ps
CPU time 71.37 seconds
Started Jun 27 06:24:48 PM PDT 24
Finished Jun 27 06:26:07 PM PDT 24
Peak memory 240508 kb
Host smart-490870bd-b9dd-4627-9ba2-7b3a577df3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456266355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2456266355
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1147166062
Short name T297
Test name
Test status
Simulation time 2496047036 ps
CPU time 8.55 seconds
Started Jun 27 06:24:53 PM PDT 24
Finished Jun 27 06:25:08 PM PDT 24
Peak memory 233180 kb
Host smart-a0c7025b-4a78-4089-96bd-c210dd5964f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147166062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1147166062
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2027263249
Short name T628
Test name
Test status
Simulation time 723570772 ps
CPU time 6.44 seconds
Started Jun 27 06:24:49 PM PDT 24
Finished Jun 27 06:25:04 PM PDT 24
Peak memory 233120 kb
Host smart-ac4541a9-b082-4e33-a118-83acfcace239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027263249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2027263249
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2328707283
Short name T146
Test name
Test status
Simulation time 1715014449 ps
CPU time 6.41 seconds
Started Jun 27 06:24:48 PM PDT 24
Finished Jun 27 06:25:03 PM PDT 24
Peak memory 224036 kb
Host smart-0233a841-7d6a-4001-9170-eebc65db92e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2328707283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2328707283
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2522378607
Short name T156
Test name
Test status
Simulation time 260432177 ps
CPU time 1.15 seconds
Started Jun 27 06:24:50 PM PDT 24
Finished Jun 27 06:24:59 PM PDT 24
Peak memory 207552 kb
Host smart-95b056be-45c3-48b1-b762-72a5de57b509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522378607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2522378607
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1875923833
Short name T689
Test name
Test status
Simulation time 7918544973 ps
CPU time 21.84 seconds
Started Jun 27 06:24:43 PM PDT 24
Finished Jun 27 06:25:13 PM PDT 24
Peak memory 216952 kb
Host smart-556f4bf6-9282-4639-92a0-d3d0ed5bfac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875923833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1875923833
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3759153792
Short name T885
Test name
Test status
Simulation time 8731032520 ps
CPU time 14.99 seconds
Started Jun 27 06:24:44 PM PDT 24
Finished Jun 27 06:25:07 PM PDT 24
Peak memory 217104 kb
Host smart-02adaced-6bd4-40c5-9846-7fa39f7af61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759153792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3759153792
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.196524500
Short name T701
Test name
Test status
Simulation time 433069349 ps
CPU time 1.85 seconds
Started Jun 27 06:24:50 PM PDT 24
Finished Jun 27 06:25:00 PM PDT 24
Peak memory 216832 kb
Host smart-b2440b36-d481-47d3-a3ca-46456e0406ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196524500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.196524500
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1370811565
Short name T395
Test name
Test status
Simulation time 309519528 ps
CPU time 0.98 seconds
Started Jun 27 06:24:48 PM PDT 24
Finished Jun 27 06:24:56 PM PDT 24
Peak memory 206460 kb
Host smart-7df8f65b-9f69-4b73-a95e-2854f631d58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370811565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1370811565
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.254064718
Short name T953
Test name
Test status
Simulation time 6382422265 ps
CPU time 23.8 seconds
Started Jun 27 06:24:47 PM PDT 24
Finished Jun 27 06:25:19 PM PDT 24
Peak memory 233288 kb
Host smart-12020fc8-da20-43bf-b531-5e3a8aff5cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254064718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.254064718
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2549713792
Short name T849
Test name
Test status
Simulation time 48142695 ps
CPU time 0.81 seconds
Started Jun 27 06:24:52 PM PDT 24
Finished Jun 27 06:25:00 PM PDT 24
Peak memory 205316 kb
Host smart-6bbb12d9-208e-4974-94b1-84282ba8ee51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549713792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2549713792
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.441010025
Short name T580
Test name
Test status
Simulation time 109984429 ps
CPU time 3.66 seconds
Started Jun 27 06:24:53 PM PDT 24
Finished Jun 27 06:25:03 PM PDT 24
Peak memory 224936 kb
Host smart-8d08bdfb-3c3d-4e04-b7b5-0b6f0c8b53e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441010025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.441010025
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2555590549
Short name T343
Test name
Test status
Simulation time 31672212 ps
CPU time 0.76 seconds
Started Jun 27 06:24:50 PM PDT 24
Finished Jun 27 06:24:59 PM PDT 24
Peak memory 206092 kb
Host smart-0a45d79f-26b3-4612-af7d-8f159f178a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555590549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2555590549
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.877216368
Short name T627
Test name
Test status
Simulation time 13604755697 ps
CPU time 68.11 seconds
Started Jun 27 06:24:52 PM PDT 24
Finished Jun 27 06:26:07 PM PDT 24
Peak memory 249724 kb
Host smart-299ccf05-055e-4924-ab69-0a4d1375584d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877216368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.877216368
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4079652669
Short name T284
Test name
Test status
Simulation time 211822417605 ps
CPU time 227.56 seconds
Started Jun 27 06:24:48 PM PDT 24
Finished Jun 27 06:28:43 PM PDT 24
Peak memory 274452 kb
Host smart-6e3d1f42-571e-4440-9656-6519f436b9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079652669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4079652669
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3489123122
Short name T527
Test name
Test status
Simulation time 79981190323 ps
CPU time 141.45 seconds
Started Jun 27 06:24:48 PM PDT 24
Finished Jun 27 06:27:17 PM PDT 24
Peak memory 249812 kb
Host smart-3c52d10f-5886-42b5-af94-d38a18aecc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489123122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3489123122
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2528628681
Short name T212
Test name
Test status
Simulation time 25209368379 ps
CPU time 190.77 seconds
Started Jun 27 06:24:50 PM PDT 24
Finished Jun 27 06:28:09 PM PDT 24
Peak memory 237372 kb
Host smart-0f92306c-2634-4607-8f6a-fb4a80163bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528628681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2528628681
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1344309063
Short name T623
Test name
Test status
Simulation time 72945168 ps
CPU time 2.32 seconds
Started Jun 27 06:24:50 PM PDT 24
Finished Jun 27 06:25:00 PM PDT 24
Peak memory 224324 kb
Host smart-023c0280-9ce9-485a-9cb6-d2b084b4bebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344309063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1344309063
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2992155762
Short name T882
Test name
Test status
Simulation time 525828206 ps
CPU time 11.26 seconds
Started Jun 27 06:24:53 PM PDT 24
Finished Jun 27 06:25:11 PM PDT 24
Peak memory 239320 kb
Host smart-a25e048c-a890-435b-80d6-f168d733387d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992155762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2992155762
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2377400936
Short name T999
Test name
Test status
Simulation time 20350798096 ps
CPU time 11.81 seconds
Started Jun 27 06:24:52 PM PDT 24
Finished Jun 27 06:25:11 PM PDT 24
Peak memory 234320 kb
Host smart-bf50abd5-be7d-452f-93db-79dadfd5af04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377400936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2377400936
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3813861960
Short name T224
Test name
Test status
Simulation time 1053679670 ps
CPU time 4.57 seconds
Started Jun 27 06:24:52 PM PDT 24
Finished Jun 27 06:25:04 PM PDT 24
Peak memory 233192 kb
Host smart-59b6c7de-df79-4515-a9a4-3d5ad48a7141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813861960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3813861960
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2373481347
Short name T461
Test name
Test status
Simulation time 896249066 ps
CPU time 4.25 seconds
Started Jun 27 06:24:52 PM PDT 24
Finished Jun 27 06:25:04 PM PDT 24
Peak memory 220752 kb
Host smart-5ae41dcd-631d-443b-94da-516cf5777708
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2373481347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2373481347
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3214629259
Short name T1007
Test name
Test status
Simulation time 8329944991 ps
CPU time 22.57 seconds
Started Jun 27 06:24:49 PM PDT 24
Finished Jun 27 06:25:19 PM PDT 24
Peak memory 225276 kb
Host smart-91cd12e1-ea0a-4d91-826c-386ffaa68020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214629259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3214629259
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3037850589
Short name T339
Test name
Test status
Simulation time 1639956546 ps
CPU time 2.76 seconds
Started Jun 27 06:24:49 PM PDT 24
Finished Jun 27 06:24:59 PM PDT 24
Peak memory 216784 kb
Host smart-6ce8d69f-f1a6-45b6-bb46-e0f77afaefa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037850589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3037850589
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1574248417
Short name T371
Test name
Test status
Simulation time 617157274 ps
CPU time 1.52 seconds
Started Jun 27 06:24:53 PM PDT 24
Finished Jun 27 06:25:01 PM PDT 24
Peak memory 208160 kb
Host smart-afc6dfa4-29bb-4596-b8be-41a1ab570c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574248417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1574248417
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.856532314
Short name T846
Test name
Test status
Simulation time 133284202 ps
CPU time 1.9 seconds
Started Jun 27 06:24:47 PM PDT 24
Finished Jun 27 06:24:56 PM PDT 24
Peak memory 216844 kb
Host smart-11051e48-c7f7-4f0f-87d7-3882272b9c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856532314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.856532314
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.724588913
Short name T75
Test name
Test status
Simulation time 26634077 ps
CPU time 0.87 seconds
Started Jun 27 06:24:53 PM PDT 24
Finished Jun 27 06:25:00 PM PDT 24
Peak memory 206476 kb
Host smart-069bcbb6-e3b6-45d3-a2ee-2e99e1c416b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724588913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.724588913
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2350685094
Short name T201
Test name
Test status
Simulation time 5411623468 ps
CPU time 14.57 seconds
Started Jun 27 06:24:47 PM PDT 24
Finished Jun 27 06:25:09 PM PDT 24
Peak memory 234312 kb
Host smart-26a041d2-6759-474a-846f-d46a16c58151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350685094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2350685094
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.300488689
Short name T967
Test name
Test status
Simulation time 37527253 ps
CPU time 0.72 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:06 PM PDT 24
Peak memory 205408 kb
Host smart-7b3f6003-9733-46bc-87b9-4a70967ab523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300488689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.300488689
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3686791821
Short name T791
Test name
Test status
Simulation time 727903587 ps
CPU time 7 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:25:17 PM PDT 24
Peak memory 224992 kb
Host smart-6ec47b8a-56d4-4ed2-8367-67ce4b4d1d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686791821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3686791821
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.839034559
Short name T787
Test name
Test status
Simulation time 16143959 ps
CPU time 0.8 seconds
Started Jun 27 06:24:48 PM PDT 24
Finished Jun 27 06:24:56 PM PDT 24
Peak memory 207064 kb
Host smart-32df7748-bbc0-4454-b56c-2ceb47a8cfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839034559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.839034559
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2464933958
Short name T353
Test name
Test status
Simulation time 20738101 ps
CPU time 0.76 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:09 PM PDT 24
Peak memory 216404 kb
Host smart-04dd5236-af53-4114-80c1-30d2f414d8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464933958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2464933958
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3089461062
Short name T460
Test name
Test status
Simulation time 6605901450 ps
CPU time 24.46 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:32 PM PDT 24
Peak memory 218304 kb
Host smart-1ec72af8-c05c-47b6-840b-a9d88824b387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089461062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3089461062
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1359787955
Short name T60
Test name
Test status
Simulation time 278965975178 ps
CPU time 179.8 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:28:10 PM PDT 24
Peak memory 251580 kb
Host smart-26f16337-0036-47fe-9e33-7ec1330652de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359787955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1359787955
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1512567035
Short name T336
Test name
Test status
Simulation time 131385927 ps
CPU time 2.78 seconds
Started Jun 27 06:25:10 PM PDT 24
Finished Jun 27 06:25:19 PM PDT 24
Peak memory 233196 kb
Host smart-e223aebe-3c89-4aa1-8d66-4c575e412467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512567035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1512567035
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1510602543
Short name T198
Test name
Test status
Simulation time 745132441 ps
CPU time 4.38 seconds
Started Jun 27 06:24:49 PM PDT 24
Finished Jun 27 06:25:02 PM PDT 24
Peak memory 233152 kb
Host smart-e71c6c4d-532c-41ac-af96-384d4b47fd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510602543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1510602543
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.105958895
Short name T244
Test name
Test status
Simulation time 144126512 ps
CPU time 2.58 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:11 PM PDT 24
Peak memory 233212 kb
Host smart-cd7b9bcd-389a-4fdd-9154-a1b2bb4b5743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105958895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.105958895
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1834629952
Short name T467
Test name
Test status
Simulation time 176188453 ps
CPU time 2.44 seconds
Started Jun 27 06:24:51 PM PDT 24
Finished Jun 27 06:25:01 PM PDT 24
Peak memory 232964 kb
Host smart-c8e08c75-293c-49d7-8bef-5d501c992b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834629952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1834629952
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.959852663
Short name T968
Test name
Test status
Simulation time 44043564205 ps
CPU time 26.36 seconds
Started Jun 27 06:24:49 PM PDT 24
Finished Jun 27 06:25:24 PM PDT 24
Peak memory 233308 kb
Host smart-5669f3bb-fdbf-4172-96c8-9b07f3dc8ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959852663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.959852663
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2802907180
Short name T964
Test name
Test status
Simulation time 1940197460 ps
CPU time 7.07 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:13 PM PDT 24
Peak memory 221128 kb
Host smart-6fcd359f-f4e1-4d47-99e0-7c0aa099e835
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2802907180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2802907180
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.830108588
Short name T443
Test name
Test status
Simulation time 19450561361 ps
CPU time 68.51 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:26:15 PM PDT 24
Peak memory 258036 kb
Host smart-25bb77dc-686b-4550-bc76-6f7ae1fa1ffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830108588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.830108588
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3885541636
Short name T162
Test name
Test status
Simulation time 13695171905 ps
CPU time 39.65 seconds
Started Jun 27 06:24:48 PM PDT 24
Finished Jun 27 06:25:35 PM PDT 24
Peak memory 216944 kb
Host smart-56639c0e-011f-43d0-8293-111a52b9431a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885541636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3885541636
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2271969332
Short name T456
Test name
Test status
Simulation time 861383787 ps
CPU time 6.24 seconds
Started Jun 27 06:24:59 PM PDT 24
Finished Jun 27 06:25:08 PM PDT 24
Peak memory 216672 kb
Host smart-87440054-b259-4c7c-855f-18f48428dafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271969332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2271969332
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2838922128
Short name T356
Test name
Test status
Simulation time 788214269 ps
CPU time 1.51 seconds
Started Jun 27 06:24:48 PM PDT 24
Finished Jun 27 06:24:58 PM PDT 24
Peak memory 208584 kb
Host smart-4c88ad54-2c20-4441-9215-cfb6582b9338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838922128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2838922128
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3081513198
Short name T829
Test name
Test status
Simulation time 991599750 ps
CPU time 0.99 seconds
Started Jun 27 06:24:51 PM PDT 24
Finished Jun 27 06:25:00 PM PDT 24
Peak memory 206364 kb
Host smart-9ce07947-2353-490d-b273-955bce5d5712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081513198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3081513198
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.69270667
Short name T363
Test name
Test status
Simulation time 190108574 ps
CPU time 2.15 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:08 PM PDT 24
Peak memory 224644 kb
Host smart-2e5a6643-9c92-4324-bbac-230ed49cd6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69270667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.69270667
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1350091928
Short name T374
Test name
Test status
Simulation time 12346464 ps
CPU time 0.73 seconds
Started Jun 27 06:25:07 PM PDT 24
Finished Jun 27 06:25:14 PM PDT 24
Peak memory 205880 kb
Host smart-cc8f65cf-5c2a-4098-a2ea-bdb144142214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350091928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1350091928
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1827405158
Short name T737
Test name
Test status
Simulation time 114671691 ps
CPU time 2.88 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:11 PM PDT 24
Peak memory 225028 kb
Host smart-0a906ad3-70a7-42b1-b3b1-cf3e2c74ea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827405158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1827405158
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3508848968
Short name T939
Test name
Test status
Simulation time 36668033 ps
CPU time 0.85 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:09 PM PDT 24
Peak memory 207080 kb
Host smart-9b5bc198-aaee-4dab-a5e3-62f628b79b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508848968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3508848968
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1745010572
Short name T605
Test name
Test status
Simulation time 9081922734 ps
CPU time 49.77 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:57 PM PDT 24
Peak memory 266124 kb
Host smart-233c6cbb-abdf-4885-a2b2-911a37a8a3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745010572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1745010572
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1849423212
Short name T254
Test name
Test status
Simulation time 298985279670 ps
CPU time 210.58 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:28:46 PM PDT 24
Peak memory 237308 kb
Host smart-4bd6bc03-9a3f-41ba-a41b-a5b2b699795a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849423212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1849423212
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3392969893
Short name T206
Test name
Test status
Simulation time 21549355618 ps
CPU time 90.83 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:26:39 PM PDT 24
Peak memory 258032 kb
Host smart-b25c7a99-8fda-4aa2-abcc-44b32135ecd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392969893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3392969893
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3123686395
Short name T800
Test name
Test status
Simulation time 75050180 ps
CPU time 2.9 seconds
Started Jun 27 06:25:02 PM PDT 24
Finished Jun 27 06:25:07 PM PDT 24
Peak memory 233192 kb
Host smart-acf329e6-5008-4dff-8c9f-ce1b53199eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123686395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3123686395
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.679746163
Short name T801
Test name
Test status
Simulation time 111649035 ps
CPU time 2.45 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:25:11 PM PDT 24
Peak memory 232892 kb
Host smart-7237f5e4-8d29-48aa-87eb-5a7dd0131547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679746163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.679746163
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3767842012
Short name T864
Test name
Test status
Simulation time 971491299 ps
CPU time 7.61 seconds
Started Jun 27 06:25:02 PM PDT 24
Finished Jun 27 06:25:13 PM PDT 24
Peak memory 224964 kb
Host smart-7dd5fa82-1147-4ca0-a779-c611ce85e0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767842012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3767842012
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.515065944
Short name T294
Test name
Test status
Simulation time 10952586247 ps
CPU time 10.96 seconds
Started Jun 27 06:25:06 PM PDT 24
Finished Jun 27 06:25:23 PM PDT 24
Peak memory 225048 kb
Host smart-71ebf78e-720a-4243-854f-9a003f7f7bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515065944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.515065944
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2866709619
Short name T196
Test name
Test status
Simulation time 209798926 ps
CPU time 3.54 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:25:19 PM PDT 24
Peak memory 225056 kb
Host smart-882e71ea-5126-4790-9dde-e3cdbcac1605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866709619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2866709619
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3954795193
Short name T944
Test name
Test status
Simulation time 1246782711 ps
CPU time 10.73 seconds
Started Jun 27 06:25:02 PM PDT 24
Finished Jun 27 06:25:16 PM PDT 24
Peak memory 220608 kb
Host smart-ca35ade5-b30c-47d5-8bc9-31180802de9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3954795193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3954795193
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2898016864
Short name T875
Test name
Test status
Simulation time 5213772689 ps
CPU time 36.05 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:44 PM PDT 24
Peak memory 216916 kb
Host smart-6ccc6e8c-c0fd-45d8-bba6-8423ad916af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898016864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2898016864
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1449724481
Short name T163
Test name
Test status
Simulation time 3922594650 ps
CPU time 12.62 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:21 PM PDT 24
Peak memory 216876 kb
Host smart-ebc6eae4-d218-43c6-8bdd-cfecaf13586f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449724481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1449724481
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2346100337
Short name T693
Test name
Test status
Simulation time 266193268 ps
CPU time 1.81 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:08 PM PDT 24
Peak memory 216988 kb
Host smart-5d29b936-7772-4a44-9511-70ce541712d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346100337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2346100337
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.708745063
Short name T499
Test name
Test status
Simulation time 17328401 ps
CPU time 0.71 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:06 PM PDT 24
Peak memory 206136 kb
Host smart-81de53c8-cd68-4373-8c66-ebd6332d7a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708745063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.708745063
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1572830486
Short name T231
Test name
Test status
Simulation time 6457678345 ps
CPU time 12.57 seconds
Started Jun 27 06:25:08 PM PDT 24
Finished Jun 27 06:25:27 PM PDT 24
Peak memory 233164 kb
Host smart-102506e8-5f90-449a-b62f-6662ebccb5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572830486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1572830486
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2045418165
Short name T815
Test name
Test status
Simulation time 13793438 ps
CPU time 0.74 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:08 PM PDT 24
Peak memory 205340 kb
Host smart-f3bb26aa-2238-4348-8b5e-a4932c9c6ef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045418165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2045418165
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4242804545
Short name T249
Test name
Test status
Simulation time 274892809 ps
CPU time 2.62 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:09 PM PDT 24
Peak memory 233396 kb
Host smart-ed396343-b111-48a0-ae1f-d5dd4776aea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242804545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4242804545
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4111264952
Short name T976
Test name
Test status
Simulation time 22509128 ps
CPU time 0.82 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:08 PM PDT 24
Peak memory 206384 kb
Host smart-bf020933-e579-43db-a4b5-d74fee9e62e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111264952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4111264952
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1307814758
Short name T420
Test name
Test status
Simulation time 1080113317 ps
CPU time 20.08 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:27 PM PDT 24
Peak memory 249632 kb
Host smart-0d49301e-bee7-4ca5-b878-110e7013d3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307814758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1307814758
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1102783147
Short name T396
Test name
Test status
Simulation time 1968551291 ps
CPU time 12.86 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:19 PM PDT 24
Peak memory 233356 kb
Host smart-d6c03b25-5e79-464d-8061-05d55e132fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102783147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1102783147
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2936080759
Short name T942
Test name
Test status
Simulation time 971039212 ps
CPU time 11.83 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:20 PM PDT 24
Peak memory 224992 kb
Host smart-f872b925-5a55-46b2-8bb5-913c1d26c0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936080759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2936080759
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3239429196
Short name T409
Test name
Test status
Simulation time 2386580696 ps
CPU time 22.18 seconds
Started Jun 27 06:25:02 PM PDT 24
Finished Jun 27 06:25:26 PM PDT 24
Peak memory 225116 kb
Host smart-8cf723fa-c814-4784-b948-75517a86c1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239429196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3239429196
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3810409980
Short name T450
Test name
Test status
Simulation time 126443543 ps
CPU time 2.53 seconds
Started Jun 27 06:25:02 PM PDT 24
Finished Jun 27 06:25:07 PM PDT 24
Peak memory 233012 kb
Host smart-7476f325-70f1-4e23-b7ee-fb5234a19525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810409980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3810409980
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1250630220
Short name T528
Test name
Test status
Simulation time 18053585059 ps
CPU time 101.5 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:26:48 PM PDT 24
Peak memory 233320 kb
Host smart-d225e66c-19d2-4ce4-8cc3-4daee3d5dee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250630220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1250630220
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3324177750
Short name T550
Test name
Test status
Simulation time 432284967 ps
CPU time 6.47 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:15 PM PDT 24
Peak memory 233240 kb
Host smart-ed720570-fde9-46a0-914b-ed7c1df3607e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324177750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3324177750
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.337411739
Short name T573
Test name
Test status
Simulation time 6700957635 ps
CPU time 6.58 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:15 PM PDT 24
Peak memory 225180 kb
Host smart-aadfee4e-8e6d-4bb6-86d1-e6e6b259c632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337411739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.337411739
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2434226342
Short name T489
Test name
Test status
Simulation time 86534030 ps
CPU time 3.37 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:25:13 PM PDT 24
Peak memory 223680 kb
Host smart-e62f604f-3efe-464e-a353-cf13d06f972b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2434226342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2434226342
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1092506409
Short name T160
Test name
Test status
Simulation time 138192733 ps
CPU time 0.89 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:25:10 PM PDT 24
Peak memory 206576 kb
Host smart-0eb122c0-93c7-4af3-bb63-f7f6496e222f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092506409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1092506409
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2150794269
Short name T940
Test name
Test status
Simulation time 11819941614 ps
CPU time 35.86 seconds
Started Jun 27 06:25:08 PM PDT 24
Finished Jun 27 06:25:51 PM PDT 24
Peak memory 220776 kb
Host smart-cee350eb-097a-4401-a515-92ea4474313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150794269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2150794269
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.278176260
Short name T702
Test name
Test status
Simulation time 221716945 ps
CPU time 2.46 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:25:12 PM PDT 24
Peak memory 216824 kb
Host smart-14bb5a6d-7aeb-43d6-8bf8-a742291a56f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278176260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.278176260
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2277421399
Short name T386
Test name
Test status
Simulation time 349943756 ps
CPU time 3.48 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:11 PM PDT 24
Peak memory 216824 kb
Host smart-4dacb50f-75d2-4dda-ba0a-d1115f32464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277421399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2277421399
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1259649472
Short name T541
Test name
Test status
Simulation time 126317482 ps
CPU time 0.9 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:25:11 PM PDT 24
Peak memory 206460 kb
Host smart-9e397f36-523c-4f49-90e2-e5647da460de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259649472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1259649472
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1193933955
Short name T916
Test name
Test status
Simulation time 719927675 ps
CPU time 2.26 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:10 PM PDT 24
Peak memory 225016 kb
Host smart-30a429f7-136c-44d4-98b2-f0d4cd2faf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193933955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1193933955
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3212024461
Short name T561
Test name
Test status
Simulation time 14388742 ps
CPU time 0.73 seconds
Started Jun 27 06:25:08 PM PDT 24
Finished Jun 27 06:25:15 PM PDT 24
Peak memory 205384 kb
Host smart-fc08e4d8-69cd-4769-8498-af0fd27005ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212024461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3212024461
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.514441061
Short name T970
Test name
Test status
Simulation time 865397823 ps
CPU time 4.04 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:25:19 PM PDT 24
Peak memory 225028 kb
Host smart-157d428a-39f7-4db5-abc9-601897cc3150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514441061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.514441061
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3910779442
Short name T948
Test name
Test status
Simulation time 44671049 ps
CPU time 0.76 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:25:11 PM PDT 24
Peak memory 206020 kb
Host smart-364e85ea-2e8a-4a0d-979e-febf535ea95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910779442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3910779442
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3488610844
Short name T292
Test name
Test status
Simulation time 51086864152 ps
CPU time 371.01 seconds
Started Jun 27 06:25:10 PM PDT 24
Finished Jun 27 06:31:27 PM PDT 24
Peak memory 264460 kb
Host smart-aaf42c21-c3f1-4103-9311-b7c42859ed96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488610844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3488610844
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3746271927
Short name T490
Test name
Test status
Simulation time 4407861520 ps
CPU time 22.19 seconds
Started Jun 27 06:25:10 PM PDT 24
Finished Jun 27 06:25:38 PM PDT 24
Peak memory 249692 kb
Host smart-ad7c8ef4-3f9c-4e35-a464-92ef828bb0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746271927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3746271927
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3037854777
Short name T331
Test name
Test status
Simulation time 5855578855 ps
CPU time 36.28 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:25:52 PM PDT 24
Peak memory 255300 kb
Host smart-2fc9e764-11a4-4b0e-836a-7a38760a26e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037854777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3037854777
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2465365704
Short name T147
Test name
Test status
Simulation time 6958475240 ps
CPU time 30.59 seconds
Started Jun 27 06:25:10 PM PDT 24
Finished Jun 27 06:25:47 PM PDT 24
Peak memory 234372 kb
Host smart-77c63fdb-f377-4e4b-9886-9e40da7af3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465365704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2465365704
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.640515727
Short name T762
Test name
Test status
Simulation time 8994321794 ps
CPU time 20.74 seconds
Started Jun 27 06:25:06 PM PDT 24
Finished Jun 27 06:25:33 PM PDT 24
Peak memory 225072 kb
Host smart-da9cecea-d705-4216-a891-115bbcd16cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640515727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.640515727
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2563784883
Short name T214
Test name
Test status
Simulation time 3393127252 ps
CPU time 18.21 seconds
Started Jun 27 06:25:08 PM PDT 24
Finished Jun 27 06:25:32 PM PDT 24
Peak memory 225168 kb
Host smart-c1d8171a-1b2b-4821-8adb-8e247d9f5ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563784883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2563784883
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2386353398
Short name T722
Test name
Test status
Simulation time 3042591867 ps
CPU time 7.24 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:25:17 PM PDT 24
Peak memory 237736 kb
Host smart-396818a9-4112-4803-8e4f-59037c50b652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386353398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2386353398
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1198105700
Short name T678
Test name
Test status
Simulation time 18222830853 ps
CPU time 20.88 seconds
Started Jun 27 06:25:06 PM PDT 24
Finished Jun 27 06:25:33 PM PDT 24
Peak memory 241224 kb
Host smart-8cad6acd-9346-44e2-afcb-2c720127b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198105700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1198105700
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2431698188
Short name T13
Test name
Test status
Simulation time 814074148 ps
CPU time 9.14 seconds
Started Jun 27 06:25:08 PM PDT 24
Finished Jun 27 06:25:24 PM PDT 24
Peak memory 222660 kb
Host smart-e6c66d38-d160-4290-8bdd-7dfe4bd4e7a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2431698188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2431698188
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2434524416
Short name T155
Test name
Test status
Simulation time 123572878 ps
CPU time 1.11 seconds
Started Jun 27 06:25:19 PM PDT 24
Finished Jun 27 06:25:26 PM PDT 24
Peak memory 207592 kb
Host smart-4066319f-2a9c-4ede-8bd3-f4de653aa0bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434524416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2434524416
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2007795382
Short name T583
Test name
Test status
Simulation time 4544558371 ps
CPU time 9.56 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:25:20 PM PDT 24
Peak memory 217024 kb
Host smart-705d3200-059a-42f8-a9c5-a1f5cad1e5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007795382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2007795382
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.272408869
Short name T342
Test name
Test status
Simulation time 299365101 ps
CPU time 1.4 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:25:11 PM PDT 24
Peak memory 208408 kb
Host smart-00798196-f6bc-4b0c-97e9-f9327ec13441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272408869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.272408869
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3650188902
Short name T558
Test name
Test status
Simulation time 99101138 ps
CPU time 0.98 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:25:11 PM PDT 24
Peak memory 208004 kb
Host smart-c1d00911-c95f-4ac4-92a6-537d76fa959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650188902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3650188902
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.102871189
Short name T775
Test name
Test status
Simulation time 124051094 ps
CPU time 0.94 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:09 PM PDT 24
Peak memory 206424 kb
Host smart-c5378157-1bd8-4722-8ed5-bf22770d1d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102871189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.102871189
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2628650309
Short name T614
Test name
Test status
Simulation time 12356354901 ps
CPU time 12.48 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:25:28 PM PDT 24
Peak memory 225096 kb
Host smart-ef5be4d0-2c3c-4afc-9696-ce264b16f03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628650309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2628650309
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1109581496
Short name T745
Test name
Test status
Simulation time 25479882 ps
CPU time 0.74 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:27 PM PDT 24
Peak memory 205944 kb
Host smart-00b988d1-c7ec-4d00-9a42-fceafd9a0990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109581496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1109581496
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.242927465
Short name T668
Test name
Test status
Simulation time 1344069943 ps
CPU time 5.62 seconds
Started Jun 27 06:25:17 PM PDT 24
Finished Jun 27 06:25:27 PM PDT 24
Peak memory 233104 kb
Host smart-50a3debe-b0cf-4bf7-b154-d9e9059cb597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242927465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.242927465
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2760633445
Short name T615
Test name
Test status
Simulation time 24945277 ps
CPU time 0.73 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:25:16 PM PDT 24
Peak memory 206084 kb
Host smart-415c280a-bbef-4688-8fb3-dcc039b1d657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760633445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2760633445
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2955900929
Short name T168
Test name
Test status
Simulation time 26864501655 ps
CPU time 200.84 seconds
Started Jun 27 06:25:13 PM PDT 24
Finished Jun 27 06:28:39 PM PDT 24
Peak memory 257748 kb
Host smart-360960d1-26eb-48ce-8d0f-32574844cc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955900929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2955900929
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.449987572
Short name T796
Test name
Test status
Simulation time 3649466907 ps
CPU time 43.29 seconds
Started Jun 27 06:25:12 PM PDT 24
Finished Jun 27 06:26:01 PM PDT 24
Peak memory 249816 kb
Host smart-deedc30a-ad16-457d-ab9f-b9cdfb26c809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449987572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.449987572
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4154396877
Short name T946
Test name
Test status
Simulation time 754927841 ps
CPU time 4.89 seconds
Started Jun 27 06:25:12 PM PDT 24
Finished Jun 27 06:25:23 PM PDT 24
Peak memory 218008 kb
Host smart-1063f4e0-0d95-4452-a659-0dbd51107125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154396877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4154396877
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4116052250
Short name T652
Test name
Test status
Simulation time 1459685265 ps
CPU time 24.04 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:50 PM PDT 24
Peak memory 233236 kb
Host smart-d3155e7f-23d3-4e3a-ba7e-c4eab551331c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116052250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4116052250
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3577183198
Short name T466
Test name
Test status
Simulation time 2801962571 ps
CPU time 39.87 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:25:49 PM PDT 24
Peak memory 249744 kb
Host smart-181432b6-d681-44d3-829b-c788f0ec726c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577183198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3577183198
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3099638533
Short name T442
Test name
Test status
Simulation time 98287576 ps
CPU time 3.72 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:30 PM PDT 24
Peak memory 224884 kb
Host smart-236e467d-e2db-469b-ad44-e80d4b2b4998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099638533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3099638533
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1797292468
Short name T584
Test name
Test status
Simulation time 3081059921 ps
CPU time 20.41 seconds
Started Jun 27 06:25:18 PM PDT 24
Finished Jun 27 06:25:43 PM PDT 24
Peak memory 233300 kb
Host smart-a3406c72-9eff-43a0-b41f-685d15821e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797292468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1797292468
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.858775583
Short name T643
Test name
Test status
Simulation time 4006386785 ps
CPU time 17.02 seconds
Started Jun 27 06:25:17 PM PDT 24
Finished Jun 27 06:25:39 PM PDT 24
Peak memory 249664 kb
Host smart-97c967bc-abb2-4213-a1b4-263dae3dd91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858775583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.858775583
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3548647281
Short name T923
Test name
Test status
Simulation time 9880880201 ps
CPU time 21.81 seconds
Started Jun 27 06:25:17 PM PDT 24
Finished Jun 27 06:25:44 PM PDT 24
Peak memory 225076 kb
Host smart-cf16cc8a-11b2-44ac-843a-e7edda76f071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548647281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3548647281
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3994667568
Short name T674
Test name
Test status
Simulation time 1683553148 ps
CPU time 15.56 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:42 PM PDT 24
Peak memory 220560 kb
Host smart-9218d808-6d4c-4671-8a7c-d94983dcdad3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3994667568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3994667568
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2404415805
Short name T974
Test name
Test status
Simulation time 19597069984 ps
CPU time 122.76 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:27:29 PM PDT 24
Peak memory 249868 kb
Host smart-30c56256-f23a-4034-92c9-98464201fcda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404415805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2404415805
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.766704260
Short name T329
Test name
Test status
Simulation time 1201349364 ps
CPU time 10.14 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:36 PM PDT 24
Peak memory 216848 kb
Host smart-43d110a3-7a4c-4ff8-8544-c53d9b5f2421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766704260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.766704260
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2701846571
Short name T720
Test name
Test status
Simulation time 1748692397 ps
CPU time 5.52 seconds
Started Jun 27 06:25:10 PM PDT 24
Finished Jun 27 06:25:22 PM PDT 24
Peak memory 216796 kb
Host smart-11cc1fd6-9218-4737-a001-6bdd82153dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701846571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2701846571
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2847161018
Short name T986
Test name
Test status
Simulation time 45653856 ps
CPU time 1.18 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:26 PM PDT 24
Peak memory 208392 kb
Host smart-d0885266-0cd1-422d-9eb2-af3d4e64bb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847161018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2847161018
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3928480975
Short name T906
Test name
Test status
Simulation time 103844969 ps
CPU time 0.79 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:25:16 PM PDT 24
Peak memory 206392 kb
Host smart-c77cb863-5391-4260-a177-ca8721fdd646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928480975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3928480975
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2600513417
Short name T744
Test name
Test status
Simulation time 118090377986 ps
CPU time 23.33 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:32 PM PDT 24
Peak memory 233364 kb
Host smart-79507319-644d-4689-88ac-6388f48bdb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600513417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2600513417
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2550851086
Short name T432
Test name
Test status
Simulation time 15726435 ps
CPU time 0.77 seconds
Started Jun 27 06:23:00 PM PDT 24
Finished Jun 27 06:23:10 PM PDT 24
Peak memory 205432 kb
Host smart-88f15597-fb99-4574-a3da-f25696d00e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550851086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
550851086
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2317716916
Short name T983
Test name
Test status
Simulation time 36895420 ps
CPU time 2.54 seconds
Started Jun 27 06:23:02 PM PDT 24
Finished Jun 27 06:23:14 PM PDT 24
Peak memory 233172 kb
Host smart-62fa2ef5-bf28-4e8c-a43a-9b1b09677a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317716916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2317716916
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3000394630
Short name T1
Test name
Test status
Simulation time 46686893 ps
CPU time 0.84 seconds
Started Jun 27 06:23:00 PM PDT 24
Finished Jun 27 06:23:10 PM PDT 24
Peak memory 207404 kb
Host smart-3bf8dcdc-2285-4081-9b05-9713a6eb2139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000394630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3000394630
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.317118389
Short name T406
Test name
Test status
Simulation time 2362748786 ps
CPU time 49.24 seconds
Started Jun 27 06:23:02 PM PDT 24
Finished Jun 27 06:24:00 PM PDT 24
Peak memory 250492 kb
Host smart-bca92b34-282c-4ee7-974d-b3b9e3228c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317118389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.317118389
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1635263772
Short name T495
Test name
Test status
Simulation time 3078185257 ps
CPU time 68.79 seconds
Started Jun 27 06:23:22 PM PDT 24
Finished Jun 27 06:24:36 PM PDT 24
Peak memory 251800 kb
Host smart-d01fc4b5-4d18-4d53-9f67-de0ddc44718a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635263772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1635263772
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.329858894
Short name T782
Test name
Test status
Simulation time 32366575196 ps
CPU time 105.08 seconds
Started Jun 27 06:23:00 PM PDT 24
Finished Jun 27 06:24:53 PM PDT 24
Peak memory 249844 kb
Host smart-0e29aaab-fd5a-44f1-8268-af4cc7c7f919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329858894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
329858894
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2187919776
Short name T555
Test name
Test status
Simulation time 957100710 ps
CPU time 4.58 seconds
Started Jun 27 06:23:25 PM PDT 24
Finished Jun 27 06:23:34 PM PDT 24
Peak memory 233172 kb
Host smart-468443d2-084a-4d13-b705-cfa90256a8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187919776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2187919776
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1100796341
Short name T486
Test name
Test status
Simulation time 13075810072 ps
CPU time 36.48 seconds
Started Jun 27 06:23:27 PM PDT 24
Finished Jun 27 06:24:07 PM PDT 24
Peak memory 249652 kb
Host smart-5648ea9a-1afa-4f38-b44b-df5187173ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100796341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1100796341
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3424302116
Short name T715
Test name
Test status
Simulation time 2613288809 ps
CPU time 11.66 seconds
Started Jun 27 06:23:02 PM PDT 24
Finished Jun 27 06:23:22 PM PDT 24
Peak memory 225132 kb
Host smart-afc613d8-515f-4dee-91b7-3bb45c0f2b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424302116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3424302116
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1041836444
Short name T610
Test name
Test status
Simulation time 23522159057 ps
CPU time 109.14 seconds
Started Jun 27 06:23:30 PM PDT 24
Finished Jun 27 06:25:24 PM PDT 24
Peak memory 241380 kb
Host smart-0f28bce5-7d6e-4b3b-91d6-9e81c2086d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041836444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1041836444
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1863383976
Short name T299
Test name
Test status
Simulation time 11771952585 ps
CPU time 11.68 seconds
Started Jun 27 06:23:25 PM PDT 24
Finished Jun 27 06:23:41 PM PDT 24
Peak memory 225140 kb
Host smart-fa9ff8c4-2f13-45f3-9a2a-cb736ac07c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863383976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1863383976
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1727999442
Short name T595
Test name
Test status
Simulation time 11645194372 ps
CPU time 29.32 seconds
Started Jun 27 06:23:24 PM PDT 24
Finished Jun 27 06:23:57 PM PDT 24
Peak memory 233316 kb
Host smart-2b2f5693-ea64-443a-8f81-2602f21e0cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727999442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1727999442
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3366546589
Short name T641
Test name
Test status
Simulation time 1752823108 ps
CPU time 10.36 seconds
Started Jun 27 06:23:28 PM PDT 24
Finished Jun 27 06:23:42 PM PDT 24
Peak memory 220500 kb
Host smart-3c0eb9b6-a129-4ccb-94aa-2630c6eda68a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3366546589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3366546589
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3212202810
Short name T71
Test name
Test status
Simulation time 173138774 ps
CPU time 1 seconds
Started Jun 27 06:23:23 PM PDT 24
Finished Jun 27 06:23:28 PM PDT 24
Peak memory 236332 kb
Host smart-4a025bd7-f27b-4f70-b4ab-c7dfc582c9b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212202810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3212202810
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1002106048
Short name T389
Test name
Test status
Simulation time 823784786 ps
CPU time 6.05 seconds
Started Jun 27 06:23:06 PM PDT 24
Finished Jun 27 06:23:21 PM PDT 24
Peak memory 216796 kb
Host smart-17557aa8-2545-44ef-9185-a20487c2ef7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002106048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1002106048
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3889892416
Short name T507
Test name
Test status
Simulation time 384116716 ps
CPU time 1.63 seconds
Started Jun 27 06:23:12 PM PDT 24
Finished Jun 27 06:23:22 PM PDT 24
Peak memory 208376 kb
Host smart-bfd12e4e-e252-4f24-8a0a-9774b1cea3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889892416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3889892416
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3714972279
Short name T919
Test name
Test status
Simulation time 395325610 ps
CPU time 3.2 seconds
Started Jun 27 06:23:12 PM PDT 24
Finished Jun 27 06:23:23 PM PDT 24
Peak memory 216760 kb
Host smart-da036528-0ab5-4468-9c1a-421652634ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714972279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3714972279
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2171042605
Short name T870
Test name
Test status
Simulation time 79460813 ps
CPU time 0.96 seconds
Started Jun 27 06:23:07 PM PDT 24
Finished Jun 27 06:23:17 PM PDT 24
Peak memory 206508 kb
Host smart-af705e8b-a66f-4f58-8482-6411cbd66a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171042605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2171042605
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1547015718
Short name T3
Test name
Test status
Simulation time 426336155 ps
CPU time 5.96 seconds
Started Jun 27 06:23:43 PM PDT 24
Finished Jun 27 06:23:52 PM PDT 24
Peak memory 224956 kb
Host smart-4331fb3f-53df-4f90-b3c5-2502e12971b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547015718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1547015718
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2743416688
Short name T421
Test name
Test status
Simulation time 12433672 ps
CPU time 0.7 seconds
Started Jun 27 06:25:19 PM PDT 24
Finished Jun 27 06:25:26 PM PDT 24
Peak memory 205928 kb
Host smart-ef37e369-1014-4dc1-84da-7dee1d0a7613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743416688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2743416688
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.26785829
Short name T181
Test name
Test status
Simulation time 182973991 ps
CPU time 3.88 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:25:19 PM PDT 24
Peak memory 232832 kb
Host smart-653cd8c8-4f1b-400a-843b-f53070ba3660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26785829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.26785829
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.256766875
Short name T423
Test name
Test status
Simulation time 35311695 ps
CPU time 0.79 seconds
Started Jun 27 06:25:07 PM PDT 24
Finished Jun 27 06:25:14 PM PDT 24
Peak memory 207388 kb
Host smart-b1461634-4d23-4faf-8b11-ea92a4d4aea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256766875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.256766875
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.872513834
Short name T519
Test name
Test status
Simulation time 48761735410 ps
CPU time 98.14 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:26:53 PM PDT 24
Peak memory 250944 kb
Host smart-4fa385e8-5f34-405e-961e-b8ecce93efbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872513834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.872513834
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2664718647
Short name T805
Test name
Test status
Simulation time 4873719220 ps
CPU time 71.98 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:26:28 PM PDT 24
Peak memory 249732 kb
Host smart-a551e155-81c1-407d-93e2-3665d55e377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664718647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2664718647
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3758291455
Short name T350
Test name
Test status
Simulation time 3388904192 ps
CPU time 51.23 seconds
Started Jun 27 06:25:11 PM PDT 24
Finished Jun 27 06:26:08 PM PDT 24
Peak memory 237760 kb
Host smart-e58c95df-b0b6-464a-b941-51694c8b96e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758291455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3758291455
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3830650704
Short name T991
Test name
Test status
Simulation time 3252308013 ps
CPU time 59.34 seconds
Started Jun 27 06:25:10 PM PDT 24
Finished Jun 27 06:26:16 PM PDT 24
Peak memory 249720 kb
Host smart-e01d251d-ece6-48be-960f-3865443727da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830650704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3830650704
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2903276808
Short name T563
Test name
Test status
Simulation time 500826218 ps
CPU time 3.16 seconds
Started Jun 27 06:25:08 PM PDT 24
Finished Jun 27 06:25:17 PM PDT 24
Peak memory 233160 kb
Host smart-9392ad68-9806-422c-8a7b-1ecbeff19dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903276808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2903276808
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.19717001
Short name T626
Test name
Test status
Simulation time 168754609 ps
CPU time 2.61 seconds
Started Jun 27 06:25:10 PM PDT 24
Finished Jun 27 06:25:19 PM PDT 24
Peak memory 233244 kb
Host smart-f5f92539-47a0-41bb-95e9-737543979cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19717001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.19717001
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2098418322
Short name T1010
Test name
Test status
Simulation time 7654403583 ps
CPU time 15.41 seconds
Started Jun 27 06:25:08 PM PDT 24
Finished Jun 27 06:25:30 PM PDT 24
Peak memory 225128 kb
Host smart-f81cc3c4-5f35-4134-a555-6bc06d4f0783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098418322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2098418322
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1659915227
Short name T748
Test name
Test status
Simulation time 614535504 ps
CPU time 6.35 seconds
Started Jun 27 06:25:08 PM PDT 24
Finished Jun 27 06:25:20 PM PDT 24
Peak memory 241048 kb
Host smart-dc2d658c-4451-46ef-bbc6-cfdb608ddbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659915227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1659915227
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3905184048
Short name T474
Test name
Test status
Simulation time 5798335414 ps
CPU time 11.62 seconds
Started Jun 27 06:25:16 PM PDT 24
Finished Jun 27 06:25:32 PM PDT 24
Peak memory 222616 kb
Host smart-b0f4307a-69ed-423d-9924-70175997b612
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3905184048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3905184048
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2142112403
Short name T20
Test name
Test status
Simulation time 145565034776 ps
CPU time 195.45 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:28:31 PM PDT 24
Peak memory 249792 kb
Host smart-5ceb4bfa-5be8-4e26-8a93-e82bddf81bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142112403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2142112403
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.552702996
Short name T569
Test name
Test status
Simulation time 3127629337 ps
CPU time 16.28 seconds
Started Jun 27 06:25:07 PM PDT 24
Finished Jun 27 06:25:30 PM PDT 24
Peak memory 220140 kb
Host smart-422332c2-1946-48d4-94ae-0134e9c073dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552702996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.552702996
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2359218181
Short name T900
Test name
Test status
Simulation time 974685523 ps
CPU time 7.49 seconds
Started Jun 27 06:25:08 PM PDT 24
Finished Jun 27 06:25:22 PM PDT 24
Peak memory 216836 kb
Host smart-ded3a037-dce4-4290-b6a1-3f2b675967cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359218181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2359218181
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1752750889
Short name T909
Test name
Test status
Simulation time 170390240 ps
CPU time 3.07 seconds
Started Jun 27 06:25:07 PM PDT 24
Finished Jun 27 06:25:17 PM PDT 24
Peak memory 216796 kb
Host smart-6b241d69-15f2-4fc2-bb7f-115272b4a4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752750889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1752750889
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.162295402
Short name T777
Test name
Test status
Simulation time 58895310 ps
CPU time 0.86 seconds
Started Jun 27 06:25:05 PM PDT 24
Finished Jun 27 06:25:11 PM PDT 24
Peak memory 206484 kb
Host smart-0a6b3d35-b462-4c0a-8908-efc7ee72aabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162295402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.162295402
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.919153615
Short name T408
Test name
Test status
Simulation time 147628568 ps
CPU time 2.41 seconds
Started Jun 27 06:25:08 PM PDT 24
Finished Jun 27 06:25:17 PM PDT 24
Peak memory 233040 kb
Host smart-57c8d1e7-a751-4be5-b7b6-40b3c2814e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919153615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.919153615
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1571999074
Short name T731
Test name
Test status
Simulation time 10816615 ps
CPU time 0.66 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:07 PM PDT 24
Peak memory 206284 kb
Host smart-3b24d31a-68c3-404f-8f44-576403096a0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571999074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1571999074
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3109143743
Short name T548
Test name
Test status
Simulation time 1780749863 ps
CPU time 5.71 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:32 PM PDT 24
Peak memory 225028 kb
Host smart-03423e5c-5124-43fd-8ba6-13e9e9c85a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109143743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3109143743
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2619749833
Short name T676
Test name
Test status
Simulation time 39144588 ps
CPU time 0.74 seconds
Started Jun 27 06:25:10 PM PDT 24
Finished Jun 27 06:25:17 PM PDT 24
Peak memory 207052 kb
Host smart-85590d46-fea7-4ebf-8bd5-cb74c63c6399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619749833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2619749833
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2447682057
Short name T192
Test name
Test status
Simulation time 6128264782 ps
CPU time 44.16 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:26:10 PM PDT 24
Peak memory 249756 kb
Host smart-9650eb8d-9a0a-4346-bb37-3c38cbbbb644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447682057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2447682057
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3184169532
Short name T223
Test name
Test status
Simulation time 29632670510 ps
CPU time 183.08 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:28:29 PM PDT 24
Peak memory 258020 kb
Host smart-91f53dd2-8f50-4ff9-b03b-7c93708f9627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184169532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3184169532
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.139262375
Short name T210
Test name
Test status
Simulation time 110287197621 ps
CPU time 529.06 seconds
Started Jun 27 06:25:13 PM PDT 24
Finished Jun 27 06:34:07 PM PDT 24
Peak memory 263796 kb
Host smart-28fa9980-374f-4aec-beb9-ca1a1f52104d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139262375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.139262375
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1341526763
Short name T661
Test name
Test status
Simulation time 279430755 ps
CPU time 3.22 seconds
Started Jun 27 06:25:10 PM PDT 24
Finished Jun 27 06:25:19 PM PDT 24
Peak memory 233128 kb
Host smart-6b06657c-24fc-4660-96a9-551c49f77d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341526763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1341526763
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.566487545
Short name T84
Test name
Test status
Simulation time 47266221575 ps
CPU time 118.73 seconds
Started Jun 27 06:25:07 PM PDT 24
Finished Jun 27 06:27:12 PM PDT 24
Peak memory 250784 kb
Host smart-e764ae27-1a9b-4379-aede-5df988f5f957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566487545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.566487545
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.521859598
Short name T11
Test name
Test status
Simulation time 377345114 ps
CPU time 4.12 seconds
Started Jun 27 06:25:12 PM PDT 24
Finished Jun 27 06:25:22 PM PDT 24
Peak memory 233136 kb
Host smart-2b2537ee-905f-4a0a-a27c-a45008903a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521859598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.521859598
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3321800465
Short name T221
Test name
Test status
Simulation time 19039195435 ps
CPU time 45.94 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:51 PM PDT 24
Peak memory 235372 kb
Host smart-fb74b9e2-beab-40ca-966a-f3cf10240a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321800465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3321800465
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4245241547
Short name T504
Test name
Test status
Simulation time 45283239866 ps
CPU time 30.43 seconds
Started Jun 27 06:25:17 PM PDT 24
Finished Jun 27 06:25:52 PM PDT 24
Peak memory 233328 kb
Host smart-b67d8e65-7f75-453a-956d-67c501b1f80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245241547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4245241547
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4247093080
Short name T835
Test name
Test status
Simulation time 29376454176 ps
CPU time 11.12 seconds
Started Jun 27 06:25:17 PM PDT 24
Finished Jun 27 06:25:33 PM PDT 24
Peak memory 235932 kb
Host smart-4387d360-c2ab-43f3-bb25-e391f927e2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247093080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4247093080
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1194333433
Short name T24
Test name
Test status
Simulation time 736700011 ps
CPU time 8.18 seconds
Started Jun 27 06:25:12 PM PDT 24
Finished Jun 27 06:25:26 PM PDT 24
Peak memory 221120 kb
Host smart-ea3a834a-fbb9-47c9-bb80-574b12d3e00c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1194333433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1194333433
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2009259742
Short name T293
Test name
Test status
Simulation time 124403861093 ps
CPU time 321.41 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:30:48 PM PDT 24
Peak memory 270872 kb
Host smart-9c0d5b98-081f-4e8b-9a39-2c76fb3bb43d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009259742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2009259742
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1174343406
Short name T393
Test name
Test status
Simulation time 9729225965 ps
CPU time 26.62 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:25:42 PM PDT 24
Peak memory 216884 kb
Host smart-eec8831b-d4b8-42ba-9de7-50c9d23b57ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174343406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1174343406
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3325138092
Short name T941
Test name
Test status
Simulation time 15890984210 ps
CPU time 17.37 seconds
Started Jun 27 06:25:08 PM PDT 24
Finished Jun 27 06:25:31 PM PDT 24
Peak memory 216856 kb
Host smart-6f1b33e7-0928-4276-a5f5-cc2e2669097e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325138092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3325138092
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2419924319
Short name T813
Test name
Test status
Simulation time 192068748 ps
CPU time 5.42 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:32 PM PDT 24
Peak memory 216832 kb
Host smart-aab13ce9-dd81-4d58-8332-1a30ea57b9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419924319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2419924319
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3319493476
Short name T653
Test name
Test status
Simulation time 37823186 ps
CPU time 0.8 seconds
Started Jun 27 06:25:15 PM PDT 24
Finished Jun 27 06:25:20 PM PDT 24
Peak memory 206428 kb
Host smart-ab619fa0-132a-48d5-baf3-840dc1d3a07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319493476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3319493476
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1655947955
Short name T844
Test name
Test status
Simulation time 6544912852 ps
CPU time 9.58 seconds
Started Jun 27 06:25:12 PM PDT 24
Finished Jun 27 06:25:27 PM PDT 24
Peak memory 233280 kb
Host smart-eded146d-9793-49d9-b11d-32221640907d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655947955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1655947955
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2231842801
Short name T529
Test name
Test status
Simulation time 14799083 ps
CPU time 0.72 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:25:29 PM PDT 24
Peak memory 206212 kb
Host smart-7e1f0f22-238b-44f7-9871-0ae1945a82bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231842801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2231842801
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1135676956
Short name T743
Test name
Test status
Simulation time 123309126 ps
CPU time 2.24 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:25:31 PM PDT 24
Peak memory 233200 kb
Host smart-03e174e7-5f19-4568-aca3-6fdee4c8b1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135676956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1135676956
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2377144896
Short name T611
Test name
Test status
Simulation time 63559339 ps
CPU time 0.79 seconds
Started Jun 27 06:25:13 PM PDT 24
Finished Jun 27 06:25:19 PM PDT 24
Peak memory 207368 kb
Host smart-03c172c7-b6b6-4417-b80d-8b691de58619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377144896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2377144896
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.89272250
Short name T40
Test name
Test status
Simulation time 15716008892 ps
CPU time 40.14 seconds
Started Jun 27 06:25:35 PM PDT 24
Finished Jun 27 06:26:21 PM PDT 24
Peak memory 257676 kb
Host smart-1eec08da-7479-449b-9bfd-3aa9e3d28b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89272250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.89272250
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.912975794
Short name T301
Test name
Test status
Simulation time 26852663292 ps
CPU time 93.07 seconds
Started Jun 27 06:25:18 PM PDT 24
Finished Jun 27 06:26:56 PM PDT 24
Peak memory 249824 kb
Host smart-1e5b7b3d-85f1-4432-b97e-4c678f9ea337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912975794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.912975794
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4085836987
Short name T951
Test name
Test status
Simulation time 52334245107 ps
CPU time 466.1 seconds
Started Jun 27 06:25:29 PM PDT 24
Finished Jun 27 06:33:20 PM PDT 24
Peak memory 251156 kb
Host smart-743efa4c-51f0-462d-9969-946c9ee23c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085836987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4085836987
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2496351615
Short name T318
Test name
Test status
Simulation time 990251962 ps
CPU time 10.56 seconds
Started Jun 27 06:25:25 PM PDT 24
Finished Jun 27 06:25:41 PM PDT 24
Peak memory 234108 kb
Host smart-4bacbc5c-6bfc-4adc-8e93-145a75a7271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496351615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2496351615
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.894443370
Short name T275
Test name
Test status
Simulation time 34632036637 ps
CPU time 77.16 seconds
Started Jun 27 06:25:32 PM PDT 24
Finished Jun 27 06:26:54 PM PDT 24
Peak memory 249768 kb
Host smart-957ed751-147e-4149-a47c-9ae55947c59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894443370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.894443370
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3739311441
Short name T932
Test name
Test status
Simulation time 148686118 ps
CPU time 3.97 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:10 PM PDT 24
Peak memory 225024 kb
Host smart-59f835f3-676f-4821-b945-0c3f0fe99697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739311441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3739311441
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.534773259
Short name T265
Test name
Test status
Simulation time 958692214 ps
CPU time 10.23 seconds
Started Jun 27 06:25:08 PM PDT 24
Finished Jun 27 06:25:25 PM PDT 24
Peak memory 233152 kb
Host smart-00fd7b86-c0dc-4634-a7c3-547359bd7ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534773259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.534773259
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.396684186
Short name T269
Test name
Test status
Simulation time 275971343 ps
CPU time 2.8 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:25:18 PM PDT 24
Peak memory 225000 kb
Host smart-4511dec7-db67-4297-917b-630e9bfc1f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396684186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.396684186
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3589786996
Short name T188
Test name
Test status
Simulation time 10274681951 ps
CPU time 25.34 seconds
Started Jun 27 06:25:16 PM PDT 24
Finished Jun 27 06:25:46 PM PDT 24
Peak memory 233264 kb
Host smart-816ce4ab-8e78-440b-a0e7-d0789a83eac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589786996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3589786996
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.648328901
Short name T975
Test name
Test status
Simulation time 18124382349 ps
CPU time 15.53 seconds
Started Jun 27 06:25:26 PM PDT 24
Finished Jun 27 06:25:47 PM PDT 24
Peak memory 223636 kb
Host smart-d57d23b2-6321-4936-b37f-0f2643db8b84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=648328901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.648328901
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2159056321
Short name T82
Test name
Test status
Simulation time 344342163038 ps
CPU time 188.53 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:28:35 PM PDT 24
Peak memory 272992 kb
Host smart-aa81e32e-976f-4f4b-a210-2ce947ecb54b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159056321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2159056321
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2218128864
Short name T789
Test name
Test status
Simulation time 765896297 ps
CPU time 8.79 seconds
Started Jun 27 06:25:10 PM PDT 24
Finished Jun 27 06:25:25 PM PDT 24
Peak memory 216740 kb
Host smart-dbe65274-ec10-467b-b4e7-0ecc750620cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218128864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2218128864
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2398266373
Short name T620
Test name
Test status
Simulation time 1634449880 ps
CPU time 6.27 seconds
Started Jun 27 06:25:03 PM PDT 24
Finished Jun 27 06:25:13 PM PDT 24
Peak memory 216848 kb
Host smart-bcb0f856-92a4-4133-96ca-35a98dc610e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398266373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2398266373
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2783198391
Short name T681
Test name
Test status
Simulation time 12334487 ps
CPU time 0.69 seconds
Started Jun 27 06:25:09 PM PDT 24
Finished Jun 27 06:25:16 PM PDT 24
Peak memory 206124 kb
Host smart-4a06d941-411f-486d-9d14-37e939ea2df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783198391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2783198391
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1568610694
Short name T865
Test name
Test status
Simulation time 31981952 ps
CPU time 0.84 seconds
Started Jun 27 06:25:04 PM PDT 24
Finished Jun 27 06:25:10 PM PDT 24
Peak memory 206424 kb
Host smart-734a54d6-08f3-42a8-9d4d-1a20bb3cdc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568610694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1568610694
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2282672952
Short name T283
Test name
Test status
Simulation time 178877088 ps
CPU time 3.46 seconds
Started Jun 27 06:25:13 PM PDT 24
Finished Jun 27 06:25:21 PM PDT 24
Peak memory 224968 kb
Host smart-5caa5aa2-08ab-47ef-b09c-2d8ff05987e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282672952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2282672952
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2608118219
Short name T385
Test name
Test status
Simulation time 43665817 ps
CPU time 0.74 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:25:30 PM PDT 24
Peak memory 205940 kb
Host smart-fc4b2570-d508-4906-907e-e0f7281a2508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608118219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2608118219
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.980442642
Short name T242
Test name
Test status
Simulation time 321566520 ps
CPU time 5.44 seconds
Started Jun 27 06:25:18 PM PDT 24
Finished Jun 27 06:25:28 PM PDT 24
Peak memory 233048 kb
Host smart-51173f63-48a2-40d6-b784-2590440cd55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980442642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.980442642
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4239521947
Short name T917
Test name
Test status
Simulation time 14387872 ps
CPU time 0.77 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:25:30 PM PDT 24
Peak memory 206080 kb
Host smart-4d267de2-50da-4306-992f-d494b3e75d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239521947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4239521947
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.840645036
Short name T219
Test name
Test status
Simulation time 2591531730 ps
CPU time 26.1 seconds
Started Jun 27 06:25:19 PM PDT 24
Finished Jun 27 06:25:50 PM PDT 24
Peak memory 241492 kb
Host smart-2c252c41-69ed-4d99-b3ee-fa1ccb13bff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840645036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.840645036
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3845795380
Short name T707
Test name
Test status
Simulation time 3978930988 ps
CPU time 70.47 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:26:47 PM PDT 24
Peak memory 249924 kb
Host smart-fd3d586d-0fee-49bf-aa5d-262aebe485a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845795380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3845795380
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.752972065
Short name T27
Test name
Test status
Simulation time 45987699576 ps
CPU time 286.13 seconds
Started Jun 27 06:25:18 PM PDT 24
Finished Jun 27 06:30:09 PM PDT 24
Peak memory 249816 kb
Host smart-dcca041c-e818-4ca0-8fa2-b2762b9b1eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752972065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.752972065
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2600758224
Short name T349
Test name
Test status
Simulation time 1366090831 ps
CPU time 7.79 seconds
Started Jun 27 06:25:24 PM PDT 24
Finished Jun 27 06:25:38 PM PDT 24
Peak memory 233160 kb
Host smart-ed1173c9-d956-414e-bbee-7817be0b977b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600758224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2600758224
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1876090455
Short name T306
Test name
Test status
Simulation time 31200461637 ps
CPU time 196.86 seconds
Started Jun 27 06:25:16 PM PDT 24
Finished Jun 27 06:28:37 PM PDT 24
Peak memory 251860 kb
Host smart-75fe420d-e90d-49da-8f47-a563863350d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876090455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1876090455
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1634549733
Short name T619
Test name
Test status
Simulation time 2305239578 ps
CPU time 2.93 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:25:39 PM PDT 24
Peak memory 225132 kb
Host smart-e73b1afd-1352-48f1-bc4c-82396149ff08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634549733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1634549733
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3038366856
Short name T55
Test name
Test status
Simulation time 4918421843 ps
CPU time 9.93 seconds
Started Jun 27 06:25:22 PM PDT 24
Finished Jun 27 06:25:38 PM PDT 24
Peak memory 233296 kb
Host smart-0955c08a-d6c7-46a7-bac1-2215d0e8455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038366856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3038366856
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.734851731
Short name T698
Test name
Test status
Simulation time 33512742038 ps
CPU time 18.97 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:25:47 PM PDT 24
Peak memory 225096 kb
Host smart-51e262e9-2505-4c68-95e0-8dfd2cb6b55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734851731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.734851731
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2407891968
Short name T779
Test name
Test status
Simulation time 36556674970 ps
CPU time 25.61 seconds
Started Jun 27 06:25:32 PM PDT 24
Finished Jun 27 06:26:03 PM PDT 24
Peak memory 233328 kb
Host smart-8c769f85-9f4d-4d9d-bae8-7706e3b8840e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407891968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2407891968
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1883250461
Short name T597
Test name
Test status
Simulation time 2269199931 ps
CPU time 5.09 seconds
Started Jun 27 06:25:17 PM PDT 24
Finished Jun 27 06:25:27 PM PDT 24
Peak memory 223820 kb
Host smart-66b3ef00-692a-468a-8b61-b9b1856318cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1883250461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1883250461
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.818254639
Short name T21
Test name
Test status
Simulation time 74892726581 ps
CPU time 409.61 seconds
Started Jun 27 06:25:21 PM PDT 24
Finished Jun 27 06:32:17 PM PDT 24
Peak memory 250356 kb
Host smart-e247de0c-7ee5-4055-809b-616c4de42ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818254639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.818254639
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1255776240
Short name T549
Test name
Test status
Simulation time 1016782897 ps
CPU time 8.07 seconds
Started Jun 27 06:25:19 PM PDT 24
Finished Jun 27 06:25:33 PM PDT 24
Peak memory 216708 kb
Host smart-610596cf-3d8c-4628-91fb-9214f468938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255776240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1255776240
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3179366665
Short name T792
Test name
Test status
Simulation time 1780878058 ps
CPU time 4.59 seconds
Started Jun 27 06:25:19 PM PDT 24
Finished Jun 27 06:25:29 PM PDT 24
Peak memory 216700 kb
Host smart-48b505b9-77e0-477c-bc7e-82b519fd39b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179366665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3179366665
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.853543946
Short name T513
Test name
Test status
Simulation time 275624303 ps
CPU time 2.91 seconds
Started Jun 27 06:25:18 PM PDT 24
Finished Jun 27 06:25:26 PM PDT 24
Peak memory 216744 kb
Host smart-2cb7bf3c-4200-4704-88ea-f5fe13c4f5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853543946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.853543946
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3754380279
Short name T806
Test name
Test status
Simulation time 223069385 ps
CPU time 1.03 seconds
Started Jun 27 06:25:21 PM PDT 24
Finished Jun 27 06:25:28 PM PDT 24
Peak memory 207464 kb
Host smart-75a18fbd-9b36-4110-9891-96f078f8161f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754380279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3754380279
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.414001503
Short name T713
Test name
Test status
Simulation time 5655533717 ps
CPU time 5.99 seconds
Started Jun 27 06:25:17 PM PDT 24
Finished Jun 27 06:25:28 PM PDT 24
Peak memory 233300 kb
Host smart-4356efe6-ffeb-40da-8b72-bd900a951f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414001503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.414001503
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1803669399
Short name T394
Test name
Test status
Simulation time 13705486 ps
CPU time 0.73 seconds
Started Jun 27 06:25:21 PM PDT 24
Finished Jun 27 06:25:28 PM PDT 24
Peak memory 206228 kb
Host smart-76232413-8f31-46b9-b7da-3fe10c0d7bb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803669399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1803669399
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1891664434
Short name T599
Test name
Test status
Simulation time 108998096 ps
CPU time 2.38 seconds
Started Jun 27 06:25:18 PM PDT 24
Finished Jun 27 06:25:25 PM PDT 24
Peak memory 224908 kb
Host smart-e07bcebf-f487-4a1b-ae42-b6a9040b0328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891664434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1891664434
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1768787807
Short name T345
Test name
Test status
Simulation time 330775954 ps
CPU time 0.78 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:25:37 PM PDT 24
Peak memory 207084 kb
Host smart-b5c4cde6-c53e-4f32-9923-f97d32f08bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768787807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1768787807
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2866774996
Short name T405
Test name
Test status
Simulation time 16651477747 ps
CPU time 39.41 seconds
Started Jun 27 06:25:29 PM PDT 24
Finished Jun 27 06:26:13 PM PDT 24
Peak memory 249752 kb
Host smart-73024008-7b75-4ea8-83f3-55277b285e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866774996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2866774996
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.26333314
Short name T755
Test name
Test status
Simulation time 2110264472 ps
CPU time 12.98 seconds
Started Jun 27 06:25:19 PM PDT 24
Finished Jun 27 06:25:37 PM PDT 24
Peak memory 218120 kb
Host smart-fc990c04-83d1-4aa4-9d06-625ff6cc975e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26333314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.26333314
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1642340271
Short name T234
Test name
Test status
Simulation time 5107117772 ps
CPU time 12.95 seconds
Started Jun 27 06:25:33 PM PDT 24
Finished Jun 27 06:25:51 PM PDT 24
Peak memory 234388 kb
Host smart-96e3d447-3169-4a3b-9d08-2d846d27bb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642340271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1642340271
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2695126287
Short name T631
Test name
Test status
Simulation time 31089671 ps
CPU time 2.13 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:25:32 PM PDT 24
Peak memory 223700 kb
Host smart-7ed7961a-1687-4aee-b5bb-ec36acaa9ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695126287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2695126287
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.100184060
Short name T54
Test name
Test status
Simulation time 21963461070 ps
CPU time 53.71 seconds
Started Jun 27 06:25:16 PM PDT 24
Finished Jun 27 06:26:14 PM PDT 24
Peak memory 233500 kb
Host smart-e3dc46d2-21fd-4fdb-bd8c-393c0940961a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100184060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.100184060
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3263519561
Short name T657
Test name
Test status
Simulation time 110650038 ps
CPU time 2.28 seconds
Started Jun 27 06:25:19 PM PDT 24
Finished Jun 27 06:25:26 PM PDT 24
Peak memory 224900 kb
Host smart-dce97eaf-d89c-45ec-9d9e-3cea39040e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263519561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3263519561
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3721370069
Short name T929
Test name
Test status
Simulation time 906656848 ps
CPU time 5.95 seconds
Started Jun 27 06:25:30 PM PDT 24
Finished Jun 27 06:25:41 PM PDT 24
Peak memory 234256 kb
Host smart-4b4296ef-d716-4d9c-a1c3-0a3ea2f19da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721370069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3721370069
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2875279202
Short name T927
Test name
Test status
Simulation time 365553345 ps
CPU time 3.35 seconds
Started Jun 27 06:25:22 PM PDT 24
Finished Jun 27 06:25:32 PM PDT 24
Peak memory 220956 kb
Host smart-271e370e-95f4-465b-a860-a6b4d9b030d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2875279202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2875279202
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.838911611
Short name T324
Test name
Test status
Simulation time 3683582937 ps
CPU time 27.64 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:54 PM PDT 24
Peak memory 216984 kb
Host smart-56b891fc-d2b5-4204-ab90-9966c895e1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838911611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.838911611
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2212202827
Short name T669
Test name
Test status
Simulation time 367024456 ps
CPU time 1.57 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:27 PM PDT 24
Peak memory 208368 kb
Host smart-7b7fcfea-afe5-455a-9338-1c87223c8031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212202827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2212202827
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.242816159
Short name T479
Test name
Test status
Simulation time 24227578 ps
CPU time 1.23 seconds
Started Jun 27 06:25:19 PM PDT 24
Finished Jun 27 06:25:26 PM PDT 24
Peak memory 208444 kb
Host smart-3bbcfca9-55d0-4977-8020-bba0bc3dfbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242816159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.242816159
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3500929532
Short name T357
Test name
Test status
Simulation time 36694173 ps
CPU time 0.75 seconds
Started Jun 27 06:25:17 PM PDT 24
Finished Jun 27 06:25:22 PM PDT 24
Peak memory 206460 kb
Host smart-82d087f6-7c9a-4875-a1fe-37d197049133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500929532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3500929532
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.249986160
Short name T672
Test name
Test status
Simulation time 4483813910 ps
CPU time 12.11 seconds
Started Jun 27 06:25:22 PM PDT 24
Finished Jun 27 06:25:40 PM PDT 24
Peak memory 225072 kb
Host smart-377d0e79-0a10-4543-8d2f-41205f2969b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249986160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.249986160
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2483154305
Short name T346
Test name
Test status
Simulation time 18517493 ps
CPU time 0.69 seconds
Started Jun 27 06:25:34 PM PDT 24
Finished Jun 27 06:25:40 PM PDT 24
Peak memory 206220 kb
Host smart-07aa32de-380a-4d25-8f3c-017a5ad36094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483154305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2483154305
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2030948176
Short name T44
Test name
Test status
Simulation time 1738375777 ps
CPU time 5.2 seconds
Started Jun 27 06:25:18 PM PDT 24
Finished Jun 27 06:25:29 PM PDT 24
Peak memory 225000 kb
Host smart-dd0d3241-717f-475c-a45c-c77e0a0a92b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030948176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2030948176
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1411676811
Short name T732
Test name
Test status
Simulation time 15467784 ps
CPU time 0.82 seconds
Started Jun 27 06:25:36 PM PDT 24
Finished Jun 27 06:25:43 PM PDT 24
Peak memory 206428 kb
Host smart-af5f6ae0-23d2-4a69-9d71-1eced04c730f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411676811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1411676811
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.404977717
Short name T186
Test name
Test status
Simulation time 105217746773 ps
CPU time 145.29 seconds
Started Jun 27 06:25:30 PM PDT 24
Finished Jun 27 06:28:01 PM PDT 24
Peak memory 257924 kb
Host smart-7d9a7872-70df-4617-9b61-3031cdd72970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404977717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.404977717
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3141967825
Short name T526
Test name
Test status
Simulation time 134701922312 ps
CPU time 162.77 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:28:12 PM PDT 24
Peak memory 254448 kb
Host smart-168577a9-172a-485a-a991-e299bd06feb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141967825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3141967825
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.133755192
Short name T182
Test name
Test status
Simulation time 7410944227 ps
CPU time 52.59 seconds
Started Jun 27 06:25:22 PM PDT 24
Finished Jun 27 06:26:20 PM PDT 24
Peak memory 225228 kb
Host smart-60e5c9a5-1d4d-4d73-ae49-15aa1a1324ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133755192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.133755192
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1020532453
Short name T817
Test name
Test status
Simulation time 263982403 ps
CPU time 3.73 seconds
Started Jun 27 06:25:19 PM PDT 24
Finished Jun 27 06:25:28 PM PDT 24
Peak memory 224976 kb
Host smart-6c1f58ee-582a-4e78-bfc7-53be6cd5d014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020532453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1020532453
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.402837487
Short name T452
Test name
Test status
Simulation time 4569109793 ps
CPU time 8.88 seconds
Started Jun 27 06:25:25 PM PDT 24
Finished Jun 27 06:25:40 PM PDT 24
Peak memory 225148 kb
Host smart-e6d62731-9747-47d2-933c-58a3f444f388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402837487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.402837487
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.267136707
Short name T774
Test name
Test status
Simulation time 656942926 ps
CPU time 8.23 seconds
Started Jun 27 06:25:26 PM PDT 24
Finished Jun 27 06:25:40 PM PDT 24
Peak memory 233240 kb
Host smart-2b1eb9c6-a4a9-499f-860f-4ce0a39c7825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267136707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.267136707
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3615960445
Short name T757
Test name
Test status
Simulation time 1539991165 ps
CPU time 10.22 seconds
Started Jun 27 06:25:32 PM PDT 24
Finished Jun 27 06:25:47 PM PDT 24
Peak memory 233152 kb
Host smart-6dd4aef8-9b7f-4d89-90f3-1ab7ae7e24ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615960445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3615960445
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2594217702
Short name T705
Test name
Test status
Simulation time 397661933 ps
CPU time 5.33 seconds
Started Jun 27 06:25:32 PM PDT 24
Finished Jun 27 06:25:43 PM PDT 24
Peak memory 233164 kb
Host smart-f12143ed-abf6-4241-a261-279a68a0391d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594217702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2594217702
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2318955968
Short name T508
Test name
Test status
Simulation time 1279068758 ps
CPU time 4.78 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:31 PM PDT 24
Peak memory 224980 kb
Host smart-b48b9e0e-19bc-4a1b-a70f-d9e505d1473a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318955968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2318955968
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.724053648
Short name T694
Test name
Test status
Simulation time 708487063 ps
CPU time 9.61 seconds
Started Jun 27 06:25:19 PM PDT 24
Finished Jun 27 06:25:34 PM PDT 24
Peak memory 220696 kb
Host smart-1f1c95fd-25cc-4714-a1fd-55b0f6921d53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=724053648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.724053648
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2560996893
Short name T911
Test name
Test status
Simulation time 12024524434 ps
CPU time 68.52 seconds
Started Jun 27 06:25:22 PM PDT 24
Finished Jun 27 06:26:37 PM PDT 24
Peak memory 249896 kb
Host smart-51f57942-1de4-4f6b-9501-34db1ccd7ecb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560996893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2560996893
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3427377491
Short name T530
Test name
Test status
Simulation time 26995970352 ps
CPU time 23.58 seconds
Started Jun 27 06:25:18 PM PDT 24
Finished Jun 27 06:25:47 PM PDT 24
Peak memory 216924 kb
Host smart-692ddd79-8630-4773-b049-4b8adcad7fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427377491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3427377491
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1306511441
Short name T616
Test name
Test status
Simulation time 6604785761 ps
CPU time 8.24 seconds
Started Jun 27 06:25:19 PM PDT 24
Finished Jun 27 06:25:33 PM PDT 24
Peak memory 216896 kb
Host smart-48ef16e6-033c-4215-84bd-0808eb21c25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306511441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1306511441
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2335068847
Short name T568
Test name
Test status
Simulation time 28943298 ps
CPU time 1.01 seconds
Started Jun 27 06:25:19 PM PDT 24
Finished Jun 27 06:25:26 PM PDT 24
Peak memory 207836 kb
Host smart-79f6ecfd-9c73-4a4f-bb0c-54e761ecd2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335068847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2335068847
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1854626443
Short name T716
Test name
Test status
Simulation time 930218447 ps
CPU time 0.95 seconds
Started Jun 27 06:25:21 PM PDT 24
Finished Jun 27 06:25:28 PM PDT 24
Peak memory 207508 kb
Host smart-d7befa15-4729-41c9-90c7-8eabf6b7fd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854626443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1854626443
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2776714121
Short name T248
Test name
Test status
Simulation time 188713520 ps
CPU time 3.61 seconds
Started Jun 27 06:25:26 PM PDT 24
Finished Jun 27 06:25:35 PM PDT 24
Peak memory 225028 kb
Host smart-379de294-ca08-4305-948a-b99b2558c71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776714121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2776714121
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1563274094
Short name T649
Test name
Test status
Simulation time 56166502 ps
CPU time 0.7 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:25:30 PM PDT 24
Peak memory 205316 kb
Host smart-f54f1456-3e73-47a2-bd7e-1fbf61575340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563274094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1563274094
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.30340472
Short name T506
Test name
Test status
Simulation time 296014360 ps
CPU time 2.18 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:25:38 PM PDT 24
Peak memory 224628 kb
Host smart-df2f8bd7-71d0-453b-b63c-afd3097ea2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30340472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.30340472
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.4123896165
Short name T352
Test name
Test status
Simulation time 26598006 ps
CPU time 0.77 seconds
Started Jun 27 06:25:36 PM PDT 24
Finished Jun 27 06:25:42 PM PDT 24
Peak memory 206092 kb
Host smart-b50673d0-db94-4d9e-8cb7-65bb0bd42d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123896165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4123896165
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3913065935
Short name T810
Test name
Test status
Simulation time 43331512 ps
CPU time 0.75 seconds
Started Jun 27 06:25:22 PM PDT 24
Finished Jun 27 06:25:29 PM PDT 24
Peak memory 216348 kb
Host smart-56f044b7-1ff8-47fb-b8f4-dd8fd770ed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913065935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3913065935
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1787528602
Short name T767
Test name
Test status
Simulation time 5666512362 ps
CPU time 78.64 seconds
Started Jun 27 06:25:19 PM PDT 24
Finished Jun 27 06:26:43 PM PDT 24
Peak memory 249840 kb
Host smart-f8556d1c-a033-490a-a1ec-101192afa2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787528602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1787528602
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.221165937
Short name T754
Test name
Test status
Simulation time 8184021269 ps
CPU time 81.88 seconds
Started Jun 27 06:25:33 PM PDT 24
Finished Jun 27 06:27:00 PM PDT 24
Peak memory 249804 kb
Host smart-57dbfd53-fb86-41e7-913e-44b57a702e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221165937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.221165937
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2945829793
Short name T428
Test name
Test status
Simulation time 2968218585 ps
CPU time 58.63 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:26:25 PM PDT 24
Peak memory 255820 kb
Host smart-1edd6535-913c-44b4-b3e7-30a62a53d884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945829793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2945829793
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1254450538
Short name T194
Test name
Test status
Simulation time 1421334402 ps
CPU time 9.01 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:25:45 PM PDT 24
Peak memory 224972 kb
Host smart-ea630dcf-5014-444c-9f66-277d2eb62be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254450538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1254450538
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1149741490
Short name T833
Test name
Test status
Simulation time 1161449241 ps
CPU time 8.5 seconds
Started Jun 27 06:25:34 PM PDT 24
Finished Jun 27 06:25:48 PM PDT 24
Peak memory 237960 kb
Host smart-29a11abd-56a2-4d48-a238-330c9f09c6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149741490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1149741490
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2073784026
Short name T795
Test name
Test status
Simulation time 4228563622 ps
CPU time 12.14 seconds
Started Jun 27 06:25:34 PM PDT 24
Finished Jun 27 06:25:52 PM PDT 24
Peak memory 233288 kb
Host smart-17dedfa7-d297-420f-b875-ca399b7d5fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073784026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2073784026
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2351504379
Short name T613
Test name
Test status
Simulation time 9660043594 ps
CPU time 8.92 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:34 PM PDT 24
Peak memory 233312 kb
Host smart-724efd88-4deb-4e76-97cd-c11ce2ab5010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351504379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2351504379
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2210853137
Short name T143
Test name
Test status
Simulation time 9087533657 ps
CPU time 11.02 seconds
Started Jun 27 06:25:24 PM PDT 24
Finished Jun 27 06:25:41 PM PDT 24
Peak memory 221368 kb
Host smart-24d9856d-8132-4b86-9a1f-11f332c04ab0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2210853137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2210853137
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3672612109
Short name T207
Test name
Test status
Simulation time 30333547179 ps
CPU time 248.93 seconds
Started Jun 27 06:25:22 PM PDT 24
Finished Jun 27 06:29:37 PM PDT 24
Peak memory 255056 kb
Host smart-23382fac-3c2d-476b-b2f4-6ad59c199524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672612109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3672612109
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3045250264
Short name T1011
Test name
Test status
Simulation time 14322092594 ps
CPU time 18.44 seconds
Started Jun 27 06:25:18 PM PDT 24
Finished Jun 27 06:25:42 PM PDT 24
Peak memory 216908 kb
Host smart-c5715b67-5384-4823-a8a4-6de287d2ee66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045250264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3045250264
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1427893973
Short name T830
Test name
Test status
Simulation time 1498742938 ps
CPU time 7.29 seconds
Started Jun 27 06:25:34 PM PDT 24
Finished Jun 27 06:25:47 PM PDT 24
Peak memory 216792 kb
Host smart-be9fb980-ca71-4e3d-bb96-ce662087b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427893973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1427893973
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.774796675
Short name T969
Test name
Test status
Simulation time 169016945 ps
CPU time 2.5 seconds
Started Jun 27 06:25:33 PM PDT 24
Finished Jun 27 06:25:41 PM PDT 24
Peak memory 216808 kb
Host smart-af1f77e1-0254-4b71-893b-c9299063be33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774796675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.774796675
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2592960636
Short name T632
Test name
Test status
Simulation time 615469994 ps
CPU time 1.08 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:26 PM PDT 24
Peak memory 207468 kb
Host smart-fce1dba3-19aa-4ebd-a9d8-21321496b693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592960636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2592960636
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1413743667
Short name T542
Test name
Test status
Simulation time 2845686591 ps
CPU time 9.19 seconds
Started Jun 27 06:25:24 PM PDT 24
Finished Jun 27 06:25:39 PM PDT 24
Peak memory 233296 kb
Host smart-4dd3cd4f-0521-43c2-91d2-3688c1f61717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413743667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1413743667
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1845220202
Short name T809
Test name
Test status
Simulation time 14717013 ps
CPU time 0.76 seconds
Started Jun 27 06:25:22 PM PDT 24
Finished Jun 27 06:25:29 PM PDT 24
Peak memory 206240 kb
Host smart-81c99759-5196-4736-a115-8b0767dfe1ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845220202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1845220202
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3147228192
Short name T582
Test name
Test status
Simulation time 1518771762 ps
CPU time 5.55 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:25:41 PM PDT 24
Peak memory 233204 kb
Host smart-c276a6c1-e754-44f5-bea0-7bb7e2b0fdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147228192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3147228192
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1424899771
Short name T426
Test name
Test status
Simulation time 14718446 ps
CPU time 0.78 seconds
Started Jun 27 06:25:34 PM PDT 24
Finished Jun 27 06:25:41 PM PDT 24
Peak memory 207432 kb
Host smart-a943363b-fde9-4b47-98d3-536caa2d1fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424899771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1424899771
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2987447963
Short name T636
Test name
Test status
Simulation time 101579651914 ps
CPU time 172.17 seconds
Started Jun 27 06:25:22 PM PDT 24
Finished Jun 27 06:28:20 PM PDT 24
Peak memory 254488 kb
Host smart-30425ba3-0333-4256-82bf-cf7831fd43e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987447963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2987447963
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1502777104
Short name T47
Test name
Test status
Simulation time 4690936498 ps
CPU time 58.56 seconds
Started Jun 27 06:25:25 PM PDT 24
Finished Jun 27 06:26:30 PM PDT 24
Peak memory 250876 kb
Host smart-593b2a61-ea3a-46f4-a0f4-4acdb83001bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502777104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1502777104
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3019768552
Short name T438
Test name
Test status
Simulation time 331974028 ps
CPU time 2.93 seconds
Started Jun 27 06:25:33 PM PDT 24
Finished Jun 27 06:25:42 PM PDT 24
Peak memory 225028 kb
Host smart-fa498aae-f774-4f2c-83c5-db3a3b9e53b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019768552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3019768552
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3151786939
Short name T232
Test name
Test status
Simulation time 17312730990 ps
CPU time 63.16 seconds
Started Jun 27 06:25:24 PM PDT 24
Finished Jun 27 06:26:33 PM PDT 24
Peak memory 233336 kb
Host smart-a6223f11-b63c-420c-b985-2cea1ceb219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151786939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3151786939
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3282616486
Short name T945
Test name
Test status
Simulation time 7694672468 ps
CPU time 6.5 seconds
Started Jun 27 06:25:25 PM PDT 24
Finished Jun 27 06:25:37 PM PDT 24
Peak memory 225096 kb
Host smart-971146a0-3f4f-4b17-b7b8-c0f2c2a68901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282616486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3282616486
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.634953247
Short name T655
Test name
Test status
Simulation time 51663196033 ps
CPU time 69.23 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:26:39 PM PDT 24
Peak memory 241496 kb
Host smart-2e8f9889-7542-45e6-9c5a-e4e5ee61f3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634953247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.634953247
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1968162286
Short name T726
Test name
Test status
Simulation time 126700540 ps
CPU time 3.77 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:25:30 PM PDT 24
Peak memory 233200 kb
Host smart-110ec086-f323-486c-b135-1229d5ae8171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968162286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1968162286
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3893639233
Short name T826
Test name
Test status
Simulation time 17966387548 ps
CPU time 26.99 seconds
Started Jun 27 06:25:24 PM PDT 24
Finished Jun 27 06:25:57 PM PDT 24
Peak memory 240572 kb
Host smart-29aeefd2-b508-44da-bd56-de884cf67160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893639233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3893639233
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1990808543
Short name T382
Test name
Test status
Simulation time 93361458 ps
CPU time 4.06 seconds
Started Jun 27 06:25:24 PM PDT 24
Finished Jun 27 06:25:34 PM PDT 24
Peak memory 223076 kb
Host smart-ed228fa9-139d-4a59-b1ec-abad99873ce0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1990808543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1990808543
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2991532488
Short name T157
Test name
Test status
Simulation time 4485362088 ps
CPU time 95.07 seconds
Started Jun 27 06:25:30 PM PDT 24
Finished Jun 27 06:27:10 PM PDT 24
Peak memory 266232 kb
Host smart-18b9adf8-1ddf-4f18-8e19-d084fc7e0541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991532488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2991532488
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3563424531
Short name T977
Test name
Test status
Simulation time 93733385137 ps
CPU time 31.03 seconds
Started Jun 27 06:25:30 PM PDT 24
Finished Jun 27 06:26:05 PM PDT 24
Peak memory 216976 kb
Host smart-836bb3c6-6363-4373-ab5a-cd59b3159562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563424531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3563424531
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.294008790
Short name T704
Test name
Test status
Simulation time 943184602 ps
CPU time 4.9 seconds
Started Jun 27 06:25:25 PM PDT 24
Finished Jun 27 06:25:36 PM PDT 24
Peak memory 216732 kb
Host smart-0e692148-e036-4849-ab92-2bbd042b8ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294008790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.294008790
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1203541688
Short name T660
Test name
Test status
Simulation time 86396101 ps
CPU time 1.26 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:25:31 PM PDT 24
Peak memory 208256 kb
Host smart-2e984032-f176-4cd7-ac4d-12cf9471ead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203541688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1203541688
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2874803294
Short name T333
Test name
Test status
Simulation time 34212154 ps
CPU time 0.84 seconds
Started Jun 27 06:25:29 PM PDT 24
Finished Jun 27 06:25:35 PM PDT 24
Peak memory 206736 kb
Host smart-48a3c021-d3a8-45ff-8d67-591c04151586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874803294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2874803294
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3913594705
Short name T404
Test name
Test status
Simulation time 63186895 ps
CPU time 2.01 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:25:38 PM PDT 24
Peak memory 223680 kb
Host smart-c3305720-b857-4442-be89-5539c2fe4ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913594705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3913594705
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.343602837
Short name T65
Test name
Test status
Simulation time 50093518 ps
CPU time 0.8 seconds
Started Jun 27 06:25:35 PM PDT 24
Finished Jun 27 06:25:41 PM PDT 24
Peak memory 205988 kb
Host smart-b416aae0-bafd-4c8e-98f3-24515f091715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343602837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.343602837
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3267032834
Short name T457
Test name
Test status
Simulation time 1446589061 ps
CPU time 3.31 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:25:33 PM PDT 24
Peak memory 225036 kb
Host smart-be4ff1f4-117d-443d-a667-a1433248a255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267032834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3267032834
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2193896046
Short name T918
Test name
Test status
Simulation time 13534024 ps
CPU time 0.75 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:25:30 PM PDT 24
Peak memory 206416 kb
Host smart-a94cd048-7606-4655-baf4-2a4ddd5aca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193896046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2193896046
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3172515595
Short name T476
Test name
Test status
Simulation time 6968597212 ps
CPU time 38.11 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:26:14 PM PDT 24
Peak memory 241520 kb
Host smart-53b8ad65-53f3-4070-bdbc-8141e7172bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172515595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3172515595
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.873418768
Short name T9
Test name
Test status
Simulation time 7123829712 ps
CPU time 51.14 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:26:27 PM PDT 24
Peak memory 250860 kb
Host smart-6e3491e0-9d63-4b4a-88fa-0665c594ca3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873418768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.873418768
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2238525295
Short name T58
Test name
Test status
Simulation time 25292374759 ps
CPU time 47.1 seconds
Started Jun 27 06:25:47 PM PDT 24
Finished Jun 27 06:26:36 PM PDT 24
Peak memory 225264 kb
Host smart-01aceeee-b1c4-451e-95ae-d1d17e9de239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238525295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2238525295
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.442842496
Short name T673
Test name
Test status
Simulation time 469582848 ps
CPU time 7.36 seconds
Started Jun 27 06:25:21 PM PDT 24
Finished Jun 27 06:25:35 PM PDT 24
Peak memory 233204 kb
Host smart-fede1060-7add-43ee-a7a0-f42f475e928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442842496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.442842496
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2127983021
Short name T227
Test name
Test status
Simulation time 81662595466 ps
CPU time 242.98 seconds
Started Jun 27 06:25:32 PM PDT 24
Finished Jun 27 06:29:41 PM PDT 24
Peak memory 256420 kb
Host smart-197abbf7-300b-476e-ac97-4bf623f70990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127983021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2127983021
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.91853892
Short name T749
Test name
Test status
Simulation time 673173835 ps
CPU time 5.03 seconds
Started Jun 27 06:25:32 PM PDT 24
Finished Jun 27 06:25:42 PM PDT 24
Peak memory 233192 kb
Host smart-2a610427-9758-4079-bae8-1cc886fb9978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91853892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.91853892
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2986739064
Short name T654
Test name
Test status
Simulation time 14265495029 ps
CPU time 134.97 seconds
Started Jun 27 06:25:20 PM PDT 24
Finished Jun 27 06:27:41 PM PDT 24
Peak memory 233336 kb
Host smart-a1ca1fc9-6ca5-4e1a-a94a-89309997b201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986739064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2986739064
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.759591412
Short name T854
Test name
Test status
Simulation time 111350250 ps
CPU time 2.62 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:25:39 PM PDT 24
Peak memory 232968 kb
Host smart-865f2671-e3f5-4abf-bfe4-379279326832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759591412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.759591412
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2729473882
Short name T492
Test name
Test status
Simulation time 173719506 ps
CPU time 2.13 seconds
Started Jun 27 06:25:24 PM PDT 24
Finished Jun 27 06:25:32 PM PDT 24
Peak memory 232988 kb
Host smart-b9589759-4228-4001-ac83-280a865dbe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729473882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2729473882
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1017339987
Short name T662
Test name
Test status
Simulation time 572802198 ps
CPU time 4.89 seconds
Started Jun 27 06:25:33 PM PDT 24
Finished Jun 27 06:25:44 PM PDT 24
Peak memory 223084 kb
Host smart-442b98e1-22e0-4acf-8198-9e6ab4a10320
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1017339987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1017339987
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1621664959
Short name T183
Test name
Test status
Simulation time 56087204489 ps
CPU time 373.54 seconds
Started Jun 27 06:25:39 PM PDT 24
Finished Jun 27 06:31:58 PM PDT 24
Peak memory 260860 kb
Host smart-85aedc60-9867-4f3b-803c-5ce2bba7c86a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621664959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1621664959
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2514310136
Short name T992
Test name
Test status
Simulation time 13667493655 ps
CPU time 36.73 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:26:06 PM PDT 24
Peak memory 217144 kb
Host smart-04362984-ce15-4f3f-8a4f-06ccb59849a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514310136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2514310136
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2937018568
Short name T133
Test name
Test status
Simulation time 332975195 ps
CPU time 2.82 seconds
Started Jun 27 06:25:25 PM PDT 24
Finished Jun 27 06:25:33 PM PDT 24
Peak memory 216700 kb
Host smart-bc3a574f-f64e-439c-9187-7238f308e82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937018568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2937018568
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2443637902
Short name T377
Test name
Test status
Simulation time 72809181 ps
CPU time 0.84 seconds
Started Jun 27 06:25:25 PM PDT 24
Finished Jun 27 06:25:31 PM PDT 24
Peak memory 206412 kb
Host smart-8ffbe46f-be36-446a-a4f8-33a5bb373030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443637902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2443637902
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4119389540
Short name T340
Test name
Test status
Simulation time 207935063 ps
CPU time 0.88 seconds
Started Jun 27 06:25:23 PM PDT 24
Finished Jun 27 06:25:30 PM PDT 24
Peak memory 206472 kb
Host smart-7b925053-0ca7-4c8d-8f7a-ac59258dcbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119389540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4119389540
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2462005407
Short name T664
Test name
Test status
Simulation time 738141938 ps
CPU time 3.82 seconds
Started Jun 27 06:25:30 PM PDT 24
Finished Jun 27 06:25:39 PM PDT 24
Peak memory 225024 kb
Host smart-8e761e93-c1c5-4105-8b53-e2b1a3a72847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462005407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2462005407
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3839004683
Short name T890
Test name
Test status
Simulation time 53713125 ps
CPU time 0.7 seconds
Started Jun 27 06:25:33 PM PDT 24
Finished Jun 27 06:25:39 PM PDT 24
Peak memory 205880 kb
Host smart-f6dfd3a6-9723-4c64-b03d-ab399874f6e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839004683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3839004683
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2229338768
Short name T836
Test name
Test status
Simulation time 1840139349 ps
CPU time 5.27 seconds
Started Jun 27 06:25:40 PM PDT 24
Finished Jun 27 06:25:50 PM PDT 24
Peak memory 233364 kb
Host smart-476590a9-1833-444d-953c-999b9b875994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229338768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2229338768
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1429993087
Short name T961
Test name
Test status
Simulation time 49907623 ps
CPU time 0.76 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:25:37 PM PDT 24
Peak memory 206072 kb
Host smart-661b1aab-183c-4494-ac19-42262ace7d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429993087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1429993087
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1437095245
Short name T236
Test name
Test status
Simulation time 3350909844 ps
CPU time 34.41 seconds
Started Jun 27 06:25:38 PM PDT 24
Finished Jun 27 06:26:18 PM PDT 24
Peak memory 250096 kb
Host smart-d3650a9e-2588-47e2-ba4d-df2a551ea15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437095245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1437095245
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.691256998
Short name T524
Test name
Test status
Simulation time 7371297510 ps
CPU time 68.26 seconds
Started Jun 27 06:25:35 PM PDT 24
Finished Jun 27 06:26:49 PM PDT 24
Peak memory 233484 kb
Host smart-886db18a-8b27-4666-af83-acd96901a8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691256998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.691256998
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3603767162
Short name T586
Test name
Test status
Simulation time 4982001679 ps
CPU time 69.99 seconds
Started Jun 27 06:25:34 PM PDT 24
Finished Jun 27 06:26:50 PM PDT 24
Peak memory 249840 kb
Host smart-28d39d0f-b586-4332-8032-333c2a5023c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603767162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3603767162
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2799775615
Short name T740
Test name
Test status
Simulation time 7166749794 ps
CPU time 48.09 seconds
Started Jun 27 06:25:42 PM PDT 24
Finished Jun 27 06:26:34 PM PDT 24
Peak memory 249732 kb
Host smart-5eabcf2a-8e8a-48cb-be34-3897f2869fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799775615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2799775615
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2975351295
Short name T912
Test name
Test status
Simulation time 65398532499 ps
CPU time 193.17 seconds
Started Jun 27 06:25:32 PM PDT 24
Finished Jun 27 06:28:56 PM PDT 24
Peak memory 256028 kb
Host smart-beae0b47-e9fe-4da1-b473-8ad55dbe0b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975351295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2975351295
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.206350091
Short name T239
Test name
Test status
Simulation time 1109510319 ps
CPU time 4.48 seconds
Started Jun 27 06:25:32 PM PDT 24
Finished Jun 27 06:25:41 PM PDT 24
Peak memory 233244 kb
Host smart-e52dc51e-355a-4ef5-ab94-6ee7d8577198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206350091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.206350091
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1090438116
Short name T520
Test name
Test status
Simulation time 2910293228 ps
CPU time 21.71 seconds
Started Jun 27 06:25:41 PM PDT 24
Finished Jun 27 06:26:07 PM PDT 24
Peak memory 225168 kb
Host smart-a16a190c-2756-422c-acaf-24acdf09f545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090438116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1090438116
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.4097194692
Short name T134
Test name
Test status
Simulation time 291293046 ps
CPU time 2.22 seconds
Started Jun 27 06:25:35 PM PDT 24
Finished Jun 27 06:25:43 PM PDT 24
Peak memory 224944 kb
Host smart-61478ab5-715f-40de-88b0-d628b1c12237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097194692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.4097194692
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1107370491
Short name T368
Test name
Test status
Simulation time 29953929 ps
CPU time 2.49 seconds
Started Jun 27 06:25:47 PM PDT 24
Finished Jun 27 06:25:52 PM PDT 24
Peak memory 233000 kb
Host smart-f63c50f5-f2b5-4b3a-8b02-dec7e0b04bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107370491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1107370491
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3411827919
Short name T587
Test name
Test status
Simulation time 204296637 ps
CPU time 4.74 seconds
Started Jun 27 06:25:36 PM PDT 24
Finished Jun 27 06:25:46 PM PDT 24
Peak memory 220056 kb
Host smart-fefdb8dd-7a9e-4f65-ad44-e029cf03d04c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3411827919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3411827919
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2421517602
Short name T16
Test name
Test status
Simulation time 251496128 ps
CPU time 1.19 seconds
Started Jun 27 06:25:43 PM PDT 24
Finished Jun 27 06:25:48 PM PDT 24
Peak memory 215644 kb
Host smart-441de1bf-49a0-44a6-864a-8f7f8d082721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421517602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2421517602
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2157486004
Short name T990
Test name
Test status
Simulation time 4926343044 ps
CPU time 26.37 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:26:02 PM PDT 24
Peak memory 217056 kb
Host smart-b6531896-b3ec-482f-ab0e-bc3f28989432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157486004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2157486004
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3641212880
Short name T639
Test name
Test status
Simulation time 2497702664 ps
CPU time 2.93 seconds
Started Jun 27 06:25:30 PM PDT 24
Finished Jun 27 06:25:38 PM PDT 24
Peak memory 216888 kb
Host smart-d856b357-83e7-4078-8905-93ead214252c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641212880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3641212880
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3337388236
Short name T503
Test name
Test status
Simulation time 11116963 ps
CPU time 0.71 seconds
Started Jun 27 06:25:33 PM PDT 24
Finished Jun 27 06:25:39 PM PDT 24
Peak memory 206124 kb
Host smart-59bd82e2-ae0d-4102-8ee3-52ae3c37fac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337388236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3337388236
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1635462295
Short name T344
Test name
Test status
Simulation time 85543484 ps
CPU time 0.86 seconds
Started Jun 27 06:25:32 PM PDT 24
Finished Jun 27 06:25:38 PM PDT 24
Peak memory 206720 kb
Host smart-7f33b0b6-6c95-4dfe-8363-c3a57af82796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635462295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1635462295
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3361945773
Short name T81
Test name
Test status
Simulation time 50629322987 ps
CPU time 19.82 seconds
Started Jun 27 06:25:31 PM PDT 24
Finished Jun 27 06:25:56 PM PDT 24
Peak memory 234384 kb
Host smart-24a166d3-1e11-40f1-a948-908db3e27c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361945773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3361945773
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3252847801
Short name T816
Test name
Test status
Simulation time 15657212 ps
CPU time 0.74 seconds
Started Jun 27 06:23:20 PM PDT 24
Finished Jun 27 06:23:26 PM PDT 24
Peak memory 205408 kb
Host smart-71fbbfcd-266d-41da-b686-43e05b7f3a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252847801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
252847801
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2595365382
Short name T259
Test name
Test status
Simulation time 11643000704 ps
CPU time 16.85 seconds
Started Jun 27 06:23:23 PM PDT 24
Finished Jun 27 06:23:44 PM PDT 24
Peak memory 225012 kb
Host smart-e5c01f3b-73f5-4c2f-b0dc-ba3b80960fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595365382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2595365382
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2439759290
Short name T481
Test name
Test status
Simulation time 20756160 ps
CPU time 0.79 seconds
Started Jun 27 06:23:05 PM PDT 24
Finished Jun 27 06:23:15 PM PDT 24
Peak memory 207100 kb
Host smart-329078dc-2db7-4dcc-bbe5-dc6be2e46cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439759290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2439759290
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.4095121632
Short name T170
Test name
Test status
Simulation time 36073245311 ps
CPU time 63.34 seconds
Started Jun 27 06:23:18 PM PDT 24
Finished Jun 27 06:24:27 PM PDT 24
Peak memory 237720 kb
Host smart-8a0b945f-51c2-455c-9e40-1f40f13260a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095121632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.4095121632
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.678535732
Short name T592
Test name
Test status
Simulation time 13579388117 ps
CPU time 118.13 seconds
Started Jun 27 06:23:02 PM PDT 24
Finished Jun 27 06:25:09 PM PDT 24
Peak memory 249840 kb
Host smart-290efef1-4a84-4f0a-836b-1128ddf224cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678535732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.678535732
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3947501505
Short name T926
Test name
Test status
Simulation time 5252423253 ps
CPU time 38.3 seconds
Started Jun 27 06:23:06 PM PDT 24
Finished Jun 27 06:23:53 PM PDT 24
Peak memory 253252 kb
Host smart-efe3c924-0e85-47cf-aaeb-ea098c56b1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947501505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3947501505
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2386946631
Short name T400
Test name
Test status
Simulation time 800873353 ps
CPU time 9.04 seconds
Started Jun 27 06:23:01 PM PDT 24
Finished Jun 27 06:23:19 PM PDT 24
Peak memory 241208 kb
Host smart-61beb048-872d-4085-a434-50e86428cb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386946631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2386946631
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2219510543
Short name T303
Test name
Test status
Simulation time 21252368507 ps
CPU time 85.3 seconds
Started Jun 27 06:23:16 PM PDT 24
Finished Jun 27 06:24:48 PM PDT 24
Peak memory 253108 kb
Host smart-3aadb4ca-b548-4c28-801c-ec1a56bae04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219510543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2219510543
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4119622354
Short name T677
Test name
Test status
Simulation time 4266937638 ps
CPU time 20.27 seconds
Started Jun 27 06:23:27 PM PDT 24
Finished Jun 27 06:23:51 PM PDT 24
Peak memory 224992 kb
Host smart-6c23a781-24f6-4a63-b418-a5388ddf5c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119622354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4119622354
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2782399584
Short name T938
Test name
Test status
Simulation time 2527713703 ps
CPU time 23.55 seconds
Started Jun 27 06:23:28 PM PDT 24
Finished Jun 27 06:23:55 PM PDT 24
Peak memory 233184 kb
Host smart-e8b4763f-9ddc-4e03-90f9-3eb4bffa4067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782399584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2782399584
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1353785875
Short name T752
Test name
Test status
Simulation time 8281648285 ps
CPU time 6.87 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:23:40 PM PDT 24
Peak memory 224928 kb
Host smart-a944c67a-3925-4205-b73b-045cf7007e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353785875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1353785875
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1091026580
Short name T260
Test name
Test status
Simulation time 41938130550 ps
CPU time 30.71 seconds
Started Jun 27 06:23:22 PM PDT 24
Finished Jun 27 06:23:58 PM PDT 24
Peak memory 234320 kb
Host smart-6ac2808e-39d8-4d65-913c-3943c165a04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091026580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1091026580
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.772166862
Short name T547
Test name
Test status
Simulation time 503183260 ps
CPU time 3.66 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:23:37 PM PDT 24
Peak memory 219452 kb
Host smart-d952d556-72cb-4c5f-9b33-6ec409c2782c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=772166862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.772166862
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1719066864
Short name T897
Test name
Test status
Simulation time 30493297320 ps
CPU time 211.69 seconds
Started Jun 27 06:23:14 PM PDT 24
Finished Jun 27 06:26:54 PM PDT 24
Peak memory 271036 kb
Host smart-5eb8cbd7-1b36-4763-94df-91cf6d87e04a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719066864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1719066864
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.600609074
Short name T326
Test name
Test status
Simulation time 1873912476 ps
CPU time 27.76 seconds
Started Jun 27 06:23:22 PM PDT 24
Finished Jun 27 06:23:55 PM PDT 24
Peak memory 216720 kb
Host smart-efd10684-1ed5-448f-9ded-d3f904e2f3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600609074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.600609074
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.4068149980
Short name T403
Test name
Test status
Simulation time 995905870 ps
CPU time 3.7 seconds
Started Jun 27 06:23:01 PM PDT 24
Finished Jun 27 06:23:14 PM PDT 24
Peak memory 216732 kb
Host smart-bd1387e7-e8b5-454c-ac59-86d2879bbbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068149980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.4068149980
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1727321907
Short name T370
Test name
Test status
Simulation time 883808969 ps
CPU time 3.13 seconds
Started Jun 27 06:23:27 PM PDT 24
Finished Jun 27 06:23:34 PM PDT 24
Peak memory 216736 kb
Host smart-a9ab3bea-afbe-4666-b6be-32c930c63cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727321907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1727321907
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2488224713
Short name T898
Test name
Test status
Simulation time 163552670 ps
CPU time 1.05 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:23:35 PM PDT 24
Peak memory 207428 kb
Host smart-5bb41577-d802-4f43-8ae3-c63a6b470973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488224713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2488224713
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2267357563
Short name T790
Test name
Test status
Simulation time 13703805667 ps
CPU time 13.64 seconds
Started Jun 27 06:23:11 PM PDT 24
Finished Jun 27 06:23:33 PM PDT 24
Peak memory 241424 kb
Host smart-11c8986d-40e4-40da-b10c-2225bd32cc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267357563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2267357563
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3417369433
Short name T359
Test name
Test status
Simulation time 15535661 ps
CPU time 0.74 seconds
Started Jun 27 06:23:12 PM PDT 24
Finished Jun 27 06:23:21 PM PDT 24
Peak memory 205944 kb
Host smart-7204f493-5635-4840-804e-042728dc7818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417369433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
417369433
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3371649666
Short name T338
Test name
Test status
Simulation time 2467376449 ps
CPU time 8.39 seconds
Started Jun 27 06:23:14 PM PDT 24
Finished Jun 27 06:23:30 PM PDT 24
Peak memory 225124 kb
Host smart-c2ac0720-9a19-49f3-9f5f-5d9ab2b7b30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371649666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3371649666
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1441171374
Short name T994
Test name
Test status
Simulation time 17438757 ps
CPU time 0.77 seconds
Started Jun 27 06:23:14 PM PDT 24
Finished Jun 27 06:23:23 PM PDT 24
Peak memory 206972 kb
Host smart-59f686e4-a89d-4dea-b2e5-96c7551c4daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441171374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1441171374
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2423948228
Short name T235
Test name
Test status
Simulation time 11924219092 ps
CPU time 81.59 seconds
Started Jun 27 06:23:13 PM PDT 24
Finished Jun 27 06:24:43 PM PDT 24
Peak memory 241464 kb
Host smart-b2ca2f6d-7386-4925-961e-53592e732ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423948228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2423948228
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1739040619
Short name T710
Test name
Test status
Simulation time 36083152678 ps
CPU time 73.51 seconds
Started Jun 27 06:23:24 PM PDT 24
Finished Jun 27 06:24:42 PM PDT 24
Peak memory 239572 kb
Host smart-0b91a2d5-d87d-4660-9a5c-f129deb4ffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739040619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1739040619
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1873967024
Short name T995
Test name
Test status
Simulation time 45717409921 ps
CPU time 360.88 seconds
Started Jun 27 06:23:42 PM PDT 24
Finished Jun 27 06:29:45 PM PDT 24
Peak memory 273272 kb
Host smart-52a4192f-cab2-4596-9770-da0b687e0d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873967024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1873967024
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1115141022
Short name T463
Test name
Test status
Simulation time 1840911256 ps
CPU time 26.47 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:23:59 PM PDT 24
Peak memory 233152 kb
Host smart-9ab399d1-4b81-4c19-8069-82d7db1dc63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115141022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1115141022
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2788705405
Short name T601
Test name
Test status
Simulation time 57260109930 ps
CPU time 376.32 seconds
Started Jun 27 06:23:28 PM PDT 24
Finished Jun 27 06:29:48 PM PDT 24
Peak memory 252180 kb
Host smart-bcb425d6-7049-427f-9d18-6e286026ea04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788705405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2788705405
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1431139852
Short name T612
Test name
Test status
Simulation time 1164808200 ps
CPU time 2.88 seconds
Started Jun 27 06:23:26 PM PDT 24
Finished Jun 27 06:23:33 PM PDT 24
Peak memory 233152 kb
Host smart-cf4e4a02-ffe0-406d-9d8c-3dd1b1c1a2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431139852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1431139852
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.576659604
Short name T947
Test name
Test status
Simulation time 58028340917 ps
CPU time 125.94 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:25:39 PM PDT 24
Peak memory 240404 kb
Host smart-e56a238a-b0c1-474d-8d22-36eac26a590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576659604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.576659604
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.236767155
Short name T278
Test name
Test status
Simulation time 15832115891 ps
CPU time 10.76 seconds
Started Jun 27 06:23:07 PM PDT 24
Finished Jun 27 06:23:27 PM PDT 24
Peak memory 233364 kb
Host smart-f3ad5b05-e21d-4c34-8f69-882cc74b79f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236767155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
236767155
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.487752444
Short name T772
Test name
Test status
Simulation time 20787649553 ps
CPU time 13.17 seconds
Started Jun 27 06:23:14 PM PDT 24
Finished Jun 27 06:23:35 PM PDT 24
Peak memory 233292 kb
Host smart-9d1ebe0b-b834-42b2-9a21-a8c10801f96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487752444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.487752444
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3160239276
Short name T379
Test name
Test status
Simulation time 170666959 ps
CPU time 3.83 seconds
Started Jun 27 06:23:20 PM PDT 24
Finished Jun 27 06:23:29 PM PDT 24
Peak memory 219896 kb
Host smart-bce147bb-bc47-4aaf-86a2-983df7ad45e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3160239276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3160239276
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1057029734
Short name T510
Test name
Test status
Simulation time 157230032 ps
CPU time 2.27 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:23:36 PM PDT 24
Peak memory 216812 kb
Host smart-dae140d3-6a87-4792-8564-5e44a5afe044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057029734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1057029734
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1426080049
Short name T437
Test name
Test status
Simulation time 2646103676 ps
CPU time 9.5 seconds
Started Jun 27 06:23:26 PM PDT 24
Finished Jun 27 06:23:40 PM PDT 24
Peak memory 216840 kb
Host smart-18473473-7272-4ced-a0b2-4d45512c992f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426080049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1426080049
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3718484715
Short name T325
Test name
Test status
Simulation time 94351160 ps
CPU time 0.91 seconds
Started Jun 27 06:23:07 PM PDT 24
Finished Jun 27 06:23:17 PM PDT 24
Peak memory 207568 kb
Host smart-f27d7454-f9ec-4687-b034-a431c8a1ad9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718484715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3718484715
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.183683419
Short name T448
Test name
Test status
Simulation time 87969449 ps
CPU time 0.86 seconds
Started Jun 27 06:23:24 PM PDT 24
Finished Jun 27 06:23:29 PM PDT 24
Peak memory 206448 kb
Host smart-725c0b31-547b-46b9-94be-fa876b852323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183683419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.183683419
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.4058215594
Short name T505
Test name
Test status
Simulation time 1023323561 ps
CPU time 7.87 seconds
Started Jun 27 06:23:14 PM PDT 24
Finished Jun 27 06:23:30 PM PDT 24
Peak memory 257520 kb
Host smart-1e48494a-2438-4e33-9bf4-6664678bfe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058215594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4058215594
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1499451746
Short name T834
Test name
Test status
Simulation time 16688017 ps
CPU time 0.78 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:23:33 PM PDT 24
Peak memory 206312 kb
Host smart-56bace76-3267-4efb-a1a3-d2630c16d110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499451746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
499451746
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2471080997
Short name T617
Test name
Test status
Simulation time 137484523 ps
CPU time 3.92 seconds
Started Jun 27 06:23:31 PM PDT 24
Finished Jun 27 06:23:39 PM PDT 24
Peak memory 224968 kb
Host smart-132aa063-8944-4a35-bb96-ac630535b8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471080997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2471080997
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.832420655
Short name T880
Test name
Test status
Simulation time 54129259 ps
CPU time 0.76 seconds
Started Jun 27 06:23:20 PM PDT 24
Finished Jun 27 06:23:26 PM PDT 24
Peak memory 207116 kb
Host smart-f3d69880-476e-4c60-abdb-c0db1e0c90f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832420655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.832420655
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3566074111
Short name T604
Test name
Test status
Simulation time 4086043172 ps
CPU time 67.42 seconds
Started Jun 27 06:23:20 PM PDT 24
Finished Jun 27 06:24:33 PM PDT 24
Peak memory 255340 kb
Host smart-9a5319e1-4bf6-4cd7-b163-1f5cf8bbbfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566074111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3566074111
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.882295832
Short name T296
Test name
Test status
Simulation time 13583263251 ps
CPU time 90.21 seconds
Started Jun 27 06:23:15 PM PDT 24
Finished Jun 27 06:24:53 PM PDT 24
Peak memory 253556 kb
Host smart-0aa558ce-917f-442a-985b-ed885ea93ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882295832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.882295832
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3944245312
Short name T468
Test name
Test status
Simulation time 20276502290 ps
CPU time 161.68 seconds
Started Jun 27 06:23:14 PM PDT 24
Finished Jun 27 06:26:04 PM PDT 24
Peak memory 240616 kb
Host smart-8ae5fe97-6ac5-4109-91df-a08543f52cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944245312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3944245312
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3284261789
Short name T980
Test name
Test status
Simulation time 3074785410 ps
CPU time 11.14 seconds
Started Jun 27 06:23:30 PM PDT 24
Finished Jun 27 06:23:46 PM PDT 24
Peak memory 225300 kb
Host smart-adee95e9-5ee5-48a2-b6cd-5e679a58e2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284261789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3284261789
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1213991611
Short name T482
Test name
Test status
Simulation time 823186962 ps
CPU time 16.74 seconds
Started Jun 27 06:23:38 PM PDT 24
Finished Jun 27 06:23:58 PM PDT 24
Peak memory 249532 kb
Host smart-a1d31aac-5f75-4de9-90c2-7ffa9ca45b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213991611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1213991611
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1888617685
Short name T566
Test name
Test status
Simulation time 85003994 ps
CPU time 2.65 seconds
Started Jun 27 06:23:17 PM PDT 24
Finished Jun 27 06:23:26 PM PDT 24
Peak memory 233128 kb
Host smart-d447b330-20e9-4c20-8055-0aba7a828226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888617685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1888617685
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2297845214
Short name T650
Test name
Test status
Simulation time 35498694984 ps
CPU time 31 seconds
Started Jun 27 06:23:15 PM PDT 24
Finished Jun 27 06:23:54 PM PDT 24
Peak memory 233288 kb
Host smart-d50de521-6ce4-44ac-9eb4-adeae34191bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297845214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2297845214
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3507408717
Short name T286
Test name
Test status
Simulation time 26020541094 ps
CPU time 20.79 seconds
Started Jun 27 06:23:25 PM PDT 24
Finished Jun 27 06:23:50 PM PDT 24
Peak memory 230756 kb
Host smart-4291c32e-d57b-415d-afd7-85332ffb6a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507408717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3507408717
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.888758741
Short name T798
Test name
Test status
Simulation time 844936665 ps
CPU time 4.79 seconds
Started Jun 27 06:23:13 PM PDT 24
Finished Jun 27 06:23:26 PM PDT 24
Peak memory 235744 kb
Host smart-93cb5dc6-4a53-443c-8d9a-0409dd3ee988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888758741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.888758741
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3079434468
Short name T411
Test name
Test status
Simulation time 13473113803 ps
CPU time 10.98 seconds
Started Jun 27 06:23:32 PM PDT 24
Finished Jun 27 06:23:46 PM PDT 24
Peak memory 220008 kb
Host smart-64a4da19-8310-4770-8d9c-fa9459de8c72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3079434468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3079434468
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.761396219
Short name T19
Test name
Test status
Simulation time 19273195443 ps
CPU time 46.46 seconds
Started Jun 27 06:23:12 PM PDT 24
Finished Jun 27 06:24:07 PM PDT 24
Peak memory 225220 kb
Host smart-db241c47-56c7-47af-991e-c137500fc1f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761396219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.761396219
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.226822539
Short name T430
Test name
Test status
Simulation time 776733213 ps
CPU time 5.82 seconds
Started Jun 27 06:23:18 PM PDT 24
Finished Jun 27 06:23:30 PM PDT 24
Peak memory 216808 kb
Host smart-04a033a1-f94c-4eee-ae1e-7e38c1887a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226822539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.226822539
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3797218727
Short name T665
Test name
Test status
Simulation time 8026606952 ps
CPU time 8.02 seconds
Started Jun 27 06:23:13 PM PDT 24
Finished Jun 27 06:23:29 PM PDT 24
Peak memory 216876 kb
Host smart-950d1f52-5d7c-4046-b8e7-a9fe23a78224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797218727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3797218727
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.279514735
Short name T872
Test name
Test status
Simulation time 137792287 ps
CPU time 1.43 seconds
Started Jun 27 06:23:43 PM PDT 24
Finished Jun 27 06:23:47 PM PDT 24
Peak memory 216708 kb
Host smart-95e1e325-e29c-4b86-b826-12b1c72a3ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279514735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.279514735
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.74998223
Short name T759
Test name
Test status
Simulation time 20753928 ps
CPU time 0.78 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:23:33 PM PDT 24
Peak memory 206428 kb
Host smart-55df11a9-a499-4c27-b660-4b92bcfc5cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74998223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.74998223
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2556223117
Short name T557
Test name
Test status
Simulation time 1483739237 ps
CPU time 7.66 seconds
Started Jun 27 06:23:34 PM PDT 24
Finished Jun 27 06:23:45 PM PDT 24
Peak memory 249408 kb
Host smart-f72e626c-8954-4b74-b7d7-cb1d9ef22195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556223117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2556223117
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.4087848949
Short name T367
Test name
Test status
Simulation time 17416429 ps
CPU time 0.75 seconds
Started Jun 27 06:23:31 PM PDT 24
Finished Jun 27 06:23:35 PM PDT 24
Peak memory 205944 kb
Host smart-b2b67dad-3dda-460d-b924-37aad5b5aa96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087848949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.4
087848949
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.488751831
Short name T659
Test name
Test status
Simulation time 442624393 ps
CPU time 3.1 seconds
Started Jun 27 06:23:17 PM PDT 24
Finished Jun 27 06:23:27 PM PDT 24
Peak memory 224904 kb
Host smart-5560cb6f-3d40-4622-8d74-7b84a4cd56d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488751831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.488751831
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3084692921
Short name T585
Test name
Test status
Simulation time 125350004 ps
CPU time 0.76 seconds
Started Jun 27 06:23:31 PM PDT 24
Finished Jun 27 06:23:36 PM PDT 24
Peak memory 207040 kb
Host smart-f8ebfb16-d444-49a7-8acf-0aa00e938e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084692921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3084692921
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2463209835
Short name T166
Test name
Test status
Simulation time 44159989632 ps
CPU time 146.19 seconds
Started Jun 27 06:23:38 PM PDT 24
Finished Jun 27 06:26:08 PM PDT 24
Peak memory 256472 kb
Host smart-8f8e27e0-147d-461f-938b-61cae7b5b274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463209835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2463209835
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3832017836
Short name T766
Test name
Test status
Simulation time 294253290 ps
CPU time 10.46 seconds
Started Jun 27 06:23:28 PM PDT 24
Finished Jun 27 06:23:42 PM PDT 24
Peak memory 233244 kb
Host smart-4f44797a-1afd-4a0c-acc0-63b0f2a97f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832017836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3832017836
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2190797582
Short name T739
Test name
Test status
Simulation time 7258816803 ps
CPU time 31.07 seconds
Started Jun 27 06:23:41 PM PDT 24
Finished Jun 27 06:24:14 PM PDT 24
Peak memory 241428 kb
Host smart-a17b69a4-65a8-4b09-b159-0219f04e2857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190797582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2190797582
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3478469633
Short name T621
Test name
Test status
Simulation time 149607470 ps
CPU time 2.2 seconds
Started Jun 27 06:23:44 PM PDT 24
Finished Jun 27 06:23:50 PM PDT 24
Peak memory 223464 kb
Host smart-b5bd794d-9321-48f6-abb4-975dd63e56f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478469633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3478469633
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1340430502
Short name T814
Test name
Test status
Simulation time 1027171486 ps
CPU time 6.82 seconds
Started Jun 27 06:23:35 PM PDT 24
Finished Jun 27 06:23:46 PM PDT 24
Peak memory 234732 kb
Host smart-5d8863a4-3031-4fcd-aaf3-cd5df0c9920b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340430502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1340430502
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.520388995
Short name T274
Test name
Test status
Simulation time 7738156214 ps
CPU time 11.97 seconds
Started Jun 27 06:23:24 PM PDT 24
Finished Jun 27 06:23:41 PM PDT 24
Peak memory 233328 kb
Host smart-7fe1b6b8-0487-47ea-9140-0b14434fc3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520388995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
520388995
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2761965191
Short name T606
Test name
Test status
Simulation time 1173536599 ps
CPU time 3.72 seconds
Started Jun 27 06:23:14 PM PDT 24
Finished Jun 27 06:23:25 PM PDT 24
Peak memory 233144 kb
Host smart-4d8c6a7e-a01f-4cf8-ae14-1ff6897b3d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761965191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2761965191
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1114838370
Short name T842
Test name
Test status
Simulation time 122907582 ps
CPU time 3.77 seconds
Started Jun 27 06:23:37 PM PDT 24
Finished Jun 27 06:23:44 PM PDT 24
Peak memory 220704 kb
Host smart-25417f51-c310-44d1-970e-475aa05cc66b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1114838370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1114838370
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1115151142
Short name T419
Test name
Test status
Simulation time 7470203903 ps
CPU time 38.59 seconds
Started Jun 27 06:23:31 PM PDT 24
Finished Jun 27 06:24:14 PM PDT 24
Peak memory 216860 kb
Host smart-d094b651-57f2-4d8f-a61e-251973ee2bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115151142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1115151142
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2587579400
Short name T666
Test name
Test status
Simulation time 4614857863 ps
CPU time 12.86 seconds
Started Jun 27 06:23:13 PM PDT 24
Finished Jun 27 06:23:34 PM PDT 24
Peak memory 216924 kb
Host smart-17fc758a-cc35-40f7-b4a9-9896f82b3c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587579400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2587579400
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3060924501
Short name T934
Test name
Test status
Simulation time 804514247 ps
CPU time 5.43 seconds
Started Jun 27 06:23:17 PM PDT 24
Finished Jun 27 06:23:29 PM PDT 24
Peak memory 216792 kb
Host smart-18da97dc-e731-4eb5-9f1a-e7556f05db74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060924501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3060924501
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.5078269
Short name T913
Test name
Test status
Simulation time 199004645 ps
CPU time 0.78 seconds
Started Jun 27 06:23:25 PM PDT 24
Finished Jun 27 06:23:30 PM PDT 24
Peak memory 206484 kb
Host smart-1c0f48ae-8c2c-41b1-9cf8-d4d94203c8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5078269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.5078269
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1877148029
Short name T255
Test name
Test status
Simulation time 204536158 ps
CPU time 2.52 seconds
Started Jun 27 06:23:34 PM PDT 24
Finished Jun 27 06:23:40 PM PDT 24
Peak memory 225000 kb
Host smart-d5d3fceb-6d99-4242-a1b5-797dd8cd21ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877148029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1877148029
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2073513151
Short name T709
Test name
Test status
Simulation time 11726343 ps
CPU time 0.68 seconds
Started Jun 27 06:23:31 PM PDT 24
Finished Jun 27 06:23:35 PM PDT 24
Peak memory 206224 kb
Host smart-d4619ebf-4606-4962-8b87-11c5ebc81e85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073513151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
073513151
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1898179962
Short name T989
Test name
Test status
Simulation time 418169098 ps
CPU time 2.72 seconds
Started Jun 27 06:23:32 PM PDT 24
Finished Jun 27 06:23:39 PM PDT 24
Peak memory 224940 kb
Host smart-b84e2de5-41b7-42ae-82ed-55c3aa8b2828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898179962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1898179962
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4201875294
Short name T570
Test name
Test status
Simulation time 51574432 ps
CPU time 0.75 seconds
Started Jun 27 06:23:24 PM PDT 24
Finished Jun 27 06:23:29 PM PDT 24
Peak memory 206404 kb
Host smart-84a75cf0-ac31-464a-bf43-2320a7a2f9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201875294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4201875294
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2063295168
Short name T225
Test name
Test status
Simulation time 176558347396 ps
CPU time 308.08 seconds
Started Jun 27 06:23:16 PM PDT 24
Finished Jun 27 06:28:31 PM PDT 24
Peak memory 254724 kb
Host smart-42fd9a76-1ac9-42c3-ac58-55eff16a59b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063295168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2063295168
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.430499149
Short name T928
Test name
Test status
Simulation time 8347123669 ps
CPU time 56.68 seconds
Started Jun 27 06:23:43 PM PDT 24
Finished Jun 27 06:24:43 PM PDT 24
Peak memory 240736 kb
Host smart-80d2bb8f-0de4-48e2-a8cb-048240b26934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430499149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.430499149
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1148977974
Short name T129
Test name
Test status
Simulation time 3293868520 ps
CPU time 53.27 seconds
Started Jun 27 06:23:16 PM PDT 24
Finished Jun 27 06:24:16 PM PDT 24
Peak memory 249836 kb
Host smart-973c1326-2f1c-4f2d-94e3-d4a89aa50d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148977974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1148977974
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.231140194
Short name T316
Test name
Test status
Simulation time 6987340958 ps
CPU time 21.41 seconds
Started Jun 27 06:23:45 PM PDT 24
Finished Jun 27 06:24:11 PM PDT 24
Peak memory 241472 kb
Host smart-b134d862-1e41-4e3e-82de-a3fa4f5695e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231140194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.231140194
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3492506572
Short name T517
Test name
Test status
Simulation time 13153143171 ps
CPU time 11.13 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:23:44 PM PDT 24
Peak memory 240772 kb
Host smart-c83dde57-4241-4424-9042-cc3235b326b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492506572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3492506572
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2814615708
Short name T279
Test name
Test status
Simulation time 1893994523 ps
CPU time 18.6 seconds
Started Jun 27 06:23:48 PM PDT 24
Finished Jun 27 06:24:10 PM PDT 24
Peak memory 233088 kb
Host smart-c68f461e-d972-4372-96d3-0683ddd02a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814615708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2814615708
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1937206444
Short name T217
Test name
Test status
Simulation time 2690244101 ps
CPU time 17.77 seconds
Started Jun 27 06:23:31 PM PDT 24
Finished Jun 27 06:23:53 PM PDT 24
Peak memory 225008 kb
Host smart-fb24e62a-1ed6-451a-a7c1-aee224ed1cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937206444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1937206444
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3801004940
Short name T202
Test name
Test status
Simulation time 3209214079 ps
CPU time 11.5 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:23:45 PM PDT 24
Peak memory 233316 kb
Host smart-d931feb1-4762-404c-805e-cbebddb6b095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801004940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3801004940
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4092215617
Short name T565
Test name
Test status
Simulation time 3252940360 ps
CPU time 13.83 seconds
Started Jun 27 06:23:28 PM PDT 24
Finished Jun 27 06:23:46 PM PDT 24
Peak memory 225056 kb
Host smart-8b541e26-f2db-430a-9a73-1fad2140aa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092215617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4092215617
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.4096928781
Short name T859
Test name
Test status
Simulation time 194318381 ps
CPU time 4.6 seconds
Started Jun 27 06:23:15 PM PDT 24
Finished Jun 27 06:23:27 PM PDT 24
Peak memory 221080 kb
Host smart-20143455-9203-4e33-a53c-e926e2a22553
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4096928781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.4096928781
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4247351182
Short name T17
Test name
Test status
Simulation time 177674992 ps
CPU time 1.05 seconds
Started Jun 27 06:23:15 PM PDT 24
Finished Jun 27 06:23:23 PM PDT 24
Peak memory 208364 kb
Host smart-7beac13c-1f3d-4482-9091-71ed7170cff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247351182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4247351182
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1071096373
Short name T637
Test name
Test status
Simulation time 3887071392 ps
CPU time 3.48 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:23:36 PM PDT 24
Peak memory 216968 kb
Host smart-c010031b-1923-43b3-8b06-6771bcd15383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071096373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1071096373
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1385729990
Short name T525
Test name
Test status
Simulation time 176676355 ps
CPU time 1.1 seconds
Started Jun 27 06:23:16 PM PDT 24
Finished Jun 27 06:23:24 PM PDT 24
Peak memory 208396 kb
Host smart-93cb6678-292b-43d6-9b2b-108f90737ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385729990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1385729990
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1479065607
Short name T578
Test name
Test status
Simulation time 35107746 ps
CPU time 0.7 seconds
Started Jun 27 06:23:29 PM PDT 24
Finished Jun 27 06:23:34 PM PDT 24
Peak memory 206368 kb
Host smart-851b5beb-52c7-4bf0-8862-e2f1d8eb8ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479065607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1479065607
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2922705996
Short name T7
Test name
Test status
Simulation time 618445538 ps
CPU time 4.33 seconds
Started Jun 27 06:23:15 PM PDT 24
Finished Jun 27 06:23:27 PM PDT 24
Peak memory 224900 kb
Host smart-d76ec528-d34c-4377-858b-1551946feb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922705996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2922705996
Directory /workspace/9.spi_device_upload/latest
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