Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2933792	1			T1	456		T2	64		T3	1
all_values[1]	2933792	1			T1	456		T2	64		T3	1
all_values[2]	2933792	1			T1	456		T2	64		T3	1
all_values[3]	2933792	1			T1	456		T2	64		T3	1
all_values[4]	2933792	1			T1	456		T2	64		T3	1
all_values[5]	2933792	1			T1	456		T2	64		T3	1
all_values[6]	2933792	1			T1	456		T2	64		T3	1
all_values[7]	2933792	1			T1	456		T2	64		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22649050

1

T1

3648

T2

512

T3

8

auto[1]

821286

1

T14

104491

T16

85

T77

409869

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23444888

1

T1

3648

T2

512

T3

8

auto[1]

25448

1

T32

26

T34

21

T37

217

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2789696	1			T1	456		T2	64		T3	1
all_values[0]	auto[0]	auto[1]	11502	1			T32	11		T34	7		T37	115
all_values[0]	auto[1]	auto[0]	131798	1			T14	9		T16	13		T77	81764
all_values[0]	auto[1]	auto[1]	796	1			T14	4		T16	1		T77	207
all_values[1]	auto[0]	auto[0]	2842565	1			T1	456		T2	64		T3	1
all_values[1]	auto[0]	auto[1]	7470	1			T32	11		T34	7		T37	80
all_values[1]	auto[1]	auto[0]	83386	1			T14	7		T16	8		T77	81814
all_values[1]	auto[1]	auto[1]	371	1			T14	11		T16	5		T77	157
all_values[2]	auto[0]	auto[0]	2784819	1			T1	456		T2	64		T3	1
all_values[2]	auto[0]	auto[1]	2794	1			T32	4		T34	7		T37	22
all_values[2]	auto[1]	auto[0]	145850	1			T14	52182		T16	6		T77	81945
all_values[2]	auto[1]	auto[1]	329	1			T14	33		T16	4		T77	26
all_values[3]	auto[0]	auto[0]	2797950	1			T1	456		T2	64		T3	1
all_values[3]	auto[0]	auto[1]	231	1			T14	6		T16	4		T77	1
all_values[3]	auto[1]	auto[0]	135407	1			T14	5		T16	5		T77	81969
all_values[3]	auto[1]	auto[1]	204	1			T14	6		T16	5		T77	2
all_values[4]	auto[0]	auto[0]	2890222	1			T1	456		T2	64		T3	1
all_values[4]	auto[0]	auto[1]	243	1			T14	8		T16	4		T77	6
all_values[4]	auto[1]	auto[0]	43116	1			T14	6		T16	9		T18	2
all_values[4]	auto[1]	auto[1]	211	1			T14	1		T77	4		T17	3
all_values[5]	auto[0]	auto[0]	2879943	1			T1	456		T2	64		T3	1
all_values[5]	auto[0]	auto[1]	182	1			T14	8		T16	3		T77	1
all_values[5]	auto[1]	auto[0]	53470	1			T14	3		T16	5		T77	2
all_values[5]	auto[1]	auto[1]	197	1			T14	4		T16	5		T77	4
all_values[6]	auto[0]	auto[0]	2752016	1			T1	456		T2	64		T3	1
all_values[6]	auto[0]	auto[1]	225	1			T14	5		T16	2		T77	2
all_values[6]	auto[1]	auto[0]	181315	1			T14	52208		T16	5		T77	81967
all_values[6]	auto[1]	auto[1]	236	1			T14	5		T16	4		T77	5
all_values[7]	auto[0]	auto[0]	2888955	1			T1	456		T2	64		T3	1
all_values[7]	auto[0]	auto[1]	237	1			T14	6		T16	3		T77	5
all_values[7]	auto[1]	auto[0]	44380	1			T14	4		T16	3		T77	2
all_values[7]	auto[1]	auto[1]	220	1			T14	3		T16	7		T77	1