Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	39177	1			T1	86		T5	2		T6	12
auto[SpiFlashAddrCfg]	8266	1			T1	46		T2	6		T6	1
auto[SpiFlashAddr3b]	9869	1			T1	51		T2	8		T6	4
auto[SpiFlashAddr4b]	8143	1			T1	57		T2	2		T6	3

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37029

1

T1

148

T2

16

T5

2

auto[1]

28426

1

T1

92

T6

12

T8

154

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35390

1

T1

138

T2

10

T5

2

auto[1]

30065

1

T1

102

T2

6

T6

7

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	44046	1			T1	114		T2	2		T5	2
values[1]	1244	1			T1	12		T2	2		T6	1
values[2]	1619	1			T1	9		T7	8		T8	5
values[3]	1574	1			T1	13		T2	2		T8	2
values[4]	1577	1			T1	4		T8	11		T9	3
values[5]	1482	1			T1	10		T2	2		T6	1
values[6]	1585	1			T1	8		T2	2		T8	8
values[7]	1585	1			T1	14		T2	2		T6	2
values[8]	10743	1			T1	56		T2	4		T6	5

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38305

1

T1

240

T2

16

T5

2

auto[1]

27150

1

T6

20

T8

296

T45

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

62026

1

T1

217

T2

16

T5

2

write

3429

1

T1

23

T8

8

T9

5

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20718

1

T1

108

T2

8

T5

2

valids[0x1]

44737

1

T1

132

T2

8

T6

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1734	1			T1	10		T6	2		T7	2
internal_process_ops[0x5a]	1656	1			T1	9		T2	2		T6	1
internal_process_ops[0x05]	24550	1			T1	10		T8	123		T9	7
internal_process_ops[0x35]	1567	1			T1	3		T6	2		T8	4
internal_process_ops[0x15]	1711	1			T1	16		T6	1		T8	6
internal_process_ops[0x03]	1168	1			T1	11		T8	1		T9	3
internal_process_ops[0x0b]	1135	1			T1	10		T8	1		T9	3
internal_process_ops[0x3b]	1188	1			T1	9		T8	6		T9	5
internal_process_ops[0x6b]	1264	1			T1	8		T8	4		T9	2
internal_process_ops[0xbb]	1267	1			T1	6		T7	8		T8	1
internal_process_ops[0xeb]	1221	1			T1	12		T7	2		T8	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63701

1

T1

229

T2

16

T5

2

auto[1]

1754

1

T1

11

T8

5

T9

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62955

1

T1

232

T2

16

T5

2

auto[1]

2500

1

T1

8

T8

12

T9

11

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

13179

1

T1

63

T5

2

T7

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7754

1

T1

18

T9

9

T48

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2695

1

T1

21

T2

6

T7

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2206

1

T1

21

T9

15

T11

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2948

1

T1

32

T2

8

T7

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2753

1

T1

16

T9

10

T48

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2526

1

T1

22

T2

2

T7

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2222

1

T1

24

T9

16

T11

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

127

1

T1

1

T44

5

T40

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

137

1

T1

2

T39

3

T14

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

107

1

T1

2

T44

4

T39

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

127

1

T9

2

T50

2

T39

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

140

1

T1

4

T51

2

T15

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

129

1

T9

1

T39

1

T14

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

94

1

T39

6

T14

1

T51

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

138

1

T169

2

T170

1

T96

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

127

1

T29

6

T52

2

T171

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

120

1

T44

1

T39

3

T14

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

105

1

T1

1

T39

2

T14

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

157

1

T1

2

T39

1

T14

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

172

1

T1

3

T39

4

T40

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

101

1

T39

1

T40

4

T51

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

115

1

T1

1

T9

2

T14

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

126

1

T1

7

T44

2

T39

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9810

1

T6

5

T8

104

T32

261

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7608

1

T6

7

T8

84

T32

210

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1260

1

T8

13

T32

20

T46

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1203

1

T6

1

T8

20

T32

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1606

1

T6

3

T8

12

T45

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1711

1

T6

1

T8

32

T32

28

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1285

1

T8

11

T45

1

T32

15

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1260

1

T6

3

T8

12

T32

18

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

62

1

T32

3

T37

1

T25

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

85

1

T32

2

T14

2

T28

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

87

1

T32

4

T37

3

T14

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

94

1

T8

1

T37

3

T14

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

100

1

T32

1

T37

5

T28

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

89

1

T32

2

T37

1

T25

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

117

1

T32

1

T37

4

T14

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

95

1

T8

2

T32

1

T37

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

81

1

T8

1

T32

5

T25

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

95

1

T28

2

T172

2

T173

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

80

1

T8

2

T37

1

T25

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

86

1

T8

1

T32

2

T34

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

68

1

T32

2

T25

2

T28

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

87

1

T8

1

T32

4

T34

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

93

1

T14

3

T25

1

T28

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

88

1

T32

3

T173

6

T174

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4686	1			T1	34		T2	2		T5	2
auto[0]	values[0]	valids[0x1]	19740	1			T1	80		T7	4		T9	39
auto[0]	values[1]	valids[0x1]	751	1			T1	12		T2	2		T9	6
auto[0]	values[2]	valids[0x0]	657	1			T1	5		T7	8		T9	3
auto[0]	values[2]	valids[0x1]	377	1			T1	4		T44	4		T39	5
auto[0]	values[3]	valids[0x0]	647	1			T1	5		T9	2		T44	4
auto[0]	values[3]	valids[0x1]	398	1			T1	8		T2	2		T9	2
auto[0]	values[4]	valids[0x0]	664	1			T1	3		T9	3		T44	4
auto[0]	values[4]	valids[0x1]	372	1			T1	1		T44	1		T39	7
auto[0]	values[5]	valids[0x0]	601	1			T1	6		T2	2		T9	1
auto[0]	values[5]	valids[0x1]	337	1			T1	4		T9	2		T44	1
auto[0]	values[6]	valids[0x0]	666	1			T1	6		T9	4		T44	8
auto[0]	values[6]	valids[0x1]	376	1			T1	2		T2	2		T9	2
auto[0]	values[7]	valids[0x0]	696	1			T1	14		T2	2		T9	5
auto[0]	values[7]	valids[0x1]	333	1			T9	2		T50	2		T44	5
auto[0]	values[8]	valids[0x0]	4475	1			T1	35		T2	2		T7	8
auto[0]	values[8]	valids[0x1]	2529	1			T1	21		T2	2		T9	14
auto[1]	values[0]	valids[0x0]	3402	1			T6	3		T8	39		T32	46
auto[1]	values[0]	valids[0x1]	16218	1			T6	8		T8	165		T32	474
auto[1]	values[1]	valids[0x1]	493	1			T6	1		T8	4		T32	11
auto[1]	values[2]	valids[0x0]	364	1			T8	4		T32	4		T37	13
auto[1]	values[2]	valids[0x1]	221	1			T8	1		T32	1		T37	4
auto[1]	values[3]	valids[0x0]	330	1			T8	2		T32	6		T37	6
auto[1]	values[3]	valids[0x1]	199	1			T32	2		T34	1		T37	8
auto[1]	values[4]	valids[0x0]	324	1			T8	3		T32	3		T34	1
auto[1]	values[4]	valids[0x1]	217	1			T8	8		T32	2		T34	1
auto[1]	values[5]	valids[0x0]	284	1			T8	2		T37	2		T14	2
auto[1]	values[5]	valids[0x1]	260	1			T6	1		T8	5		T32	2
auto[1]	values[6]	valids[0x0]	317	1			T8	5		T45	2		T32	6
auto[1]	values[6]	valids[0x1]	226	1			T8	3		T34	3		T37	3
auto[1]	values[7]	valids[0x0]	320	1			T6	2		T8	5		T32	9
auto[1]	values[7]	valids[0x1]	236	1			T8	9		T32	2		T46	2
auto[1]	values[8]	valids[0x0]	2285	1			T6	3		T8	28		T45	3
auto[1]	values[8]	valids[0x1]	1454	1			T6	2		T8	13		T32	29