Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3478478

1

T1

18317

T2

1

T5

8

auto[1]

32198

1

T1

181

T8

116

T9

130

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

718909

1

T1

540

T2

1

T5

8

auto[1]

2791767

1

T1

17958

T6

558

T8

4065

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	672014	1			T1	812		T2	1		T6	2
auto[524288:1048575]	360775	1			T1	4612		T5	3		T8	4
auto[1048576:1572863]	391004	1			T1	4280		T8	392		T9	2291
auto[1572864:2097151]	401081	1			T1	827		T6	7		T8	816
auto[2097152:2621439]	486377	1			T1	2941		T6	593		T8	1630
auto[2621440:3145727]	396375	1			T1	340		T5	5		T8	37
auto[3145728:3670015]	402989	1			T1	1999		T8	13		T9	5702
auto[3670016:4194303]	400061	1			T1	2687		T8	285		T9	729

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2828584

1

T1

18492

T2

1

T5

6

auto[1]

682092

1

T1

6

T5

2

T8

14

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3076365

1

T1

17219

T2

1

T6

595

auto[1]

434311

1

T1

1279

T5

8

T6

7

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	131638	1			T1	44		T2	1		T6	2
auto[0]	auto[0]	auto[0:524287]	auto[1]	473427	1			T1	768		T8	913		T9	304
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	61615	1			T1	60		T8	4		T9	21
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	244098	1			T1	4014		T9	769		T49	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	58184	1			T1	46		T8	3		T9	29
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	280083	1			T1	4069		T8	388		T9	2252
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	75466	1			T1	49		T8	8		T9	13
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	270542	1			T1	516		T8	258		T49	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	96295	1			T1	59		T6	35		T8	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	327618	1			T1	2716		T6	558		T8	1628
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	76060	1			T1	62		T8	2		T9	20
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	261558	1			T1	128		T8	1		T9	2285
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	108530	1			T1	16		T9	84		T12	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	244331	1			T1	1983		T9	5600		T32	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	98152	1			T1	50		T8	2		T9	58
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	241558	1			T1	2606		T8	129		T9	644
auto[0]	auto[1]	auto[0:524287]	auto[0]	800	1			T8	1		T32	4		T37	8
auto[0]	auto[1]	auto[0:524287]	auto[1]	60988	1			T32	5		T39	7		T14	512
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1544	1			T1	17		T5	3		T32	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	49290	1			T1	512		T37	1980		T14	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	842	1			T1	23		T8	1		T32	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	47526	1			T1	128		T32	1		T37	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	809	1			T1	6		T6	7		T8	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	49376	1			T1	256		T8	513		T32	1156
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1012	1			T1	24		T9	9		T32	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	57736	1			T32	514		T34	513		T37	129
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	916	1			T1	19		T5	5		T8	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	54192	1			T1	128		T8	2		T32	397
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	670	1			T8	3		T9	4		T37	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	46444	1			T8	1		T37	259		T39	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2406	1			T1	18		T8	1		T9	17
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	54772	1			T8	128		T9	5		T44	4
auto[1]	auto[0]	auto[0:524287]	auto[0]	518	1			T8	4		T9	5		T32	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	4225	1			T8	15		T37	2		T39	18
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	387	1			T1	6		T32	2		T44	6
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3294	1			T9	87		T32	61		T39	8
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	368	1			T1	7		T9	10		T32	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3436	1			T1	4		T32	2		T39	31
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	453	1			T8	2		T9	6		T32	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3807	1			T8	24		T32	2		T37	9
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	351	1			T9	3		T14	4		T51	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2609	1			T14	5		T15	46		T52	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	391	1			T1	3		T8	1		T32	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2450	1			T8	1		T32	43		T37	26
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	422	1			T9	14		T39	1		T14	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2083	1			T39	5		T14	6		T25	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	361	1			T1	13		T8	1		T9	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2055	1			T8	24		T32	6		T39	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	72	1			T32	2		T39	4		T52	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	346	1			T32	58		T39	3		T52	10
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	105	1			T1	3		T37	1		T172	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	442	1			T37	10		T51	2		T96	12
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	63	1			T1	3		T32	1		T39	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	502	1			T32	14		T39	4		T15	44
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	78	1			T8	1		T32	4		T37	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	550	1			T8	9		T32	59		T37	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	109	1			T1	12		T32	1		T34	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	647	1			T1	130		T32	15		T34	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	74	1			T8	2		T32	2		T39	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	734	1			T8	23		T32	91		T39	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	113	1			T8	1		T37	3		T40	17
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	396	1			T8	8		T37	12		T28	38
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	105	1			T9	3		T28	3		T51	5
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	652	1			T28	22		T51	81		T194	12

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2371695	1			T1	17186		T2	1		T6	595
auto[0]	auto[0]	auto[1]	677460	1			T8	5		T12	1		T45	1652
auto[0]	auto[1]	auto[0]	425454	1			T1	1131		T5	6		T6	7
auto[0]	auto[1]	auto[1]	3869	1			T5	2		T32	5		T37	2
auto[1]	auto[0]	auto[0]	26590	1			T1	30		T8	65		T9	119
auto[1]	auto[0]	auto[1]	620	1			T1	3		T8	7		T9	8
auto[1]	auto[1]	auto[0]	4845	1			T1	145		T8	42		T9	2
auto[1]	auto[1]	auto[1]	143	1			T1	3		T8	2		T9	1