Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2933792	1			T1	456		T2	64		T3	1
all_pins[1]	2933792	1			T1	456		T2	64		T3	1
all_pins[2]	2933792	1			T1	456		T2	64		T3	1
all_pins[3]	2933792	1			T1	456		T2	64		T3	1
all_pins[4]	2933792	1			T1	456		T2	64		T3	1
all_pins[5]	2933792	1			T1	456		T2	64		T3	1
all_pins[6]	2933792	1			T1	456		T2	64		T3	1
all_pins[7]	2933792	1			T1	456		T2	64		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23292320	1			T1	3648		T2	512		T3	8
values[0x1]	178016	1			T14	52266		T16	31		T77	82335
transitions[0x0=>0x1]	176423	1			T14	52255		T16	22		T77	82124
transitions[0x1=>0x0]	176433	1			T14	52255		T16	23		T77	82124

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2932914	1			T1	456		T2	64		T3	1
all_pins[0]	values[0x1]	878	1			T14	4		T16	1		T77	228
all_pins[0]	transitions[0x0=>0x1]	639	1			T14	2		T77	55		T18	4
all_pins[0]	transitions[0x1=>0x0]	151	1			T14	9		T16	4		T77	2
all_pins[1]	values[0x0]	2933402	1			T1	456		T2	64		T3	1
all_pins[1]	values[0x1]	390	1			T14	11		T16	5		T77	175
all_pins[1]	transitions[0x0=>0x1]	308	1			T14	8		T16	3		T77	144
all_pins[1]	transitions[0x1=>0x0]	266	1			T14	35		T16	2		T77	1
all_pins[2]	values[0x0]	2933444	1			T1	456		T2	64		T3	1
all_pins[2]	values[0x1]	348	1			T14	38		T16	4		T77	32
all_pins[2]	transitions[0x0=>0x1]	297	1			T14	36		T16	2		T77	30
all_pins[2]	transitions[0x1=>0x0]	153	1			T14	4		T16	3		T17	4
all_pins[3]	values[0x0]	2933588	1			T1	456		T2	64		T3	1
all_pins[3]	values[0x1]	204	1			T14	6		T16	5		T77	2
all_pins[3]	transitions[0x0=>0x1]	155	1			T14	6		T16	5		T77	2
all_pins[3]	transitions[0x1=>0x0]	162	1			T14	1		T77	4		T17	2
all_pins[4]	values[0x0]	2933581	1			T1	456		T2	64		T3	1
all_pins[4]	values[0x1]	211	1			T14	1		T77	4		T17	3
all_pins[4]	transitions[0x0=>0x1]	162	1			T14	1		T77	2		T17	3
all_pins[4]	transitions[0x1=>0x0]	1646	1			T14	4		T16	5		T77	2
all_pins[5]	values[0x0]	2932097	1			T1	456		T2	64		T3	1
all_pins[5]	values[0x1]	1695	1			T14	4		T16	5		T77	4
all_pins[5]	transitions[0x0=>0x1]	686	1			T14	2		T16	3		T77	2
all_pins[5]	transitions[0x1=>0x0]	173061	1			T14	52197		T16	2		T77	81887
all_pins[6]	values[0x0]	2759722	1			T1	456		T2	64		T3	1
all_pins[6]	values[0x1]	174070	1			T14	52199		T16	4		T77	81889
all_pins[6]	transitions[0x0=>0x1]	174016	1			T14	52199		T16	3		T77	81888
all_pins[6]	transitions[0x1=>0x0]	166	1			T14	3		T16	6		T18	2
all_pins[7]	values[0x0]	2933572	1			T1	456		T2	64		T3	1
all_pins[7]	values[0x1]	220	1			T14	3		T16	7		T77	1
all_pins[7]	transitions[0x0=>0x1]	160	1			T14	1		T16	6		T77	1
all_pins[7]	transitions[0x1=>0x0]	828	1			T14	2		T16	1		T77	228