Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22401

1

T1

148

T2

16

T5

2

auto[1]

15904

1

T1

92

T9

54

T11

6

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5146	1			T9	20		T48	18		T54	2
values[1]	4557	1			T7	20		T150	6		T50	14
values[2]	5469	1			T9	20		T44	80		T201	20
values[3]	6205	1			T1	60		T9	60		T39	73
values[4]	4409	1			T1	60		T110	2		T39	74
values[5]	3822	1			T1	40		T5	2		T9	20
values[6]	4536	1			T1	60		T9	20		T12	12
values[7]	4161	1			T1	20		T2	16		T49	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4407	1			T1	20		T5	2		T48	18
values[1]	4668	1			T1	40		T9	40		T44	20
values[2]	5046	1			T1	60		T9	20		T12	12
values[3]	5017	1			T1	40		T2	16		T54	2
values[4]	5029	1			T7	20		T11	6		T44	20
values[5]	4664	1			T9	20		T55	4		T44	40
values[6]	4700	1			T150	6		T110	2		T44	40
values[7]	4774	1			T1	80		T9	60		T49	12

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	233	1			T103	20		T195	2		T194	12
auto[0]	values[0]	values[1]	263	1			T9	14		T14	9		T52	10
auto[0]	values[0]	values[2]	283	1			T44	12		T39	29		T225	8
auto[0]	values[0]	values[3]	527	1			T54	2		T39	23		T17	13
auto[0]	values[0]	values[4]	324	1			T209	31		T196	10		T210	22
auto[0]	values[0]	values[5]	492	1			T51	7		T212	4		T226	14
auto[0]	values[0]	values[6]	551	1			T39	16		T15	141		T169	15
auto[0]	values[0]	values[7]	223	1			T51	27		T227	2		T196	9
auto[0]	values[1]	values[0]	300	1			T52	26		T194	12		T209	11
auto[0]	values[1]	values[1]	348	1			T44	11		T39	9		T14	17
auto[0]	values[1]	values[2]	442	1			T23	8		T154	12		T179	11
auto[0]	values[1]	values[3]	207	1			T29	45		T218	15		T228	7
auto[0]	values[1]	values[4]	225	1			T7	20		T39	15		T170	10
auto[0]	values[1]	values[5]	349	1			T14	13		T40	7		T229	6
auto[0]	values[1]	values[6]	416	1			T150	6		T52	7		T169	14
auto[0]	values[1]	values[7]	313	1			T39	14		T51	10		T198	39
auto[0]	values[2]	values[0]	431	1			T44	11		T15	9		T52	20
auto[0]	values[2]	values[1]	317	1			T15	12		T194	8		T184	14
auto[0]	values[2]	values[2]	570	1			T51	25		T169	7		T203	8
auto[0]	values[2]	values[3]	502	1			T194	12		T168	13		T230	12
auto[0]	values[2]	values[4]	404	1			T52	11		T176	10		T210	12
auto[0]	values[2]	values[5]	526	1			T44	13		T40	6		T202	14
auto[0]	values[2]	values[6]	269	1			T44	19		T14	14		T51	8
auto[0]	values[2]	values[7]	446	1			T9	11		T194	10		T77	20
auto[0]	values[3]	values[0]	375	1			T40	14		T15	9		T192	20
auto[0]	values[3]	values[1]	542	1			T1	11		T96	20		T209	106
auto[0]	values[3]	values[2]	277	1			T1	12		T39	10		T41	6
auto[0]	values[3]	values[3]	405	1			T39	15		T209	37		T19	7
auto[0]	values[3]	values[4]	396	1			T52	17		T77	12		T17	9
auto[0]	values[3]	values[5]	425	1			T9	9		T231	2		T176	14
auto[0]	values[3]	values[6]	288	1			T15	19		T170	13		T198	16
auto[0]	values[3]	values[7]	588	1			T1	13		T9	28		T39	13
auto[0]	values[4]	values[0]	320	1			T39	28		T52	11		T169	6
auto[0]	values[4]	values[1]	367	1			T52	14		T226	12		T21	55
auto[0]	values[4]	values[2]	403	1			T1	27		T14	33		T30	2
auto[0]	values[4]	values[3]	470	1			T190	10		T169	16		T170	11
auto[0]	values[4]	values[4]	359	1			T15	12		T96	28		T176	8
auto[0]	values[4]	values[5]	176	1			T232	4		T171	13		T21	7
auto[0]	values[4]	values[6]	376	1			T110	2		T171	15		T204	19
auto[0]	values[4]	values[7]	264	1			T1	17		T39	24		T182	2
auto[0]	values[5]	values[0]	325	1			T5	2		T169	9		T96	12
auto[0]	values[5]	values[1]	346	1			T9	9		T14	13		T209	81
auto[0]	values[5]	values[2]	259	1			T39	12		T233	14		T15	14
auto[0]	values[5]	values[3]	146	1			T1	12		T226	16		T210	11
auto[0]	values[5]	values[4]	272	1			T52	24		T101	12		T196	11
auto[0]	values[5]	values[5]	133	1			T77	17		T176	4		T210	12
auto[0]	values[5]	values[6]	419	1			T125	10		T196	13		T234	2
auto[0]	values[5]	values[7]	270	1			T1	6		T26	16		T77	14
auto[0]	values[6]	values[0]	262	1			T1	12		T15	13		T170	12
auto[0]	values[6]	values[1]	395	1			T1	13		T96	9		T171	15
auto[0]	values[6]	values[2]	245	1			T9	15		T12	12		T154	90
auto[0]	values[6]	values[3]	585	1			T1	13		T169	7		T209	12
auto[0]	values[6]	values[4]	393	1			T44	8		T194	9		T17	7
auto[0]	values[6]	values[5]	254	1			T55	4		T52	14		T17	13
auto[0]	values[6]	values[6]	214	1			T77	5		T210	9		T21	14
auto[0]	values[6]	values[7]	410	1			T15	78		T101	12		T196	46
auto[0]	values[7]	values[0]	264	1			T221	12		T187	9		T179	12
auto[0]	values[7]	values[1]	229	1			T40	10		T15	14		T52	10
auto[0]	values[7]	values[2]	591	1			T51	10		T15	15		T100	10
auto[0]	values[7]	values[3]	250	1			T2	16		T52	16		T220	14
auto[0]	values[7]	values[4]	184	1			T77	9		T171	18		T184	31
auto[0]	values[7]	values[5]	450	1			T44	14		T14	11		T40	13
auto[0]	values[7]	values[6]	201	1			T17	16		T176	11		T209	12
auto[0]	values[7]	values[7]	312	1			T1	12		T49	12		T170	13
auto[1]	values[0]	values[0]	374	1			T48	18		T194	8		T177	14
auto[1]	values[0]	values[1]	202	1			T9	6		T14	12		T52	10
auto[1]	values[0]	values[2]	181	1			T44	8		T39	11		T235	10
auto[1]	values[0]	values[3]	290	1			T39	8		T17	16		T220	13
auto[1]	values[0]	values[4]	374	1			T209	10		T196	26		T210	20
auto[1]	values[0]	values[5]	279	1			T51	13		T226	6		T177	12
auto[1]	values[0]	values[6]	355	1			T39	6		T15	8		T169	5
auto[1]	values[0]	values[7]	195	1			T51	13		T196	11		T193	6
auto[1]	values[1]	values[0]	283	1			T52	20		T194	43		T209	9
auto[1]	values[1]	values[1]	263	1			T44	9		T39	11		T14	6
auto[1]	values[1]	values[2]	339	1			T23	119		T154	17		T179	9
auto[1]	values[1]	values[3]	85	1			T218	5		T228	13		T236	8
auto[1]	values[1]	values[4]	199	1			T39	7		T170	10		T96	10
auto[1]	values[1]	values[5]	204	1			T14	12		T40	13		T51	11
auto[1]	values[1]	values[6]	226	1			T52	47		T169	6		T209	8
auto[1]	values[1]	values[7]	358	1			T50	14		T39	6		T51	10
auto[1]	values[2]	values[0]	209	1			T44	9		T15	15		T52	6
auto[1]	values[2]	values[1]	262	1			T15	17		T194	12		T184	8
auto[1]	values[2]	values[2]	166	1			T51	15		T169	13		T210	8
auto[1]	values[2]	values[3]	337	1			T201	20		T194	8		T211	24
auto[1]	values[2]	values[4]	381	1			T52	9		T176	10		T210	8
auto[1]	values[2]	values[5]	243	1			T44	7		T40	14		T101	8
auto[1]	values[2]	values[6]	242	1			T44	21		T14	6		T51	12
auto[1]	values[2]	values[7]	164	1			T9	9		T194	10		T77	7
auto[1]	values[3]	values[0]	152	1			T40	6		T15	35		T228	13
auto[1]	values[3]	values[1]	360	1			T1	9		T96	5		T209	6
auto[1]	values[3]	values[2]	337	1			T1	8		T39	10		T51	6
auto[1]	values[3]	values[3]	446	1			T39	9		T209	7		T19	13
auto[1]	values[3]	values[4]	560	1			T52	14		T77	8		T17	11
auto[1]	values[3]	values[5]	222	1			T9	11		T176	6		T21	9
auto[1]	values[3]	values[6]	396	1			T15	85		T170	7		T198	40
auto[1]	values[3]	values[7]	436	1			T1	7		T9	12		T39	16
auto[1]	values[4]	values[0]	228	1			T39	17		T52	9		T169	14
auto[1]	values[4]	values[1]	202	1			T52	14		T226	8		T21	8
auto[1]	values[4]	values[2]	205	1			T1	13		T14	19		T17	8
auto[1]	values[4]	values[3]	213	1			T169	4		T170	9		T193	9
auto[1]	values[4]	values[4]	356	1			T15	13		T96	34		T237	12
auto[1]	values[4]	values[5]	103	1			T238	2		T171	10		T21	13
auto[1]	values[4]	values[6]	210	1			T171	8		T204	6		T154	5
auto[1]	values[4]	values[7]	157	1			T1	3		T39	5		T170	14
auto[1]	values[5]	values[0]	214	1			T169	11		T96	8		T196	8
auto[1]	values[5]	values[1]	153	1			T9	11		T14	9		T222	18
auto[1]	values[5]	values[2]	446	1			T39	40		T15	6		T101	8
auto[1]	values[5]	values[3]	91	1			T1	8		T226	4		T210	9
auto[1]	values[5]	values[4]	181	1			T11	6		T52	5		T101	8
auto[1]	values[5]	values[5]	170	1			T77	6		T176	16		T210	8
auto[1]	values[5]	values[6]	159	1			T196	8		T139	8		T207	12
auto[1]	values[5]	values[7]	238	1			T1	14		T77	6		T218	4
auto[1]	values[6]	values[0]	270	1			T1	8		T15	13		T170	8
auto[1]	values[6]	values[1]	247	1			T1	7		T96	11		T171	5
auto[1]	values[6]	values[2]	95	1			T9	5		T154	12		T85	8
auto[1]	values[6]	values[3]	281	1			T1	7		T57	6		T169	13
auto[1]	values[6]	values[4]	199	1			T44	12		T194	49		T214	16
auto[1]	values[6]	values[5]	258	1			T52	6		T17	8		T101	5
auto[1]	values[6]	values[6]	228	1			T77	17		T210	14		T21	11
auto[1]	values[6]	values[7]	200	1			T15	11		T239	4		T101	8
auto[1]	values[7]	values[0]	167	1			T187	40		T179	8		T240	7
auto[1]	values[7]	values[1]	172	1			T40	10		T15	19		T52	10
auto[1]	values[7]	values[2]	207	1			T51	10		T15	8		T209	10
auto[1]	values[7]	values[3]	182	1			T52	8		T220	6		T218	5
auto[1]	values[7]	values[4]	222	1			T77	11		T171	2		T184	18
auto[1]	values[7]	values[5]	380	1			T44	6		T14	12		T40	7
auto[1]	values[7]	values[6]	150	1			T17	7		T176	9		T209	8
auto[1]	values[7]	values[7]	200	1			T1	8		T170	7		T96	18