Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18834

1

T1

123

T2

8

T5

1

auto[1]

46621

1

T1

117

T2

8

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	1420	1			T1	14		T8	2		T9	3
auto[4:7]	27756	1			T1	30		T5	2		T6	1
auto[8:11]	1432	1			T1	12		T7	2		T8	1
auto[12:15]	307	1			T2	2		T8	2		T32	2
auto[16:19]	341	1			T1	2		T8	1		T32	1
auto[20:23]	2002	1			T1	18		T6	1		T8	9
auto[24:27]	379	1			T1	3		T8	6		T11	2
auto[28:31]	318	1			T1	1		T8	5		T32	2
auto[32:35]	343	1			T1	3		T6	1		T8	1
auto[36:39]	303	1			T2	2		T8	5		T9	1
auto[40:43]	333	1			T1	5		T32	6		T37	3
auto[44:47]	382	1			T1	4		T2	2		T8	1
auto[48:51]	346	1			T1	3		T8	2		T32	2
auto[52:55]	1829	1			T1	3		T6	2		T8	5
auto[56:59]	1397	1			T1	10		T8	6		T9	5
auto[60:63]	319	1			T6	1		T8	1		T32	1
auto[64:67]	311	1			T1	1		T6	1		T8	1
auto[68:71]	390	1			T1	9		T8	1		T9	2
auto[72:75]	332	1			T9	1		T32	1		T44	5
auto[76:79]	321	1			T8	4		T9	5		T32	3
auto[80:83]	314	1			T1	8		T9	1		T37	2
auto[84:87]	298	1			T8	1		T32	4		T37	4
auto[88:91]	1909	1			T1	10		T2	2		T6	1
auto[92:95]	377	1			T1	1		T8	1		T9	1
auto[96:99]	342	1			T1	4		T2	2		T8	2
auto[100:103]	340	1			T1	1		T6	2		T8	4
auto[104:107]	1508	1			T1	8		T8	4		T9	3
auto[108:111]	372	1			T1	1		T2	2		T6	1
auto[112:115]	359	1			T8	2		T9	1		T32	1
auto[116:119]	357	1			T8	2		T9	4		T32	3
auto[120:123]	323	1			T1	1		T8	1		T32	2
auto[124:127]	363	1			T1	3		T8	3		T9	1
auto[128:131]	319	1			T1	4		T8	3		T9	1
auto[132:135]	332	1			T1	2		T9	1		T32	2
auto[136:139]	337	1			T1	2		T8	4		T9	2
auto[140:143]	320	1			T1	1		T8	4		T9	4
auto[144:147]	317	1			T1	2		T9	1		T32	5
auto[148:151]	302	1			T8	2		T9	1		T32	3
auto[152:155]	377	1			T1	2		T8	4		T9	1
auto[156:159]	2019	1			T1	12		T6	2		T7	2
auto[160:163]	335	1			T8	3		T9	1		T32	2
auto[164:167]	329	1			T8	3		T9	1		T37	4
auto[168:171]	334	1			T1	1		T9	2		T32	2
auto[172:175]	374	1			T1	1		T32	2		T37	3
auto[176:179]	365	1			T1	1		T7	2		T9	2
auto[180:183]	1907	1			T1	5		T6	1		T8	8
auto[184:187]	1527	1			T1	8		T6	1		T7	8
auto[188:191]	327	1			T1	1		T9	1		T48	4
auto[192:195]	353	1			T8	3		T9	2		T32	3
auto[196:199]	347	1			T1	3		T8	2		T32	3
auto[200:203]	362	1			T1	6		T8	1		T32	2
auto[204:207]	368	1			T1	2		T7	2		T8	3
auto[208:211]	353	1			T1	2		T9	3		T32	1
auto[212:215]	369	1			T8	1		T9	1		T32	2
auto[216:219]	347	1			T1	2		T8	1		T9	2
auto[220:223]	303	1			T1	1		T32	2		T34	2
auto[224:227]	352	1			T2	2		T8	1		T9	1
auto[228:231]	308	1			T9	1		T48	2		T32	3
auto[232:235]	3030	1			T1	19		T6	1		T7	4
auto[236:239]	361	1			T8	3		T9	1		T32	5
auto[240:243]	329	1			T6	2		T37	3		T14	2
auto[244:247]	372	1			T2	2		T6	1		T32	1
auto[248:251]	324	1			T1	5		T9	1		T32	3
auto[252:255]	333	1			T1	3		T6	1		T9	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	540	1			T1	5		T9	2		T57	1
auto[0:3]	auto[1]	880	1			T1	9		T8	2		T9	1
auto[4:7]	auto[0]	7003	1			T1	15		T5	1		T9	8
auto[4:7]	auto[1]	20753	1			T1	15		T5	1		T6	1
auto[8:11]	auto[0]	544	1			T1	9		T7	1		T9	3
auto[8:11]	auto[1]	888	1			T1	3		T7	1		T8	1
auto[12:15]	auto[0]	82	1			T2	1		T39	2		T77	4
auto[12:15]	auto[1]	225	1			T2	1		T8	2		T32	2
auto[16:19]	auto[0]	94	1			T1	2		T14	2		T51	1
auto[16:19]	auto[1]	247	1			T8	1		T32	1		T37	3
auto[20:23]	auto[0]	596	1			T1	16		T9	3		T110	1
auto[20:23]	auto[1]	1406	1			T1	2		T6	1		T8	9
auto[24:27]	auto[0]	87	1			T1	3		T11	1		T220	1
auto[24:27]	auto[1]	292	1			T8	6		T11	1		T32	3
auto[28:31]	auto[0]	83	1			T15	1		T194	1		T96	1
auto[28:31]	auto[1]	235	1			T1	1		T8	5		T32	2
auto[32:35]	auto[0]	87	1			T39	1		T15	1		T169	2
auto[32:35]	auto[1]	256	1			T1	3		T6	1		T8	1
auto[36:39]	auto[0]	78	1			T2	1		T44	1		T40	1
auto[36:39]	auto[1]	225	1			T2	1		T8	5		T9	1
auto[40:43]	auto[0]	102	1			T1	2		T44	2		T39	1
auto[40:43]	auto[1]	231	1			T1	3		T32	6		T37	3
auto[44:47]	auto[0]	113	1			T2	1		T44	2		T39	2
auto[44:47]	auto[1]	269	1			T1	4		T2	1		T8	1
auto[48:51]	auto[0]	106	1			T39	1		T169	5		T96	1
auto[48:51]	auto[1]	240	1			T1	3		T8	2		T32	2
auto[52:55]	auto[0]	576	1			T1	3		T9	5		T48	1
auto[52:55]	auto[1]	1253	1			T6	2		T8	5		T9	1
auto[56:59]	auto[0]	518	1			T1	5		T9	3		T11	1
auto[56:59]	auto[1]	879	1			T1	5		T8	6		T9	2
auto[60:63]	auto[0]	102	1			T50	1		T39	2		T29	3
auto[60:63]	auto[1]	217	1			T6	1		T8	1		T32	1
auto[64:67]	auto[0]	101	1			T1	1		T9	2		T57	1
auto[64:67]	auto[1]	210	1			T6	1		T8	1		T32	3
auto[68:71]	auto[0]	131	1			T1	3		T44	4		T39	2
auto[68:71]	auto[1]	259	1			T1	6		T8	1		T9	2
auto[72:75]	auto[0]	110	1			T9	1		T44	5		T51	1
auto[72:75]	auto[1]	222	1			T32	1		T39	1		T14	1
auto[76:79]	auto[0]	94	1			T9	2		T44	2		T39	2
auto[76:79]	auto[1]	227	1			T8	4		T9	3		T32	3
auto[80:83]	auto[0]	109	1			T1	5		T14	1		T40	2
auto[80:83]	auto[1]	205	1			T1	3		T9	1		T37	2
auto[84:87]	auto[0]	78	1			T44	2		T39	1		T40	2
auto[84:87]	auto[1]	220	1			T8	1		T32	4		T37	4
auto[88:91]	auto[0]	538	1			T1	8		T2	1		T9	2
auto[88:91]	auto[1]	1371	1			T1	2		T2	1		T6	1
auto[92:95]	auto[0]	115	1			T1	1		T39	6		T14	6
auto[92:95]	auto[1]	262	1			T8	1		T9	1		T32	5
auto[96:99]	auto[0]	103	1			T1	2		T2	1		T39	2
auto[96:99]	auto[1]	239	1			T1	2		T2	1		T8	2
auto[100:103]	auto[0]	86	1			T39	1		T51	1		T15	2
auto[100:103]	auto[1]	254	1			T1	1		T6	2		T8	4
auto[104:107]	auto[0]	575	1			T1	3		T9	2		T48	1
auto[104:107]	auto[1]	933	1			T1	5		T8	4		T9	1
auto[108:111]	auto[0]	122	1			T2	1		T201	1		T40	1
auto[108:111]	auto[1]	250	1			T1	1		T2	1		T6	1
auto[112:115]	auto[0]	103	1			T44	2		T14	1		T40	1
auto[112:115]	auto[1]	256	1			T8	2		T9	1		T32	1
auto[116:119]	auto[0]	101	1			T9	2		T14	2		T40	1
auto[116:119]	auto[1]	256	1			T8	2		T9	2		T32	3
auto[120:123]	auto[0]	90	1			T1	1		T44	2		T14	1
auto[120:123]	auto[1]	233	1			T8	1		T32	2		T14	4
auto[124:127]	auto[0]	99	1			T1	1		T9	1		T39	2
auto[124:127]	auto[1]	264	1			T1	2		T8	3		T37	4
auto[128:131]	auto[0]	99	1			T9	1		T39	1		T52	2
auto[128:131]	auto[1]	220	1			T1	4		T8	3		T32	5
auto[132:135]	auto[0]	91	1			T1	1		T14	5		T40	2
auto[132:135]	auto[1]	241	1			T1	1		T9	1		T32	2
auto[136:139]	auto[0]	102	1			T1	2		T9	2		T54	1
auto[136:139]	auto[1]	235	1			T8	4		T34	2		T54	1
auto[140:143]	auto[0]	104	1			T1	1		T9	2		T44	1
auto[140:143]	auto[1]	216	1			T8	4		T9	2		T32	4
auto[144:147]	auto[0]	71	1			T9	1		T39	2		T14	1
auto[144:147]	auto[1]	246	1			T1	2		T32	5		T37	4
auto[148:151]	auto[0]	72	1			T9	1		T44	1		T51	1
auto[148:151]	auto[1]	230	1			T8	2		T32	3		T34	1
auto[152:155]	auto[0]	123	1			T1	1		T9	1		T39	1
auto[152:155]	auto[1]	254	1			T1	1		T8	4		T32	1
auto[156:159]	auto[0]	601	1			T1	5		T7	1		T9	1
auto[156:159]	auto[1]	1418	1			T1	7		T6	2		T7	1
auto[160:163]	auto[0]	105	1			T232	1		T51	1		T15	3
auto[160:163]	auto[1]	230	1			T8	3		T9	1		T32	2
auto[164:167]	auto[0]	95	1			T44	2		T40	1		T52	4
auto[164:167]	auto[1]	234	1			T8	3		T9	1		T37	4
auto[168:171]	auto[0]	89	1			T50	1		T44	2		T15	1
auto[168:171]	auto[1]	245	1			T1	1		T9	2		T32	2
auto[172:175]	auto[0]	106	1			T44	3		T39	1		T14	1
auto[172:175]	auto[1]	268	1			T1	1		T32	2		T37	3
auto[176:179]	auto[0]	103	1			T7	1		T9	1		T44	1
auto[176:179]	auto[1]	262	1			T1	1		T7	1		T9	1
auto[180:183]	auto[0]	542	1			T1	2		T12	3		T44	4
auto[180:183]	auto[1]	1365	1			T1	3		T6	1		T8	8
auto[184:187]	auto[0]	571	1			T1	3		T7	4		T9	2
auto[184:187]	auto[1]	956	1			T1	5		T6	1		T7	4
auto[188:191]	auto[0]	92	1			T1	1		T48	2		T44	1
auto[188:191]	auto[1]	235	1			T9	1		T48	2		T32	3
auto[192:195]	auto[0]	89	1			T9	1		T39	2		T15	1
auto[192:195]	auto[1]	264	1			T8	3		T9	1		T32	3
auto[196:199]	auto[0]	97	1			T52	2		T222	1		T176	1
auto[196:199]	auto[1]	250	1			T1	3		T8	2		T32	3
auto[200:203]	auto[0]	119	1			T1	5		T39	2		T51	5
auto[200:203]	auto[1]	243	1			T1	1		T8	1		T32	2
auto[204:207]	auto[0]	122	1			T1	1		T7	1		T9	2
auto[204:207]	auto[1]	246	1			T1	1		T7	1		T8	3
auto[208:211]	auto[0]	78	1			T9	1		T39	3		T15	3
auto[208:211]	auto[1]	275	1			T1	2		T9	2		T32	1
auto[212:215]	auto[0]	120	1			T44	3		T39	4		T14	1
auto[212:215]	auto[1]	249	1			T8	1		T9	1		T32	2
auto[216:219]	auto[0]	117	1			T1	1		T40	2		T15	1
auto[216:219]	auto[1]	230	1			T1	1		T8	1		T9	2
auto[220:223]	auto[0]	89	1			T39	1		T14	3		T15	4
auto[220:223]	auto[1]	214	1			T1	1		T32	2		T34	2
auto[224:227]	auto[0]	110	1			T2	1		T9	1		T39	3
auto[224:227]	auto[1]	242	1			T2	1		T8	1		T37	3
auto[228:231]	auto[0]	86	1			T48	1		T40	1		T51	1
auto[228:231]	auto[1]	222	1			T9	1		T48	1		T32	3
auto[232:235]	auto[0]	1071	1			T1	11		T7	2		T9	10
auto[232:235]	auto[1]	1959	1			T1	8		T6	1		T7	2
auto[236:239]	auto[0]	91	1			T14	2		T51	2		T15	2
auto[236:239]	auto[1]	270	1			T8	3		T9	1		T32	5
auto[240:243]	auto[0]	108	1			T14	1		T51	1		T169	1
auto[240:243]	auto[1]	221	1			T6	2		T37	3		T14	1
auto[244:247]	auto[0]	109	1			T2	1		T50	1		T39	1
auto[244:247]	auto[1]	263	1			T2	1		T6	1		T32	1
auto[248:251]	auto[0]	101	1			T1	2		T9	1		T39	2
auto[248:251]	auto[1]	223	1			T1	3		T32	3		T37	1
auto[252:255]	auto[0]	95	1			T1	2		T39	2		T222	1
auto[252:255]	auto[1]	238	1			T1	1		T6	1		T9	1