Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	457	1			T1	3		T9	3		T44	4
auto[ReadAddrCrossIntoMailbox]	372	1			T1	3		T39	4		T14	1
auto[ReadAddrCrossOutOfMailbox]	383	1			T1	3		T44	4		T39	3
auto[ReadAddrCrossAllMailbox]	262	1			T1	1		T44	1		T39	3
auto[ReadAddrOutsideMailbox]	4368	1			T1	46		T7	10		T9	24

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2759

1

T1

22

T7

5

T9

13

auto[1]

3083

1

T1

34

T7

5

T9

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	961	1			T1	11		T9	3		T57	2
read_ops[0x0b]	907	1			T1	10		T9	3		T150	2
read_ops[0x3b]	940	1			T1	9		T9	5		T11	2
read_ops[0x6b]	1015	1			T1	8		T9	2		T48	2
read_ops[0xbb]	1042	1			T1	6		T7	8		T9	9
read_ops[0xeb]	977	1			T1	12		T7	2		T9	5

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T44	1		T51	1		T17	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T1	2		T39	1		T14	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	38	1			T39	1		T169	1		T194	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	40	1			T1	2		T15	1		T52	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T39	1		T51	2		T15	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T40	1		T171	1		T17	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T39	1		T169	1		T184	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T52	1		T101	1		T198	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	327	1			T1	3		T9	2		T57	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	372	1			T1	4		T9	1		T57	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T194	1		T17	1		T154	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T1	1		T44	1		T51	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T39	1		T194	1		T209	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	39	1			T15	1		T52	3		T101	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T44	1		T171	2		T17	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T44	1		T52	1		T96	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T52	1		T17	1		T213	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T96	2		T209	1		T213	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	338	1			T1	5		T9	1		T150	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	351	1			T1	4		T9	2		T150	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T44	1		T39	1		T52	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T39	1		T170	1		T171	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T96	1		T19	1		T20	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T39	1		T40	1		T169	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T1	1		T44	1		T14	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T194	1		T198	1		T226	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T39	1		T96	1		T101	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T40	1		T194	1		T171	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	316	1			T1	4		T9	3		T11	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	382	1			T1	4		T9	2		T11	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T9	1		T39	1		T194	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T40	1		T169	1		T170	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T39	1		T198	1		T196	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T51	2		T52	1		T77	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T39	1		T15	1		T194	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	45	1			T1	1		T44	1		T170	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T169	1		T17	1		T101	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T15	1		T96	1		T193	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	362	1			T1	3		T48	1		T50	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	390	1			T1	4		T9	1		T48	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T9	1		T194	1		T219	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T15	1		T169	1		T194	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T52	1		T194	1		T170	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	39	1			T14	1		T52	2		T170	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T39	1		T51	1		T241	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	40	1			T1	1		T194	1		T170	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T39	1		T196	1		T218	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	33	1			T14	1		T40	1		T96	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	370	1			T1	1		T7	4		T9	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	400	1			T1	4		T7	4		T9	7
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T9	1		T39	1		T14	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T44	1		T219	1		T77	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T1	1		T20	1		T242	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T51	1		T96	1		T17	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T194	1		T170	1		T96	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T15	1		T194	1		T96	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T1	1		T14	1		T52	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T44	1		T52	1		T176	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	374	1			T1	3		T7	1		T9	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	386	1			T1	7		T7	1		T9	1