Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5004	1			T9	60		T39	76		T232	4
values[1]	5547	1			T1	40		T49	12		T50	14
values[2]	4466	1			T1	60		T7	20		T9	40
values[3]	4273	1			T1	40		T44	20		T39	24
values[4]	4745	1			T1	40		T5	2		T57	6
values[5]	5412	1			T1	20		T12	12		T150	6
values[6]	4266	1			T1	20		T2	16		T9	20
values[7]	4592	1			T1	20		T9	20		T48	18

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4993	1			T1	20		T9	20		T11	6
values[1]	4791	1			T1	40		T55	4		T39	109
values[2]	4814	1			T2	16		T5	2		T110	2
values[3]	5272	1			T1	20		T12	12		T50	14
values[4]	5240	1			T1	40		T7	20		T150	6
values[5]	4832	1			T1	40		T9	60		T39	52
values[6]	4130	1			T1	60		T9	20		T48	18
values[7]	4233	1			T1	20		T9	40		T49	12

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37270

1

T1

229

T2

16

T5

2

auto[1]

1035

1

T1

11

T9

3

T50

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	762	1			T9	20		T52	28		T194	37
auto[0]	values[0]	values[1]	733	1			T39	23		T51	20		T52	20
auto[0]	values[0]	values[2]	840	1			T229	6		T15	25		T169	20
auto[0]	values[0]	values[3]	496	1			T39	19		T232	4		T51	20
auto[0]	values[0]	values[4]	493	1			T52	29		T194	50		T220	20
auto[0]	values[0]	values[5]	536	1			T9	38		T226	11		T23	28
auto[0]	values[0]	values[6]	569	1			T39	27		T14	23		T101	20
auto[0]	values[0]	values[7]	452	1			T196	36		T20	31		T187	20
auto[0]	values[1]	values[0]	802	1			T1	19		T44	40		T26	16
auto[0]	values[1]	values[1]	729	1			T55	4		T39	40		T171	40
auto[0]	values[1]	values[2]	714	1			T39	40		T176	19		T193	42
auto[0]	values[1]	values[3]	684	1			T50	12		T52	23		T198	17
auto[0]	values[1]	values[4]	601	1			T1	18		T233	14		T182	2
auto[0]	values[1]	values[5]	764	1			T96	20		T209	19		T198	31
auto[0]	values[1]	values[6]	367	1			T209	20		T193	24		T243	20
auto[0]	values[1]	values[7]	745	1			T49	12		T14	22		T96	22
auto[0]	values[2]	values[0]	374	1			T11	6		T103	20		T14	23
auto[0]	values[2]	values[1]	536	1			T51	20		T15	23		T20	78
auto[0]	values[2]	values[2]	743	1			T39	21		T171	20		T17	22
auto[0]	values[2]	values[3]	484	1			T1	20		T14	16		T101	20
auto[0]	values[2]	values[4]	712	1			T7	20		T176	15		T209	39
auto[0]	values[2]	values[5]	626	1			T1	20		T40	18		T244	8
auto[0]	values[2]	values[6]	456	1			T1	19		T9	20		T14	20
auto[0]	values[2]	values[7]	391	1			T9	19		T238	2		T170	37
auto[0]	values[3]	values[0]	730	1			T201	20		T52	19		T171	21
auto[0]	values[3]	values[1]	585	1			T39	24		T195	2		T202	14
auto[0]	values[3]	values[2]	399	1			T15	20		T17	22		T196	20
auto[0]	values[3]	values[3]	532	1			T40	17		T169	58		T170	20
auto[0]	values[3]	values[4]	758	1			T41	6		T52	31		T190	10
auto[0]	values[3]	values[5]	573	1			T40	16		T170	20		T187	20
auto[0]	values[3]	values[6]	241	1			T1	38		T44	20		T227	2
auto[0]	values[3]	values[7]	329	1			T196	19		T210	22		T245	8
auto[0]	values[4]	values[0]	821	1			T39	29		T171	23		T42	34
auto[0]	values[4]	values[1]	604	1			T17	20		T230	12		T191	22
auto[0]	values[4]	values[2]	516	1			T5	2		T44	20		T39	28
auto[0]	values[4]	values[3]	707	1			T44	58		T246	22		T23	20
auto[0]	values[4]	values[4]	502	1			T57	6		T125	10		T14	20
auto[0]	values[4]	values[5]	523	1			T1	20		T14	21		T40	19
auto[0]	values[4]	values[6]	270	1			T40	17		T15	18		T196	21
auto[0]	values[4]	values[7]	668	1			T1	18		T40	20		T203	8
auto[0]	values[5]	values[0]	541	1			T44	19		T15	23		T96	19
auto[0]	values[5]	values[1]	460	1			T1	17		T39	19		T194	57
auto[0]	values[5]	values[2]	547	1			T14	27		T52	20		T101	20
auto[0]	values[5]	values[3]	966	1			T12	12		T15	117		T52	52
auto[0]	values[5]	values[4]	808	1			T150	6		T29	45		T52	20
auto[0]	values[5]	values[5]	498	1			T52	49		T194	53		T247	10
auto[0]	values[5]	values[6]	707	1			T39	22		T15	28		T52	25
auto[0]	values[5]	values[7]	732	1			T198	181		T20	19		T185	20
auto[0]	values[6]	values[0]	357	1			T15	52		T52	18		T170	19
auto[0]	values[6]	values[1]	431	1			T1	20		T77	24		T218	22
auto[0]	values[6]	values[2]	670	1			T2	16		T110	2		T96	25
auto[0]	values[6]	values[3]	626	1			T54	2		T101	35		T198	27
auto[0]	values[6]	values[4]	487	1			T209	88		T198	20		T212	4
auto[0]	values[6]	values[5]	546	1			T9	20		T15	93		T96	29
auto[0]	values[6]	values[6]	648	1			T171	20		T17	20		T101	16
auto[0]	values[6]	values[7]	411	1			T51	16		T248	6		T176	18
auto[0]	values[7]	values[0]	453	1			T225	8		T210	20		T42	181
auto[0]	values[7]	values[1]	585	1			T51	38		T169	20		T176	15
auto[0]	values[7]	values[2]	278	1			T51	20		T154	40		T249	2
auto[0]	values[7]	values[3]	622	1			T169	18		T17	20		T168	20
auto[0]	values[7]	values[4]	762	1			T1	20		T15	25		T17	20
auto[0]	values[7]	values[5]	628	1			T39	51		T231	2		T176	19
auto[0]	values[7]	values[6]	739	1			T48	18		T14	20		T30	2
auto[0]	values[7]	values[7]	401	1			T9	20		T52	20		T96	20
auto[1]	values[0]	values[0]	23	1			T194	3		T96	5		T204	2
auto[1]	values[0]	values[1]	16	1			T39	2		T169	1		T210	2
auto[1]	values[0]	values[2]	10	1			T250	3		T251	1		T252	2
auto[1]	values[0]	values[3]	16	1			T39	1		T176	3		T241	5
auto[1]	values[0]	values[4]	13	1			T210	1		T253	1		T254	1
auto[1]	values[0]	values[5]	17	1			T9	2		T226	9		T187	1
auto[1]	values[0]	values[6]	19	1			T39	4		T14	1		T250	1
auto[1]	values[0]	values[7]	9	1			T42	1		T61	1		T255	2
auto[1]	values[1]	values[0]	22	1			T1	1		T96	1		T77	1
auto[1]	values[1]	values[1]	28	1			T171	3		T176	2		T209	2
auto[1]	values[1]	values[2]	14	1			T176	1		T23	1		T235	2
auto[1]	values[1]	values[3]	19	1			T50	2		T52	1		T198	3
auto[1]	values[1]	values[4]	15	1			T1	2		T23	1		T240	1
auto[1]	values[1]	values[5]	17	1			T209	1		T198	2		T226	1
auto[1]	values[1]	values[6]	9	1			T193	2		T256	2		T61	1
auto[1]	values[1]	values[7]	17	1			T96	4		T196	1		T21	1
auto[1]	values[2]	values[0]	13	1			T51	2		T184	3		T42	2
auto[1]	values[2]	values[1]	14	1			T15	1		T20	1		T187	1
auto[1]	values[2]	values[2]	17	1			T39	1		T21	2		T154	1
auto[1]	values[2]	values[3]	28	1			T14	5		T154	3		T257	2
auto[1]	values[2]	values[4]	22	1			T176	5		T209	5		T198	1
auto[1]	values[2]	values[5]	19	1			T40	2		T251	1		T253	1
auto[1]	values[2]	values[6]	18	1			T1	1		T77	2		T17	1
auto[1]	values[2]	values[7]	13	1			T9	1		T170	3		T258	2
auto[1]	values[3]	values[0]	19	1			T52	1		T184	1		T177	3
auto[1]	values[3]	values[1]	14	1			T194	2		T154	1		T259	3
auto[1]	values[3]	values[2]	15	1			T17	1		T240	1		T260	4
auto[1]	values[3]	values[3]	21	1			T40	3		T169	2		T179	2
auto[1]	values[3]	values[4]	23	1			T184	2		T88	6		T258	3
auto[1]	values[3]	values[5]	19	1			T40	4		T178	2		T139	1
auto[1]	values[3]	values[6]	8	1			T1	2		T140	3		T261	3
auto[1]	values[3]	values[7]	7	1			T196	1		T260	1		T262	2
auto[1]	values[4]	values[0]	23	1			T263	2		T236	1		T264	2
auto[1]	values[4]	values[1]	12	1			T21	2		T178	1		T253	1
auto[1]	values[4]	values[2]	10	1			T39	1		T15	2		T17	1
auto[1]	values[4]	values[3]	13	1			T44	2		T265	1		T61	2
auto[1]	values[4]	values[4]	15	1			T14	1		T218	1		T266	1
auto[1]	values[4]	values[5]	23	1			T14	2		T40	1		T209	1
auto[1]	values[4]	values[6]	20	1			T40	3		T15	2		T258	7
auto[1]	values[4]	values[7]	18	1			T1	2		T184	1		T20	1
auto[1]	values[5]	values[0]	24	1			T44	1		T96	1		T77	4
auto[1]	values[5]	values[1]	11	1			T1	3		T39	1		T194	1
auto[1]	values[5]	values[2]	15	1			T14	1		T240	1		T267	1
auto[1]	values[5]	values[3]	33	1			T15	5		T52	2		T216	1
auto[1]	values[5]	values[4]	14	1			T209	3		T184	2		T20	1
auto[1]	values[5]	values[5]	19	1			T194	2		T188	1		T268	1
auto[1]	values[5]	values[6]	24	1			T15	1		T52	1		T209	4
auto[1]	values[5]	values[7]	13	1			T20	1		T253	4		T269	4
auto[1]	values[6]	values[0]	14	1			T52	2		T170	1		T270	3
auto[1]	values[6]	values[1]	9	1			T20	2		T42	5		T253	1
auto[1]	values[6]	values[2]	14	1			T101	3		T267	3		T158	1
auto[1]	values[6]	values[3]	8	1			T101	5		T266	1		T251	1
auto[1]	values[6]	values[4]	6	1			T259	1		T254	5		-	-
auto[1]	values[6]	values[5]	9	1			T15	3		T178	1		T188	2
auto[1]	values[6]	values[6]	12	1			T101	4		T198	1		T235	1
auto[1]	values[6]	values[7]	18	1			T51	4		T176	2		T269	1
auto[1]	values[7]	values[0]	15	1			T42	3		T261	1		T160	6
auto[1]	values[7]	values[1]	24	1			T51	2		T176	5		T178	3
auto[1]	values[7]	values[2]	12	1			T179	4		T235	2		T271	2
auto[1]	values[7]	values[3]	17	1			T169	2		T42	2		T266	3
auto[1]	values[7]	values[4]	9	1			T15	1		T101	1		T19	2
auto[1]	values[7]	values[5]	15	1			T39	1		T176	1		T101	2
auto[1]	values[7]	values[6]	23	1			T14	5		T51	1		T211	2
auto[1]	values[7]	values[7]	9	1			T154	2		T181	2		T272	1