Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	909	1			T14	20		T16	17		T77	10
all_values[1]	909	1			T14	20		T16	17		T77	10
all_values[2]	909	1			T14	20		T16	17		T77	10
all_values[3]	909	1			T14	20		T16	17		T77	10
all_values[4]	909	1			T14	20		T16	17		T77	10
all_values[5]	909	1			T14	20		T16	17		T77	10
all_values[6]	909	1			T14	20		T16	17		T77	10
all_values[7]	909	1			T14	20		T16	17		T77	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3915

1

T14

100

T16

66

T77

36

auto[1]

3357

1

T14

60

T16

70

T77

44

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2880

1

T14

65

T16

62

T77

20

auto[1]

4392

1

T14

95

T16

74

T77

60

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4112

1

T14

88

T16

76

T77

43

auto[1]

3160

1

T14

72

T16

60

T77

37

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	179	1			T14	7		T16	4		T77	2
all_values[0]	auto[0]	auto[0]	auto[1]	79	1			T14	3		T77	1		T18	1
all_values[0]	auto[0]	auto[1]	auto[0]	164	1			T14	4		T16	8		T77	1
all_values[0]	auto[0]	auto[1]	auto[1]	87	1			T77	1		T18	4		T168	4
all_values[0]	auto[1]	auto[0]	auto[1]	215	1			T14	4		T16	1		T77	4
all_values[0]	auto[1]	auto[1]	auto[1]	185	1			T14	2		T16	4		T77	1
all_values[1]	auto[0]	auto[0]	auto[0]	185	1			T14	3		T16	2		T17	2
all_values[1]	auto[0]	auto[0]	auto[1]	97	1			T14	2		T16	1		T77	1
all_values[1]	auto[0]	auto[1]	auto[0]	155	1			T14	3		T16	2		T77	1
all_values[1]	auto[0]	auto[1]	auto[1]	88	1			T14	2		T16	2		T77	3
all_values[1]	auto[1]	auto[0]	auto[1]	218	1			T14	3		T16	6		T77	3
all_values[1]	auto[1]	auto[1]	auto[1]	166	1			T14	7		T16	4		T77	2
all_values[2]	auto[0]	auto[0]	auto[0]	190	1			T14	4		T16	4		T77	2
all_values[2]	auto[0]	auto[0]	auto[1]	73	1			T77	1		T168	2		T19	1
all_values[2]	auto[0]	auto[1]	auto[0]	160	1			T14	3		T16	4		T17	2
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T14	1		T16	2		T77	2
all_values[2]	auto[1]	auto[0]	auto[1]	201	1			T14	7		T16	4		T77	2
all_values[2]	auto[1]	auto[1]	auto[1]	195	1			T14	5		T16	3		T77	3
all_values[3]	auto[0]	auto[0]	auto[0]	186	1			T14	5		T16	3		T77	1
all_values[3]	auto[0]	auto[0]	auto[1]	94	1			T14	2		T16	2		T77	1
all_values[3]	auto[0]	auto[1]	auto[0]	155	1			T16	2		T77	5		T17	1
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T14	5		T16	1		T77	1
all_values[3]	auto[1]	auto[0]	auto[1]	215	1			T14	5		T16	2		T77	1
all_values[3]	auto[1]	auto[1]	auto[1]	173	1			T14	3		T16	7		T77	1
all_values[4]	auto[0]	auto[0]	auto[0]	197	1			T14	3		T16	6		T17	3
all_values[4]	auto[0]	auto[0]	auto[1]	100	1			T14	4		T16	1		T77	1
all_values[4]	auto[0]	auto[1]	auto[0]	136	1			T14	6		T16	5		T18	2
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T77	2		T17	1		T168	1
all_values[4]	auto[1]	auto[0]	auto[1]	224	1			T14	7		T16	4		T77	5
all_values[4]	auto[1]	auto[1]	auto[1]	174	1			T16	1		T77	2		T17	1
all_values[5]	auto[0]	auto[0]	auto[0]	289	1			T14	5		T16	4		T77	2
all_values[5]	auto[0]	auto[1]	auto[0]	241	1			T14	3		T16	5		T77	3
all_values[5]	auto[1]	auto[0]	auto[1]	201	1			T14	9		T16	2		T77	1
all_values[5]	auto[1]	auto[1]	auto[1]	178	1			T14	3		T16	6		T77	4
all_values[6]	auto[0]	auto[0]	auto[0]	180	1			T14	4		T16	7		T77	1
all_values[6]	auto[0]	auto[0]	auto[1]	84	1			T14	1		T16	1		T77	1
all_values[6]	auto[0]	auto[1]	auto[0]	144	1			T14	5		T16	2		T17	1
all_values[6]	auto[0]	auto[1]	auto[1]	91	1			T14	1		T16	1		T77	4
all_values[6]	auto[1]	auto[0]	auto[1]	220	1			T14	6		T16	2		T17	2
all_values[6]	auto[1]	auto[1]	auto[1]	190	1			T14	3		T16	4		T77	4
all_values[7]	auto[0]	auto[0]	auto[0]	177	1			T14	9		T16	4		T77	1
all_values[7]	auto[0]	auto[0]	auto[1]	90	1			T14	2		T16	2		T77	2
all_values[7]	auto[0]	auto[1]	auto[0]	142	1			T14	1		T77	1		T17	1
all_values[7]	auto[0]	auto[1]	auto[1]	95	1			T16	1		T77	2		T18	2
all_values[7]	auto[1]	auto[0]	auto[1]	221	1			T14	5		T16	4		T77	3
all_values[7]	auto[1]	auto[1]	auto[1]	184	1			T14	3		T16	6		T77	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal