Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1760

1

T3

9

T31

2

T32

4

auto[1]

1794

1

T3

15

T31

8

T32

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1927

1

T32

6

T33

10

T34

13

auto[1]

1627

1

T3

24

T31

10

T35

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2838

1

T3

24

T31

10

T32

3

auto[1]

716

1

T32

3

T33

4

T34

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	683	1			T3	7		T31	3		T32	1
valid[1]	703	1			T3	3		T32	1		T33	2
valid[2]	706	1			T3	4		T31	2		T32	1
valid[3]	716	1			T3	3		T31	2		T32	1
valid[4]	746	1			T3	7		T31	3		T32	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	100	1			T14	2		T25	1		T15	1
auto[0]	auto[0]	valid[0]	auto[1]	171	1			T3	4		T15	1		T98	3
auto[0]	auto[0]	valid[1]	auto[0]	129	1			T14	2		T25	1		T15	2
auto[0]	auto[0]	valid[1]	auto[1]	153	1			T3	1		T14	1		T97	1
auto[0]	auto[0]	valid[2]	auto[0]	133	1			T34	2		T39	1		T25	1
auto[0]	auto[0]	valid[2]	auto[1]	144	1			T3	1		T35	1		T97	1
auto[0]	auto[0]	valid[3]	auto[0]	111	1			T34	2		T39	1		T14	1
auto[0]	auto[0]	valid[3]	auto[1]	172	1			T3	1		T31	1		T35	1
auto[0]	auto[0]	valid[4]	auto[0]	142	1			T32	1		T33	2		T39	3
auto[0]	auto[0]	valid[4]	auto[1]	150	1			T3	2		T31	1		T35	1
auto[0]	auto[1]	valid[0]	auto[0]	104	1			T14	1		T15	4		T56	1
auto[0]	auto[1]	valid[0]	auto[1]	178	1			T3	3		T31	3		T14	1
auto[0]	auto[1]	valid[1]	auto[0]	119	1			T32	1		T33	2		T37	1
auto[0]	auto[1]	valid[1]	auto[1]	163	1			T3	2		T14	2		T97	1
auto[0]	auto[1]	valid[2]	auto[0]	120	1			T33	1		T34	3		T37	1
auto[0]	auto[1]	valid[2]	auto[1]	169	1			T3	3		T31	2		T97	1
auto[0]	auto[1]	valid[3]	auto[0]	136	1			T34	1		T39	1		T14	3
auto[0]	auto[1]	valid[3]	auto[1]	146	1			T3	2		T31	1		T97	3
auto[0]	auto[1]	valid[4]	auto[0]	117	1			T32	1		T33	1		T34	1
auto[0]	auto[1]	valid[4]	auto[1]	181	1			T3	5		T31	2		T15	1
auto[1]	auto[0]	valid[0]	auto[0]	62	1			T32	1		T33	1		T34	1
auto[1]	auto[0]	valid[1]	auto[0]	68	1			T39	1		T25	1		T27	1
auto[1]	auto[0]	valid[2]	auto[0]	74	1			T32	1		T34	1		T14	1
auto[1]	auto[0]	valid[3]	auto[0]	84	1			T32	1		T33	1		T34	1
auto[1]	auto[0]	valid[4]	auto[0]	67	1			T14	2		T27	1		T56	1
auto[1]	auto[1]	valid[0]	auto[0]	68	1			T33	1		T14	1		T286	1
auto[1]	auto[1]	valid[1]	auto[0]	71	1			T39	1		T14	2		T25	1
auto[1]	auto[1]	valid[2]	auto[0]	66	1			T34	1		T39	2		T15	1
auto[1]	auto[1]	valid[3]	auto[0]	67	1			T56	1		T288	2		T96	2
auto[1]	auto[1]	valid[4]	auto[0]	89	1			T33	1		T39	1		T15	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal