Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47846

1

T32

146

T33

300

T34

446

auto[1]

16832

1

T3

384

T31

10

T35

82

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47066

1

T3

384

T31

10

T32

92

auto[1]

17612

1

T32

54

T33

113

T34

152

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33374	1			T3	190		T31	10		T32	79
others[1]	5476	1			T3	38		T32	8		T33	32
others[2]	5427	1			T3	28		T32	8		T33	18
others[3]	6210	1			T3	33		T32	15		T33	33
interest[1]	3571	1			T3	18		T32	11		T33	11
interest[4]	21773	1			T3	126		T31	10		T32	52
interest[64]	10620	1			T3	77		T32	25		T33	49

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15521	1			T32	55		T33	94		T34	155
auto[0]	auto[0]	others[1]	2591	1			T32	4		T33	16		T34	22
auto[0]	auto[0]	others[2]	2469	1			T32	6		T33	12		T34	25
auto[0]	auto[0]	others[3]	2942	1			T32	8		T33	25		T34	20
auto[0]	auto[0]	interest[1]	1656	1			T32	6		T33	7		T34	17
auto[0]	auto[0]	interest[4]	10110	1			T32	35		T33	67		T34	95
auto[0]	auto[0]	interest[64]	5055	1			T32	13		T33	33		T34	55
auto[0]	auto[1]	others[0]	8864	1			T3	190		T31	10		T35	34
auto[0]	auto[1]	others[1]	1349	1			T3	38		T35	4		T14	6
auto[0]	auto[1]	others[2]	1428	1			T3	28		T35	9		T14	6
auto[0]	auto[1]	others[3]	1557	1			T3	33		T35	7		T14	6
auto[0]	auto[1]	interest[1]	953	1			T3	18		T35	6		T14	13
auto[0]	auto[1]	interest[4]	5841	1			T3	126		T31	10		T35	21
auto[0]	auto[1]	interest[64]	2681	1			T3	77		T35	22		T14	22
auto[1]	auto[0]	others[0]	8989	1			T32	24		T33	63		T34	74
auto[1]	auto[0]	others[1]	1536	1			T32	4		T33	16		T34	12
auto[1]	auto[0]	others[2]	1530	1			T32	2		T33	6		T34	12
auto[1]	auto[0]	others[3]	1711	1			T32	7		T33	8		T34	20
auto[1]	auto[0]	interest[1]	962	1			T32	5		T33	4		T34	7
auto[1]	auto[0]	interest[4]	5822	1			T32	17		T33	44		T34	41
auto[1]	auto[0]	interest[64]	2884	1			T32	12		T33	16		T34	27

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal