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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.19 95.45 99.21


Total test records in report: 1129
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T1023 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3413416191 Jun 28 05:30:24 PM PDT 24 Jun 28 05:30:25 PM PDT 24 165607550 ps
T1024 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2584201651 Jun 28 05:30:45 PM PDT 24 Jun 28 05:30:47 PM PDT 24 15886291 ps
T1025 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2187579890 Jun 28 05:30:45 PM PDT 24 Jun 28 05:30:47 PM PDT 24 30934810 ps
T1026 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.284143426 Jun 28 05:30:10 PM PDT 24 Jun 28 05:30:45 PM PDT 24 1345455401 ps
T124 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4255164241 Jun 28 05:30:24 PM PDT 24 Jun 28 05:30:26 PM PDT 24 118225071 ps
T112 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3660832150 Jun 28 05:30:25 PM PDT 24 Jun 28 05:30:30 PM PDT 24 124406172 ps
T136 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.516741952 Jun 28 05:30:37 PM PDT 24 Jun 28 05:30:41 PM PDT 24 35245671 ps
T113 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1507279217 Jun 28 05:30:39 PM PDT 24 Jun 28 05:30:43 PM PDT 24 52959046 ps
T1027 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2882110553 Jun 28 05:30:39 PM PDT 24 Jun 28 05:30:42 PM PDT 24 43005296 ps
T137 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.783024707 Jun 28 05:30:12 PM PDT 24 Jun 28 05:30:14 PM PDT 24 56005557 ps
T1028 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1799017327 Jun 28 05:30:46 PM PDT 24 Jun 28 05:30:48 PM PDT 24 39480069 ps
T1029 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3049599346 Jun 28 05:29:59 PM PDT 24 Jun 28 05:30:08 PM PDT 24 480280750 ps
T111 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.608750557 Jun 28 05:30:34 PM PDT 24 Jun 28 05:30:40 PM PDT 24 143071653 ps
T1030 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.903070149 Jun 28 05:30:48 PM PDT 24 Jun 28 05:30:50 PM PDT 24 16813312 ps
T1031 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2737359825 Jun 28 05:30:23 PM PDT 24 Jun 28 05:30:25 PM PDT 24 58830055 ps
T163 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.350177905 Jun 28 05:30:35 PM PDT 24 Jun 28 05:30:54 PM PDT 24 3041229831 ps
T1032 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1362350347 Jun 28 05:30:27 PM PDT 24 Jun 28 05:30:31 PM PDT 24 75866272 ps
T1033 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3987359784 Jun 28 05:30:34 PM PDT 24 Jun 28 05:30:36 PM PDT 24 16388863 ps
T1034 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.117615292 Jun 28 05:30:13 PM PDT 24 Jun 28 05:30:17 PM PDT 24 245752471 ps
T1035 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3907820041 Jun 28 05:30:12 PM PDT 24 Jun 28 05:30:15 PM PDT 24 21475520 ps
T1036 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1382425039 Jun 28 05:30:12 PM PDT 24 Jun 28 05:30:16 PM PDT 24 689938799 ps
T1037 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2734782880 Jun 28 05:30:00 PM PDT 24 Jun 28 05:30:01 PM PDT 24 73980821 ps
T1038 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3783657375 Jun 28 05:30:36 PM PDT 24 Jun 28 05:30:42 PM PDT 24 152685270 ps
T1039 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.746594734 Jun 28 05:30:24 PM PDT 24 Jun 28 05:30:26 PM PDT 24 36998971 ps
T1040 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2156885155 Jun 28 05:30:44 PM PDT 24 Jun 28 05:30:46 PM PDT 24 15236969 ps
T1041 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2676242579 Jun 28 05:30:00 PM PDT 24 Jun 28 05:30:01 PM PDT 24 11248469 ps
T161 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1044189179 Jun 28 05:30:36 PM PDT 24 Jun 28 05:30:44 PM PDT 24 340741566 ps
T1042 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2957351407 Jun 28 05:30:12 PM PDT 24 Jun 28 05:30:14 PM PDT 24 81435650 ps
T1043 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1487867575 Jun 28 05:30:13 PM PDT 24 Jun 28 05:30:41 PM PDT 24 4962428607 ps
T1044 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3297482832 Jun 28 05:30:13 PM PDT 24 Jun 28 05:30:17 PM PDT 24 279967212 ps
T1045 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1526893584 Jun 28 05:30:36 PM PDT 24 Jun 28 05:30:38 PM PDT 24 18644793 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1431334411 Jun 28 05:30:12 PM PDT 24 Jun 28 05:30:16 PM PDT 24 49277475 ps
T1047 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.41108952 Jun 28 05:30:13 PM PDT 24 Jun 28 05:30:36 PM PDT 24 311224214 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1580521367 Jun 28 05:30:12 PM PDT 24 Jun 28 05:30:22 PM PDT 24 404230578 ps
T116 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1601266849 Jun 28 05:30:26 PM PDT 24 Jun 28 05:30:31 PM PDT 24 143335253 ps
T1049 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1670220038 Jun 28 05:30:11 PM PDT 24 Jun 28 05:30:15 PM PDT 24 42997582 ps
T162 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.974003770 Jun 28 05:29:59 PM PDT 24 Jun 28 05:30:26 PM PDT 24 907412488 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3711576696 Jun 28 05:30:13 PM PDT 24 Jun 28 05:30:17 PM PDT 24 247251347 ps
T1051 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2193312396 Jun 28 05:30:35 PM PDT 24 Jun 28 05:30:37 PM PDT 24 38859862 ps
T1052 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3218225788 Jun 28 05:30:27 PM PDT 24 Jun 28 05:30:32 PM PDT 24 453858239 ps
T1053 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2926411674 Jun 28 05:30:24 PM PDT 24 Jun 28 05:30:27 PM PDT 24 143422264 ps
T1054 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.322208775 Jun 28 05:30:48 PM PDT 24 Jun 28 05:30:50 PM PDT 24 13282211 ps
T1055 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1772487772 Jun 28 05:30:27 PM PDT 24 Jun 28 05:30:33 PM PDT 24 1679229828 ps
T165 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2119806107 Jun 28 05:30:24 PM PDT 24 Jun 28 05:30:38 PM PDT 24 2199782058 ps
T1056 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2490379942 Jun 28 05:30:12 PM PDT 24 Jun 28 05:30:38 PM PDT 24 3160643690 ps
T164 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2007998867 Jun 28 05:30:13 PM PDT 24 Jun 28 05:30:40 PM PDT 24 3841253732 ps
T166 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2352153564 Jun 28 05:30:34 PM PDT 24 Jun 28 05:30:44 PM PDT 24 3722951196 ps
T1057 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3374296734 Jun 28 05:30:45 PM PDT 24 Jun 28 05:30:47 PM PDT 24 13367385 ps
T1058 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.538326041 Jun 28 05:30:39 PM PDT 24 Jun 28 05:30:43 PM PDT 24 260819977 ps
T1059 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3859528346 Jun 28 05:30:25 PM PDT 24 Jun 28 05:30:31 PM PDT 24 242633838 ps
T1060 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2930062105 Jun 28 05:30:35 PM PDT 24 Jun 28 05:30:38 PM PDT 24 175060011 ps
T1061 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2000719932 Jun 28 05:30:26 PM PDT 24 Jun 28 05:30:31 PM PDT 24 94041405 ps
T1062 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3372732185 Jun 28 05:30:12 PM PDT 24 Jun 28 05:30:15 PM PDT 24 110681673 ps
T117 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.641966615 Jun 28 05:30:13 PM PDT 24 Jun 28 05:30:16 PM PDT 24 100314669 ps
T115 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.668468089 Jun 28 05:30:11 PM PDT 24 Jun 28 05:30:18 PM PDT 24 375776187 ps
T1063 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.885948253 Jun 28 05:30:25 PM PDT 24 Jun 28 05:30:27 PM PDT 24 16448248 ps
T1064 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3283566259 Jun 28 05:30:47 PM PDT 24 Jun 28 05:30:49 PM PDT 24 17345661 ps
T1065 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3186554175 Jun 28 05:30:39 PM PDT 24 Jun 28 05:30:42 PM PDT 24 57897751 ps
T1066 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3031340190 Jun 28 05:29:53 PM PDT 24 Jun 28 05:29:56 PM PDT 24 108659163 ps
T1067 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3748105990 Jun 28 05:30:39 PM PDT 24 Jun 28 05:30:43 PM PDT 24 52185180 ps
T1068 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1295728181 Jun 28 05:30:43 PM PDT 24 Jun 28 05:30:45 PM PDT 24 180889283 ps
T167 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3876196187 Jun 28 05:30:34 PM PDT 24 Jun 28 05:30:50 PM PDT 24 2172212867 ps
T120 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.67203433 Jun 28 05:30:40 PM PDT 24 Jun 28 05:30:44 PM PDT 24 91469999 ps
T118 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.769078781 Jun 28 05:30:24 PM PDT 24 Jun 28 05:30:28 PM PDT 24 65366177 ps
T1069 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2770714712 Jun 28 05:30:47 PM PDT 24 Jun 28 05:30:49 PM PDT 24 14233658 ps
T1070 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4292042965 Jun 28 05:30:38 PM PDT 24 Jun 28 05:30:41 PM PDT 24 10861579 ps
T1071 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3876691120 Jun 28 05:30:49 PM PDT 24 Jun 28 05:30:51 PM PDT 24 59597593 ps
T1072 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3424580463 Jun 28 05:30:12 PM PDT 24 Jun 28 05:30:14 PM PDT 24 16770422 ps
T1073 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3240895275 Jun 28 05:29:52 PM PDT 24 Jun 28 05:29:53 PM PDT 24 19839537 ps
T1074 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3414694792 Jun 28 05:30:26 PM PDT 24 Jun 28 05:30:48 PM PDT 24 521701049 ps
T1075 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2329226409 Jun 28 05:30:24 PM PDT 24 Jun 28 05:30:28 PM PDT 24 53065348 ps
T1076 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.917876451 Jun 28 05:30:34 PM PDT 24 Jun 28 05:30:36 PM PDT 24 25728019 ps
T1077 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3456336033 Jun 28 05:30:35 PM PDT 24 Jun 28 05:30:38 PM PDT 24 67078785 ps
T1078 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2715305194 Jun 28 05:30:11 PM PDT 24 Jun 28 05:30:13 PM PDT 24 27411176 ps
T1079 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.320945070 Jun 28 05:30:44 PM PDT 24 Jun 28 05:30:46 PM PDT 24 60540802 ps
T1080 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2114226023 Jun 28 05:30:24 PM PDT 24 Jun 28 05:30:27 PM PDT 24 48217624 ps
T1081 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3543762606 Jun 28 05:30:47 PM PDT 24 Jun 28 05:30:49 PM PDT 24 16395195 ps
T1082 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.730736027 Jun 28 05:30:38 PM PDT 24 Jun 28 05:30:54 PM PDT 24 573213751 ps
T1083 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1556238291 Jun 28 05:30:36 PM PDT 24 Jun 28 05:30:41 PM PDT 24 278140458 ps
T1084 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1951596424 Jun 28 05:30:39 PM PDT 24 Jun 28 05:30:42 PM PDT 24 41612325 ps
T1085 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4267776943 Jun 28 05:30:26 PM PDT 24 Jun 28 05:30:29 PM PDT 24 66179672 ps
T1086 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.469366726 Jun 28 05:30:01 PM PDT 24 Jun 28 05:30:16 PM PDT 24 931797146 ps
T119 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1655214348 Jun 28 05:30:27 PM PDT 24 Jun 28 05:30:32 PM PDT 24 245702022 ps
T121 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1948312449 Jun 28 05:30:11 PM PDT 24 Jun 28 05:30:15 PM PDT 24 93454120 ps
T1087 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1262989442 Jun 28 05:29:58 PM PDT 24 Jun 28 05:30:01 PM PDT 24 49949416 ps
T1088 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1063152970 Jun 28 05:30:27 PM PDT 24 Jun 28 05:30:31 PM PDT 24 106354152 ps
T1089 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2537185454 Jun 28 05:30:37 PM PDT 24 Jun 28 05:30:40 PM PDT 24 15883906 ps
T1090 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3499967435 Jun 28 05:30:52 PM PDT 24 Jun 28 05:30:53 PM PDT 24 53856523 ps
T1091 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4011677324 Jun 28 05:30:35 PM PDT 24 Jun 28 05:30:40 PM PDT 24 827239443 ps
T1092 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3699414271 Jun 28 05:30:48 PM PDT 24 Jun 28 05:30:50 PM PDT 24 50281972 ps
T1093 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2983034776 Jun 28 05:30:13 PM PDT 24 Jun 28 05:30:15 PM PDT 24 40110887 ps
T1094 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.343585977 Jun 28 05:30:46 PM PDT 24 Jun 28 05:30:48 PM PDT 24 27438550 ps
T1095 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.633784928 Jun 28 05:30:26 PM PDT 24 Jun 28 05:30:37 PM PDT 24 278226617 ps
T1096 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1455118702 Jun 28 05:30:35 PM PDT 24 Jun 28 05:30:39 PM PDT 24 43681715 ps
T1097 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.446320248 Jun 28 05:30:01 PM PDT 24 Jun 28 05:30:03 PM PDT 24 52928140 ps
T1098 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1684884011 Jun 28 05:30:00 PM PDT 24 Jun 28 05:30:01 PM PDT 24 17090062 ps
T1099 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2673006233 Jun 28 05:30:46 PM PDT 24 Jun 28 05:30:48 PM PDT 24 20017232 ps
T1100 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3148144919 Jun 28 05:30:45 PM PDT 24 Jun 28 05:30:47 PM PDT 24 25623912 ps
T1101 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3104599653 Jun 28 05:30:46 PM PDT 24 Jun 28 05:30:48 PM PDT 24 19974093 ps
T1102 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1189481021 Jun 28 05:29:53 PM PDT 24 Jun 28 05:29:56 PM PDT 24 87937732 ps
T1103 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3608940327 Jun 28 05:30:26 PM PDT 24 Jun 28 05:30:31 PM PDT 24 107548242 ps
T1104 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1730263262 Jun 28 05:30:25 PM PDT 24 Jun 28 05:30:30 PM PDT 24 460336554 ps
T1105 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2033514111 Jun 28 05:30:24 PM PDT 24 Jun 28 05:30:32 PM PDT 24 266922267 ps
T1106 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.146937585 Jun 28 05:29:59 PM PDT 24 Jun 28 05:30:02 PM PDT 24 44741320 ps
T1107 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2848404746 Jun 28 05:30:35 PM PDT 24 Jun 28 05:30:41 PM PDT 24 160210071 ps
T1108 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.71091250 Jun 28 05:30:38 PM PDT 24 Jun 28 05:30:44 PM PDT 24 330266050 ps
T1109 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2429541187 Jun 28 05:30:39 PM PDT 24 Jun 28 05:30:41 PM PDT 24 16637628 ps
T1110 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2751157199 Jun 28 05:30:38 PM PDT 24 Jun 28 05:30:42 PM PDT 24 99700205 ps
T1111 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2482008129 Jun 28 05:30:38 PM PDT 24 Jun 28 05:31:04 PM PDT 24 4091359663 ps
T1112 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3518427040 Jun 28 05:29:59 PM PDT 24 Jun 28 05:30:04 PM PDT 24 114182109 ps
T1113 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.68537439 Jun 28 05:30:11 PM PDT 24 Jun 28 05:30:25 PM PDT 24 648008642 ps
T1114 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4072570346 Jun 28 05:30:03 PM PDT 24 Jun 28 05:30:06 PM PDT 24 324505788 ps
T1115 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1966306636 Jun 28 05:30:26 PM PDT 24 Jun 28 05:30:35 PM PDT 24 865593328 ps
T1116 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1487892409 Jun 28 05:30:38 PM PDT 24 Jun 28 05:30:41 PM PDT 24 13679204 ps
T1117 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2630527024 Jun 28 05:30:34 PM PDT 24 Jun 28 05:30:38 PM PDT 24 419301255 ps
T1118 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2990758543 Jun 28 05:30:37 PM PDT 24 Jun 28 05:30:39 PM PDT 24 14086395 ps
T1119 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2571810509 Jun 28 05:30:25 PM PDT 24 Jun 28 05:30:28 PM PDT 24 102948698 ps
T1120 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2551271127 Jun 28 05:29:49 PM PDT 24 Jun 28 05:29:51 PM PDT 24 17087458 ps
T1121 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1345681965 Jun 28 05:30:25 PM PDT 24 Jun 28 05:30:29 PM PDT 24 64098017 ps
T95 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2112464590 Jun 28 05:30:10 PM PDT 24 Jun 28 05:30:13 PM PDT 24 177870007 ps
T1122 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3324989030 Jun 28 05:30:35 PM PDT 24 Jun 28 05:30:37 PM PDT 24 31605841 ps
T175 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2802399334 Jun 28 05:30:37 PM PDT 24 Jun 28 05:30:42 PM PDT 24 148255006 ps
T1123 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1517362247 Jun 28 05:30:44 PM PDT 24 Jun 28 05:30:46 PM PDT 24 126566252 ps
T1124 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1277649987 Jun 28 05:29:55 PM PDT 24 Jun 28 05:30:01 PM PDT 24 66940818 ps
T1125 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2295473950 Jun 28 05:30:01 PM PDT 24 Jun 28 05:30:04 PM PDT 24 108556005 ps
T1126 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1460265357 Jun 28 05:30:00 PM PDT 24 Jun 28 05:30:01 PM PDT 24 153121797 ps
T1127 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.183303961 Jun 28 05:30:15 PM PDT 24 Jun 28 05:30:16 PM PDT 24 16527832 ps
T1128 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1989484572 Jun 28 05:30:24 PM PDT 24 Jun 28 05:30:30 PM PDT 24 106076199 ps
T1129 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.499146827 Jun 28 05:30:25 PM PDT 24 Jun 28 05:30:30 PM PDT 24 151780869 ps

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.19415462
Short name T9
Test name
Test status
Simulation time 141552588297 ps
CPU time 136.9 seconds
Started Jun 28 05:34:04 PM PDT 24
Finished Jun 28 05:36:22 PM PDT 24
Peak memory 255204 kb
Host smart-f225fe41-da61-44ba-a27e-712cf7a9b05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19415462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.19415462
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2235677056
Short name T14
Test name
Test status
Simulation time 399431355092 ps
CPU time 534.23 seconds
Started Jun 28 05:34:10 PM PDT 24
Finished Jun 28 05:43:05 PM PDT 24
Peak memory 274148 kb
Host smart-8d9ac90b-8d53-4313-80f1-43fefedaf411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235677056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2235677056
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4200952156
Short name T39
Test name
Test status
Simulation time 326757741450 ps
CPU time 264.3 seconds
Started Jun 28 05:34:20 PM PDT 24
Finished Jun 28 05:38:45 PM PDT 24
Peak memory 269436 kb
Host smart-65c26012-91dc-4595-b336-2f7e41d71165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200952156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4200952156
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3326297718
Short name T122
Test name
Test status
Simulation time 635210412 ps
CPU time 15.21 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:41 PM PDT 24
Peak memory 216700 kb
Host smart-b83c723c-af4a-49cd-a670-63ed19672786
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326297718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3326297718
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1796097343
Short name T15
Test name
Test status
Simulation time 45648344428 ps
CPU time 237.36 seconds
Started Jun 28 05:35:42 PM PDT 24
Finished Jun 28 05:39:40 PM PDT 24
Peak memory 299332 kb
Host smart-0ac1ffb7-7f84-43d2-8f46-69cea13a8424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796097343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1796097343
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1340093285
Short name T78
Test name
Test status
Simulation time 15533355 ps
CPU time 0.76 seconds
Started Jun 28 05:31:33 PM PDT 24
Finished Jun 28 05:31:34 PM PDT 24
Peak memory 216548 kb
Host smart-2f38fbd1-c402-48a1-afc6-2962983caf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340093285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1340093285
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2564416112
Short name T17
Test name
Test status
Simulation time 249754175261 ps
CPU time 622.35 seconds
Started Jun 28 05:35:03 PM PDT 24
Finished Jun 28 05:45:28 PM PDT 24
Peak memory 266148 kb
Host smart-bcabf36a-6e13-4fd2-8f36-5a8f2ea1eab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564416112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2564416112
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2248850088
Short name T184
Test name
Test status
Simulation time 991698604852 ps
CPU time 733.68 seconds
Started Jun 28 05:31:41 PM PDT 24
Finished Jun 28 05:43:55 PM PDT 24
Peak memory 274392 kb
Host smart-81ba8e3f-1e01-4a7b-89c1-91cb87c530ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248850088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2248850088
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.595574278
Short name T77
Test name
Test status
Simulation time 435844260271 ps
CPU time 750.16 seconds
Started Jun 28 05:34:47 PM PDT 24
Finished Jun 28 05:47:19 PM PDT 24
Peak memory 274208 kb
Host smart-19bad7f7-cbf0-4eae-8992-c61f986981d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595574278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.595574278
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.541282041
Short name T109
Test name
Test status
Simulation time 163154002 ps
CPU time 3.87 seconds
Started Jun 28 05:30:38 PM PDT 24
Finished Jun 28 05:30:43 PM PDT 24
Peak memory 215580 kb
Host smart-43e493b8-ed9a-40bd-ba46-64859072f6c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541282041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.541282041
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.4088985930
Short name T46
Test name
Test status
Simulation time 1474625387 ps
CPU time 8.88 seconds
Started Jun 28 05:34:36 PM PDT 24
Finished Jun 28 05:34:45 PM PDT 24
Peak memory 224996 kb
Host smart-c29e8405-e7b9-4662-b233-443abeef7b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088985930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.4088985930
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.491929666
Short name T10
Test name
Test status
Simulation time 22249683 ps
CPU time 0.76 seconds
Started Jun 28 05:32:56 PM PDT 24
Finished Jun 28 05:32:59 PM PDT 24
Peak memory 205960 kb
Host smart-72d1b266-5c39-4aad-8833-3654b8d6a80b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491929666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.491929666
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.155924291
Short name T154
Test name
Test status
Simulation time 36113091855 ps
CPU time 450.88 seconds
Started Jun 28 05:34:31 PM PDT 24
Finished Jun 28 05:42:03 PM PDT 24
Peak memory 289684 kb
Host smart-1ad21c73-8442-4dea-92d1-70234d0dc74d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155924291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.155924291
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2981357551
Short name T52
Test name
Test status
Simulation time 71944373570 ps
CPU time 399.64 seconds
Started Jun 28 05:34:08 PM PDT 24
Finished Jun 28 05:40:48 PM PDT 24
Peak memory 269488 kb
Host smart-5b968161-4ca5-4144-96d8-2d65e5c95ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981357551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2981357551
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2899539057
Short name T253
Test name
Test status
Simulation time 146117948536 ps
CPU time 681.36 seconds
Started Jun 28 05:34:08 PM PDT 24
Finished Jun 28 05:45:30 PM PDT 24
Peak memory 274012 kb
Host smart-2116aec0-3661-46eb-ab10-a8fb6c8bec64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899539057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2899539057
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4093157422
Short name T94
Test name
Test status
Simulation time 66882179 ps
CPU time 1.23 seconds
Started Jun 28 05:29:51 PM PDT 24
Finished Jun 28 05:29:53 PM PDT 24
Peak memory 207212 kb
Host smart-7fcd7782-92d2-4efb-8d83-bb33a46a8830
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093157422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4093157422
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3512733679
Short name T96
Test name
Test status
Simulation time 11016291491 ps
CPU time 180.47 seconds
Started Jun 28 05:35:26 PM PDT 24
Finished Jun 28 05:38:27 PM PDT 24
Peak memory 262112 kb
Host smart-8dc5b3b6-514a-49aa-a089-e98bbf628e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512733679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3512733679
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3839212655
Short name T25
Test name
Test status
Simulation time 189395730485 ps
CPU time 401.94 seconds
Started Jun 28 05:34:21 PM PDT 24
Finished Jun 28 05:41:04 PM PDT 24
Peak memory 250040 kb
Host smart-f2e2d4ed-0c16-4529-9d39-956d1dd93fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839212655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3839212655
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3769759045
Short name T235
Test name
Test status
Simulation time 74918055672 ps
CPU time 546.93 seconds
Started Jun 28 05:32:10 PM PDT 24
Finished Jun 28 05:41:18 PM PDT 24
Peak memory 265908 kb
Host smart-17387266-463d-4fa1-8c00-905f56c7cf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769759045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3769759045
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.34404143
Short name T260
Test name
Test status
Simulation time 217694039230 ps
CPU time 360.54 seconds
Started Jun 28 05:33:08 PM PDT 24
Finished Jun 28 05:39:10 PM PDT 24
Peak memory 266116 kb
Host smart-98f2e7be-23da-4c5f-a09a-4018c1279a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34404143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.34404143
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1574157219
Short name T193
Test name
Test status
Simulation time 107076324311 ps
CPU time 776.81 seconds
Started Jun 28 05:35:02 PM PDT 24
Finished Jun 28 05:47:59 PM PDT 24
Peak memory 266344 kb
Host smart-2a10b183-a943-4aba-ac08-b0dd390da90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574157219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1574157219
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.348474141
Short name T80
Test name
Test status
Simulation time 174316433 ps
CPU time 1.23 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:31:37 PM PDT 24
Peak memory 237440 kb
Host smart-a95b01a4-d730-473c-be37-4a2cd5dd3a3a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348474141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.348474141
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1956428894
Short name T492
Test name
Test status
Simulation time 6390301885 ps
CPU time 131.84 seconds
Started Jun 28 05:35:16 PM PDT 24
Finished Jun 28 05:37:29 PM PDT 24
Peak memory 258056 kb
Host smart-9f1e3ae2-2663-4fc6-8f9e-b3753dffc242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956428894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1956428894
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.298358556
Short name T32
Test name
Test status
Simulation time 8084895575 ps
CPU time 82.3 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:33:58 PM PDT 24
Peak memory 257608 kb
Host smart-2518321e-7fad-4c4e-b6e9-088a7407d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298358556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.298358556
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.974003770
Short name T162
Test name
Test status
Simulation time 907412488 ps
CPU time 25.96 seconds
Started Jun 28 05:29:59 PM PDT 24
Finished Jun 28 05:30:26 PM PDT 24
Peak memory 215352 kb
Host smart-f9c023c9-c54f-4613-bbea-753149fa5af3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974003770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.974003770
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.799084313
Short name T61
Test name
Test status
Simulation time 15134700834 ps
CPU time 198.76 seconds
Started Jun 28 05:35:16 PM PDT 24
Finished Jun 28 05:38:36 PM PDT 24
Peak memory 266252 kb
Host smart-caa7e2ee-bf9c-40a8-ae8a-770a24f988c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799084313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.799084313
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4221294501
Short name T266
Test name
Test status
Simulation time 40975915518 ps
CPU time 257.25 seconds
Started Jun 28 05:33:26 PM PDT 24
Finished Jun 28 05:37:45 PM PDT 24
Peak memory 273624 kb
Host smart-42515f15-a2dc-4020-bb36-31719379fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221294501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4221294501
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1987337113
Short name T261
Test name
Test status
Simulation time 8728941317 ps
CPU time 56.64 seconds
Started Jun 28 05:34:08 PM PDT 24
Finished Jun 28 05:35:06 PM PDT 24
Peak memory 241480 kb
Host smart-bb6ad3b0-7a3b-43ce-b148-bc3db427f6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987337113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1987337113
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3723344958
Short name T259
Test name
Test status
Simulation time 49284692646 ps
CPU time 363.07 seconds
Started Jun 28 05:35:28 PM PDT 24
Finished Jun 28 05:41:33 PM PDT 24
Peak memory 266092 kb
Host smart-79881283-5276-4a2b-afbb-b172f4318e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723344958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3723344958
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3278672794
Short name T22
Test name
Test status
Simulation time 22591534952 ps
CPU time 126.57 seconds
Started Jun 28 05:32:34 PM PDT 24
Finished Jun 28 05:34:42 PM PDT 24
Peak memory 271224 kb
Host smart-cbeb0fdd-d4b3-4e0f-8e16-3b073438c481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278672794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3278672794
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1138984694
Short name T269
Test name
Test status
Simulation time 19430294619 ps
CPU time 101.74 seconds
Started Jun 28 05:31:39 PM PDT 24
Finished Jun 28 05:33:22 PM PDT 24
Peak memory 251912 kb
Host smart-37e84100-4f39-4fe7-b094-6aec5d8fe876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138984694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1138984694
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.668468089
Short name T115
Test name
Test status
Simulation time 375776187 ps
CPU time 5.35 seconds
Started Jun 28 05:30:11 PM PDT 24
Finished Jun 28 05:30:18 PM PDT 24
Peak memory 215552 kb
Host smart-2472de8d-db8d-493d-9b15-8a42b51faf28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668468089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.668468089
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4176637510
Short name T149
Test name
Test status
Simulation time 3821970919 ps
CPU time 48.26 seconds
Started Jun 28 05:32:43 PM PDT 24
Finished Jun 28 05:33:32 PM PDT 24
Peak memory 233324 kb
Host smart-761cca77-9498-4488-8c89-c982b812bc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176637510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4176637510
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.4024690681
Short name T864
Test name
Test status
Simulation time 46161610115 ps
CPU time 229.67 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:35:25 PM PDT 24
Peak memory 265864 kb
Host smart-0d8fe59c-d8aa-481f-bb6b-67e1915340db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024690681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.4024690681
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1237302772
Short name T1
Test name
Test status
Simulation time 7554438275 ps
CPU time 95.28 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:34:10 PM PDT 24
Peak memory 261656 kb
Host smart-1db6a650-de65-4fbd-a459-6c82aa9ec7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237302772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1237302772
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3721266411
Short name T274
Test name
Test status
Simulation time 1703633023 ps
CPU time 36.37 seconds
Started Jun 28 05:33:23 PM PDT 24
Finished Jun 28 05:34:00 PM PDT 24
Peak memory 225560 kb
Host smart-fa4a2d28-008b-4e15-90a1-4ef892b1194e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721266411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3721266411
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1271904615
Short name T51
Test name
Test status
Simulation time 50359830920 ps
CPU time 206.87 seconds
Started Jun 28 05:31:38 PM PDT 24
Finished Jun 28 05:35:06 PM PDT 24
Peak memory 256800 kb
Host smart-02b0c3e9-5c96-4dad-8c7b-148d580e804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271904615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1271904615
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.436596899
Short name T48
Test name
Test status
Simulation time 13970517504 ps
CPU time 12.61 seconds
Started Jun 28 05:31:47 PM PDT 24
Finished Jun 28 05:32:01 PM PDT 24
Peak memory 233288 kb
Host smart-93bc45bd-12a0-4d3f-9699-6ba49989d7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436596899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
436596899
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2802399334
Short name T175
Test name
Test status
Simulation time 148255006 ps
CPU time 3.82 seconds
Started Jun 28 05:30:37 PM PDT 24
Finished Jun 28 05:30:42 PM PDT 24
Peak memory 215632 kb
Host smart-9904a99a-4dce-459c-9e46-0774ffdcecee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802399334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2802399334
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2064294951
Short name T104
Test name
Test status
Simulation time 4751531281 ps
CPU time 16.87 seconds
Started Jun 28 05:29:55 PM PDT 24
Finished Jun 28 05:30:13 PM PDT 24
Peak memory 216204 kb
Host smart-e3ce55be-9579-4271-b1cd-ccb6167f3b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064294951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2064294951
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2352153564
Short name T166
Test name
Test status
Simulation time 3722951196 ps
CPU time 8.92 seconds
Started Jun 28 05:30:34 PM PDT 24
Finished Jun 28 05:30:44 PM PDT 24
Peak memory 215364 kb
Host smart-55d7b58d-bf31-40ba-a28c-ccdd4a1d008e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352153564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2352153564
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1284093664
Short name T217
Test name
Test status
Simulation time 15685716829 ps
CPU time 125.14 seconds
Started Jun 28 05:32:50 PM PDT 24
Finished Jun 28 05:34:56 PM PDT 24
Peak memory 250156 kb
Host smart-d5f553cb-01e6-403f-be13-3b6849bac195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284093664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1284093664
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.4207963989
Short name T840
Test name
Test status
Simulation time 28950925859 ps
CPU time 218.97 seconds
Started Jun 28 05:32:57 PM PDT 24
Finished Jun 28 05:36:38 PM PDT 24
Peak memory 267168 kb
Host smart-0b934210-c6b1-4352-ab02-8d251c9c87fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207963989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.4207963989
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2585926957
Short name T84
Test name
Test status
Simulation time 2110903452 ps
CPU time 37.57 seconds
Started Jun 28 05:34:47 PM PDT 24
Finished Jun 28 05:35:27 PM PDT 24
Peak memory 241536 kb
Host smart-8f870973-5d91-4783-8d72-185221c8b0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585926957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2585926957
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1277649987
Short name T1124
Test name
Test status
Simulation time 66940818 ps
CPU time 4.64 seconds
Started Jun 28 05:29:55 PM PDT 24
Finished Jun 28 05:30:01 PM PDT 24
Peak memory 215636 kb
Host smart-0b3932a6-1d3b-4738-b549-072c55a1a234
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277649987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
277649987
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2112464590
Short name T95
Test name
Test status
Simulation time 177870007 ps
CPU time 1.39 seconds
Started Jun 28 05:30:10 PM PDT 24
Finished Jun 28 05:30:13 PM PDT 24
Peak memory 207144 kb
Host smart-719399d9-e998-444a-8df8-59ee24d73afe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112464590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2112464590
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.868983842
Short name T43
Test name
Test status
Simulation time 60088110495 ps
CPU time 217.22 seconds
Started Jun 28 05:34:59 PM PDT 24
Finished Jun 28 05:38:38 PM PDT 24
Peak memory 251468 kb
Host smart-fd2915cf-366e-4ae4-a3a4-9d55a1979764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868983842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.868983842
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3020453455
Short name T134
Test name
Test status
Simulation time 1248111592 ps
CPU time 15.75 seconds
Started Jun 28 05:29:58 PM PDT 24
Finished Jun 28 05:30:15 PM PDT 24
Peak memory 215396 kb
Host smart-9c747d57-c22c-4971-8c7c-4b2e23b8a6c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020453455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3020453455
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2919132981
Short name T152
Test name
Test status
Simulation time 19486855821 ps
CPU time 24.14 seconds
Started Jun 28 05:29:48 PM PDT 24
Finished Jun 28 05:30:13 PM PDT 24
Peak memory 207164 kb
Host smart-a8186abe-1e2f-4197-80ae-1be8167bec70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919132981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2919132981
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1262989442
Short name T1087
Test name
Test status
Simulation time 49949416 ps
CPU time 1.8 seconds
Started Jun 28 05:29:58 PM PDT 24
Finished Jun 28 05:30:01 PM PDT 24
Peak memory 216660 kb
Host smart-0639901a-e282-4be4-8d73-41dafdecb89d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262989442 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1262989442
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3031340190
Short name T1066
Test name
Test status
Simulation time 108659163 ps
CPU time 1.81 seconds
Started Jun 28 05:29:53 PM PDT 24
Finished Jun 28 05:29:56 PM PDT 24
Peak memory 215392 kb
Host smart-bb1b94d5-84ac-4082-a0ea-891bb7d3b8e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031340190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
031340190
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3240895275
Short name T1073
Test name
Test status
Simulation time 19839537 ps
CPU time 0.72 seconds
Started Jun 28 05:29:52 PM PDT 24
Finished Jun 28 05:29:53 PM PDT 24
Peak memory 203852 kb
Host smart-993d79e6-1168-4de0-8bec-0c92eec10ba4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240895275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
240895275
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1189481021
Short name T1102
Test name
Test status
Simulation time 87937732 ps
CPU time 1.79 seconds
Started Jun 28 05:29:53 PM PDT 24
Finished Jun 28 05:29:56 PM PDT 24
Peak memory 215292 kb
Host smart-8d97cbd8-3eb0-4bfe-868a-86150b496476
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189481021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1189481021
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2551271127
Short name T1120
Test name
Test status
Simulation time 17087458 ps
CPU time 0.66 seconds
Started Jun 28 05:29:49 PM PDT 24
Finished Jun 28 05:29:51 PM PDT 24
Peak memory 203724 kb
Host smart-6b340716-f937-45fd-b061-a33b24e5ba0c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551271127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2551271127
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.446320248
Short name T1097
Test name
Test status
Simulation time 52928140 ps
CPU time 1.68 seconds
Started Jun 28 05:30:01 PM PDT 24
Finished Jun 28 05:30:03 PM PDT 24
Peak memory 207084 kb
Host smart-4300c0e2-394c-4784-9c83-7484625d645c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446320248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.446320248
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3049599346
Short name T1029
Test name
Test status
Simulation time 480280750 ps
CPU time 8.61 seconds
Started Jun 28 05:29:59 PM PDT 24
Finished Jun 28 05:30:08 PM PDT 24
Peak memory 215392 kb
Host smart-f0c3310b-0bd1-4c55-9ff3-1261b2814317
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049599346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3049599346
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.469366726
Short name T1086
Test name
Test status
Simulation time 931797146 ps
CPU time 14.11 seconds
Started Jun 28 05:30:01 PM PDT 24
Finished Jun 28 05:30:16 PM PDT 24
Peak memory 207188 kb
Host smart-8098987e-46ee-46a6-823c-95bd31b8b7a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469366726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.469366726
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2734782880
Short name T1037
Test name
Test status
Simulation time 73980821 ps
CPU time 0.95 seconds
Started Jun 28 05:30:00 PM PDT 24
Finished Jun 28 05:30:01 PM PDT 24
Peak memory 206924 kb
Host smart-7c844c1e-bb62-4642-a8d2-29581daa7e0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734782880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2734782880
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.146937585
Short name T1106
Test name
Test status
Simulation time 44741320 ps
CPU time 1.6 seconds
Started Jun 28 05:29:59 PM PDT 24
Finished Jun 28 05:30:02 PM PDT 24
Peak memory 215476 kb
Host smart-a011c019-2469-428d-8271-5a1b3edbc982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146937585 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.146937585
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3889180312
Short name T142
Test name
Test status
Simulation time 229583965 ps
CPU time 2.86 seconds
Started Jun 28 05:29:59 PM PDT 24
Finished Jun 28 05:30:03 PM PDT 24
Peak memory 215192 kb
Host smart-df264a02-345c-48e0-98e8-72861827a6be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889180312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
889180312
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1684884011
Short name T1098
Test name
Test status
Simulation time 17090062 ps
CPU time 0.72 seconds
Started Jun 28 05:30:00 PM PDT 24
Finished Jun 28 05:30:01 PM PDT 24
Peak memory 203848 kb
Host smart-e53e959a-ecef-4f4b-8e6c-6c410b9dd852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684884011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
684884011
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3713067057
Short name T126
Test name
Test status
Simulation time 53500484 ps
CPU time 1.95 seconds
Started Jun 28 05:29:59 PM PDT 24
Finished Jun 28 05:30:02 PM PDT 24
Peak memory 215388 kb
Host smart-dcb8fb77-275e-4040-9e6c-07067b764cd1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713067057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3713067057
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2676242579
Short name T1041
Test name
Test status
Simulation time 11248469 ps
CPU time 0.75 seconds
Started Jun 28 05:30:00 PM PDT 24
Finished Jun 28 05:30:01 PM PDT 24
Peak memory 203728 kb
Host smart-562c98cb-2972-4390-9b6e-8166b27c4f87
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676242579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2676242579
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2295473950
Short name T1125
Test name
Test status
Simulation time 108556005 ps
CPU time 3.15 seconds
Started Jun 28 05:30:01 PM PDT 24
Finished Jun 28 05:30:04 PM PDT 24
Peak memory 215392 kb
Host smart-501ecf9d-2279-4b53-af72-f64c7dbaffb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295473950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2295473950
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3518427040
Short name T1112
Test name
Test status
Simulation time 114182109 ps
CPU time 3.66 seconds
Started Jun 28 05:29:59 PM PDT 24
Finished Jun 28 05:30:04 PM PDT 24
Peak memory 215616 kb
Host smart-ec7f5ad9-9dd8-430a-ba66-564b17276f57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518427040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
518427040
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2321027641
Short name T74
Test name
Test status
Simulation time 338020317 ps
CPU time 8.86 seconds
Started Jun 28 05:29:59 PM PDT 24
Finished Jun 28 05:30:08 PM PDT 24
Peak memory 215896 kb
Host smart-a1566caa-ab9c-4cc2-8346-697c3cb6aeaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321027641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2321027641
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1063152970
Short name T1088
Test name
Test status
Simulation time 106354152 ps
CPU time 1.61 seconds
Started Jun 28 05:30:27 PM PDT 24
Finished Jun 28 05:30:31 PM PDT 24
Peak memory 215444 kb
Host smart-424221d8-e537-4cb8-9520-2bad4bafa499
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063152970 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1063152970
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2574096595
Short name T130
Test name
Test status
Simulation time 93606007 ps
CPU time 2.42 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:28 PM PDT 24
Peak memory 215268 kb
Host smart-3dcb3b96-375f-44f8-8689-8e5ed1187558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574096595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2574096595
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.885948253
Short name T1063
Test name
Test status
Simulation time 16448248 ps
CPU time 0.71 seconds
Started Jun 28 05:30:25 PM PDT 24
Finished Jun 28 05:30:27 PM PDT 24
Peak memory 204044 kb
Host smart-2361a2e6-3096-47d7-8bb2-4558ac82a71c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885948253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.885948253
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1772487772
Short name T1055
Test name
Test status
Simulation time 1679229828 ps
CPU time 3.97 seconds
Started Jun 28 05:30:27 PM PDT 24
Finished Jun 28 05:30:33 PM PDT 24
Peak memory 215400 kb
Host smart-cf3dfcb1-8257-4f20-8ec1-9b260eaefb1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772487772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1772487772
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4270162222
Short name T105
Test name
Test status
Simulation time 26055765 ps
CPU time 1.49 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:27 PM PDT 24
Peak memory 215556 kb
Host smart-8493a08d-a139-4bd0-aa6e-86211fee6290
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270162222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4270162222
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2571810509
Short name T1119
Test name
Test status
Simulation time 102948698 ps
CPU time 1.87 seconds
Started Jun 28 05:30:25 PM PDT 24
Finished Jun 28 05:30:28 PM PDT 24
Peak memory 216408 kb
Host smart-101ae0dc-e6ed-482e-9d30-edf1553aa47f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571810509 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2571810509
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1362350347
Short name T1032
Test name
Test status
Simulation time 75866272 ps
CPU time 1.99 seconds
Started Jun 28 05:30:27 PM PDT 24
Finished Jun 28 05:30:31 PM PDT 24
Peak memory 215324 kb
Host smart-4a267478-e31a-42e0-89db-c316819f55c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362350347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1362350347
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1561346524
Short name T1014
Test name
Test status
Simulation time 33651775 ps
CPU time 0.73 seconds
Started Jun 28 05:30:26 PM PDT 24
Finished Jun 28 05:30:28 PM PDT 24
Peak memory 203828 kb
Host smart-d41f3cef-6af8-4bf7-87ad-037b8b3629ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561346524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1561346524
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.413150585
Short name T153
Test name
Test status
Simulation time 546822699 ps
CPU time 3.16 seconds
Started Jun 28 05:30:27 PM PDT 24
Finished Jun 28 05:30:32 PM PDT 24
Peak memory 215296 kb
Host smart-33ecf9ff-70b1-4aa0-adfc-4e9f8f6b2d80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413150585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.413150585
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1601266849
Short name T116
Test name
Test status
Simulation time 143335253 ps
CPU time 3.36 seconds
Started Jun 28 05:30:26 PM PDT 24
Finished Jun 28 05:30:31 PM PDT 24
Peak memory 215512 kb
Host smart-4f87c4ba-ca8c-4125-a1f6-84fda241f48d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601266849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1601266849
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.633784928
Short name T1095
Test name
Test status
Simulation time 278226617 ps
CPU time 8.92 seconds
Started Jun 28 05:30:26 PM PDT 24
Finished Jun 28 05:30:37 PM PDT 24
Peak memory 215464 kb
Host smart-a03b6815-6257-455c-87c0-db9bafc590f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633784928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.633784928
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.51169023
Short name T106
Test name
Test status
Simulation time 38693742 ps
CPU time 2.77 seconds
Started Jun 28 05:30:36 PM PDT 24
Finished Jun 28 05:30:40 PM PDT 24
Peak memory 216848 kb
Host smart-b4fda5c2-855c-44b2-ad88-04d2eaf2182e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51169023 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.51169023
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2930062105
Short name T1060
Test name
Test status
Simulation time 175060011 ps
CPU time 1.41 seconds
Started Jun 28 05:30:35 PM PDT 24
Finished Jun 28 05:30:38 PM PDT 24
Peak memory 207128 kb
Host smart-c89c55dd-8ff2-4540-8fb7-39a4a4f02fab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930062105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2930062105
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3987359784
Short name T1033
Test name
Test status
Simulation time 16388863 ps
CPU time 0.77 seconds
Started Jun 28 05:30:34 PM PDT 24
Finished Jun 28 05:30:36 PM PDT 24
Peak memory 204160 kb
Host smart-ff463a8b-8dcb-4601-a05b-66f2e7d21864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987359784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3987359784
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2630527024
Short name T1117
Test name
Test status
Simulation time 419301255 ps
CPU time 3.16 seconds
Started Jun 28 05:30:34 PM PDT 24
Finished Jun 28 05:30:38 PM PDT 24
Peak memory 215320 kb
Host smart-9d1cadee-c9f4-4cfe-b86b-d88da11eb432
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630527024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2630527024
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3608940327
Short name T1103
Test name
Test status
Simulation time 107548242 ps
CPU time 3.16 seconds
Started Jun 28 05:30:26 PM PDT 24
Finished Jun 28 05:30:31 PM PDT 24
Peak memory 215516 kb
Host smart-f733a210-cc4a-4d43-905f-c21c12963d93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608940327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3608940327
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3186554175
Short name T1065
Test name
Test status
Simulation time 57897751 ps
CPU time 1.86 seconds
Started Jun 28 05:30:39 PM PDT 24
Finished Jun 28 05:30:42 PM PDT 24
Peak memory 216480 kb
Host smart-b278737f-f429-4c9a-a71c-5adf7de18bd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186554175 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3186554175
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2193312396
Short name T1051
Test name
Test status
Simulation time 38859862 ps
CPU time 1.34 seconds
Started Jun 28 05:30:35 PM PDT 24
Finished Jun 28 05:30:37 PM PDT 24
Peak memory 207144 kb
Host smart-3ae77dd1-5a06-4b49-abd0-9fb837dbdee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193312396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2193312396
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1526893584
Short name T1045
Test name
Test status
Simulation time 18644793 ps
CPU time 0.77 seconds
Started Jun 28 05:30:36 PM PDT 24
Finished Jun 28 05:30:38 PM PDT 24
Peak memory 204176 kb
Host smart-ae78bd05-0246-4083-82c7-0fa3cdd51c01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526893584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1526893584
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3783657375
Short name T1038
Test name
Test status
Simulation time 152685270 ps
CPU time 4.32 seconds
Started Jun 28 05:30:36 PM PDT 24
Finished Jun 28 05:30:42 PM PDT 24
Peak memory 215300 kb
Host smart-9bb837b4-287f-4bd0-8416-423727e5734d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783657375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3783657375
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2848404746
Short name T1107
Test name
Test status
Simulation time 160210071 ps
CPU time 4 seconds
Started Jun 28 05:30:35 PM PDT 24
Finished Jun 28 05:30:41 PM PDT 24
Peak memory 215624 kb
Host smart-b661da4c-1261-4574-9845-2e89e6fe0856
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848404746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2848404746
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.730736027
Short name T1082
Test name
Test status
Simulation time 573213751 ps
CPU time 13.82 seconds
Started Jun 28 05:30:38 PM PDT 24
Finished Jun 28 05:30:54 PM PDT 24
Peak memory 215336 kb
Host smart-e97af602-802f-437e-a55c-c2324ed4a5bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730736027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.730736027
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.538326041
Short name T1058
Test name
Test status
Simulation time 260819977 ps
CPU time 1.73 seconds
Started Jun 28 05:30:39 PM PDT 24
Finished Jun 28 05:30:43 PM PDT 24
Peak memory 215380 kb
Host smart-ae69037c-b8cd-41a0-a05b-8b280c6679a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538326041 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.538326041
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4024446641
Short name T132
Test name
Test status
Simulation time 232198771 ps
CPU time 2.86 seconds
Started Jun 28 05:30:38 PM PDT 24
Finished Jun 28 05:30:42 PM PDT 24
Peak memory 215320 kb
Host smart-e8e69479-84c9-4d5f-975a-08d7efa2e506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024446641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4024446641
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2537185454
Short name T1089
Test name
Test status
Simulation time 15883906 ps
CPU time 0.74 seconds
Started Jun 28 05:30:37 PM PDT 24
Finished Jun 28 05:30:40 PM PDT 24
Peak memory 204164 kb
Host smart-99383efb-4611-49e3-bd62-0297df10f04c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537185454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2537185454
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1455118702
Short name T1096
Test name
Test status
Simulation time 43681715 ps
CPU time 2.94 seconds
Started Jun 28 05:30:35 PM PDT 24
Finished Jun 28 05:30:39 PM PDT 24
Peak memory 215392 kb
Host smart-a3a64095-a9f0-4df1-b669-01472845c3f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455118702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1455118702
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2693238241
Short name T107
Test name
Test status
Simulation time 1866946008 ps
CPU time 5.61 seconds
Started Jun 28 05:30:34 PM PDT 24
Finished Jun 28 05:30:40 PM PDT 24
Peak memory 215628 kb
Host smart-fe18182f-030d-4b4b-b30f-677922564c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693238241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2693238241
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3302879906
Short name T75
Test name
Test status
Simulation time 400244761 ps
CPU time 6.63 seconds
Started Jun 28 05:30:37 PM PDT 24
Finished Jun 28 05:30:46 PM PDT 24
Peak memory 216712 kb
Host smart-0058a716-4b59-4921-a552-ef34b6557c81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302879906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3302879906
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.71091250
Short name T1108
Test name
Test status
Simulation time 330266050 ps
CPU time 3.74 seconds
Started Jun 28 05:30:38 PM PDT 24
Finished Jun 28 05:30:44 PM PDT 24
Peak memory 217508 kb
Host smart-ee9c2510-9b9c-4a00-acf7-5c4a98b70151
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71091250 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.71091250
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3456336033
Short name T1077
Test name
Test status
Simulation time 67078785 ps
CPU time 1.15 seconds
Started Jun 28 05:30:35 PM PDT 24
Finished Jun 28 05:30:38 PM PDT 24
Peak memory 215316 kb
Host smart-4a4a887c-7958-4ed1-9a5c-5a80b43f8810
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456336033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3456336033
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3324989030
Short name T1122
Test name
Test status
Simulation time 31605841 ps
CPU time 0.81 seconds
Started Jun 28 05:30:35 PM PDT 24
Finished Jun 28 05:30:37 PM PDT 24
Peak memory 203844 kb
Host smart-84d3e646-a358-4b96-acd5-b3f33f21709c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324989030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3324989030
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4011677324
Short name T1091
Test name
Test status
Simulation time 827239443 ps
CPU time 3.59 seconds
Started Jun 28 05:30:35 PM PDT 24
Finished Jun 28 05:30:40 PM PDT 24
Peak memory 215380 kb
Host smart-ab3633a5-aa2f-4bd9-87a9-ca0308cfa8de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011677324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4011677324
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.67203433
Short name T120
Test name
Test status
Simulation time 91469999 ps
CPU time 2.69 seconds
Started Jun 28 05:30:40 PM PDT 24
Finished Jun 28 05:30:44 PM PDT 24
Peak memory 215428 kb
Host smart-432eaa40-abfd-4046-9f74-751dc83f791c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67203433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.67203433
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1044189179
Short name T161
Test name
Test status
Simulation time 340741566 ps
CPU time 6.31 seconds
Started Jun 28 05:30:36 PM PDT 24
Finished Jun 28 05:30:44 PM PDT 24
Peak memory 215444 kb
Host smart-20ba7ece-c8d0-4137-9060-5c3835eb0835
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044189179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1044189179
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.917876451
Short name T1076
Test name
Test status
Simulation time 25728019 ps
CPU time 1.96 seconds
Started Jun 28 05:30:34 PM PDT 24
Finished Jun 28 05:30:36 PM PDT 24
Peak memory 216436 kb
Host smart-2443f0de-a2b2-49c1-b686-f4a23d6d2d37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917876451 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.917876451
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3802891304
Short name T129
Test name
Test status
Simulation time 200986379 ps
CPU time 2.54 seconds
Started Jun 28 05:30:35 PM PDT 24
Finished Jun 28 05:30:39 PM PDT 24
Peak memory 215388 kb
Host smart-32eca432-739a-4683-86cc-56361c64ef52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802891304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3802891304
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2429541187
Short name T1109
Test name
Test status
Simulation time 16637628 ps
CPU time 0.74 seconds
Started Jun 28 05:30:39 PM PDT 24
Finished Jun 28 05:30:41 PM PDT 24
Peak memory 203856 kb
Host smart-a5e946d0-4979-48c5-8ad1-b358c9afc2e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429541187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2429541187
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.460636218
Short name T1021
Test name
Test status
Simulation time 68983734 ps
CPU time 1.85 seconds
Started Jun 28 05:30:39 PM PDT 24
Finished Jun 28 05:30:43 PM PDT 24
Peak memory 207028 kb
Host smart-97784df6-de48-4176-a402-2316b1676c43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460636218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.460636218
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.608750557
Short name T111
Test name
Test status
Simulation time 143071653 ps
CPU time 4.37 seconds
Started Jun 28 05:30:34 PM PDT 24
Finished Jun 28 05:30:40 PM PDT 24
Peak memory 215532 kb
Host smart-17515208-9b01-40bc-b9bf-dc735dd5218e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608750557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.608750557
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2482008129
Short name T1111
Test name
Test status
Simulation time 4091359663 ps
CPU time 23.93 seconds
Started Jun 28 05:30:38 PM PDT 24
Finished Jun 28 05:31:04 PM PDT 24
Peak memory 215740 kb
Host smart-110705fa-62eb-4079-b53d-f63e81352816
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482008129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2482008129
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2751157199
Short name T1110
Test name
Test status
Simulation time 99700205 ps
CPU time 1.85 seconds
Started Jun 28 05:30:38 PM PDT 24
Finished Jun 28 05:30:42 PM PDT 24
Peak memory 216352 kb
Host smart-bf7c6b2d-777e-4dc7-b030-fe84ee928697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751157199 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2751157199
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1370042565
Short name T133
Test name
Test status
Simulation time 93312193 ps
CPU time 2.67 seconds
Started Jun 28 05:30:40 PM PDT 24
Finished Jun 28 05:30:44 PM PDT 24
Peak memory 207080 kb
Host smart-8ca21449-dea1-4936-b575-ad7d15c920e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370042565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1370042565
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4292042965
Short name T1070
Test name
Test status
Simulation time 10861579 ps
CPU time 0.69 seconds
Started Jun 28 05:30:38 PM PDT 24
Finished Jun 28 05:30:41 PM PDT 24
Peak memory 204012 kb
Host smart-2c5b4394-f76c-4e62-ac6f-50c62665c752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292042965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
4292042965
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.675777345
Short name T1016
Test name
Test status
Simulation time 230798000 ps
CPU time 4.11 seconds
Started Jun 28 05:30:38 PM PDT 24
Finished Jun 28 05:30:44 PM PDT 24
Peak memory 215180 kb
Host smart-b494b11d-1937-44af-a286-f7dac1f68a39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675777345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.675777345
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3876196187
Short name T167
Test name
Test status
Simulation time 2172212867 ps
CPU time 15.58 seconds
Started Jun 28 05:30:34 PM PDT 24
Finished Jun 28 05:30:50 PM PDT 24
Peak memory 215644 kb
Host smart-635f1841-23ef-4a20-bd8f-9d19ab8888fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876196187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3876196187
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2882110553
Short name T1027
Test name
Test status
Simulation time 43005296 ps
CPU time 1.72 seconds
Started Jun 28 05:30:39 PM PDT 24
Finished Jun 28 05:30:42 PM PDT 24
Peak memory 215500 kb
Host smart-64120687-fcc3-4dfe-9c78-978af72bedfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882110553 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2882110553
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1951596424
Short name T1084
Test name
Test status
Simulation time 41612325 ps
CPU time 1.34 seconds
Started Jun 28 05:30:39 PM PDT 24
Finished Jun 28 05:30:42 PM PDT 24
Peak memory 215244 kb
Host smart-949068c9-f434-4fe4-b87a-f7b9240c540f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951596424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1951596424
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2990758543
Short name T1118
Test name
Test status
Simulation time 14086395 ps
CPU time 0.72 seconds
Started Jun 28 05:30:37 PM PDT 24
Finished Jun 28 05:30:39 PM PDT 24
Peak memory 203880 kb
Host smart-2506700f-c862-4b2d-ba3e-f804533a6762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990758543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2990758543
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1556238291
Short name T1083
Test name
Test status
Simulation time 278140458 ps
CPU time 3.65 seconds
Started Jun 28 05:30:36 PM PDT 24
Finished Jun 28 05:30:41 PM PDT 24
Peak memory 215376 kb
Host smart-3187d134-f010-4a7f-a263-962ffc316fe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556238291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1556238291
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1514813238
Short name T76
Test name
Test status
Simulation time 634710658 ps
CPU time 14.16 seconds
Started Jun 28 05:30:35 PM PDT 24
Finished Jun 28 05:30:50 PM PDT 24
Peak memory 215488 kb
Host smart-f3455b04-0d9c-425a-a8e6-557224ac0cea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514813238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1514813238
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3748105990
Short name T1067
Test name
Test status
Simulation time 52185180 ps
CPU time 1.99 seconds
Started Jun 28 05:30:39 PM PDT 24
Finished Jun 28 05:30:43 PM PDT 24
Peak memory 216280 kb
Host smart-4138da63-8289-4607-8c2e-269487e70466
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748105990 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3748105990
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.516741952
Short name T136
Test name
Test status
Simulation time 35245671 ps
CPU time 2.34 seconds
Started Jun 28 05:30:37 PM PDT 24
Finished Jun 28 05:30:41 PM PDT 24
Peak memory 215600 kb
Host smart-33dbe3df-d71d-46c6-bc34-d0b0fd53c3f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516741952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.516741952
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1487892409
Short name T1116
Test name
Test status
Simulation time 13679204 ps
CPU time 0.73 seconds
Started Jun 28 05:30:38 PM PDT 24
Finished Jun 28 05:30:41 PM PDT 24
Peak memory 203692 kb
Host smart-7a50a3c2-205a-456b-9ce5-ebf88fc18027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487892409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1487892409
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.672123972
Short name T1017
Test name
Test status
Simulation time 512778674 ps
CPU time 2.88 seconds
Started Jun 28 05:30:35 PM PDT 24
Finished Jun 28 05:30:39 PM PDT 24
Peak memory 215328 kb
Host smart-a722df78-1360-46ea-83d7-8391133a7f1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672123972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.672123972
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1507279217
Short name T113
Test name
Test status
Simulation time 52959046 ps
CPU time 1.77 seconds
Started Jun 28 05:30:39 PM PDT 24
Finished Jun 28 05:30:43 PM PDT 24
Peak memory 215416 kb
Host smart-15015a58-d98b-40d7-a69f-a5cfeae7720e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507279217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1507279217
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.350177905
Short name T163
Test name
Test status
Simulation time 3041229831 ps
CPU time 17.24 seconds
Started Jun 28 05:30:35 PM PDT 24
Finished Jun 28 05:30:54 PM PDT 24
Peak memory 215472 kb
Host smart-10fe7d2e-eabf-437d-8509-e23fb699d639
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350177905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.350177905
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1487867575
Short name T1043
Test name
Test status
Simulation time 4962428607 ps
CPU time 25.7 seconds
Started Jun 28 05:30:13 PM PDT 24
Finished Jun 28 05:30:41 PM PDT 24
Peak memory 207168 kb
Host smart-825f0863-9fe8-4222-b8c6-4afa6997c5c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487867575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1487867575
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2490379942
Short name T1056
Test name
Test status
Simulation time 3160643690 ps
CPU time 24.59 seconds
Started Jun 28 05:30:12 PM PDT 24
Finished Jun 28 05:30:38 PM PDT 24
Peak memory 207256 kb
Host smart-9287771a-6b12-4eb9-b8d1-9d8de4d868bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490379942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2490379942
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.783024707
Short name T137
Test name
Test status
Simulation time 56005557 ps
CPU time 1.17 seconds
Started Jun 28 05:30:12 PM PDT 24
Finished Jun 28 05:30:14 PM PDT 24
Peak memory 216332 kb
Host smart-05c795f0-6746-489d-934b-c32c1871f81a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783024707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.783024707
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2715305194
Short name T1078
Test name
Test status
Simulation time 27411176 ps
CPU time 2.04 seconds
Started Jun 28 05:30:11 PM PDT 24
Finished Jun 28 05:30:13 PM PDT 24
Peak memory 216416 kb
Host smart-b0ee0c5a-3be6-412b-a655-92e673ff9d1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715305194 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2715305194
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3372732185
Short name T1062
Test name
Test status
Simulation time 110681673 ps
CPU time 1.99 seconds
Started Jun 28 05:30:12 PM PDT 24
Finished Jun 28 05:30:15 PM PDT 24
Peak memory 215416 kb
Host smart-09b567cb-7ab4-485f-931e-69b437b12933
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372732185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
372732185
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1460265357
Short name T1126
Test name
Test status
Simulation time 153121797 ps
CPU time 0.73 seconds
Started Jun 28 05:30:00 PM PDT 24
Finished Jun 28 05:30:01 PM PDT 24
Peak memory 204276 kb
Host smart-cc1a7fe1-f85c-4135-96fc-13fefdfc87f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460265357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
460265357
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1431334411
Short name T1046
Test name
Test status
Simulation time 49277475 ps
CPU time 1.85 seconds
Started Jun 28 05:30:12 PM PDT 24
Finished Jun 28 05:30:16 PM PDT 24
Peak memory 215392 kb
Host smart-660f7221-e86d-429a-b9bb-e522224a6368
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431334411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1431334411
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2107678730
Short name T1020
Test name
Test status
Simulation time 12930629 ps
CPU time 0.72 seconds
Started Jun 28 05:30:02 PM PDT 24
Finished Jun 28 05:30:04 PM PDT 24
Peak memory 203732 kb
Host smart-dd9db05b-797c-4d7b-b00f-5b14e7e2bcc8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107678730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2107678730
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.117615292
Short name T1034
Test name
Test status
Simulation time 245752471 ps
CPU time 3.07 seconds
Started Jun 28 05:30:13 PM PDT 24
Finished Jun 28 05:30:17 PM PDT 24
Peak memory 215388 kb
Host smart-839a3fd5-39db-444c-a6a6-64978e6beb0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117615292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.117615292
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4072570346
Short name T1114
Test name
Test status
Simulation time 324505788 ps
CPU time 2.14 seconds
Started Jun 28 05:30:03 PM PDT 24
Finished Jun 28 05:30:06 PM PDT 24
Peak memory 215628 kb
Host smart-64af235d-3fbf-47d2-9cc1-944a15c02dba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072570346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
072570346
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2156885155
Short name T1040
Test name
Test status
Simulation time 15236969 ps
CPU time 0.73 seconds
Started Jun 28 05:30:44 PM PDT 24
Finished Jun 28 05:30:46 PM PDT 24
Peak memory 203704 kb
Host smart-22f18682-5b02-4d13-89d7-7c1e5f6c0c4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156885155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2156885155
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1799017327
Short name T1028
Test name
Test status
Simulation time 39480069 ps
CPU time 0.75 seconds
Started Jun 28 05:30:46 PM PDT 24
Finished Jun 28 05:30:48 PM PDT 24
Peak memory 203844 kb
Host smart-67517967-f1dd-48d8-87a7-3fba116a7d7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799017327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1799017327
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3876691120
Short name T1071
Test name
Test status
Simulation time 59597593 ps
CPU time 0.77 seconds
Started Jun 28 05:30:49 PM PDT 24
Finished Jun 28 05:30:51 PM PDT 24
Peak memory 203856 kb
Host smart-94737721-f6c5-4b85-9fea-e70fe47d13c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876691120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3876691120
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3699414271
Short name T1092
Test name
Test status
Simulation time 50281972 ps
CPU time 0.8 seconds
Started Jun 28 05:30:48 PM PDT 24
Finished Jun 28 05:30:50 PM PDT 24
Peak memory 204160 kb
Host smart-363d73b6-f483-41cb-bb7d-3db27658d2ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699414271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3699414271
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2032895367
Short name T1007
Test name
Test status
Simulation time 26256177 ps
CPU time 0.72 seconds
Started Jun 28 05:30:45 PM PDT 24
Finished Jun 28 05:30:46 PM PDT 24
Peak memory 203812 kb
Host smart-428477a6-95ba-4683-8d17-988981c632d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032895367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2032895367
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3283566259
Short name T1064
Test name
Test status
Simulation time 17345661 ps
CPU time 0.77 seconds
Started Jun 28 05:30:47 PM PDT 24
Finished Jun 28 05:30:49 PM PDT 24
Peak memory 203848 kb
Host smart-677887be-2e84-40c6-8cb2-99b8bd734088
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283566259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3283566259
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1834525033
Short name T1008
Test name
Test status
Simulation time 43206425 ps
CPU time 0.72 seconds
Started Jun 28 05:30:45 PM PDT 24
Finished Jun 28 05:30:47 PM PDT 24
Peak memory 204160 kb
Host smart-77b9727e-e469-4ce7-a0db-27acbbb686f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834525033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1834525033
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3543762606
Short name T1081
Test name
Test status
Simulation time 16395195 ps
CPU time 0.73 seconds
Started Jun 28 05:30:47 PM PDT 24
Finished Jun 28 05:30:49 PM PDT 24
Peak memory 203848 kb
Host smart-bd51b6b7-db0d-4162-9e12-35bc1cbcd78c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543762606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3543762606
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.343585977
Short name T1094
Test name
Test status
Simulation time 27438550 ps
CPU time 0.71 seconds
Started Jun 28 05:30:46 PM PDT 24
Finished Jun 28 05:30:48 PM PDT 24
Peak memory 203816 kb
Host smart-73f38f1d-9c2c-4472-bb02-685b81c4445d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343585977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.343585977
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1517362247
Short name T1123
Test name
Test status
Simulation time 126566252 ps
CPU time 0.72 seconds
Started Jun 28 05:30:44 PM PDT 24
Finished Jun 28 05:30:46 PM PDT 24
Peak memory 204156 kb
Host smart-b096acd2-a111-408d-a1bd-6e92eb0bf2ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517362247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1517362247
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1580521367
Short name T1048
Test name
Test status
Simulation time 404230578 ps
CPU time 8.37 seconds
Started Jun 28 05:30:12 PM PDT 24
Finished Jun 28 05:30:22 PM PDT 24
Peak memory 215284 kb
Host smart-7ca05a84-3fd8-4b71-ae7b-8e6ad01eaa6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580521367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1580521367
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1620483557
Short name T1005
Test name
Test status
Simulation time 8175385390 ps
CPU time 34.8 seconds
Started Jun 28 05:30:12 PM PDT 24
Finished Jun 28 05:30:48 PM PDT 24
Peak memory 207244 kb
Host smart-1935f899-8f10-46fb-b0eb-b0dc9c0f6495
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620483557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1620483557
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1914763251
Short name T114
Test name
Test status
Simulation time 106765511 ps
CPU time 2.82 seconds
Started Jun 28 05:30:11 PM PDT 24
Finished Jun 28 05:30:15 PM PDT 24
Peak memory 216496 kb
Host smart-54baf23a-c953-428b-996e-c173ea7222f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914763251 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1914763251
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3297482832
Short name T1044
Test name
Test status
Simulation time 279967212 ps
CPU time 1.97 seconds
Started Jun 28 05:30:13 PM PDT 24
Finished Jun 28 05:30:17 PM PDT 24
Peak memory 215288 kb
Host smart-10b7834d-27fc-4859-9134-10f99f69951e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297482832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
297482832
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2983034776
Short name T1093
Test name
Test status
Simulation time 40110887 ps
CPU time 0.66 seconds
Started Jun 28 05:30:13 PM PDT 24
Finished Jun 28 05:30:15 PM PDT 24
Peak memory 203856 kb
Host smart-fc03da67-9ef5-4956-8487-2382655db5d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983034776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
983034776
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.493298277
Short name T128
Test name
Test status
Simulation time 82521472 ps
CPU time 1.8 seconds
Started Jun 28 05:30:12 PM PDT 24
Finished Jun 28 05:30:15 PM PDT 24
Peak memory 215532 kb
Host smart-69d9c522-d3a3-4539-8a6d-df40e5fcda8f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493298277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.493298277
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3907820041
Short name T1035
Test name
Test status
Simulation time 21475520 ps
CPU time 0.67 seconds
Started Jun 28 05:30:12 PM PDT 24
Finished Jun 28 05:30:15 PM PDT 24
Peak memory 203684 kb
Host smart-04fc623e-1b3b-48cc-b13b-e79126a0d7ec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907820041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3907820041
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.920429741
Short name T1013
Test name
Test status
Simulation time 29963074 ps
CPU time 1.77 seconds
Started Jun 28 05:30:13 PM PDT 24
Finished Jun 28 05:30:16 PM PDT 24
Peak memory 215380 kb
Host smart-a9b68787-fbc3-4082-a0d3-859ca2cf3c94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920429741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.920429741
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2007998867
Short name T164
Test name
Test status
Simulation time 3841253732 ps
CPU time 25.69 seconds
Started Jun 28 05:30:13 PM PDT 24
Finished Jun 28 05:30:40 PM PDT 24
Peak memory 215636 kb
Host smart-d1ce269c-abd9-4883-9592-1bd0ab02123e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007998867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2007998867
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.322208775
Short name T1054
Test name
Test status
Simulation time 13282211 ps
CPU time 0.74 seconds
Started Jun 28 05:30:48 PM PDT 24
Finished Jun 28 05:30:50 PM PDT 24
Peak memory 203856 kb
Host smart-7cea4af4-765b-44ab-9ce6-6cba63523c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322208775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.322208775
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2770714712
Short name T1069
Test name
Test status
Simulation time 14233658 ps
CPU time 0.74 seconds
Started Jun 28 05:30:47 PM PDT 24
Finished Jun 28 05:30:49 PM PDT 24
Peak memory 203852 kb
Host smart-53494c3f-87b0-4351-8a97-b951336c1353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770714712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2770714712
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2673006233
Short name T1099
Test name
Test status
Simulation time 20017232 ps
CPU time 0.74 seconds
Started Jun 28 05:30:46 PM PDT 24
Finished Jun 28 05:30:48 PM PDT 24
Peak memory 204332 kb
Host smart-22bcf5b6-ceb6-4b42-b522-2d26fcdc68fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673006233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2673006233
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3374296734
Short name T1057
Test name
Test status
Simulation time 13367385 ps
CPU time 0.75 seconds
Started Jun 28 05:30:45 PM PDT 24
Finished Jun 28 05:30:47 PM PDT 24
Peak memory 203856 kb
Host smart-cee3ac71-e9f4-4da1-b12f-173eca6703a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374296734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3374296734
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2796086534
Short name T1012
Test name
Test status
Simulation time 63582774 ps
CPU time 0.74 seconds
Started Jun 28 05:30:49 PM PDT 24
Finished Jun 28 05:30:51 PM PDT 24
Peak memory 203880 kb
Host smart-1850bab8-7a14-462a-be39-fdaf5ca831c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796086534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2796086534
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1217678652
Short name T1009
Test name
Test status
Simulation time 34658836 ps
CPU time 0.75 seconds
Started Jun 28 05:30:51 PM PDT 24
Finished Jun 28 05:30:52 PM PDT 24
Peak memory 204148 kb
Host smart-7adf6f8a-90fb-44cd-b8a8-78aeb88adee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217678652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1217678652
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3499967435
Short name T1090
Test name
Test status
Simulation time 53856523 ps
CPU time 0.76 seconds
Started Jun 28 05:30:52 PM PDT 24
Finished Jun 28 05:30:53 PM PDT 24
Peak memory 203716 kb
Host smart-ad926aaa-b239-41e3-bf08-0986f5762a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499967435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3499967435
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.253833746
Short name T1019
Test name
Test status
Simulation time 42787342 ps
CPU time 0.79 seconds
Started Jun 28 05:30:48 PM PDT 24
Finished Jun 28 05:30:50 PM PDT 24
Peak memory 203840 kb
Host smart-8798a42c-058a-4196-9d6d-bfd57dae0efe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253833746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.253833746
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2257595079
Short name T1022
Test name
Test status
Simulation time 24196666 ps
CPU time 0.76 seconds
Started Jun 28 05:30:46 PM PDT 24
Finished Jun 28 05:30:48 PM PDT 24
Peak memory 204164 kb
Host smart-1a06c962-8a63-4fcd-ac0f-2347db7b6b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257595079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2257595079
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.320945070
Short name T1079
Test name
Test status
Simulation time 60540802 ps
CPU time 0.81 seconds
Started Jun 28 05:30:44 PM PDT 24
Finished Jun 28 05:30:46 PM PDT 24
Peak memory 203956 kb
Host smart-8a885c80-312c-407f-819d-8324bf3985c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320945070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.320945070
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.41108952
Short name T1047
Test name
Test status
Simulation time 311224214 ps
CPU time 21.45 seconds
Started Jun 28 05:30:13 PM PDT 24
Finished Jun 28 05:30:36 PM PDT 24
Peak memory 215396 kb
Host smart-fcbb8006-ad17-45c0-a6e3-d9c670897e4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41108952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
aliasing.41108952
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.284143426
Short name T1026
Test name
Test status
Simulation time 1345455401 ps
CPU time 33.57 seconds
Started Jun 28 05:30:10 PM PDT 24
Finished Jun 28 05:30:45 PM PDT 24
Peak memory 207100 kb
Host smart-f9469e61-d33c-43ee-9006-6fcb41bea3f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284143426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.284143426
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.183303961
Short name T1127
Test name
Test status
Simulation time 16527832 ps
CPU time 1.04 seconds
Started Jun 28 05:30:15 PM PDT 24
Finished Jun 28 05:30:16 PM PDT 24
Peak memory 206844 kb
Host smart-a0e917ec-bec0-47ba-9f94-9e8f6e23d0cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183303961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.183303961
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1670220038
Short name T1049
Test name
Test status
Simulation time 42997582 ps
CPU time 1.77 seconds
Started Jun 28 05:30:11 PM PDT 24
Finished Jun 28 05:30:15 PM PDT 24
Peak memory 215392 kb
Host smart-0a9d5014-8be5-47ab-aa9c-3d6f3a801836
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670220038 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1670220038
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1382425039
Short name T1036
Test name
Test status
Simulation time 689938799 ps
CPU time 2.31 seconds
Started Jun 28 05:30:12 PM PDT 24
Finished Jun 28 05:30:16 PM PDT 24
Peak memory 207180 kb
Host smart-e2682e78-46f6-458a-b1ab-6a3a58f1a8c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382425039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
382425039
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3424580463
Short name T1072
Test name
Test status
Simulation time 16770422 ps
CPU time 0.78 seconds
Started Jun 28 05:30:12 PM PDT 24
Finished Jun 28 05:30:14 PM PDT 24
Peak memory 203840 kb
Host smart-597281a6-4a16-4b9b-a8fe-a86c2c836f92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424580463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
424580463
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2904418197
Short name T131
Test name
Test status
Simulation time 115018689 ps
CPU time 1.34 seconds
Started Jun 28 05:30:12 PM PDT 24
Finished Jun 28 05:30:14 PM PDT 24
Peak memory 215324 kb
Host smart-9ffa9e92-2eed-41ef-8ce5-1eeb76be26ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904418197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2904418197
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2957351407
Short name T1042
Test name
Test status
Simulation time 81435650 ps
CPU time 0.65 seconds
Started Jun 28 05:30:12 PM PDT 24
Finished Jun 28 05:30:14 PM PDT 24
Peak memory 203684 kb
Host smart-5d0a0243-64f7-4838-ac5f-0b16ef0ce58a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957351407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2957351407
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3711576696
Short name T1050
Test name
Test status
Simulation time 247251347 ps
CPU time 1.97 seconds
Started Jun 28 05:30:13 PM PDT 24
Finished Jun 28 05:30:17 PM PDT 24
Peak memory 215300 kb
Host smart-4c6427bd-2426-4a89-8600-bc67e5bc0417
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711576696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3711576696
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1948312449
Short name T121
Test name
Test status
Simulation time 93454120 ps
CPU time 2.38 seconds
Started Jun 28 05:30:11 PM PDT 24
Finished Jun 28 05:30:15 PM PDT 24
Peak memory 215696 kb
Host smart-c800cca0-ec51-440a-80a5-ccbef8f6c56b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948312449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
948312449
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.68537439
Short name T1113
Test name
Test status
Simulation time 648008642 ps
CPU time 13.61 seconds
Started Jun 28 05:30:11 PM PDT 24
Finished Jun 28 05:30:25 PM PDT 24
Peak memory 215400 kb
Host smart-686acddd-aac1-436a-8d18-b47dbce9c84a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68537439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_t
l_intg_err.68537439
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1252500878
Short name T1010
Test name
Test status
Simulation time 47817505 ps
CPU time 0.76 seconds
Started Jun 28 05:30:45 PM PDT 24
Finished Jun 28 05:30:47 PM PDT 24
Peak memory 204056 kb
Host smart-049d421a-3142-45ca-b373-eb130f485f0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252500878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1252500878
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4060481642
Short name T1015
Test name
Test status
Simulation time 42841059 ps
CPU time 0.69 seconds
Started Jun 28 05:30:48 PM PDT 24
Finished Jun 28 05:30:50 PM PDT 24
Peak memory 203856 kb
Host smart-d0650996-c68e-48fc-88ea-36cb6e2d2bde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060481642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
4060481642
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2584201651
Short name T1024
Test name
Test status
Simulation time 15886291 ps
CPU time 0.75 seconds
Started Jun 28 05:30:45 PM PDT 24
Finished Jun 28 05:30:47 PM PDT 24
Peak memory 203856 kb
Host smart-7ed83047-82ad-43e4-a9ba-53dc1a4d8d8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584201651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2584201651
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3313835189
Short name T1018
Test name
Test status
Simulation time 14753156 ps
CPU time 0.73 seconds
Started Jun 28 05:30:47 PM PDT 24
Finished Jun 28 05:30:49 PM PDT 24
Peak memory 203848 kb
Host smart-a6aff31f-c033-44d0-9af4-c360b9c2f486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313835189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3313835189
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3104599653
Short name T1101
Test name
Test status
Simulation time 19974093 ps
CPU time 0.72 seconds
Started Jun 28 05:30:46 PM PDT 24
Finished Jun 28 05:30:48 PM PDT 24
Peak memory 203852 kb
Host smart-c182e4a9-7ca2-4b9c-9b38-da82640067be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104599653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3104599653
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3148144919
Short name T1100
Test name
Test status
Simulation time 25623912 ps
CPU time 0.73 seconds
Started Jun 28 05:30:45 PM PDT 24
Finished Jun 28 05:30:47 PM PDT 24
Peak memory 203856 kb
Host smart-7fd76b29-2347-4f47-90f1-6f659fdf627e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148144919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3148144919
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.903070149
Short name T1030
Test name
Test status
Simulation time 16813312 ps
CPU time 0.75 seconds
Started Jun 28 05:30:48 PM PDT 24
Finished Jun 28 05:30:50 PM PDT 24
Peak memory 203828 kb
Host smart-f2c0d9d5-6a90-4ee8-bdd8-5dc28bb61253
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903070149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.903070149
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1034727414
Short name T1006
Test name
Test status
Simulation time 16860244 ps
CPU time 0.74 seconds
Started Jun 28 05:30:46 PM PDT 24
Finished Jun 28 05:30:48 PM PDT 24
Peak memory 204164 kb
Host smart-70c36065-34cc-40ae-af88-e535a0c7e144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034727414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1034727414
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2187579890
Short name T1025
Test name
Test status
Simulation time 30934810 ps
CPU time 0.75 seconds
Started Jun 28 05:30:45 PM PDT 24
Finished Jun 28 05:30:47 PM PDT 24
Peak memory 203736 kb
Host smart-0b3b0edb-de4f-47f0-9e20-36c179592c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187579890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2187579890
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1295728181
Short name T1068
Test name
Test status
Simulation time 180889283 ps
CPU time 0.76 seconds
Started Jun 28 05:30:43 PM PDT 24
Finished Jun 28 05:30:45 PM PDT 24
Peak memory 203856 kb
Host smart-741ee46a-0c0b-434c-83d8-71f82d6b4d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295728181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1295728181
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.499146827
Short name T1129
Test name
Test status
Simulation time 151780869 ps
CPU time 2.78 seconds
Started Jun 28 05:30:25 PM PDT 24
Finished Jun 28 05:30:30 PM PDT 24
Peak memory 216468 kb
Host smart-9507c906-dba2-4772-971a-105fa705199b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499146827 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.499146827
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2114226023
Short name T1080
Test name
Test status
Simulation time 48217624 ps
CPU time 1.39 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:27 PM PDT 24
Peak memory 207196 kb
Host smart-dbeec944-6e17-4a56-85ba-c9895ef6b281
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114226023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
114226023
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3413416191
Short name T1023
Test name
Test status
Simulation time 165607550 ps
CPU time 0.71 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:25 PM PDT 24
Peak memory 203752 kb
Host smart-695ce9df-56d7-4cfd-a666-95b85398c605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413416191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
413416191
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2520196169
Short name T151
Test name
Test status
Simulation time 819269558 ps
CPU time 4.42 seconds
Started Jun 28 05:30:27 PM PDT 24
Finished Jun 28 05:30:33 PM PDT 24
Peak memory 215388 kb
Host smart-9705f2a5-597d-447b-85e8-37b2a0aaf7e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520196169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2520196169
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.641966615
Short name T117
Test name
Test status
Simulation time 100314669 ps
CPU time 1.93 seconds
Started Jun 28 05:30:13 PM PDT 24
Finished Jun 28 05:30:16 PM PDT 24
Peak memory 215560 kb
Host smart-05c04a0e-a5d2-4644-8bfc-53cd82933e82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641966615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.641966615
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2033514111
Short name T1105
Test name
Test status
Simulation time 266922267 ps
CPU time 6.7 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:32 PM PDT 24
Peak memory 215356 kb
Host smart-a0585113-ec76-4984-a945-08e2374c904d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033514111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2033514111
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2329226409
Short name T1075
Test name
Test status
Simulation time 53065348 ps
CPU time 3.82 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:28 PM PDT 24
Peak memory 218536 kb
Host smart-a27dff88-326f-48cd-a603-4cf717323486
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329226409 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2329226409
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2926411674
Short name T1053
Test name
Test status
Simulation time 143422264 ps
CPU time 1.36 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:27 PM PDT 24
Peak memory 215380 kb
Host smart-f20c3eb0-656f-49e9-a88a-a994753a5981
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926411674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
926411674
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2737359825
Short name T1031
Test name
Test status
Simulation time 58830055 ps
CPU time 0.76 seconds
Started Jun 28 05:30:23 PM PDT 24
Finished Jun 28 05:30:25 PM PDT 24
Peak memory 203848 kb
Host smart-b8d10b7a-1b93-4d9c-b4e3-c183fe78fe39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737359825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
737359825
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3218225788
Short name T1052
Test name
Test status
Simulation time 453858239 ps
CPU time 3.12 seconds
Started Jun 28 05:30:27 PM PDT 24
Finished Jun 28 05:30:32 PM PDT 24
Peak memory 215380 kb
Host smart-5adf4a2d-0e0e-45f1-a847-3c0ccd21f2dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218225788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3218225788
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1655214348
Short name T119
Test name
Test status
Simulation time 245702022 ps
CPU time 3.33 seconds
Started Jun 28 05:30:27 PM PDT 24
Finished Jun 28 05:30:32 PM PDT 24
Peak memory 215512 kb
Host smart-e9cdf39e-64ca-446c-a989-fb4df8224ab1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655214348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
655214348
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2119806107
Short name T165
Test name
Test status
Simulation time 2199782058 ps
CPU time 13.37 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:38 PM PDT 24
Peak memory 215884 kb
Host smart-a5738c82-b53e-4c21-8ac2-883dcd149b82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119806107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2119806107
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4004249776
Short name T108
Test name
Test status
Simulation time 69334326 ps
CPU time 2.59 seconds
Started Jun 28 05:30:26 PM PDT 24
Finished Jun 28 05:30:31 PM PDT 24
Peak memory 217616 kb
Host smart-34f0002d-3c33-4d32-9fc5-0459d398542b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004249776 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.4004249776
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1444454475
Short name T127
Test name
Test status
Simulation time 80051315 ps
CPU time 1.46 seconds
Started Jun 28 05:30:27 PM PDT 24
Finished Jun 28 05:30:30 PM PDT 24
Peak memory 207196 kb
Host smart-24579de3-16b0-44cf-b73b-7e6d85096119
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444454475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
444454475
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.746594734
Short name T1039
Test name
Test status
Simulation time 36998971 ps
CPU time 0.72 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:26 PM PDT 24
Peak memory 203856 kb
Host smart-4625f65b-5e81-4f8f-849a-5af8a0f0f5aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746594734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.746594734
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1730263262
Short name T1104
Test name
Test status
Simulation time 460336554 ps
CPU time 2.68 seconds
Started Jun 28 05:30:25 PM PDT 24
Finished Jun 28 05:30:30 PM PDT 24
Peak memory 215340 kb
Host smart-d0a29c47-0c0b-4350-8070-3123e4cb7423
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730263262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1730263262
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3660832150
Short name T112
Test name
Test status
Simulation time 124406172 ps
CPU time 3.38 seconds
Started Jun 28 05:30:25 PM PDT 24
Finished Jun 28 05:30:30 PM PDT 24
Peak memory 215548 kb
Host smart-ecb1fa66-7ecf-49d5-b528-963db7e34520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660832150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
660832150
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3414694792
Short name T1074
Test name
Test status
Simulation time 521701049 ps
CPU time 20.21 seconds
Started Jun 28 05:30:26 PM PDT 24
Finished Jun 28 05:30:48 PM PDT 24
Peak memory 215400 kb
Host smart-74e1d8a9-10a8-4799-a9a5-79c50170cdb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414694792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3414694792
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2000719932
Short name T1061
Test name
Test status
Simulation time 94041405 ps
CPU time 3.03 seconds
Started Jun 28 05:30:26 PM PDT 24
Finished Jun 28 05:30:31 PM PDT 24
Peak memory 217740 kb
Host smart-3d1ea39e-f282-4d47-b3b4-950ee7976fcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000719932 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2000719932
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4267776943
Short name T1085
Test name
Test status
Simulation time 66179672 ps
CPU time 1.3 seconds
Started Jun 28 05:30:26 PM PDT 24
Finished Jun 28 05:30:29 PM PDT 24
Peak memory 215256 kb
Host smart-546ed431-801f-43c5-9153-93e98033afe2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267776943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
267776943
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2741916909
Short name T1011
Test name
Test status
Simulation time 20336723 ps
CPU time 0.79 seconds
Started Jun 28 05:30:27 PM PDT 24
Finished Jun 28 05:30:29 PM PDT 24
Peak memory 203832 kb
Host smart-d58f8abd-c5c0-443a-9ab9-1a3401d0a4a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741916909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
741916909
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1989484572
Short name T1128
Test name
Test status
Simulation time 106076199 ps
CPU time 3.83 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:30 PM PDT 24
Peak memory 215340 kb
Host smart-2f6ceace-2fb8-4d07-b237-2ec705539951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989484572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1989484572
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.769078781
Short name T118
Test name
Test status
Simulation time 65366177 ps
CPU time 1.93 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:28 PM PDT 24
Peak memory 215528 kb
Host smart-aa68c492-94dd-46e5-a6c2-3906d6d9e52b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769078781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.769078781
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1966306636
Short name T1115
Test name
Test status
Simulation time 865593328 ps
CPU time 7.05 seconds
Started Jun 28 05:30:26 PM PDT 24
Finished Jun 28 05:30:35 PM PDT 24
Peak memory 215384 kb
Host smart-7dcb5c12-af18-419b-bdcd-d952fc501a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966306636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1966306636
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1345681965
Short name T1121
Test name
Test status
Simulation time 64098017 ps
CPU time 1.85 seconds
Started Jun 28 05:30:25 PM PDT 24
Finished Jun 28 05:30:29 PM PDT 24
Peak memory 215540 kb
Host smart-726e95ca-033a-4b01-a4cf-2fbe7cc17ae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345681965 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1345681965
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1810544228
Short name T135
Test name
Test status
Simulation time 138721536 ps
CPU time 2.4 seconds
Started Jun 28 05:30:25 PM PDT 24
Finished Jun 28 05:30:29 PM PDT 24
Peak memory 215316 kb
Host smart-6925ab10-42fe-4349-82c9-93bb4c5cc1b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810544228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
810544228
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2166618489
Short name T1004
Test name
Test status
Simulation time 17546363 ps
CPU time 0.74 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:26 PM PDT 24
Peak memory 203816 kb
Host smart-1ee8ff64-53fa-48eb-bb4e-763007aba1ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166618489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
166618489
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3859528346
Short name T1059
Test name
Test status
Simulation time 242633838 ps
CPU time 3.52 seconds
Started Jun 28 05:30:25 PM PDT 24
Finished Jun 28 05:30:31 PM PDT 24
Peak memory 215372 kb
Host smart-106f2552-dc3c-478b-8d53-7feb7d1efcc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859528346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3859528346
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4255164241
Short name T124
Test name
Test status
Simulation time 118225071 ps
CPU time 1.93 seconds
Started Jun 28 05:30:24 PM PDT 24
Finished Jun 28 05:30:26 PM PDT 24
Peak memory 215616 kb
Host smart-01eb4f3c-ee6b-4e84-b7b4-f20ea8a10568
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255164241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
255164241
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2068776026
Short name T123
Test name
Test status
Simulation time 680240597 ps
CPU time 16.7 seconds
Started Jun 28 05:30:27 PM PDT 24
Finished Jun 28 05:30:45 PM PDT 24
Peak memory 215440 kb
Host smart-129a59d9-c27d-467f-96b4-4c69429c05c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068776026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2068776026
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1397959064
Short name T319
Test name
Test status
Simulation time 16380522 ps
CPU time 0.74 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:31:36 PM PDT 24
Peak memory 205964 kb
Host smart-3793a07a-738c-4a7e-8537-aaa8940e2d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397959064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
397959064
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2358550837
Short name T879
Test name
Test status
Simulation time 137232095 ps
CPU time 4.37 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:31:40 PM PDT 24
Peak memory 233104 kb
Host smart-49702131-37bb-4795-8018-38a8ac59b223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358550837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2358550837
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1348924999
Short name T681
Test name
Test status
Simulation time 95839051 ps
CPU time 0.75 seconds
Started Jun 28 05:31:36 PM PDT 24
Finished Jun 28 05:31:38 PM PDT 24
Peak memory 206060 kb
Host smart-7c89544d-abf9-4938-9dca-35822c707373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348924999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1348924999
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2063615202
Short name T324
Test name
Test status
Simulation time 4900205739 ps
CPU time 38.26 seconds
Started Jun 28 05:31:39 PM PDT 24
Finished Jun 28 05:32:18 PM PDT 24
Peak memory 239808 kb
Host smart-a63342b4-1ba6-475a-ae0f-a86243c55d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063615202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2063615202
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2500869739
Short name T478
Test name
Test status
Simulation time 1012204252 ps
CPU time 7.07 seconds
Started Jun 28 05:31:35 PM PDT 24
Finished Jun 28 05:31:43 PM PDT 24
Peak memory 241232 kb
Host smart-788d0dc6-0989-4ed6-93c0-7a3bcf8a5907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500869739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2500869739
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3174002210
Short name T172
Test name
Test status
Simulation time 1404530324 ps
CPU time 32.08 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:32:08 PM PDT 24
Peak memory 249588 kb
Host smart-1b11083d-a86f-4ea8-b09f-95db85df10c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174002210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3174002210
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3506442344
Short name T682
Test name
Test status
Simulation time 1018956727 ps
CPU time 11.89 seconds
Started Jun 28 05:31:33 PM PDT 24
Finished Jun 28 05:31:45 PM PDT 24
Peak memory 233160 kb
Host smart-6dfd98f4-6d5d-4f49-9774-892f3c55ef62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506442344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3506442344
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1819392161
Short name T325
Test name
Test status
Simulation time 3562282173 ps
CPU time 37.03 seconds
Started Jun 28 05:31:35 PM PDT 24
Finished Jun 28 05:32:13 PM PDT 24
Peak memory 233280 kb
Host smart-2ab4617d-6836-4715-abef-516faf80ab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819392161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1819392161
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3425538669
Short name T361
Test name
Test status
Simulation time 4921604392 ps
CPU time 6.32 seconds
Started Jun 28 05:31:36 PM PDT 24
Finished Jun 28 05:31:44 PM PDT 24
Peak memory 233340 kb
Host smart-cbd05d02-b32d-4fec-853d-39921a4f8e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425538669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3425538669
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.41200701
Short name T982
Test name
Test status
Simulation time 738360446 ps
CPU time 6.59 seconds
Started Jun 28 05:31:38 PM PDT 24
Finished Jun 28 05:31:46 PM PDT 24
Peak memory 233132 kb
Host smart-0ae1f790-f8ba-4bb8-aca4-dc0b5a850d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41200701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.41200701
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2298137791
Short name T890
Test name
Test status
Simulation time 1628683120 ps
CPU time 9.87 seconds
Started Jun 28 05:31:37 PM PDT 24
Finished Jun 28 05:31:48 PM PDT 24
Peak memory 223572 kb
Host smart-8ddb9012-363d-466b-af2c-c72fc2595e81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2298137791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2298137791
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3242216524
Short name T19
Test name
Test status
Simulation time 40510046398 ps
CPU time 128.5 seconds
Started Jun 28 05:31:32 PM PDT 24
Finished Jun 28 05:33:41 PM PDT 24
Peak memory 253636 kb
Host smart-403b64fa-e4a1-4ac4-a64d-e7f4b2f116cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242216524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3242216524
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.75546733
Short name T685
Test name
Test status
Simulation time 6131870018 ps
CPU time 22.74 seconds
Started Jun 28 05:31:35 PM PDT 24
Finished Jun 28 05:31:59 PM PDT 24
Peak memory 217220 kb
Host smart-caeb393d-7a99-47f3-adc8-285d43410564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75546733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.75546733
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3914297154
Short name T708
Test name
Test status
Simulation time 213749114 ps
CPU time 1.22 seconds
Started Jun 28 05:31:38 PM PDT 24
Finished Jun 28 05:31:40 PM PDT 24
Peak memory 208376 kb
Host smart-d93c7430-fee5-45ef-abf6-4296d2138bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914297154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3914297154
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2933130666
Short name T701
Test name
Test status
Simulation time 471919405 ps
CPU time 2 seconds
Started Jun 28 05:31:33 PM PDT 24
Finished Jun 28 05:31:37 PM PDT 24
Peak memory 208576 kb
Host smart-3d2a31ac-6fd5-40c5-8f09-9460693e999b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933130666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2933130666
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2739103718
Short name T589
Test name
Test status
Simulation time 131076932 ps
CPU time 0.9 seconds
Started Jun 28 05:31:39 PM PDT 24
Finished Jun 28 05:31:41 PM PDT 24
Peak memory 206324 kb
Host smart-7ea9c6ee-7c8c-47e5-babe-cc87db393c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739103718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2739103718
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1676191916
Short name T814
Test name
Test status
Simulation time 226981670 ps
CPU time 4.13 seconds
Started Jun 28 05:31:36 PM PDT 24
Finished Jun 28 05:31:41 PM PDT 24
Peak memory 224928 kb
Host smart-7823930a-23b2-42a8-9271-472d1d17ea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676191916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1676191916
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3883461439
Short name T690
Test name
Test status
Simulation time 10110441 ps
CPU time 0.69 seconds
Started Jun 28 05:31:43 PM PDT 24
Finished Jun 28 05:31:44 PM PDT 24
Peak memory 205792 kb
Host smart-6a4620ae-0382-42e0-8f6f-fea1acc2f0b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883461439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
883461439
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.4144644596
Short name T524
Test name
Test status
Simulation time 96503452 ps
CPU time 2.22 seconds
Started Jun 28 05:31:39 PM PDT 24
Finished Jun 28 05:31:42 PM PDT 24
Peak memory 224632 kb
Host smart-4caf63ba-7ae2-4d6e-8727-007052305dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144644596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.4144644596
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2888040850
Short name T488
Test name
Test status
Simulation time 15841821 ps
CPU time 0.82 seconds
Started Jun 28 05:31:39 PM PDT 24
Finished Jun 28 05:31:41 PM PDT 24
Peak memory 207088 kb
Host smart-5e75d1cd-5d03-4f72-ac68-a08b8fd08ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888040850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2888040850
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.287150760
Short name T883
Test name
Test status
Simulation time 7946916682 ps
CPU time 91.12 seconds
Started Jun 28 05:31:38 PM PDT 24
Finished Jun 28 05:33:10 PM PDT 24
Peak memory 268288 kb
Host smart-8f3b0424-fb52-4330-a32e-9530a6c345a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287150760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.287150760
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1378967452
Short name T595
Test name
Test status
Simulation time 13820455046 ps
CPU time 61.61 seconds
Started Jun 28 05:31:43 PM PDT 24
Finished Jun 28 05:32:45 PM PDT 24
Peak memory 251956 kb
Host smart-f6765429-06eb-4bcb-80e3-ad31698558d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378967452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1378967452
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.121893848
Short name T581
Test name
Test status
Simulation time 4873469683 ps
CPU time 23.88 seconds
Started Jun 28 05:31:42 PM PDT 24
Finished Jun 28 05:32:07 PM PDT 24
Peak memory 225176 kb
Host smart-86be5ccc-a19f-4373-96d6-77d9cfecc40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121893848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
121893848
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4260650652
Short name T809
Test name
Test status
Simulation time 86192008 ps
CPU time 3.42 seconds
Started Jun 28 05:31:41 PM PDT 24
Finished Jun 28 05:31:45 PM PDT 24
Peak memory 233152 kb
Host smart-0017dac3-4104-427a-8ae0-ea8796aaca41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260650652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4260650652
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2201223620
Short name T309
Test name
Test status
Simulation time 79134900 ps
CPU time 2.81 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:31:38 PM PDT 24
Peak memory 233160 kb
Host smart-5c6671e1-f6b2-4e21-9413-744862f30109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201223620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2201223620
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1787232135
Short name T566
Test name
Test status
Simulation time 234689174 ps
CPU time 5.32 seconds
Started Jun 28 05:31:37 PM PDT 24
Finished Jun 28 05:31:44 PM PDT 24
Peak memory 224928 kb
Host smart-7797667b-0f97-4940-b9c7-d1dd35d4b6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787232135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1787232135
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.215202474
Short name T575
Test name
Test status
Simulation time 27566164815 ps
CPU time 35.48 seconds
Started Jun 28 05:31:38 PM PDT 24
Finished Jun 28 05:32:14 PM PDT 24
Peak memory 225144 kb
Host smart-9de98749-3814-4593-b9fa-0a41810d658b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215202474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
215202474
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3272030488
Short name T979
Test name
Test status
Simulation time 216146787 ps
CPU time 2.41 seconds
Started Jun 28 05:31:39 PM PDT 24
Finished Jun 28 05:31:42 PM PDT 24
Peak memory 223664 kb
Host smart-74331773-c162-45ac-bb68-7334c5976508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272030488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3272030488
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.103554171
Short name T644
Test name
Test status
Simulation time 180837920 ps
CPU time 4.69 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:31:40 PM PDT 24
Peak memory 223432 kb
Host smart-e7d353b9-01e9-46ac-9ec4-3f6f10dba2c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=103554171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.103554171
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.385711875
Short name T82
Test name
Test status
Simulation time 58998775 ps
CPU time 1.1 seconds
Started Jun 28 05:31:43 PM PDT 24
Finished Jun 28 05:31:44 PM PDT 24
Peak memory 236712 kb
Host smart-8c14e7d5-263d-4b7e-8f40-ffc345c144cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385711875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.385711875
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2789741126
Short name T168
Test name
Test status
Simulation time 5216623987 ps
CPU time 28.26 seconds
Started Jun 28 05:31:43 PM PDT 24
Finished Jun 28 05:32:12 PM PDT 24
Peak memory 237748 kb
Host smart-d14a8d39-5c30-49de-8c7f-b56c31838a97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789741126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2789741126
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1059692514
Short name T282
Test name
Test status
Simulation time 9169428873 ps
CPU time 23.84 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:32:00 PM PDT 24
Peak memory 216936 kb
Host smart-5813122c-adf0-4a13-8773-38c4691a5ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059692514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1059692514
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3745152637
Short name T784
Test name
Test status
Simulation time 3983090110 ps
CPU time 3.87 seconds
Started Jun 28 05:31:37 PM PDT 24
Finished Jun 28 05:31:42 PM PDT 24
Peak memory 216732 kb
Host smart-a0433596-74f8-405c-aff5-96d748b2d21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745152637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3745152637
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.668828140
Short name T27
Test name
Test status
Simulation time 82622294 ps
CPU time 2.01 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:31:37 PM PDT 24
Peak memory 216740 kb
Host smart-2773ccd3-060a-498f-912b-58895ad9e77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668828140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.668828140
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3725739396
Short name T554
Test name
Test status
Simulation time 33734353 ps
CPU time 0.82 seconds
Started Jun 28 05:31:35 PM PDT 24
Finished Jun 28 05:31:37 PM PDT 24
Peak memory 206480 kb
Host smart-1457a0fd-a81c-4097-b398-f77803e46cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725739396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3725739396
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3630496537
Short name T684
Test name
Test status
Simulation time 140847273 ps
CPU time 2.49 seconds
Started Jun 28 05:31:41 PM PDT 24
Finished Jun 28 05:31:44 PM PDT 24
Peak memory 224940 kb
Host smart-cf3fbc6b-eb5d-4e47-b82d-63ca5646ad0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630496537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3630496537
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3470941200
Short name T375
Test name
Test status
Simulation time 25922296 ps
CPU time 0.75 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:35 PM PDT 24
Peak memory 205408 kb
Host smart-6b06e547-e068-48e6-9f0e-d2acd417d84d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470941200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3470941200
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3355151543
Short name T308
Test name
Test status
Simulation time 227746009 ps
CPU time 5.74 seconds
Started Jun 28 05:32:31 PM PDT 24
Finished Jun 28 05:32:38 PM PDT 24
Peak memory 233208 kb
Host smart-21ff6e1b-8b47-43dd-b251-5c758f81bafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355151543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3355151543
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3222874782
Short name T981
Test name
Test status
Simulation time 30345672 ps
CPU time 0.79 seconds
Started Jun 28 05:32:22 PM PDT 24
Finished Jun 28 05:32:24 PM PDT 24
Peak memory 207092 kb
Host smart-be1d5eb9-0365-47ab-a168-58231086fe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222874782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3222874782
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2536335028
Short name T372
Test name
Test status
Simulation time 110307731960 ps
CPU time 194.34 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:35:50 PM PDT 24
Peak memory 266124 kb
Host smart-ae2a39e7-523b-4c66-a4c8-4451a7aa3a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536335028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2536335028
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.4267140757
Short name T254
Test name
Test status
Simulation time 49454873082 ps
CPU time 192.72 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:35:46 PM PDT 24
Peak memory 257860 kb
Host smart-2abc93b9-2755-4f3f-85df-9348a022e66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267140757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.4267140757
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1602487157
Short name T710
Test name
Test status
Simulation time 157536080212 ps
CPU time 293.33 seconds
Started Jun 28 05:32:34 PM PDT 24
Finished Jun 28 05:37:30 PM PDT 24
Peak memory 251876 kb
Host smart-3ce68664-2e0f-4b38-b415-ffcf29fbb1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602487157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1602487157
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3345826052
Short name T660
Test name
Test status
Simulation time 3267419205 ps
CPU time 10.26 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:44 PM PDT 24
Peak memory 225116 kb
Host smart-d4df2141-cbe6-47ce-a10f-786fad5ae77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345826052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3345826052
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2116355601
Short name T212
Test name
Test status
Simulation time 54106499 ps
CPU time 2.94 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:32:38 PM PDT 24
Peak memory 224932 kb
Host smart-36b13078-bd03-4655-abe9-22b6b905f19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116355601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2116355601
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1708560369
Short name T729
Test name
Test status
Simulation time 11663226075 ps
CPU time 14.64 seconds
Started Jun 28 05:32:31 PM PDT 24
Finished Jun 28 05:32:48 PM PDT 24
Peak memory 233280 kb
Host smart-865579f9-0b77-4e07-b117-2789f9a17983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708560369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1708560369
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.65365511
Short name T525
Test name
Test status
Simulation time 18079436529 ps
CPU time 25.49 seconds
Started Jun 28 05:32:31 PM PDT 24
Finished Jun 28 05:32:58 PM PDT 24
Peak memory 253520 kb
Host smart-9eedcc63-675d-4c9b-892f-215cc036a72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65365511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.65365511
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4265029784
Short name T244
Test name
Test status
Simulation time 3346885689 ps
CPU time 7.08 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:41 PM PDT 24
Peak memory 225296 kb
Host smart-34ccd0f9-0e72-406f-9184-0bc7b63f77f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265029784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4265029784
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2958258640
Short name T395
Test name
Test status
Simulation time 497455836 ps
CPU time 5.2 seconds
Started Jun 28 05:32:31 PM PDT 24
Finished Jun 28 05:32:37 PM PDT 24
Peak memory 220056 kb
Host smart-631bac6e-a3b6-4312-8e96-95dafb253649
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2958258640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2958258640
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3682938717
Short name T669
Test name
Test status
Simulation time 57679461 ps
CPU time 1.23 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:32:36 PM PDT 24
Peak memory 207396 kb
Host smart-6468051a-e621-41a5-af7d-f95704900f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682938717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3682938717
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3277482961
Short name T344
Test name
Test status
Simulation time 3101787573 ps
CPU time 16.67 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:32:51 PM PDT 24
Peak memory 216900 kb
Host smart-20a8c389-9f0d-480d-98be-4d475375343d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277482961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3277482961
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.4094012049
Short name T339
Test name
Test status
Simulation time 5082748030 ps
CPU time 10.87 seconds
Started Jun 28 05:32:20 PM PDT 24
Finished Jun 28 05:32:31 PM PDT 24
Peak memory 216896 kb
Host smart-54d2e4e3-6c63-4d42-99fc-a3cf7a06a585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094012049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4094012049
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.580275341
Short name T394
Test name
Test status
Simulation time 61723790 ps
CPU time 0.79 seconds
Started Jun 28 05:32:34 PM PDT 24
Finished Jun 28 05:32:37 PM PDT 24
Peak memory 206464 kb
Host smart-38a634f8-6f9f-46c6-8145-90881575520e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580275341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.580275341
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.495427156
Short name T792
Test name
Test status
Simulation time 30210230 ps
CPU time 0.78 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:32:35 PM PDT 24
Peak memory 206456 kb
Host smart-514a162f-fab9-4bc3-b8cd-2e75986ce0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495427156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.495427156
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.665160047
Short name T926
Test name
Test status
Simulation time 2272280207 ps
CPU time 9.2 seconds
Started Jun 28 05:32:30 PM PDT 24
Finished Jun 28 05:32:40 PM PDT 24
Peak memory 241500 kb
Host smart-26611a8f-b887-423a-b224-e6bafb0ebf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665160047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.665160047
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3458394964
Short name T377
Test name
Test status
Simulation time 15021870 ps
CPU time 0.77 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:32:36 PM PDT 24
Peak memory 205300 kb
Host smart-528adae1-c9dd-46f0-886c-d408354dc9f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458394964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3458394964
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4245544325
Short name T436
Test name
Test status
Simulation time 1777889722 ps
CPU time 6.56 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:41 PM PDT 24
Peak memory 224888 kb
Host smart-c1515dbe-3081-492d-bc42-92e76c1b6510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245544325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4245544325
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4198555954
Short name T336
Test name
Test status
Simulation time 29756890 ps
CPU time 0.77 seconds
Started Jun 28 05:32:31 PM PDT 24
Finished Jun 28 05:32:32 PM PDT 24
Peak memory 207392 kb
Host smart-ba51655c-7550-4f70-8626-c68210b90758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198555954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4198555954
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.317913208
Short name T173
Test name
Test status
Simulation time 147656647315 ps
CPU time 165.27 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:35:21 PM PDT 24
Peak memory 256620 kb
Host smart-9e266654-f65f-49a2-ad04-ac7e48d9a556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317913208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.317913208
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2100625536
Short name T750
Test name
Test status
Simulation time 1132817037 ps
CPU time 19.92 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:53 PM PDT 24
Peak memory 252332 kb
Host smart-00308a41-00ff-45c0-b43d-197eb55c4328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100625536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2100625536
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1872925430
Short name T255
Test name
Test status
Simulation time 26651981390 ps
CPU time 272.44 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:37:08 PM PDT 24
Peak memory 254444 kb
Host smart-3772e047-9e3c-434c-8e2b-7fa51f625aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872925430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1872925430
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2443507879
Short name T318
Test name
Test status
Simulation time 122383117 ps
CPU time 4.52 seconds
Started Jun 28 05:32:37 PM PDT 24
Finished Jun 28 05:32:42 PM PDT 24
Peak memory 224916 kb
Host smart-bc489932-3663-4974-b997-8c70cd361775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443507879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2443507879
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1186202401
Short name T64
Test name
Test status
Simulation time 13180357043 ps
CPU time 44.76 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:33:18 PM PDT 24
Peak memory 257848 kb
Host smart-ed9f0b32-8bdf-4f62-95f8-3279f719793f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186202401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1186202401
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.589896626
Short name T191
Test name
Test status
Simulation time 15855122196 ps
CPU time 19.46 seconds
Started Jun 28 05:32:36 PM PDT 24
Finished Jun 28 05:32:57 PM PDT 24
Peak memory 233288 kb
Host smart-2f434adb-a1a3-4d80-b9e9-3d3f2857e6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589896626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.589896626
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3720179540
Short name T655
Test name
Test status
Simulation time 3397684974 ps
CPU time 15.81 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:50 PM PDT 24
Peak memory 233252 kb
Host smart-5fa2d13a-5578-4367-b7a0-01321eed0091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720179540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3720179540
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2008285525
Short name T205
Test name
Test status
Simulation time 6463908303 ps
CPU time 11.74 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:45 PM PDT 24
Peak memory 233308 kb
Host smart-ba62a8b8-7088-42fe-a28b-3ca695bb2184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008285525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2008285525
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2026971461
Short name T391
Test name
Test status
Simulation time 1446405835 ps
CPU time 6.21 seconds
Started Jun 28 05:32:39 PM PDT 24
Finished Jun 28 05:32:46 PM PDT 24
Peak memory 241092 kb
Host smart-da16f431-2b09-4aaa-a536-9626e78e22c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026971461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2026971461
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3410796274
Short name T442
Test name
Test status
Simulation time 260438053 ps
CPU time 3.22 seconds
Started Jun 28 05:32:34 PM PDT 24
Finished Jun 28 05:32:40 PM PDT 24
Peak memory 219992 kb
Host smart-4c25a85b-e69e-4450-936a-3521c74bff97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3410796274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3410796274
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.960278267
Short name T455
Test name
Test status
Simulation time 390897656 ps
CPU time 3.24 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:32:38 PM PDT 24
Peak memory 216772 kb
Host smart-038321fa-f6fa-4d5b-993a-b7ad5fb346b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960278267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.960278267
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.516662351
Short name T399
Test name
Test status
Simulation time 3315476448 ps
CPU time 10.05 seconds
Started Jun 28 05:32:38 PM PDT 24
Finished Jun 28 05:32:49 PM PDT 24
Peak memory 216696 kb
Host smart-b87d5296-c122-49c9-82de-3fa210c492d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516662351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.516662351
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4109599964
Short name T767
Test name
Test status
Simulation time 182474190 ps
CPU time 2.42 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:36 PM PDT 24
Peak memory 216764 kb
Host smart-4e496426-20aa-43ee-a927-2ff2342c2851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109599964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4109599964
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3186526390
Short name T678
Test name
Test status
Simulation time 103279271 ps
CPU time 0.94 seconds
Started Jun 28 05:32:35 PM PDT 24
Finished Jun 28 05:32:38 PM PDT 24
Peak memory 206456 kb
Host smart-552a5d3f-6d02-4c48-8552-4028f26dbf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186526390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3186526390
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3544301050
Short name T606
Test name
Test status
Simulation time 889018584 ps
CPU time 5.45 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:39 PM PDT 24
Peak memory 233216 kb
Host smart-01d8b26a-8edd-4140-abca-38813da72535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544301050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3544301050
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2280609731
Short name T562
Test name
Test status
Simulation time 12915276 ps
CPU time 0.8 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:32:36 PM PDT 24
Peak memory 205944 kb
Host smart-302075e1-2307-48a6-b34b-cf2906bbf64d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280609731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2280609731
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3193680765
Short name T247
Test name
Test status
Simulation time 1969722262 ps
CPU time 6.18 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:39 PM PDT 24
Peak memory 224936 kb
Host smart-10e63c4a-556c-449b-bddb-ab4d631fac96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193680765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3193680765
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3647984791
Short name T332
Test name
Test status
Simulation time 58552466 ps
CPU time 0.82 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:35 PM PDT 24
Peak memory 207092 kb
Host smart-1bb852a7-4d08-4fca-9862-64e5448830dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647984791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3647984791
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.4188352758
Short name T934
Test name
Test status
Simulation time 450273120159 ps
CPU time 564.63 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:42:00 PM PDT 24
Peak memory 267260 kb
Host smart-7360c2ce-751c-490f-aa49-cabb241fc1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188352758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.4188352758
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3211846459
Short name T484
Test name
Test status
Simulation time 61421677229 ps
CPU time 139.69 seconds
Started Jun 28 05:32:38 PM PDT 24
Finished Jun 28 05:34:59 PM PDT 24
Peak memory 250020 kb
Host smart-f56012e1-c5b1-48e2-ba19-e5c4f1ee8e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211846459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3211846459
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2658857601
Short name T780
Test name
Test status
Simulation time 66119454 ps
CPU time 3.17 seconds
Started Jun 28 05:32:34 PM PDT 24
Finished Jun 28 05:32:39 PM PDT 24
Peak memory 233144 kb
Host smart-a21b7412-4639-4482-bfeb-e0acead33377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658857601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2658857601
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2749393968
Short name T774
Test name
Test status
Simulation time 18544123377 ps
CPU time 139.33 seconds
Started Jun 28 05:32:34 PM PDT 24
Finished Jun 28 05:34:56 PM PDT 24
Peak memory 249724 kb
Host smart-64aa23d0-fdfc-4775-994d-05590aa819f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749393968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2749393968
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.519106643
Short name T41
Test name
Test status
Simulation time 1865212847 ps
CPU time 5.57 seconds
Started Jun 28 05:32:34 PM PDT 24
Finished Jun 28 05:32:42 PM PDT 24
Peak memory 233116 kb
Host smart-f313db9a-5658-4ca8-b3f5-680a09f83068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519106643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.519106643
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1320384176
Short name T939
Test name
Test status
Simulation time 448967172 ps
CPU time 5.73 seconds
Started Jun 28 05:32:34 PM PDT 24
Finished Jun 28 05:32:41 PM PDT 24
Peak memory 224828 kb
Host smart-4203179b-dd0c-4c41-8dae-08db5ee056ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320384176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1320384176
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1044319554
Short name T503
Test name
Test status
Simulation time 36602271787 ps
CPU time 20.25 seconds
Started Jun 28 05:32:35 PM PDT 24
Finished Jun 28 05:32:57 PM PDT 24
Peak memory 233352 kb
Host smart-960eefab-8651-44b8-9050-a442939d5922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044319554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1044319554
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.609955661
Short name T728
Test name
Test status
Simulation time 360789162 ps
CPU time 2.2 seconds
Started Jun 28 05:32:34 PM PDT 24
Finished Jun 28 05:32:38 PM PDT 24
Peak memory 225000 kb
Host smart-e8ec08ee-4962-44ef-9a57-895cb3ab0047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609955661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.609955661
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.29360257
Short name T47
Test name
Test status
Simulation time 236220209 ps
CPU time 6.12 seconds
Started Jun 28 05:32:34 PM PDT 24
Finished Jun 28 05:32:43 PM PDT 24
Peak memory 219296 kb
Host smart-8edb303d-ddcf-4f31-838a-fb4ca7e7bf66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=29360257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direc
t.29360257
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3639193592
Short name T23
Test name
Test status
Simulation time 4337892060 ps
CPU time 89.61 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:34:05 PM PDT 24
Peak memory 257904 kb
Host smart-ed391b30-58f7-4be0-918a-51f76fb7f01e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639193592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3639193592
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2610974225
Short name T855
Test name
Test status
Simulation time 2600277549 ps
CPU time 4.58 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:39 PM PDT 24
Peak memory 216868 kb
Host smart-5cc8f2b4-57f8-4860-b260-fd28715ad214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610974225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2610974225
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2658999296
Short name T477
Test name
Test status
Simulation time 3988137119 ps
CPU time 5.34 seconds
Started Jun 28 05:32:36 PM PDT 24
Finished Jun 28 05:32:42 PM PDT 24
Peak memory 216940 kb
Host smart-c8b3b037-013d-4ffa-b905-d8208f93a175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658999296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2658999296
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3036139519
Short name T871
Test name
Test status
Simulation time 487867455 ps
CPU time 2.83 seconds
Started Jun 28 05:32:35 PM PDT 24
Finished Jun 28 05:32:40 PM PDT 24
Peak memory 216752 kb
Host smart-7edb2540-89aa-4784-bc88-bacc90e5bc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036139519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3036139519
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3038467049
Short name T977
Test name
Test status
Simulation time 141432049 ps
CPU time 0.92 seconds
Started Jun 28 05:32:39 PM PDT 24
Finished Jun 28 05:32:40 PM PDT 24
Peak memory 206428 kb
Host smart-9538ff0d-65af-4bef-b5aa-44a195892902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038467049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3038467049
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1923229786
Short name T452
Test name
Test status
Simulation time 2065870079 ps
CPU time 6.94 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:32:42 PM PDT 24
Peak memory 237124 kb
Host smart-0c656daa-1095-431a-8b29-a2453374d565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923229786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1923229786
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2023162878
Short name T819
Test name
Test status
Simulation time 21884838 ps
CPU time 0.8 seconds
Started Jun 28 05:32:46 PM PDT 24
Finished Jun 28 05:32:48 PM PDT 24
Peak memory 205400 kb
Host smart-a34b8f94-7c89-4a88-a254-556fe5674174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023162878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2023162878
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1122548467
Short name T529
Test name
Test status
Simulation time 867140804 ps
CPU time 3.57 seconds
Started Jun 28 05:32:34 PM PDT 24
Finished Jun 28 05:32:40 PM PDT 24
Peak memory 224964 kb
Host smart-89fd9051-1b63-43ab-98ee-0db586ea2a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122548467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1122548467
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.4137321920
Short name T546
Test name
Test status
Simulation time 16228063 ps
CPU time 0.79 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:32:36 PM PDT 24
Peak memory 207404 kb
Host smart-dca8063d-8c4c-4728-bb6d-58219da44f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137321920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.4137321920
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3538928483
Short name T706
Test name
Test status
Simulation time 227828408188 ps
CPU time 410.5 seconds
Started Jun 28 05:32:45 PM PDT 24
Finished Jun 28 05:39:36 PM PDT 24
Peak memory 251772 kb
Host smart-638b264a-c480-407c-a0dd-1e8de4206515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538928483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3538928483
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2387117160
Short name T62
Test name
Test status
Simulation time 50245313751 ps
CPU time 220.93 seconds
Started Jun 28 05:32:45 PM PDT 24
Finished Jun 28 05:36:27 PM PDT 24
Peak memory 257760 kb
Host smart-1ff95e54-55f1-4dc3-ae5c-950359491919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387117160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2387117160
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.4130573225
Short name T358
Test name
Test status
Simulation time 68612563 ps
CPU time 3.65 seconds
Started Jun 28 05:32:45 PM PDT 24
Finished Jun 28 05:32:50 PM PDT 24
Peak memory 233164 kb
Host smart-343daf0a-6862-4d07-af9f-0328ed1edcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130573225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4130573225
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3150991724
Short name T914
Test name
Test status
Simulation time 76635718413 ps
CPU time 120.87 seconds
Started Jun 28 05:32:44 PM PDT 24
Finished Jun 28 05:34:46 PM PDT 24
Peak memory 249700 kb
Host smart-84e9da86-ae1f-4282-8cf7-d816979b9284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150991724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3150991724
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1690618663
Short name T402
Test name
Test status
Simulation time 3209843102 ps
CPU time 11.12 seconds
Started Jun 28 05:32:36 PM PDT 24
Finished Jun 28 05:32:48 PM PDT 24
Peak memory 225088 kb
Host smart-f755865f-3b4a-4a18-9a97-3edd6f8551e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690618663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1690618663
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1176096232
Short name T55
Test name
Test status
Simulation time 20279143708 ps
CPU time 30.89 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:33:07 PM PDT 24
Peak memory 251752 kb
Host smart-a77959a5-8c49-4b9e-b500-99f952f085d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176096232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1176096232
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1451413933
Short name T579
Test name
Test status
Simulation time 1626975216 ps
CPU time 7.6 seconds
Started Jun 28 05:32:36 PM PDT 24
Finished Jun 28 05:32:45 PM PDT 24
Peak memory 224932 kb
Host smart-99256dcb-9571-4b20-a3fe-85695973a53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451413933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1451413933
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.304810224
Short name T713
Test name
Test status
Simulation time 15880282497 ps
CPU time 21.19 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:32:56 PM PDT 24
Peak memory 225140 kb
Host smart-098ff870-0c23-496e-a23b-39b9f21b3675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304810224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.304810224
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3012152185
Short name T146
Test name
Test status
Simulation time 1323849695 ps
CPU time 10.89 seconds
Started Jun 28 05:32:46 PM PDT 24
Finished Jun 28 05:32:58 PM PDT 24
Peak memory 223604 kb
Host smart-ea0af463-8dbf-498c-85a8-db898f06ce0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3012152185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3012152185
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2460947352
Short name T59
Test name
Test status
Simulation time 66759709019 ps
CPU time 620.36 seconds
Started Jun 28 05:32:44 PM PDT 24
Finished Jun 28 05:43:05 PM PDT 24
Peak memory 271916 kb
Host smart-377b2a28-4f23-4b61-ba13-0928ac34773a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460947352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2460947352
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.466838185
Short name T537
Test name
Test status
Simulation time 29730826 ps
CPU time 0.71 seconds
Started Jun 28 05:32:33 PM PDT 24
Finished Jun 28 05:32:35 PM PDT 24
Peak memory 206192 kb
Host smart-7b980fda-b69f-44ce-8c65-c0064a4fcd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466838185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.466838185
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.780131079
Short name T450
Test name
Test status
Simulation time 36826695 ps
CPU time 0.78 seconds
Started Jun 28 05:32:35 PM PDT 24
Finished Jun 28 05:32:38 PM PDT 24
Peak memory 206208 kb
Host smart-b4a28ac8-17b8-42ee-9b00-53e98c5959ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780131079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.780131079
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4182059550
Short name T925
Test name
Test status
Simulation time 2870195817 ps
CPU time 12.55 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:46 PM PDT 24
Peak memory 216864 kb
Host smart-56b96c63-cf29-4f71-a179-8d8d58ca05dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182059550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4182059550
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3391426565
Short name T638
Test name
Test status
Simulation time 20409534 ps
CPU time 0.71 seconds
Started Jun 28 05:32:37 PM PDT 24
Finished Jun 28 05:32:39 PM PDT 24
Peak memory 206036 kb
Host smart-ef243c5b-5523-4d08-bc42-f49a2b477bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391426565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3391426565
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2194728674
Short name T812
Test name
Test status
Simulation time 2998785694 ps
CPU time 4.3 seconds
Started Jun 28 05:32:32 PM PDT 24
Finished Jun 28 05:32:38 PM PDT 24
Peak memory 233352 kb
Host smart-ff082f27-b676-4643-8bd5-1a1567b77170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194728674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2194728674
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.4172305037
Short name T299
Test name
Test status
Simulation time 35186056 ps
CPU time 0.69 seconds
Started Jun 28 05:32:47 PM PDT 24
Finished Jun 28 05:32:48 PM PDT 24
Peak memory 205296 kb
Host smart-da91e0dc-6c03-4535-8c9d-80a827b10f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172305037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4172305037
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.40110207
Short name T620
Test name
Test status
Simulation time 2596788998 ps
CPU time 24.94 seconds
Started Jun 28 05:32:47 PM PDT 24
Finished Jun 28 05:33:13 PM PDT 24
Peak memory 233300 kb
Host smart-359ba0da-8aee-4211-9bff-e2701e25212a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40110207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.40110207
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.617974453
Short name T418
Test name
Test status
Simulation time 19974893 ps
CPU time 0.8 seconds
Started Jun 28 05:32:46 PM PDT 24
Finished Jun 28 05:32:48 PM PDT 24
Peak memory 207428 kb
Host smart-ff7b857d-da4c-4b29-94d8-44417b369263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617974453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.617974453
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1435497286
Short name T888
Test name
Test status
Simulation time 19540012607 ps
CPU time 49.96 seconds
Started Jun 28 05:32:46 PM PDT 24
Finished Jun 28 05:33:37 PM PDT 24
Peak memory 257080 kb
Host smart-2433c4d4-6b28-45de-9e4c-2bcd064f7933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435497286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1435497286
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1167437658
Short name T974
Test name
Test status
Simulation time 12875566057 ps
CPU time 101.14 seconds
Started Jun 28 05:32:43 PM PDT 24
Finished Jun 28 05:34:25 PM PDT 24
Peak memory 249844 kb
Host smart-8256ec1e-60ac-4f41-a30c-190ecdd7e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167437658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1167437658
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2632496
Short name T666
Test name
Test status
Simulation time 13532511437 ps
CPU time 91.07 seconds
Started Jun 28 05:32:47 PM PDT 24
Finished Jun 28 05:34:19 PM PDT 24
Peak memory 252040 kb
Host smart-2d1670f6-ec7e-4c5f-a8af-d5e50cc66cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.2632496
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1100695861
Short name T403
Test name
Test status
Simulation time 12634394 ps
CPU time 0.77 seconds
Started Jun 28 05:32:45 PM PDT 24
Finished Jun 28 05:32:47 PM PDT 24
Peak memory 216404 kb
Host smart-bcdb44cc-3f73-4ea5-b565-a50b8238dc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100695861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1100695861
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.577078456
Short name T186
Test name
Test status
Simulation time 190658778 ps
CPU time 4.03 seconds
Started Jun 28 05:32:45 PM PDT 24
Finished Jun 28 05:32:51 PM PDT 24
Peak memory 233216 kb
Host smart-2158ba60-e597-4644-9fe2-0677cbdb1cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577078456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.577078456
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.58562861
Short name T877
Test name
Test status
Simulation time 932087873 ps
CPU time 8.68 seconds
Started Jun 28 05:32:48 PM PDT 24
Finished Jun 28 05:32:57 PM PDT 24
Peak memory 228644 kb
Host smart-921532f2-535b-43b7-97f1-61ab66c67e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58562861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.58562861
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.361388086
Short name T479
Test name
Test status
Simulation time 1213540851 ps
CPU time 2.54 seconds
Started Jun 28 05:32:46 PM PDT 24
Finished Jun 28 05:32:50 PM PDT 24
Peak memory 224896 kb
Host smart-e17119df-24b5-461f-b26d-16b5016aa635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361388086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.361388086
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2273577834
Short name T870
Test name
Test status
Simulation time 967714910 ps
CPU time 9.2 seconds
Started Jun 28 05:32:45 PM PDT 24
Finished Jun 28 05:32:56 PM PDT 24
Peak memory 233108 kb
Host smart-cb235934-eab7-4708-9092-122e4c1e1060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273577834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2273577834
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4206685425
Short name T397
Test name
Test status
Simulation time 771290510 ps
CPU time 12.59 seconds
Started Jun 28 05:32:45 PM PDT 24
Finished Jun 28 05:32:58 PM PDT 24
Peak memory 220732 kb
Host smart-0bc747a4-7832-4ebe-92cd-a67bd49ca845
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4206685425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4206685425
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2708437178
Short name T793
Test name
Test status
Simulation time 19863363687 ps
CPU time 173.87 seconds
Started Jun 28 05:32:46 PM PDT 24
Finished Jun 28 05:35:41 PM PDT 24
Peak memory 250048 kb
Host smart-32c77384-1c21-47b3-bb71-0d3740b3fe02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708437178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2708437178
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2499407372
Short name T657
Test name
Test status
Simulation time 15536137 ps
CPU time 0.71 seconds
Started Jun 28 05:32:48 PM PDT 24
Finished Jun 28 05:32:49 PM PDT 24
Peak memory 206132 kb
Host smart-a0e22c48-9278-4101-95ac-6a0bb2ce5201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499407372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2499407372
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2903212478
Short name T878
Test name
Test status
Simulation time 776392895 ps
CPU time 4.65 seconds
Started Jun 28 05:32:47 PM PDT 24
Finished Jun 28 05:32:53 PM PDT 24
Peak memory 216748 kb
Host smart-b47d0258-b77c-437f-9b17-ba9d5bb1ccbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903212478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2903212478
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2099525892
Short name T917
Test name
Test status
Simulation time 106553575 ps
CPU time 2.28 seconds
Started Jun 28 05:32:46 PM PDT 24
Finished Jun 28 05:32:49 PM PDT 24
Peak memory 216792 kb
Host smart-663e9b74-7cea-4b1a-93ed-32f0a95fd24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099525892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2099525892
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2483994107
Short name T469
Test name
Test status
Simulation time 76801325 ps
CPU time 0.78 seconds
Started Jun 28 05:32:46 PM PDT 24
Finished Jun 28 05:32:48 PM PDT 24
Peak memory 206456 kb
Host smart-e00f4cfc-10cc-4f68-b2ee-c41533a2bc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483994107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2483994107
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.4005622158
Short name T904
Test name
Test status
Simulation time 96448181 ps
CPU time 2.69 seconds
Started Jun 28 05:32:45 PM PDT 24
Finished Jun 28 05:32:48 PM PDT 24
Peak memory 233280 kb
Host smart-1e8dbfe6-c2ae-426b-9cd2-16548832df6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005622158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4005622158
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2297326616
Short name T315
Test name
Test status
Simulation time 32878601 ps
CPU time 0.75 seconds
Started Jun 28 05:32:59 PM PDT 24
Finished Jun 28 05:33:01 PM PDT 24
Peak memory 205404 kb
Host smart-0eba5cc3-af45-4300-a251-69c0b94ff831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297326616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2297326616
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.917874451
Short name T807
Test name
Test status
Simulation time 418594569 ps
CPU time 3.23 seconds
Started Jun 28 05:32:45 PM PDT 24
Finished Jun 28 05:32:49 PM PDT 24
Peak memory 224936 kb
Host smart-b3da556a-2983-41e4-8677-919145f9f0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917874451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.917874451
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.919742277
Short name T550
Test name
Test status
Simulation time 36231495 ps
CPU time 0.8 seconds
Started Jun 28 05:32:45 PM PDT 24
Finished Jun 28 05:32:46 PM PDT 24
Peak memory 207400 kb
Host smart-e4d16798-e70d-4712-bf63-e8c8c0a660ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919742277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.919742277
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1927884703
Short name T631
Test name
Test status
Simulation time 7164648758 ps
CPU time 37.73 seconds
Started Jun 28 05:32:48 PM PDT 24
Finished Jun 28 05:33:26 PM PDT 24
Peak memory 251400 kb
Host smart-31c3611b-c509-494a-b750-7046014c7ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927884703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1927884703
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2843194365
Short name T720
Test name
Test status
Simulation time 32867549735 ps
CPU time 111.06 seconds
Started Jun 28 05:32:51 PM PDT 24
Finished Jun 28 05:34:43 PM PDT 24
Peak memory 241620 kb
Host smart-6dc2a1c6-bad3-4be1-a3bc-9419aebdd31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843194365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2843194365
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.987141480
Short name T216
Test name
Test status
Simulation time 29049409626 ps
CPU time 238.11 seconds
Started Jun 28 05:32:47 PM PDT 24
Finished Jun 28 05:36:46 PM PDT 24
Peak memory 256640 kb
Host smart-9a1c0355-c34b-4f04-8ba4-16f290f7b09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987141480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.987141480
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1471802829
Short name T412
Test name
Test status
Simulation time 327613777 ps
CPU time 6.51 seconds
Started Jun 28 05:32:47 PM PDT 24
Finished Jun 28 05:32:54 PM PDT 24
Peak memory 233184 kb
Host smart-5c52380e-0b95-4bc9-bb51-1dd5df58f006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471802829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1471802829
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3367263902
Short name T177
Test name
Test status
Simulation time 190624081439 ps
CPU time 59.08 seconds
Started Jun 28 05:32:47 PM PDT 24
Finished Jun 28 05:33:47 PM PDT 24
Peak memory 233288 kb
Host smart-1ad0ef46-708f-484b-a750-596b25900edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367263902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3367263902
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2606626983
Short name T769
Test name
Test status
Simulation time 1765577698 ps
CPU time 5.78 seconds
Started Jun 28 05:32:46 PM PDT 24
Finished Jun 28 05:32:53 PM PDT 24
Peak memory 233100 kb
Host smart-5530161b-2b88-470a-a714-20797f86ff37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606626983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2606626983
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3429544676
Short name T423
Test name
Test status
Simulation time 575883118 ps
CPU time 14.6 seconds
Started Jun 28 05:32:44 PM PDT 24
Finished Jun 28 05:32:59 PM PDT 24
Peak memory 250628 kb
Host smart-fac2c502-5af0-4c69-afd9-062deddb2ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429544676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3429544676
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2670020809
Short name T983
Test name
Test status
Simulation time 3122907599 ps
CPU time 6.89 seconds
Started Jun 28 05:32:45 PM PDT 24
Finished Jun 28 05:32:53 PM PDT 24
Peak memory 233348 kb
Host smart-9b1e5007-a7f5-490a-a495-a0c57d572ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670020809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2670020809
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1922733512
Short name T473
Test name
Test status
Simulation time 13069624370 ps
CPU time 11.03 seconds
Started Jun 28 05:32:47 PM PDT 24
Finished Jun 28 05:32:59 PM PDT 24
Peak memory 233356 kb
Host smart-2a63c06b-2e79-408a-ab46-dc4e3c280932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922733512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1922733512
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2707921142
Short name T808
Test name
Test status
Simulation time 258699074 ps
CPU time 4.52 seconds
Started Jun 28 05:32:45 PM PDT 24
Finished Jun 28 05:32:50 PM PDT 24
Peak memory 220564 kb
Host smart-729ccbcf-bd16-422a-87ed-a79702c69826
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2707921142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2707921142
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3050025593
Short name T181
Test name
Test status
Simulation time 18442869829 ps
CPU time 139.81 seconds
Started Jun 28 05:32:46 PM PDT 24
Finished Jun 28 05:35:07 PM PDT 24
Peak memory 241628 kb
Host smart-b2f78667-7ff1-488a-a433-689e17c13ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050025593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3050025593
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1520469375
Short name T417
Test name
Test status
Simulation time 402606726 ps
CPU time 6.04 seconds
Started Jun 28 05:32:46 PM PDT 24
Finished Jun 28 05:32:53 PM PDT 24
Peak memory 217076 kb
Host smart-3d0274df-c596-474e-b9a9-1b532d120a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520469375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1520469375
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3363500340
Short name T832
Test name
Test status
Simulation time 1094163328 ps
CPU time 3.86 seconds
Started Jun 28 05:32:44 PM PDT 24
Finished Jun 28 05:32:49 PM PDT 24
Peak memory 216824 kb
Host smart-c4579f29-1dd1-4fac-b126-38f31f7e60e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363500340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3363500340
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.905763043
Short name T868
Test name
Test status
Simulation time 155401394 ps
CPU time 2.05 seconds
Started Jun 28 05:32:44 PM PDT 24
Finished Jun 28 05:32:47 PM PDT 24
Peak memory 216756 kb
Host smart-298b104a-4861-4112-8261-8ff28e756784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905763043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.905763043
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3994599463
Short name T852
Test name
Test status
Simulation time 86796223 ps
CPU time 0.9 seconds
Started Jun 28 05:32:51 PM PDT 24
Finished Jun 28 05:32:52 PM PDT 24
Peak memory 206436 kb
Host smart-8d02ef34-8793-4535-80a9-a75a65b5c9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994599463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3994599463
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4111067052
Short name T430
Test name
Test status
Simulation time 7481216341 ps
CPU time 22.28 seconds
Started Jun 28 05:32:51 PM PDT 24
Finished Jun 28 05:33:14 PM PDT 24
Peak memory 224988 kb
Host smart-12748766-eeab-4073-a88f-bb9103a38c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111067052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4111067052
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2457008517
Short name T520
Test name
Test status
Simulation time 364541941 ps
CPU time 4.95 seconds
Started Jun 28 05:32:56 PM PDT 24
Finished Jun 28 05:33:02 PM PDT 24
Peak memory 233136 kb
Host smart-ce14c19a-a0c6-457b-a600-c65d60560e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457008517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2457008517
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.4089707412
Short name T311
Test name
Test status
Simulation time 28660811 ps
CPU time 0.81 seconds
Started Jun 28 05:32:58 PM PDT 24
Finished Jun 28 05:33:00 PM PDT 24
Peak memory 207092 kb
Host smart-94a74a83-645b-4525-8f35-fe881f6f56b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089707412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.4089707412
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2065984429
Short name T896
Test name
Test status
Simulation time 9754366498 ps
CPU time 66.33 seconds
Started Jun 28 05:33:10 PM PDT 24
Finished Jun 28 05:34:18 PM PDT 24
Peak memory 224384 kb
Host smart-8cc9a024-0c18-4bf9-bebf-4c92e640901b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065984429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2065984429
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4111398936
Short name T842
Test name
Test status
Simulation time 3093268991 ps
CPU time 41.37 seconds
Started Jun 28 05:32:56 PM PDT 24
Finished Jun 28 05:33:39 PM PDT 24
Peak memory 240568 kb
Host smart-b2c0942c-e3a9-48ee-9386-1fc865d99297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111398936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4111398936
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4259655981
Short name T637
Test name
Test status
Simulation time 1377695834 ps
CPU time 37.6 seconds
Started Jun 28 05:32:58 PM PDT 24
Finished Jun 28 05:33:37 PM PDT 24
Peak memory 250464 kb
Host smart-b0561ce0-1e65-44d2-a75f-76ed984cc820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259655981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4259655981
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1685644738
Short name T712
Test name
Test status
Simulation time 3687728490 ps
CPU time 23.85 seconds
Started Jun 28 05:32:57 PM PDT 24
Finished Jun 28 05:33:22 PM PDT 24
Peak memory 241432 kb
Host smart-6733212d-87f6-48ca-bced-ad481888132f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685644738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1685644738
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2680846967
Short name T262
Test name
Test status
Simulation time 176144650597 ps
CPU time 529.56 seconds
Started Jun 28 05:32:55 PM PDT 24
Finished Jun 28 05:41:46 PM PDT 24
Peak memory 256568 kb
Host smart-4995a109-f1c2-41ec-9bde-5b9522d564d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680846967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2680846967
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.676308650
Short name T49
Test name
Test status
Simulation time 4549733922 ps
CPU time 22.27 seconds
Started Jun 28 05:32:56 PM PDT 24
Finished Jun 28 05:33:20 PM PDT 24
Peak memory 225088 kb
Host smart-52652f27-030a-4552-8594-90ad31267511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676308650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.676308650
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2936642809
Short name T495
Test name
Test status
Simulation time 497510349 ps
CPU time 9.64 seconds
Started Jun 28 05:32:55 PM PDT 24
Finished Jun 28 05:33:04 PM PDT 24
Peak memory 233124 kb
Host smart-1e6078b5-fa2f-4404-ba42-2a7ab0a7ef7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936642809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2936642809
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.598127336
Short name T854
Test name
Test status
Simulation time 24030154909 ps
CPU time 17.98 seconds
Started Jun 28 05:32:57 PM PDT 24
Finished Jun 28 05:33:17 PM PDT 24
Peak memory 236348 kb
Host smart-00a32636-5e90-4aea-963e-e93450fb7722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598127336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.598127336
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1673572787
Short name T838
Test name
Test status
Simulation time 28135939307 ps
CPU time 11.69 seconds
Started Jun 28 05:32:55 PM PDT 24
Finished Jun 28 05:33:08 PM PDT 24
Peak memory 234984 kb
Host smart-62cba79a-0347-4249-9911-ce20f2c53b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673572787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1673572787
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1390877005
Short name T961
Test name
Test status
Simulation time 2074499687 ps
CPU time 9.04 seconds
Started Jun 28 05:32:58 PM PDT 24
Finished Jun 28 05:33:08 PM PDT 24
Peak memory 223620 kb
Host smart-098a5cbd-3ae1-4c11-99e5-edf4a97b1cb2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1390877005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1390877005
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3219081628
Short name T916
Test name
Test status
Simulation time 16516802879 ps
CPU time 141.7 seconds
Started Jun 28 05:32:57 PM PDT 24
Finished Jun 28 05:35:21 PM PDT 24
Peak memory 238180 kb
Host smart-d7ff9278-aac8-490f-9e06-3bcccc87ba6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219081628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3219081628
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2214525986
Short name T778
Test name
Test status
Simulation time 49921041499 ps
CPU time 17.31 seconds
Started Jun 28 05:32:57 PM PDT 24
Finished Jun 28 05:33:16 PM PDT 24
Peak memory 216888 kb
Host smart-afb3de99-d9e5-4b98-a963-248a87ca71c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214525986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2214525986
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4229401043
Short name T933
Test name
Test status
Simulation time 29219085 ps
CPU time 0.77 seconds
Started Jun 28 05:32:57 PM PDT 24
Finished Jun 28 05:32:59 PM PDT 24
Peak memory 206180 kb
Host smart-1f54e8d5-6dd6-4623-b77c-35129c35901d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229401043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4229401043
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1324076013
Short name T976
Test name
Test status
Simulation time 21020796 ps
CPU time 0.82 seconds
Started Jun 28 05:32:58 PM PDT 24
Finished Jun 28 05:33:00 PM PDT 24
Peak memory 206464 kb
Host smart-8622777f-df7d-41e2-8ec8-aae304e9e5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324076013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1324076013
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1383079838
Short name T845
Test name
Test status
Simulation time 52847572 ps
CPU time 0.75 seconds
Started Jun 28 05:32:55 PM PDT 24
Finished Jun 28 05:32:57 PM PDT 24
Peak memory 206424 kb
Host smart-2c7dc5ab-a58f-4f03-aea3-83009a0b5a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383079838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1383079838
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1170903059
Short name T603
Test name
Test status
Simulation time 32455186480 ps
CPU time 26.36 seconds
Started Jun 28 05:32:56 PM PDT 24
Finished Jun 28 05:33:24 PM PDT 24
Peak memory 241304 kb
Host smart-36882d95-7a79-4dcc-b78c-2374ec2c3157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170903059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1170903059
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3371565184
Short name T680
Test name
Test status
Simulation time 19133089 ps
CPU time 0.76 seconds
Started Jun 28 05:32:58 PM PDT 24
Finished Jun 28 05:33:00 PM PDT 24
Peak memory 205372 kb
Host smart-ad193f20-92b5-4ad5-9fcb-ee16cd95444c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371565184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3371565184
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2864454362
Short name T5
Test name
Test status
Simulation time 66430723 ps
CPU time 2.35 seconds
Started Jun 28 05:32:57 PM PDT 24
Finished Jun 28 05:33:01 PM PDT 24
Peak memory 233192 kb
Host smart-ab377b95-6a68-4777-8b3c-1a5cf4a268ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864454362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2864454362
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.902982826
Short name T447
Test name
Test status
Simulation time 31472343 ps
CPU time 0.78 seconds
Started Jun 28 05:33:10 PM PDT 24
Finished Jun 28 05:33:13 PM PDT 24
Peak memory 206028 kb
Host smart-2090cdb8-ca8a-4cd8-915e-833edad44f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902982826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.902982826
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1421584895
Short name T823
Test name
Test status
Simulation time 8203081445 ps
CPU time 106.45 seconds
Started Jun 28 05:32:57 PM PDT 24
Finished Jun 28 05:34:45 PM PDT 24
Peak memory 257568 kb
Host smart-e888c97a-7f97-4d6d-a4be-fa2ba58029d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421584895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1421584895
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1578612579
Short name T966
Test name
Test status
Simulation time 12035500188 ps
CPU time 159.12 seconds
Started Jun 28 05:32:58 PM PDT 24
Finished Jun 28 05:35:38 PM PDT 24
Peak memory 267112 kb
Host smart-7bb5cc3f-5c51-4287-811e-1e305a9d0ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578612579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1578612579
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2691476779
Short name T507
Test name
Test status
Simulation time 750619612 ps
CPU time 12.78 seconds
Started Jun 28 05:33:10 PM PDT 24
Finished Jun 28 05:33:25 PM PDT 24
Peak memory 233356 kb
Host smart-3921ce3a-1c17-48b3-9365-56d2afce8798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691476779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2691476779
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1904453575
Short name T40
Test name
Test status
Simulation time 1682841607 ps
CPU time 44.33 seconds
Started Jun 28 05:32:56 PM PDT 24
Finished Jun 28 05:33:42 PM PDT 24
Peak memory 263316 kb
Host smart-d2b94492-569e-4b84-9b94-a0d55c6b33c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904453575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1904453575
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3831350412
Short name T383
Test name
Test status
Simulation time 343356366 ps
CPU time 6.71 seconds
Started Jun 28 05:32:57 PM PDT 24
Finished Jun 28 05:33:06 PM PDT 24
Peak memory 224836 kb
Host smart-4b64aa22-c206-43e2-9ead-412a58f8f953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831350412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3831350412
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.485720770
Short name T245
Test name
Test status
Simulation time 1729826460 ps
CPU time 13.35 seconds
Started Jun 28 05:32:59 PM PDT 24
Finished Jun 28 05:33:13 PM PDT 24
Peak memory 224960 kb
Host smart-02542def-56cd-4fa7-b04a-4ee1d3ccca92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485720770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.485720770
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1752951833
Short name T763
Test name
Test status
Simulation time 10852968286 ps
CPU time 18.19 seconds
Started Jun 28 05:32:55 PM PDT 24
Finished Jun 28 05:33:14 PM PDT 24
Peak memory 225056 kb
Host smart-5a56c0ed-d8de-4e55-9c40-0b877b01a19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752951833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1752951833
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2728739939
Short name T647
Test name
Test status
Simulation time 6314340876 ps
CPU time 19.37 seconds
Started Jun 28 05:32:56 PM PDT 24
Finished Jun 28 05:33:16 PM PDT 24
Peak memory 233352 kb
Host smart-2ab3023d-8638-4643-82f0-66b58d004c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728739939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2728739939
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1013413857
Short name T406
Test name
Test status
Simulation time 686157200 ps
CPU time 6.55 seconds
Started Jun 28 05:33:00 PM PDT 24
Finished Jun 28 05:33:07 PM PDT 24
Peak memory 220572 kb
Host smart-681a6e6b-952e-4532-bcfb-f830744c74b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1013413857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1013413857
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.408579142
Short name T408
Test name
Test status
Simulation time 44864733 ps
CPU time 0.98 seconds
Started Jun 28 05:33:01 PM PDT 24
Finished Jun 28 05:33:02 PM PDT 24
Peak memory 207216 kb
Host smart-2aacaa87-d45c-45b4-9c44-b634a66a726a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408579142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.408579142
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2508575717
Short name T834
Test name
Test status
Simulation time 1234984951 ps
CPU time 9.07 seconds
Started Jun 28 05:32:56 PM PDT 24
Finished Jun 28 05:33:07 PM PDT 24
Peak memory 216732 kb
Host smart-109def9d-764a-48e4-9a65-ddbc833d62a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508575717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2508575717
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.133341618
Short name T320
Test name
Test status
Simulation time 27380326528 ps
CPU time 20.42 seconds
Started Jun 28 05:32:55 PM PDT 24
Finished Jun 28 05:33:17 PM PDT 24
Peak memory 216896 kb
Host smart-ac6a041d-9b2e-4e33-90c4-2d6f8b86a965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133341618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.133341618
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2845558123
Short name T287
Test name
Test status
Simulation time 621694108 ps
CPU time 5.84 seconds
Started Jun 28 05:32:56 PM PDT 24
Finished Jun 28 05:33:04 PM PDT 24
Peak memory 216700 kb
Host smart-267e5378-bdb0-45b3-ac4f-f0c8581da565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845558123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2845558123
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1887532511
Short name T329
Test name
Test status
Simulation time 30177058 ps
CPU time 0.78 seconds
Started Jun 28 05:33:01 PM PDT 24
Finished Jun 28 05:33:02 PM PDT 24
Peak memory 206452 kb
Host smart-904c9b80-fb35-4270-b20a-c3ee6588f756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887532511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1887532511
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1012252449
Short name T866
Test name
Test status
Simulation time 13108306363 ps
CPU time 11.31 seconds
Started Jun 28 05:32:57 PM PDT 24
Finished Jun 28 05:33:10 PM PDT 24
Peak memory 225084 kb
Host smart-d8f15073-ab88-4cb5-977a-e5ccde47772e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012252449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1012252449
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3121051610
Short name T950
Test name
Test status
Simulation time 34941681 ps
CPU time 0.73 seconds
Started Jun 28 05:33:07 PM PDT 24
Finished Jun 28 05:33:08 PM PDT 24
Peak memory 206416 kb
Host smart-e17edce3-b4dc-42c1-9b91-16dc567a7f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121051610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3121051610
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.41911760
Short name T600
Test name
Test status
Simulation time 186096488 ps
CPU time 3.16 seconds
Started Jun 28 05:33:01 PM PDT 24
Finished Jun 28 05:33:05 PM PDT 24
Peak memory 233152 kb
Host smart-df775cdc-8a8a-49c3-a118-b872f2ceb292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41911760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.41911760
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2545484761
Short name T322
Test name
Test status
Simulation time 17262432 ps
CPU time 0.78 seconds
Started Jun 28 05:33:10 PM PDT 24
Finished Jun 28 05:33:13 PM PDT 24
Peak memory 207360 kb
Host smart-fbc904c3-effb-4914-b35f-58e6496711b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545484761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2545484761
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1234890069
Short name T189
Test name
Test status
Simulation time 56160114029 ps
CPU time 110.01 seconds
Started Jun 28 05:33:11 PM PDT 24
Finished Jun 28 05:35:03 PM PDT 24
Peak memory 249724 kb
Host smart-088a1954-572c-4618-bf00-c0b41ef37c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234890069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1234890069
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4044011659
Short name T944
Test name
Test status
Simulation time 21388644916 ps
CPU time 52.34 seconds
Started Jun 28 05:33:09 PM PDT 24
Finished Jun 28 05:34:04 PM PDT 24
Peak memory 240308 kb
Host smart-fc1523cb-517a-4a01-85b0-1f0768da4e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044011659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4044011659
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2814614044
Short name T781
Test name
Test status
Simulation time 11696359364 ps
CPU time 115.16 seconds
Started Jun 28 05:33:07 PM PDT 24
Finished Jun 28 05:35:04 PM PDT 24
Peak memory 240812 kb
Host smart-518a6304-2afb-421d-b90d-740dec305395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814614044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2814614044
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2649255685
Short name T894
Test name
Test status
Simulation time 1448811314 ps
CPU time 9.04 seconds
Started Jun 28 05:33:10 PM PDT 24
Finished Jun 28 05:33:21 PM PDT 24
Peak memory 224980 kb
Host smart-55e47bc8-f809-42e4-8629-4464919fbe5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649255685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2649255685
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1947794575
Short name T28
Test name
Test status
Simulation time 38689202659 ps
CPU time 262.72 seconds
Started Jun 28 05:33:07 PM PDT 24
Finished Jun 28 05:37:32 PM PDT 24
Peak memory 266072 kb
Host smart-48387ba2-ffba-4646-b25a-41efc2222554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947794575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1947794575
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.617304197
Short name T648
Test name
Test status
Simulation time 3349937583 ps
CPU time 12.05 seconds
Started Jun 28 05:32:55 PM PDT 24
Finished Jun 28 05:33:08 PM PDT 24
Peak memory 225064 kb
Host smart-1ef186f3-7568-4c21-9419-5a6f68b2f8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617304197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.617304197
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1639885199
Short name T702
Test name
Test status
Simulation time 5497357952 ps
CPU time 8.85 seconds
Started Jun 28 05:32:55 PM PDT 24
Finished Jun 28 05:33:04 PM PDT 24
Peak memory 233296 kb
Host smart-8adf830b-3434-4582-8571-a7ec53ce4d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639885199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1639885199
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2752306461
Short name T365
Test name
Test status
Simulation time 158929158 ps
CPU time 3.47 seconds
Started Jun 28 05:33:10 PM PDT 24
Finished Jun 28 05:33:16 PM PDT 24
Peak memory 232548 kb
Host smart-2f40df40-0b2a-45a0-87f1-e0a721652172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752306461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2752306461
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3990221148
Short name T490
Test name
Test status
Simulation time 162152664 ps
CPU time 2.62 seconds
Started Jun 28 05:32:56 PM PDT 24
Finished Jun 28 05:33:01 PM PDT 24
Peak memory 233244 kb
Host smart-6f800570-1fd5-484b-a594-b476bc768992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990221148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3990221148
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2944869373
Short name T102
Test name
Test status
Simulation time 6910920371 ps
CPU time 20.62 seconds
Started Jun 28 05:33:08 PM PDT 24
Finished Jun 28 05:33:30 PM PDT 24
Peak memory 222024 kb
Host smart-ad8254a2-833b-4649-86fb-688a673f509b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2944869373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2944869373
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1262820380
Short name T156
Test name
Test status
Simulation time 60834412436 ps
CPU time 68.91 seconds
Started Jun 28 05:33:08 PM PDT 24
Finished Jun 28 05:34:18 PM PDT 24
Peak memory 241672 kb
Host smart-eed101ae-17b8-499c-aaa0-dd54a778fb58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262820380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1262820380
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1557425646
Short name T836
Test name
Test status
Simulation time 3451103463 ps
CPU time 12.39 seconds
Started Jun 28 05:32:59 PM PDT 24
Finished Jun 28 05:33:12 PM PDT 24
Peak memory 217132 kb
Host smart-16898383-2ddf-4e82-be62-e36924864638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557425646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1557425646
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.185928555
Short name T3
Test name
Test status
Simulation time 27190705524 ps
CPU time 17.53 seconds
Started Jun 28 05:33:02 PM PDT 24
Finished Jun 28 05:33:20 PM PDT 24
Peak memory 217972 kb
Host smart-9d067b6e-d1e3-4898-b6ef-daf3e96d3247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185928555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.185928555
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3836731722
Short name T817
Test name
Test status
Simulation time 355581049 ps
CPU time 4.14 seconds
Started Jun 28 05:32:57 PM PDT 24
Finished Jun 28 05:33:03 PM PDT 24
Peak memory 216748 kb
Host smart-05e2e5e5-5503-4c91-800a-afd1cd98d167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836731722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3836731722
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3986977079
Short name T510
Test name
Test status
Simulation time 66777019 ps
CPU time 0.78 seconds
Started Jun 28 05:32:58 PM PDT 24
Finished Jun 28 05:33:00 PM PDT 24
Peak memory 206444 kb
Host smart-217f8c79-4a95-4ea4-837e-e0dff332f596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986977079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3986977079
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2405655408
Short name T630
Test name
Test status
Simulation time 16554986775 ps
CPU time 14.67 seconds
Started Jun 28 05:33:00 PM PDT 24
Finished Jun 28 05:33:15 PM PDT 24
Peak memory 233308 kb
Host smart-9b6e6494-1502-4615-ab39-ac459d22a6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405655408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2405655408
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2622911510
Short name T636
Test name
Test status
Simulation time 14356540 ps
CPU time 0.72 seconds
Started Jun 28 05:33:15 PM PDT 24
Finished Jun 28 05:33:16 PM PDT 24
Peak memory 205956 kb
Host smart-47773cc8-7ebf-4de1-ad20-65d22e1fd174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622911510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2622911510
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3900552433
Short name T504
Test name
Test status
Simulation time 608598083 ps
CPU time 2.71 seconds
Started Jun 28 05:33:13 PM PDT 24
Finished Jun 28 05:33:17 PM PDT 24
Peak memory 225016 kb
Host smart-d1c1265a-6b5f-4e8f-9daa-b4db047d090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900552433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3900552433
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3789230388
Short name T875
Test name
Test status
Simulation time 74590273 ps
CPU time 0.8 seconds
Started Jun 28 05:33:07 PM PDT 24
Finished Jun 28 05:33:10 PM PDT 24
Peak memory 207092 kb
Host smart-59e5a932-1913-4c42-ba54-9b9a59779ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789230388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3789230388
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.4011404218
Short name T929
Test name
Test status
Simulation time 47854310071 ps
CPU time 385.46 seconds
Started Jun 28 05:33:06 PM PDT 24
Finished Jun 28 05:39:32 PM PDT 24
Peak memory 256576 kb
Host smart-60e57dc4-7050-47cb-8c57-7e6734355261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011404218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4011404218
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.141642756
Short name T654
Test name
Test status
Simulation time 25689943114 ps
CPU time 240.18 seconds
Started Jun 28 05:33:07 PM PDT 24
Finished Jun 28 05:37:09 PM PDT 24
Peak memory 256880 kb
Host smart-e8872c19-9a7d-481c-b395-eeed46c3574b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141642756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.141642756
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1751795094
Short name T911
Test name
Test status
Simulation time 919678251 ps
CPU time 18.51 seconds
Started Jun 28 05:33:14 PM PDT 24
Finished Jun 28 05:33:33 PM PDT 24
Peak memory 241504 kb
Host smart-76a42690-9d6e-495d-bd8f-0c8b49c2c0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751795094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1751795094
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2260350821
Short name T276
Test name
Test status
Simulation time 795442393 ps
CPU time 16.33 seconds
Started Jun 28 05:33:08 PM PDT 24
Finished Jun 28 05:33:26 PM PDT 24
Peak memory 238404 kb
Host smart-c20c24b9-22bd-4291-ae55-4279e3ee422f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260350821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2260350821
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2960710308
Short name T268
Test name
Test status
Simulation time 4631230784 ps
CPU time 87.46 seconds
Started Jun 28 05:33:08 PM PDT 24
Finished Jun 28 05:34:38 PM PDT 24
Peak memory 253652 kb
Host smart-9026a177-2d84-4dc0-9e84-7a5af80fffbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960710308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2960710308
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1339237658
Short name T932
Test name
Test status
Simulation time 283082743 ps
CPU time 5.46 seconds
Started Jun 28 05:33:09 PM PDT 24
Finished Jun 28 05:33:17 PM PDT 24
Peak memory 225012 kb
Host smart-b364d76c-a927-4b00-ac03-e141730eb671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339237658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1339237658
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3833850935
Short name T242
Test name
Test status
Simulation time 154942317 ps
CPU time 4.4 seconds
Started Jun 28 05:33:11 PM PDT 24
Finished Jun 28 05:33:17 PM PDT 24
Peak memory 233156 kb
Host smart-5ee02760-cdf0-4436-8186-667cf9019fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833850935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3833850935
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2968172629
Short name T577
Test name
Test status
Simulation time 3144503417 ps
CPU time 12.93 seconds
Started Jun 28 05:33:08 PM PDT 24
Finished Jun 28 05:33:22 PM PDT 24
Peak memory 249328 kb
Host smart-d1425e25-91fc-4b2b-9da5-94b9e800ef8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968172629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2968172629
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3501096761
Short name T795
Test name
Test status
Simulation time 75802821154 ps
CPU time 14.18 seconds
Started Jun 28 05:33:13 PM PDT 24
Finished Jun 28 05:33:28 PM PDT 24
Peak memory 233308 kb
Host smart-d036e2ae-6dbe-4367-9b8b-883a7797670c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501096761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3501096761
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.924148733
Short name T446
Test name
Test status
Simulation time 364608014 ps
CPU time 5.29 seconds
Started Jun 28 05:33:07 PM PDT 24
Finished Jun 28 05:33:13 PM PDT 24
Peak memory 223164 kb
Host smart-a1f0d751-56c7-4fa0-ad63-34b187d86fa2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=924148733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.924148733
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3279087787
Short name T60
Test name
Test status
Simulation time 26397985340 ps
CPU time 139.17 seconds
Started Jun 28 05:33:05 PM PDT 24
Finished Jun 28 05:35:24 PM PDT 24
Peak memory 264184 kb
Host smart-78c96339-861b-4e54-943c-15a5820b0582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279087787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3279087787
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2727243414
Short name T536
Test name
Test status
Simulation time 2508854355 ps
CPU time 21.67 seconds
Started Jun 28 05:33:09 PM PDT 24
Finished Jun 28 05:33:32 PM PDT 24
Peak memory 216956 kb
Host smart-765d45ba-2697-440e-8f0d-ca208c34182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727243414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2727243414
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.822824237
Short name T35
Test name
Test status
Simulation time 4154168313 ps
CPU time 3.41 seconds
Started Jun 28 05:33:09 PM PDT 24
Finished Jun 28 05:33:15 PM PDT 24
Peak memory 216928 kb
Host smart-cdc89d9a-4cfa-44f1-ad65-324ea4e52d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822824237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.822824237
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3657853821
Short name T327
Test name
Test status
Simulation time 267108930 ps
CPU time 4.4 seconds
Started Jun 28 05:33:08 PM PDT 24
Finished Jun 28 05:33:14 PM PDT 24
Peak memory 216824 kb
Host smart-26886bb0-1b90-4272-858d-109965bccc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657853821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3657853821
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.35565770
Short name T443
Test name
Test status
Simulation time 11329035 ps
CPU time 0.67 seconds
Started Jun 28 05:33:07 PM PDT 24
Finished Jun 28 05:33:08 PM PDT 24
Peak memory 206108 kb
Host smart-752a684c-a19a-4204-aeb7-dd8b0bfb00b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35565770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.35565770
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3229764320
Short name T798
Test name
Test status
Simulation time 1104571720 ps
CPU time 3.12 seconds
Started Jun 28 05:33:10 PM PDT 24
Finished Jun 28 05:33:15 PM PDT 24
Peak memory 225008 kb
Host smart-3d12d990-dd75-4203-a3d7-a0e293aa1573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229764320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3229764320
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1664707115
Short name T900
Test name
Test status
Simulation time 12324470 ps
CPU time 0.73 seconds
Started Jun 28 05:31:42 PM PDT 24
Finished Jun 28 05:31:43 PM PDT 24
Peak memory 205404 kb
Host smart-771b0b13-5c91-4caa-ba2c-eb1339262b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664707115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
664707115
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2309669751
Short name T354
Test name
Test status
Simulation time 440978427 ps
CPU time 4.48 seconds
Started Jun 28 05:31:40 PM PDT 24
Finished Jun 28 05:31:46 PM PDT 24
Peak memory 224912 kb
Host smart-d8027a77-4b16-47ab-8d73-ccd3602f5eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309669751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2309669751
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.128435432
Short name T761
Test name
Test status
Simulation time 14584067 ps
CPU time 0.79 seconds
Started Jun 28 05:31:37 PM PDT 24
Finished Jun 28 05:31:39 PM PDT 24
Peak memory 207060 kb
Host smart-21b43b3b-0f84-411b-a1e2-17b986cda0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128435432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.128435432
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2211421334
Short name T569
Test name
Test status
Simulation time 78546334322 ps
CPU time 380.43 seconds
Started Jun 28 05:31:42 PM PDT 24
Finished Jun 28 05:38:03 PM PDT 24
Peak memory 253124 kb
Host smart-94b926b2-1f9b-41ae-bb8f-fad9a7a1898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211421334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2211421334
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1548152829
Short name T284
Test name
Test status
Simulation time 43525528095 ps
CPU time 139.59 seconds
Started Jun 28 05:31:38 PM PDT 24
Finished Jun 28 05:33:59 PM PDT 24
Peak memory 241204 kb
Host smart-320ac55c-8ec0-4513-96e1-18d3909a3cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548152829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1548152829
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1992747034
Short name T625
Test name
Test status
Simulation time 7139246076 ps
CPU time 9.87 seconds
Started Jun 28 05:31:43 PM PDT 24
Finished Jun 28 05:31:54 PM PDT 24
Peak memory 233344 kb
Host smart-34db53dc-6935-4c55-9ef0-e82c1e0da68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992747034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1992747034
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1354522721
Short name T605
Test name
Test status
Simulation time 25816610763 ps
CPU time 48.56 seconds
Started Jun 28 05:31:40 PM PDT 24
Finished Jun 28 05:32:29 PM PDT 24
Peak memory 241524 kb
Host smart-86e8cf76-9950-44ab-ba06-ea3d3868238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354522721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1354522721
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1095231589
Short name T743
Test name
Test status
Simulation time 718412199 ps
CPU time 3.92 seconds
Started Jun 28 05:31:43 PM PDT 24
Finished Jun 28 05:31:48 PM PDT 24
Peak memory 232200 kb
Host smart-60706211-9295-400c-b542-e213b1da6912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095231589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1095231589
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.923468055
Short name T464
Test name
Test status
Simulation time 6889713472 ps
CPU time 36.95 seconds
Started Jun 28 05:31:41 PM PDT 24
Finished Jun 28 05:32:19 PM PDT 24
Peak memory 225076 kb
Host smart-9d3bd0e5-a052-4e83-a7ac-9b2dd8aff9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923468055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.923468055
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.365885172
Short name T214
Test name
Test status
Simulation time 2549880901 ps
CPU time 13.35 seconds
Started Jun 28 05:31:41 PM PDT 24
Finished Jun 28 05:31:55 PM PDT 24
Peak memory 225040 kb
Host smart-458f11e4-32f9-44c1-874e-948a4b42fe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365885172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
365885172
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3668640851
Short name T779
Test name
Test status
Simulation time 4934499228 ps
CPU time 5.33 seconds
Started Jun 28 05:31:39 PM PDT 24
Finished Jun 28 05:31:46 PM PDT 24
Peak memory 233340 kb
Host smart-72ae539c-4b3e-4d0d-86b2-be8c805fa9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668640851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3668640851
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4217265028
Short name T143
Test name
Test status
Simulation time 535527886 ps
CPU time 5.1 seconds
Started Jun 28 05:31:43 PM PDT 24
Finished Jun 28 05:31:49 PM PDT 24
Peak memory 222756 kb
Host smart-327878dd-a96d-45e8-9f8c-7607444aa700
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4217265028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4217265028
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3399319678
Short name T81
Test name
Test status
Simulation time 181627881 ps
CPU time 1.27 seconds
Started Jun 28 05:31:49 PM PDT 24
Finished Jun 28 05:31:50 PM PDT 24
Peak memory 236916 kb
Host smart-9a282929-1e64-4022-a713-5b77cf2c0c4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399319678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3399319678
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3047909422
Short name T764
Test name
Test status
Simulation time 16844078987 ps
CPU time 56.75 seconds
Started Jun 28 05:31:41 PM PDT 24
Finished Jun 28 05:32:39 PM PDT 24
Peak memory 252064 kb
Host smart-0013eb78-8d37-4ceb-bd40-b70c134821c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047909422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3047909422
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.358474062
Short name T505
Test name
Test status
Simulation time 21563190074 ps
CPU time 29.28 seconds
Started Jun 28 05:31:37 PM PDT 24
Finished Jun 28 05:32:08 PM PDT 24
Peak memory 216924 kb
Host smart-28b2420c-f2fe-4f1d-b163-acbfbcb3bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358474062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.358474062
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1700233254
Short name T351
Test name
Test status
Simulation time 847303087 ps
CPU time 1.99 seconds
Started Jun 28 05:31:39 PM PDT 24
Finished Jun 28 05:31:42 PM PDT 24
Peak memory 216584 kb
Host smart-34a288f3-9833-442c-901a-80020e241845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700233254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1700233254
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1580750899
Short name T844
Test name
Test status
Simulation time 43081348 ps
CPU time 0.85 seconds
Started Jun 28 05:31:41 PM PDT 24
Finished Jun 28 05:31:43 PM PDT 24
Peak memory 207516 kb
Host smart-95a1c8da-ee69-42fd-aeef-3c804f66cdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580750899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1580750899
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1753474618
Short name T632
Test name
Test status
Simulation time 23301792 ps
CPU time 0.81 seconds
Started Jun 28 05:31:35 PM PDT 24
Finished Jun 28 05:31:37 PM PDT 24
Peak memory 206436 kb
Host smart-085655a5-c42b-4cd5-94ae-bda4cb2b5248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753474618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1753474618
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3337208440
Short name T928
Test name
Test status
Simulation time 2866828866 ps
CPU time 6.43 seconds
Started Jun 28 05:31:43 PM PDT 24
Finished Jun 28 05:31:50 PM PDT 24
Peak memory 225152 kb
Host smart-705bc670-6296-458c-9120-01bc3791d0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337208440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3337208440
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1604352713
Short name T863
Test name
Test status
Simulation time 18145819 ps
CPU time 0.72 seconds
Started Jun 28 05:33:24 PM PDT 24
Finished Jun 28 05:33:25 PM PDT 24
Peak memory 205396 kb
Host smart-65a9dced-8463-4d75-b4c5-4b2ac30da9ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604352713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1604352713
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3832686264
Short name T355
Test name
Test status
Simulation time 1010726157 ps
CPU time 4.59 seconds
Started Jun 28 05:33:09 PM PDT 24
Finished Jun 28 05:33:16 PM PDT 24
Peak memory 233192 kb
Host smart-b208c93b-8397-43ab-8645-f08f619865a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832686264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3832686264
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3419498358
Short name T411
Test name
Test status
Simulation time 70143073 ps
CPU time 0.78 seconds
Started Jun 28 05:33:07 PM PDT 24
Finished Jun 28 05:33:09 PM PDT 24
Peak memory 207348 kb
Host smart-f95efdb3-ced9-4b0f-985d-e86e83f1d609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419498358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3419498358
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2532917745
Short name T826
Test name
Test status
Simulation time 6005144539 ps
CPU time 77.53 seconds
Started Jun 28 05:33:26 PM PDT 24
Finished Jun 28 05:34:45 PM PDT 24
Peak memory 257904 kb
Host smart-6934dde9-2326-45a5-b7c0-c4e913f9d371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532917745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2532917745
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.384650562
Short name T283
Test name
Test status
Simulation time 10285874644 ps
CPU time 90.9 seconds
Started Jun 28 05:33:24 PM PDT 24
Finished Jun 28 05:34:57 PM PDT 24
Peak memory 249868 kb
Host smart-46b0d8c6-9ddf-4aae-9cdc-bcfcdcd9a8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384650562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.384650562
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3865934248
Short name T570
Test name
Test status
Simulation time 1135238429 ps
CPU time 11.84 seconds
Started Jun 28 05:33:07 PM PDT 24
Finished Jun 28 05:33:20 PM PDT 24
Peak memory 233316 kb
Host smart-ebebcec3-d6ba-4752-a55e-d699852cb260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865934248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3865934248
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3188828027
Short name T100
Test name
Test status
Simulation time 3155209902 ps
CPU time 8.58 seconds
Started Jun 28 05:33:08 PM PDT 24
Finished Jun 28 05:33:19 PM PDT 24
Peak memory 225020 kb
Host smart-c1f84364-47d3-4b45-b420-6277c7c5b065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188828027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3188828027
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.249835991
Short name T608
Test name
Test status
Simulation time 845766885 ps
CPU time 11.27 seconds
Started Jun 28 05:33:11 PM PDT 24
Finished Jun 28 05:33:24 PM PDT 24
Peak memory 233172 kb
Host smart-a5c7d39d-73a4-4c38-863b-c179a56c2ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249835991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.249835991
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.4030770185
Short name T201
Test name
Test status
Simulation time 1920462736 ps
CPU time 8.01 seconds
Started Jun 28 05:33:10 PM PDT 24
Finished Jun 28 05:33:19 PM PDT 24
Peak memory 233156 kb
Host smart-577f3dc3-422f-496a-8c23-d255d8116ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030770185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.4030770185
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1956549547
Short name T674
Test name
Test status
Simulation time 2832149983 ps
CPU time 9.75 seconds
Started Jun 28 05:33:06 PM PDT 24
Finished Jun 28 05:33:17 PM PDT 24
Peak memory 233296 kb
Host smart-1d526066-8f04-45d4-8ae3-6106247d7524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956549547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1956549547
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.365629663
Short name T145
Test name
Test status
Simulation time 624578694 ps
CPU time 3.68 seconds
Started Jun 28 05:33:29 PM PDT 24
Finished Jun 28 05:33:33 PM PDT 24
Peak memory 220784 kb
Host smart-32ef73c7-0339-4b1e-885a-18212de2b4f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=365629663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.365629663
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1409223737
Short name T980
Test name
Test status
Simulation time 67520184147 ps
CPU time 191.62 seconds
Started Jun 28 05:33:25 PM PDT 24
Finished Jun 28 05:36:38 PM PDT 24
Peak memory 253388 kb
Host smart-9a8594a6-5bee-43d6-9d16-2317a875a3be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409223737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1409223737
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.326555324
Short name T33
Test name
Test status
Simulation time 4642599498 ps
CPU time 27.55 seconds
Started Jun 28 05:33:09 PM PDT 24
Finished Jun 28 05:33:39 PM PDT 24
Peak memory 216872 kb
Host smart-bad14f96-aa72-4b16-8616-d686d96afba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326555324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.326555324
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2565212049
Short name T829
Test name
Test status
Simulation time 9538788027 ps
CPU time 14.95 seconds
Started Jun 28 05:33:08 PM PDT 24
Finished Jun 28 05:33:25 PM PDT 24
Peak memory 216912 kb
Host smart-b25d6485-4ba1-4b23-bae1-72e8ffb187a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565212049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2565212049
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2727818402
Short name T302
Test name
Test status
Simulation time 24575560 ps
CPU time 0.76 seconds
Started Jun 28 05:33:08 PM PDT 24
Finished Jun 28 05:33:10 PM PDT 24
Peak memory 206364 kb
Host smart-c120caf4-55d9-430b-8499-36dc8dc58f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727818402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2727818402
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3892259389
Short name T748
Test name
Test status
Simulation time 115542431 ps
CPU time 0.88 seconds
Started Jun 28 05:33:11 PM PDT 24
Finished Jun 28 05:33:13 PM PDT 24
Peak memory 206456 kb
Host smart-561adb43-b193-450a-918f-52081b2c96fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892259389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3892259389
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.205903065
Short name T523
Test name
Test status
Simulation time 1613174296 ps
CPU time 14.23 seconds
Started Jun 28 05:33:11 PM PDT 24
Finished Jun 28 05:33:27 PM PDT 24
Peak memory 241416 kb
Host smart-f0f7e044-1a04-4816-bf0d-82400e5e1075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205903065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.205903065
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1827504779
Short name T420
Test name
Test status
Simulation time 44563963 ps
CPU time 0.74 seconds
Started Jun 28 05:33:25 PM PDT 24
Finished Jun 28 05:33:27 PM PDT 24
Peak memory 205948 kb
Host smart-9a64d148-0c2f-4ea0-8985-7a761a8f17aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827504779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1827504779
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2593368637
Short name T747
Test name
Test status
Simulation time 114371451 ps
CPU time 2.3 seconds
Started Jun 28 05:33:24 PM PDT 24
Finished Jun 28 05:33:27 PM PDT 24
Peak memory 223580 kb
Host smart-654ea01c-dac1-4b7b-8ff5-94c591407460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593368637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2593368637
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2069368884
Short name T923
Test name
Test status
Simulation time 19409107 ps
CPU time 0.78 seconds
Started Jun 28 05:33:24 PM PDT 24
Finished Jun 28 05:33:27 PM PDT 24
Peak memory 207092 kb
Host smart-56695021-b1a1-41ef-b13a-0fcd2efcae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069368884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2069368884
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1391417882
Short name T556
Test name
Test status
Simulation time 12837261822 ps
CPU time 34.91 seconds
Started Jun 28 05:33:25 PM PDT 24
Finished Jun 28 05:34:01 PM PDT 24
Peak memory 241524 kb
Host smart-8db89e5e-cd92-4d6b-beb0-cb6e8f330792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391417882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1391417882
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3319788547
Short name T58
Test name
Test status
Simulation time 67600781201 ps
CPU time 354.71 seconds
Started Jun 28 05:33:23 PM PDT 24
Finished Jun 28 05:39:19 PM PDT 24
Peak memory 256948 kb
Host smart-a1e61728-f81b-4e56-9328-2ade5fa4b94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319788547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3319788547
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3158757033
Short name T68
Test name
Test status
Simulation time 138676680131 ps
CPU time 349.95 seconds
Started Jun 28 05:33:26 PM PDT 24
Finished Jun 28 05:39:18 PM PDT 24
Peak memory 250172 kb
Host smart-5e27d56f-7acc-4351-9aa2-56759df78215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158757033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3158757033
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3310983812
Short name T475
Test name
Test status
Simulation time 1909093240 ps
CPU time 15.74 seconds
Started Jun 28 05:33:24 PM PDT 24
Finished Jun 28 05:33:41 PM PDT 24
Peak memory 237532 kb
Host smart-bb333fb3-68b6-46f6-ae14-1a53e3f2bfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310983812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3310983812
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1466959297
Short name T407
Test name
Test status
Simulation time 461591848 ps
CPU time 3.92 seconds
Started Jun 28 05:33:24 PM PDT 24
Finished Jun 28 05:33:29 PM PDT 24
Peak memory 233232 kb
Host smart-95c3670b-5019-43ba-a2c1-09041a66e74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466959297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1466959297
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3475185253
Short name T663
Test name
Test status
Simulation time 4505098227 ps
CPU time 44.16 seconds
Started Jun 28 05:33:24 PM PDT 24
Finished Jun 28 05:34:10 PM PDT 24
Peak memory 233308 kb
Host smart-484de1ee-ecf6-4cb5-a2f3-90ecabef000b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475185253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3475185253
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1263145206
Short name T11
Test name
Test status
Simulation time 6150471456 ps
CPU time 8.39 seconds
Started Jun 28 05:33:29 PM PDT 24
Finished Jun 28 05:33:38 PM PDT 24
Peak memory 233308 kb
Host smart-2757d1a9-6d30-4d40-a95e-b6824d2c00c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263145206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1263145206
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4107671767
Short name T337
Test name
Test status
Simulation time 1015673794 ps
CPU time 7.31 seconds
Started Jun 28 05:33:27 PM PDT 24
Finished Jun 28 05:33:35 PM PDT 24
Peak memory 233128 kb
Host smart-1b26d68c-bbdd-43e5-accd-9fc9d153e463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107671767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4107671767
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3881903322
Short name T342
Test name
Test status
Simulation time 1433550549 ps
CPU time 7.35 seconds
Started Jun 28 05:33:26 PM PDT 24
Finished Jun 28 05:33:35 PM PDT 24
Peak memory 222012 kb
Host smart-97f37df2-ed8c-4c32-b6d3-cd035c30df98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3881903322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3881903322
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3582721496
Short name T539
Test name
Test status
Simulation time 55405715 ps
CPU time 1.06 seconds
Started Jun 28 05:33:26 PM PDT 24
Finished Jun 28 05:33:29 PM PDT 24
Peak memory 207704 kb
Host smart-45425b2d-ae39-4814-aa9c-a6a2bfe80ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582721496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3582721496
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3262635499
Short name T4
Test name
Test status
Simulation time 14875438 ps
CPU time 0.78 seconds
Started Jun 28 05:33:25 PM PDT 24
Finished Jun 28 05:33:27 PM PDT 24
Peak memory 206216 kb
Host smart-b17aeb2e-44a3-48ad-8b95-b2f998ca6d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262635499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3262635499
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2461252813
Short name T711
Test name
Test status
Simulation time 19209774037 ps
CPU time 3.73 seconds
Started Jun 28 05:33:23 PM PDT 24
Finished Jun 28 05:33:27 PM PDT 24
Peak memory 217036 kb
Host smart-120adc8a-86c7-4984-a627-e68a4a16ce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461252813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2461252813
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1247016947
Short name T955
Test name
Test status
Simulation time 67918886 ps
CPU time 0.95 seconds
Started Jun 28 05:33:25 PM PDT 24
Finished Jun 28 05:33:28 PM PDT 24
Peak memory 207672 kb
Host smart-d31daab0-ea5b-4ad2-8907-c937c4166ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247016947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1247016947
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1668973249
Short name T301
Test name
Test status
Simulation time 97428211 ps
CPU time 0.92 seconds
Started Jun 28 05:33:26 PM PDT 24
Finished Jun 28 05:33:29 PM PDT 24
Peak memory 206384 kb
Host smart-133ca87a-bddc-4afb-983a-52ef12773afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668973249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1668973249
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1902573165
Short name T368
Test name
Test status
Simulation time 58529968 ps
CPU time 2.09 seconds
Started Jun 28 05:33:28 PM PDT 24
Finished Jun 28 05:33:31 PM PDT 24
Peak memory 224808 kb
Host smart-1970138b-ca76-487d-a234-3267045b9c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902573165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1902573165
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3319661431
Short name T628
Test name
Test status
Simulation time 13702089 ps
CPU time 0.76 seconds
Started Jun 28 05:33:28 PM PDT 24
Finished Jun 28 05:33:30 PM PDT 24
Peak memory 205404 kb
Host smart-fb2e4c7b-3f4f-420d-8bb3-9b4025f73fca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319661431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3319661431
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.4145360163
Short name T633
Test name
Test status
Simulation time 4201937046 ps
CPU time 12.05 seconds
Started Jun 28 05:33:26 PM PDT 24
Finished Jun 28 05:33:40 PM PDT 24
Peak memory 225236 kb
Host smart-037906b6-dde8-4327-9149-6feb78874cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145360163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.4145360163
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3883291779
Short name T483
Test name
Test status
Simulation time 37429222 ps
CPU time 0.83 seconds
Started Jun 28 05:33:28 PM PDT 24
Finished Jun 28 05:33:30 PM PDT 24
Peak memory 207080 kb
Host smart-8a4e08b0-05dd-477a-91cd-3233b48d874a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883291779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3883291779
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.4097775023
Short name T197
Test name
Test status
Simulation time 2599956013 ps
CPU time 59.85 seconds
Started Jun 28 05:33:26 PM PDT 24
Finished Jun 28 05:34:28 PM PDT 24
Peak memory 249880 kb
Host smart-e6c90797-4fcb-46f3-b1d9-17c001d4a005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097775023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.4097775023
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2982919077
Short name T931
Test name
Test status
Simulation time 40140555703 ps
CPU time 373.69 seconds
Started Jun 28 05:33:29 PM PDT 24
Finished Jun 28 05:39:43 PM PDT 24
Peak memory 252728 kb
Host smart-1bb4c25d-8035-4858-9d09-95b474860550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982919077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2982919077
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1384464497
Short name T271
Test name
Test status
Simulation time 37428711641 ps
CPU time 377.39 seconds
Started Jun 28 05:33:24 PM PDT 24
Finished Jun 28 05:39:43 PM PDT 24
Peak memory 254484 kb
Host smart-7e52f80f-5501-4a3c-88b1-031056290b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384464497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1384464497
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3183378300
Short name T279
Test name
Test status
Simulation time 175206311 ps
CPU time 6.79 seconds
Started Jun 28 05:33:25 PM PDT 24
Finished Jun 28 05:33:33 PM PDT 24
Peak memory 224948 kb
Host smart-14a67a61-c668-4edb-912a-3bd2f506d7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183378300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3183378300
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3831484150
Short name T6
Test name
Test status
Simulation time 27806322464 ps
CPU time 22.63 seconds
Started Jun 28 05:33:26 PM PDT 24
Finished Jun 28 05:33:50 PM PDT 24
Peak memory 225140 kb
Host smart-259211f5-7d92-4b34-8b3b-59c0c116facf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831484150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3831484150
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1072073943
Short name T516
Test name
Test status
Simulation time 15010022531 ps
CPU time 11.08 seconds
Started Jun 28 05:33:25 PM PDT 24
Finished Jun 28 05:33:38 PM PDT 24
Peak memory 233296 kb
Host smart-ea37eea4-5e68-4d2f-b5df-c0e67c24a992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072073943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1072073943
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1978523163
Short name T549
Test name
Test status
Simulation time 16534342784 ps
CPU time 39.36 seconds
Started Jun 28 05:33:23 PM PDT 24
Finished Jun 28 05:34:03 PM PDT 24
Peak memory 224960 kb
Host smart-f46a9c4e-49f0-42a7-bb46-2b72b43dac29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978523163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1978523163
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1841465871
Short name T428
Test name
Test status
Simulation time 816117806 ps
CPU time 4.02 seconds
Started Jun 28 05:33:27 PM PDT 24
Finished Jun 28 05:33:32 PM PDT 24
Peak memory 224932 kb
Host smart-4d47d16d-c8a7-4cb9-9ee4-964398a0d367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841465871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1841465871
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.13082157
Short name T687
Test name
Test status
Simulation time 3724872756 ps
CPU time 5.06 seconds
Started Jun 28 05:33:24 PM PDT 24
Finished Jun 28 05:33:31 PM PDT 24
Peak memory 225140 kb
Host smart-d008e79f-1709-49c9-ad32-af2e93bb7dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13082157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.13082157
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2285763298
Short name T349
Test name
Test status
Simulation time 13786090270 ps
CPU time 8.99 seconds
Started Jun 28 05:33:29 PM PDT 24
Finished Jun 28 05:33:39 PM PDT 24
Peak memory 223368 kb
Host smart-300a925a-e009-4674-97b3-c594470bc69a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2285763298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2285763298
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3792721455
Short name T486
Test name
Test status
Simulation time 5463901158 ps
CPU time 75.65 seconds
Started Jun 28 05:33:27 PM PDT 24
Finished Jun 28 05:34:44 PM PDT 24
Peak memory 259864 kb
Host smart-4f1f283c-28ff-4358-b8ce-88be2dc1e080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792721455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3792721455
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3122309260
Short name T346
Test name
Test status
Simulation time 68853260547 ps
CPU time 52.86 seconds
Started Jun 28 05:33:24 PM PDT 24
Finished Jun 28 05:34:18 PM PDT 24
Peak memory 216900 kb
Host smart-1341171d-3be1-4f09-a210-e6406a519826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122309260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3122309260
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2667869350
Short name T583
Test name
Test status
Simulation time 476275184 ps
CPU time 4.26 seconds
Started Jun 28 05:33:27 PM PDT 24
Finished Jun 28 05:33:32 PM PDT 24
Peak memory 216776 kb
Host smart-ef9b0510-ac49-48e4-b786-2c818d9ac22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667869350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2667869350
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1934037975
Short name T940
Test name
Test status
Simulation time 45838601 ps
CPU time 0.78 seconds
Started Jun 28 05:33:25 PM PDT 24
Finished Jun 28 05:33:27 PM PDT 24
Peak memory 206464 kb
Host smart-33252901-f68c-4488-b24d-2fcc65db88fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934037975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1934037975
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.752311990
Short name T805
Test name
Test status
Simulation time 172216383 ps
CPU time 0.88 seconds
Started Jun 28 05:33:27 PM PDT 24
Finished Jun 28 05:33:29 PM PDT 24
Peak memory 206432 kb
Host smart-c6343fca-37a8-42f5-bd94-eb71f1eb76ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752311990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.752311990
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.4029371387
Short name T726
Test name
Test status
Simulation time 905006696 ps
CPU time 8.03 seconds
Started Jun 28 05:33:24 PM PDT 24
Finished Jun 28 05:33:32 PM PDT 24
Peak memory 233196 kb
Host smart-a3e929e5-6454-48b8-805b-8b374987401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029371387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4029371387
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.836578206
Short name T912
Test name
Test status
Simulation time 57220293 ps
CPU time 0.75 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:33:40 PM PDT 24
Peak memory 205868 kb
Host smart-2c5a4757-e261-4a22-a516-0db34955012c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836578206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.836578206
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1017407147
Short name T310
Test name
Test status
Simulation time 129342910 ps
CPU time 0.77 seconds
Started Jun 28 05:33:24 PM PDT 24
Finished Jun 28 05:33:27 PM PDT 24
Peak memory 206056 kb
Host smart-1e6c838e-16c5-4429-9a58-93464514964e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017407147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1017407147
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2607212769
Short name T185
Test name
Test status
Simulation time 22759439508 ps
CPU time 67.91 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:34:46 PM PDT 24
Peak memory 241500 kb
Host smart-49761ed5-6735-4731-bd6c-17286183856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607212769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2607212769
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.748708779
Short name T141
Test name
Test status
Simulation time 7605882781 ps
CPU time 136.44 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:35:54 PM PDT 24
Peak memory 267480 kb
Host smart-6b08cbc0-2369-46d3-adcc-f6e1d0618c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748708779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.748708779
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1221040513
Short name T752
Test name
Test status
Simulation time 19301078903 ps
CPU time 203.87 seconds
Started Jun 28 05:33:35 PM PDT 24
Finished Jun 28 05:36:59 PM PDT 24
Peak memory 250972 kb
Host smart-438e201c-2ff4-4918-bb42-5b460990cb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221040513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1221040513
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2445660640
Short name T953
Test name
Test status
Simulation time 145154815 ps
CPU time 2.75 seconds
Started Jun 28 05:33:39 PM PDT 24
Finished Jun 28 05:33:44 PM PDT 24
Peak memory 233196 kb
Host smart-6ae0ecbd-65ab-4232-8588-ca7db550e583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445660640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2445660640
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2084689588
Short name T833
Test name
Test status
Simulation time 22440228621 ps
CPU time 73.88 seconds
Started Jun 28 05:33:36 PM PDT 24
Finished Jun 28 05:34:50 PM PDT 24
Peak memory 250508 kb
Host smart-4e0e57bd-1b68-4dd9-898e-f8b56344d2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084689588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2084689588
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4257081725
Short name T386
Test name
Test status
Simulation time 10630831951 ps
CPU time 39.48 seconds
Started Jun 28 05:33:41 PM PDT 24
Finished Jun 28 05:34:22 PM PDT 24
Peak memory 224984 kb
Host smart-19f7eebf-fe04-4701-a621-eb54a408423e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257081725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4257081725
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2584734323
Short name T799
Test name
Test status
Simulation time 1492677125 ps
CPU time 20.11 seconds
Started Jun 28 05:33:40 PM PDT 24
Finished Jun 28 05:34:02 PM PDT 24
Peak memory 240128 kb
Host smart-68207ead-6d87-458d-9e6e-df7c6075f5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584734323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2584734323
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.887914401
Short name T734
Test name
Test status
Simulation time 172767154 ps
CPU time 2.28 seconds
Started Jun 28 05:33:41 PM PDT 24
Finished Jun 28 05:33:46 PM PDT 24
Peak memory 224724 kb
Host smart-f255f4d4-614d-474e-8738-eebc8e051ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887914401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.887914401
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3118975445
Short name T617
Test name
Test status
Simulation time 6023517415 ps
CPU time 22.26 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:34:01 PM PDT 24
Peak memory 249664 kb
Host smart-622398a9-20ed-445d-a69a-ba56f3d11dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118975445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3118975445
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3408571159
Short name T789
Test name
Test status
Simulation time 7021535093 ps
CPU time 15.9 seconds
Started Jun 28 05:33:39 PM PDT 24
Finished Jun 28 05:33:58 PM PDT 24
Peak memory 223624 kb
Host smart-02b0578c-41c1-45e9-ae81-429c7c3ee087
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3408571159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3408571159
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.605136368
Short name T270
Test name
Test status
Simulation time 9131531342 ps
CPU time 110.56 seconds
Started Jun 28 05:33:42 PM PDT 24
Finished Jun 28 05:35:34 PM PDT 24
Peak memory 267416 kb
Host smart-9e88fc2b-3a28-4975-9e62-773665dfe74d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605136368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.605136368
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4109817731
Short name T297
Test name
Test status
Simulation time 845559780 ps
CPU time 2.56 seconds
Started Jun 28 05:33:24 PM PDT 24
Finished Jun 28 05:33:28 PM PDT 24
Peak memory 217116 kb
Host smart-8c2924c7-7379-4941-b71c-0a79864a2451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109817731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4109817731
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1015858848
Short name T547
Test name
Test status
Simulation time 1998706095 ps
CPU time 3.24 seconds
Started Jun 28 05:33:25 PM PDT 24
Finished Jun 28 05:33:30 PM PDT 24
Peak memory 216832 kb
Host smart-936b991c-580f-4b04-a876-f2cc5d0ebb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015858848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1015858848
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2114833700
Short name T304
Test name
Test status
Simulation time 45362452 ps
CPU time 1.15 seconds
Started Jun 28 05:33:39 PM PDT 24
Finished Jun 28 05:33:42 PM PDT 24
Peak memory 208388 kb
Host smart-937de429-5cb7-4390-afbb-8a415e8d36fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114833700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2114833700
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.103450816
Short name T918
Test name
Test status
Simulation time 48534955 ps
CPU time 0.88 seconds
Started Jun 28 05:33:25 PM PDT 24
Finished Jun 28 05:33:28 PM PDT 24
Peak memory 206620 kb
Host smart-e90a12f5-cde4-4287-955f-1a7233bfb4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103450816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.103450816
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.653954627
Short name T232
Test name
Test status
Simulation time 205357844 ps
CPU time 3.84 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:33:42 PM PDT 24
Peak memory 233112 kb
Host smart-c45941a7-72b9-4779-8dde-87b6f2e69af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653954627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.653954627
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3862760178
Short name T913
Test name
Test status
Simulation time 109172564 ps
CPU time 0.73 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:33:39 PM PDT 24
Peak memory 205400 kb
Host smart-bd8d715b-1259-46b0-a9bc-461de209119b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862760178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3862760178
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1669331670
Short name T873
Test name
Test status
Simulation time 186387347 ps
CPU time 2.97 seconds
Started Jun 28 05:33:40 PM PDT 24
Finished Jun 28 05:33:45 PM PDT 24
Peak memory 233180 kb
Host smart-c08db0e3-4bd5-475f-bc3a-19e6241394ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669331670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1669331670
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1645411484
Short name T24
Test name
Test status
Simulation time 13013505 ps
CPU time 0.77 seconds
Started Jun 28 05:33:39 PM PDT 24
Finished Jun 28 05:33:42 PM PDT 24
Peak memory 206400 kb
Host smart-54f51037-873c-4ab7-98b6-7b6925927172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645411484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1645411484
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2430665021
Short name T971
Test name
Test status
Simulation time 81302129302 ps
CPU time 566.56 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:43:05 PM PDT 24
Peak memory 265004 kb
Host smart-f6d7aeac-8b32-45d3-9658-e3e111086c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430665021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2430665021
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3052749060
Short name T289
Test name
Test status
Simulation time 28591565114 ps
CPU time 60.88 seconds
Started Jun 28 05:33:42 PM PDT 24
Finished Jun 28 05:34:45 PM PDT 24
Peak memory 225180 kb
Host smart-bd24aff8-672c-4a42-8923-dce5f95b59bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052749060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3052749060
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1607207552
Short name T698
Test name
Test status
Simulation time 4828614499 ps
CPU time 138.69 seconds
Started Jun 28 05:33:40 PM PDT 24
Finished Jun 28 05:36:01 PM PDT 24
Peak memory 274364 kb
Host smart-94779cd3-cfc4-4b72-916e-242c8e7a1340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607207552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1607207552
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1692496245
Short name T425
Test name
Test status
Simulation time 185062625 ps
CPU time 4.05 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:33:43 PM PDT 24
Peak memory 233132 kb
Host smart-c4d4eaa4-fbb1-462c-b99e-bf649ce10349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692496245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1692496245
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3503301753
Short name T848
Test name
Test status
Simulation time 3308317101 ps
CPU time 79.66 seconds
Started Jun 28 05:33:35 PM PDT 24
Finished Jun 28 05:34:56 PM PDT 24
Peak memory 266108 kb
Host smart-23e52410-b338-409a-b297-53a4028acaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503301753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3503301753
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1693189941
Short name T694
Test name
Test status
Simulation time 1792579029 ps
CPU time 22.63 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:34:01 PM PDT 24
Peak memory 233180 kb
Host smart-6b10986d-17f9-4d16-86fd-1de2f6721731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693189941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1693189941
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2716451569
Short name T756
Test name
Test status
Simulation time 747644411 ps
CPU time 9.48 seconds
Started Jun 28 05:33:41 PM PDT 24
Finished Jun 28 05:33:53 PM PDT 24
Peak memory 234208 kb
Host smart-ecef07a1-b012-4b25-9cb4-9cd7a82e7a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716451569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2716451569
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2330676781
Short name T885
Test name
Test status
Simulation time 9683373472 ps
CPU time 17.51 seconds
Started Jun 28 05:33:42 PM PDT 24
Finished Jun 28 05:34:02 PM PDT 24
Peak memory 233248 kb
Host smart-5d89bf34-6f45-42a6-824d-82358cd801e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330676781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2330676781
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3983342113
Short name T723
Test name
Test status
Simulation time 50140217974 ps
CPU time 28.59 seconds
Started Jun 28 05:33:41 PM PDT 24
Finished Jun 28 05:34:12 PM PDT 24
Peak memory 241096 kb
Host smart-20a7946d-bcdb-4c84-ab25-56a933a31ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983342113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3983342113
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3751402223
Short name T551
Test name
Test status
Simulation time 2697813838 ps
CPU time 9.5 seconds
Started Jun 28 05:33:42 PM PDT 24
Finished Jun 28 05:33:53 PM PDT 24
Peak memory 219324 kb
Host smart-0df0ef31-d25b-4c38-bc9a-c852ca17658c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3751402223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3751402223
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3662733267
Short name T263
Test name
Test status
Simulation time 27694607770 ps
CPU time 88.98 seconds
Started Jun 28 05:33:36 PM PDT 24
Finished Jun 28 05:35:05 PM PDT 24
Peak memory 249776 kb
Host smart-3452c557-3607-4e1c-a2b6-4a9208d27945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662733267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3662733267
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.562179665
Short name T571
Test name
Test status
Simulation time 444706818 ps
CPU time 5.78 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:33:44 PM PDT 24
Peak memory 216776 kb
Host smart-966b6aa5-0938-475b-8c04-d1f5aea7a36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562179665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.562179665
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1017190668
Short name T511
Test name
Test status
Simulation time 4482484935 ps
CPU time 5.15 seconds
Started Jun 28 05:33:42 PM PDT 24
Finished Jun 28 05:33:49 PM PDT 24
Peak memory 216960 kb
Host smart-f360d433-0966-48c4-8cda-4a10fac0bc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017190668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1017190668
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1934765744
Short name T295
Test name
Test status
Simulation time 192624255 ps
CPU time 2.1 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:33:40 PM PDT 24
Peak memory 216776 kb
Host smart-187a8cd0-84b2-495f-9b59-599d1b75e63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934765744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1934765744
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.890954315
Short name T731
Test name
Test status
Simulation time 41936949 ps
CPU time 0.74 seconds
Started Jun 28 05:33:36 PM PDT 24
Finished Jun 28 05:33:37 PM PDT 24
Peak memory 206480 kb
Host smart-13b60b25-874d-4af9-972f-e786be87c066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890954315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.890954315
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.545552549
Short name T927
Test name
Test status
Simulation time 2819622933 ps
CPU time 10.85 seconds
Started Jun 28 05:33:35 PM PDT 24
Finished Jun 28 05:33:46 PM PDT 24
Peak memory 233312 kb
Host smart-3d600214-0722-42a6-81ec-ec8b70dae4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545552549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.545552549
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.450489781
Short name T424
Test name
Test status
Simulation time 23520186 ps
CPU time 0.7 seconds
Started Jun 28 05:33:39 PM PDT 24
Finished Jun 28 05:33:41 PM PDT 24
Peak memory 205992 kb
Host smart-cfac3ee5-bad9-454c-a258-d69505c185ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450489781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.450489781
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.753380604
Short name T249
Test name
Test status
Simulation time 334434373 ps
CPU time 3.62 seconds
Started Jun 28 05:33:38 PM PDT 24
Finished Jun 28 05:33:44 PM PDT 24
Peak memory 233184 kb
Host smart-3924f9d7-4a14-4a99-967a-50f72c6320e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753380604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.753380604
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3501926749
Short name T895
Test name
Test status
Simulation time 152243705 ps
CPU time 0.83 seconds
Started Jun 28 05:33:39 PM PDT 24
Finished Jun 28 05:33:42 PM PDT 24
Peak memory 207420 kb
Host smart-092dbf5e-5e6b-41c1-9f59-bd10bad6de69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501926749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3501926749
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1833811961
Short name T619
Test name
Test status
Simulation time 6790986843 ps
CPU time 22.59 seconds
Started Jun 28 05:33:43 PM PDT 24
Finished Jun 28 05:34:07 PM PDT 24
Peak memory 225136 kb
Host smart-5e22773e-db4e-402b-9004-a9007d2ff235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833811961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1833811961
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.342494057
Short name T634
Test name
Test status
Simulation time 51998291552 ps
CPU time 76.58 seconds
Started Jun 28 05:33:36 PM PDT 24
Finished Jun 28 05:34:54 PM PDT 24
Peak memory 249852 kb
Host smart-66dee83d-7df8-4390-a6c4-877ec3d405b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342494057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.342494057
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1643540199
Short name T241
Test name
Test status
Simulation time 5975423254 ps
CPU time 56.86 seconds
Started Jun 28 05:33:41 PM PDT 24
Finished Jun 28 05:34:40 PM PDT 24
Peak memory 246640 kb
Host smart-c857a94f-c4c3-4426-9e74-40adfe5b3db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643540199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1643540199
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2280113927
Short name T273
Test name
Test status
Simulation time 435710738 ps
CPU time 7.39 seconds
Started Jun 28 05:33:38 PM PDT 24
Finished Jun 28 05:33:48 PM PDT 24
Peak memory 238484 kb
Host smart-92538c4c-0137-4770-9e28-cddf9c195772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280113927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2280113927
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.103508736
Short name T937
Test name
Test status
Simulation time 27177670696 ps
CPU time 120.58 seconds
Started Jun 28 05:33:41 PM PDT 24
Finished Jun 28 05:35:44 PM PDT 24
Peak memory 256304 kb
Host smart-01aad724-de10-4d25-ae3f-09425d1fdc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103508736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.103508736
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1701535147
Short name T202
Test name
Test status
Simulation time 8240230263 ps
CPU time 23.73 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:34:01 PM PDT 24
Peak memory 225136 kb
Host smart-3f40fc3b-07ed-4546-b33a-672260435afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701535147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1701535147
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3166866470
Short name T103
Test name
Test status
Simulation time 5100087017 ps
CPU time 27.21 seconds
Started Jun 28 05:33:38 PM PDT 24
Finished Jun 28 05:34:07 PM PDT 24
Peak memory 223276 kb
Host smart-6b32ebec-52c9-4187-b2e4-eff40bb74396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166866470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3166866470
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2604745640
Short name T653
Test name
Test status
Simulation time 1832404921 ps
CPU time 8.49 seconds
Started Jun 28 05:33:41 PM PDT 24
Finished Jun 28 05:33:52 PM PDT 24
Peak memory 240936 kb
Host smart-92a304fb-e7c6-40b5-8dc0-3775667984ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604745640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2604745640
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1488160025
Short name T323
Test name
Test status
Simulation time 18369501284 ps
CPU time 18.77 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:33:57 PM PDT 24
Peak memory 233360 kb
Host smart-fb3a6469-fe19-42c1-b07e-94629839e5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488160025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1488160025
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.230853145
Short name T810
Test name
Test status
Simulation time 212814308 ps
CPU time 4.03 seconds
Started Jun 28 05:33:40 PM PDT 24
Finished Jun 28 05:33:46 PM PDT 24
Peak memory 219268 kb
Host smart-73578390-51ce-476e-9a5e-38790cb237f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=230853145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.230853145
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2386085430
Short name T160
Test name
Test status
Simulation time 47357223660 ps
CPU time 426.92 seconds
Started Jun 28 05:33:40 PM PDT 24
Finished Jun 28 05:40:49 PM PDT 24
Peak memory 264824 kb
Host smart-c2a64a6f-30b5-42a2-9239-6b17cf074aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386085430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2386085430
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1750694986
Short name T313
Test name
Test status
Simulation time 24278885 ps
CPU time 0.69 seconds
Started Jun 28 05:33:36 PM PDT 24
Finished Jun 28 05:33:37 PM PDT 24
Peak memory 206240 kb
Host smart-859b4672-2214-4b59-9156-a5b7c7fc39f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750694986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1750694986
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1295146475
Short name T715
Test name
Test status
Simulation time 7858561430 ps
CPU time 4.07 seconds
Started Jun 28 05:33:41 PM PDT 24
Finished Jun 28 05:33:47 PM PDT 24
Peak memory 217732 kb
Host smart-02f22227-d960-4de2-908b-5e286cc2ccd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295146475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1295146475
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2056363052
Short name T696
Test name
Test status
Simulation time 29835476 ps
CPU time 0.91 seconds
Started Jun 28 05:33:39 PM PDT 24
Finished Jun 28 05:33:42 PM PDT 24
Peak memory 207464 kb
Host smart-73d86bda-8fe3-4e2e-a791-5c8baceaf9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056363052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2056363052
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1515200452
Short name T91
Test name
Test status
Simulation time 19620821 ps
CPU time 0.77 seconds
Started Jun 28 05:33:40 PM PDT 24
Finished Jun 28 05:33:43 PM PDT 24
Peak memory 206380 kb
Host smart-522c6e5b-125b-4c72-8e84-63483d03b126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515200452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1515200452
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.49446765
Short name T991
Test name
Test status
Simulation time 35055891891 ps
CPU time 39.02 seconds
Started Jun 28 05:33:42 PM PDT 24
Finished Jun 28 05:34:23 PM PDT 24
Peak memory 224988 kb
Host smart-242abb8f-dc7c-4f90-9d69-09a811d15257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49446765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.49446765
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2131025471
Short name T427
Test name
Test status
Simulation time 17300522 ps
CPU time 0.68 seconds
Started Jun 28 05:33:40 PM PDT 24
Finished Jun 28 05:33:43 PM PDT 24
Peak memory 206300 kb
Host smart-95ecac07-5735-486e-9a96-4ffb54cba11a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131025471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2131025471
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4210279891
Short name T12
Test name
Test status
Simulation time 66586287 ps
CPU time 2.71 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:33:41 PM PDT 24
Peak memory 225004 kb
Host smart-b6775041-6ef5-4bfe-9bdc-708addb0f5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210279891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4210279891
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1293369311
Short name T419
Test name
Test status
Simulation time 195008965 ps
CPU time 0.77 seconds
Started Jun 28 05:33:38 PM PDT 24
Finished Jun 28 05:33:41 PM PDT 24
Peak memory 206000 kb
Host smart-d9a970f8-5877-4f46-8560-3eb17c6eff65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293369311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1293369311
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1721777234
Short name T773
Test name
Test status
Simulation time 12692621494 ps
CPU time 52.2 seconds
Started Jun 28 05:33:39 PM PDT 24
Finished Jun 28 05:34:33 PM PDT 24
Peak memory 249740 kb
Host smart-0ccf8743-24b8-45e5-8fb3-8d63bf060167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721777234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1721777234
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.366629492
Short name T207
Test name
Test status
Simulation time 4339393987 ps
CPU time 41.1 seconds
Started Jun 28 05:33:41 PM PDT 24
Finished Jun 28 05:34:25 PM PDT 24
Peak memory 239752 kb
Host smart-ca6cb8a9-a7a0-4233-95f3-161baace8716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366629492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.366629492
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.4199021750
Short name T171
Test name
Test status
Simulation time 433852246635 ps
CPU time 572.24 seconds
Started Jun 28 05:33:39 PM PDT 24
Finished Jun 28 05:43:14 PM PDT 24
Peak memory 255548 kb
Host smart-458bbece-1288-4eaf-aba3-12ad713d8345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199021750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.4199021750
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4270027522
Short name T45
Test name
Test status
Simulation time 957216496 ps
CPU time 8.94 seconds
Started Jun 28 05:33:38 PM PDT 24
Finished Jun 28 05:33:48 PM PDT 24
Peak memory 225012 kb
Host smart-c77cf5c7-3665-4a39-be7d-25cb0b22964e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270027522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4270027522
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1835423732
Short name T101
Test name
Test status
Simulation time 42627583908 ps
CPU time 211.28 seconds
Started Jun 28 05:33:40 PM PDT 24
Finished Jun 28 05:37:13 PM PDT 24
Peak memory 274072 kb
Host smart-0c6f7e41-ceee-4cf2-ad42-aa29b6e87ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835423732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1835423732
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2031300909
Short name T602
Test name
Test status
Simulation time 475789034 ps
CPU time 2.49 seconds
Started Jun 28 05:33:36 PM PDT 24
Finished Jun 28 05:33:39 PM PDT 24
Peak memory 233160 kb
Host smart-93633cf3-d8ce-40ac-a2a6-9be638a47370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031300909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2031300909
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3690683910
Short name T910
Test name
Test status
Simulation time 728906971 ps
CPU time 16.35 seconds
Started Jun 28 05:33:40 PM PDT 24
Finished Jun 28 05:33:59 PM PDT 24
Peak memory 240316 kb
Host smart-75d81899-ab4c-4c20-a214-e9b691f236ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690683910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3690683910
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1321869635
Short name T53
Test name
Test status
Simulation time 115408814 ps
CPU time 2.45 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:33:41 PM PDT 24
Peak memory 233012 kb
Host smart-894330cf-cded-47c2-ad49-1cdd502234d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321869635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1321869635
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2634561956
Short name T717
Test name
Test status
Simulation time 17902377924 ps
CPU time 14.36 seconds
Started Jun 28 05:33:36 PM PDT 24
Finished Jun 28 05:33:51 PM PDT 24
Peak memory 225172 kb
Host smart-ee1c6445-71eb-4e31-ab02-8556d2890b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634561956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2634561956
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.4063478018
Short name T434
Test name
Test status
Simulation time 7766638371 ps
CPU time 11.68 seconds
Started Jun 28 05:33:39 PM PDT 24
Finished Jun 28 05:33:53 PM PDT 24
Peak memory 219952 kb
Host smart-70b967c6-436a-4b38-b869-d996ba7c78bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4063478018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.4063478018
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3256107974
Short name T786
Test name
Test status
Simulation time 51216770059 ps
CPU time 270.41 seconds
Started Jun 28 05:33:39 PM PDT 24
Finished Jun 28 05:38:11 PM PDT 24
Peak memory 266252 kb
Host smart-3dafd210-0bc5-4cf1-b4d2-3651130bf7ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256107974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3256107974
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1293160365
Short name T755
Test name
Test status
Simulation time 7089185651 ps
CPU time 25.4 seconds
Started Jun 28 05:33:37 PM PDT 24
Finished Jun 28 05:34:03 PM PDT 24
Peak memory 220896 kb
Host smart-47917050-8d9c-4159-b427-40a817860a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293160365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1293160365
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3114940973
Short name T348
Test name
Test status
Simulation time 4489349188 ps
CPU time 8.33 seconds
Started Jun 28 05:33:41 PM PDT 24
Finished Jun 28 05:33:51 PM PDT 24
Peak memory 216816 kb
Host smart-2235dee3-1d69-452b-b803-beb61be92b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114940973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3114940973
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3877748582
Short name T920
Test name
Test status
Simulation time 155393309 ps
CPU time 1.71 seconds
Started Jun 28 05:33:42 PM PDT 24
Finished Jun 28 05:33:46 PM PDT 24
Peak memory 216740 kb
Host smart-3aace6ed-ff13-47c4-88ea-361f71875512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877748582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3877748582
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2025533219
Short name T366
Test name
Test status
Simulation time 130391566 ps
CPU time 0.92 seconds
Started Jun 28 05:33:39 PM PDT 24
Finished Jun 28 05:33:42 PM PDT 24
Peak memory 206396 kb
Host smart-0c71505c-2482-48d2-9f93-15ebdfae6414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025533219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2025533219
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1396217355
Short name T451
Test name
Test status
Simulation time 633684115 ps
CPU time 6.53 seconds
Started Jun 28 05:33:42 PM PDT 24
Finished Jun 28 05:33:50 PM PDT 24
Peak memory 233160 kb
Host smart-aad5b60d-1346-424d-b1ec-b8feb59014c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396217355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1396217355
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4049779298
Short name T410
Test name
Test status
Simulation time 14188498 ps
CPU time 0.74 seconds
Started Jun 28 05:33:52 PM PDT 24
Finished Jun 28 05:33:53 PM PDT 24
Peak memory 205904 kb
Host smart-5d02f98c-8496-463e-a00c-72954298e3a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049779298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4049779298
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3883597959
Short name T531
Test name
Test status
Simulation time 40956499 ps
CPU time 2.53 seconds
Started Jun 28 05:33:50 PM PDT 24
Finished Jun 28 05:33:53 PM PDT 24
Peak memory 233192 kb
Host smart-6f5e0ce5-917d-46dc-a74a-80a77f4c0f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883597959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3883597959
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.421708264
Short name T36
Test name
Test status
Simulation time 17237219 ps
CPU time 0.76 seconds
Started Jun 28 05:33:39 PM PDT 24
Finished Jun 28 05:33:43 PM PDT 24
Peak memory 206056 kb
Host smart-dadf800f-4d6e-42d3-b490-191bede267f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421708264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.421708264
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.377749283
Short name T978
Test name
Test status
Simulation time 2701001863 ps
CPU time 53.98 seconds
Started Jun 28 05:33:52 PM PDT 24
Finished Jun 28 05:34:47 PM PDT 24
Peak memory 249720 kb
Host smart-b31041d4-7527-4970-92b4-4003899739be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377749283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.377749283
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3257949690
Short name T218
Test name
Test status
Simulation time 68772824032 ps
CPU time 359.96 seconds
Started Jun 28 05:33:57 PM PDT 24
Finished Jun 28 05:39:58 PM PDT 24
Peak memory 257776 kb
Host smart-0d5827cb-9cd0-4d9e-ba20-a8ef2a53ee22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257949690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3257949690
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3560888306
Short name T250
Test name
Test status
Simulation time 2326729542 ps
CPU time 53.34 seconds
Started Jun 28 05:33:49 PM PDT 24
Finished Jun 28 05:34:43 PM PDT 24
Peak memory 255816 kb
Host smart-e175824d-9f1e-4adf-9c67-dc7107cc3b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560888306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3560888306
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.407762859
Short name T275
Test name
Test status
Simulation time 3177647060 ps
CPU time 14.17 seconds
Started Jun 28 05:33:52 PM PDT 24
Finished Jun 28 05:34:07 PM PDT 24
Peak memory 233324 kb
Host smart-69ba8a48-4886-4ff9-9887-11f0e190030b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407762859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.407762859
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.967021167
Short name T558
Test name
Test status
Simulation time 7742547856 ps
CPU time 8.63 seconds
Started Jun 28 05:33:56 PM PDT 24
Finished Jun 28 05:34:05 PM PDT 24
Peak memory 233304 kb
Host smart-78977c6a-9a5a-45e9-966c-0ab9ff88c66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967021167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.967021167
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3087656211
Short name T231
Test name
Test status
Simulation time 1686886709 ps
CPU time 4.57 seconds
Started Jun 28 05:33:51 PM PDT 24
Finished Jun 28 05:33:56 PM PDT 24
Peak memory 224960 kb
Host smart-17ef733f-5e7d-42a0-929b-2f2433e1def2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087656211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3087656211
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4182985766
Short name T650
Test name
Test status
Simulation time 1497326782 ps
CPU time 5.4 seconds
Started Jun 28 05:33:48 PM PDT 24
Finished Jun 28 05:33:54 PM PDT 24
Peak memory 239944 kb
Host smart-6a0ff184-5cf9-4d1e-84da-02980436421a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182985766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4182985766
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.184510208
Short name T385
Test name
Test status
Simulation time 920919008 ps
CPU time 6.06 seconds
Started Jun 28 05:33:51 PM PDT 24
Finished Jun 28 05:33:58 PM PDT 24
Peak memory 240968 kb
Host smart-4612bac7-0e03-48a2-998f-62fc5506c167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184510208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.184510208
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3202132446
Short name T144
Test name
Test status
Simulation time 419801101 ps
CPU time 4.17 seconds
Started Jun 28 05:33:50 PM PDT 24
Finished Jun 28 05:33:55 PM PDT 24
Peak memory 223652 kb
Host smart-9dad9414-de97-48a0-83a9-8c8aed8983d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3202132446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3202132446
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1291953535
Short name T155
Test name
Test status
Simulation time 570814967222 ps
CPU time 244.51 seconds
Started Jun 28 05:33:47 PM PDT 24
Finished Jun 28 05:37:52 PM PDT 24
Peak memory 238596 kb
Host smart-f9cd38a4-9cad-428a-82af-9ad7ee4b0d83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291953535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1291953535
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3856367966
Short name T621
Test name
Test status
Simulation time 3663097421 ps
CPU time 32.49 seconds
Started Jun 28 05:33:47 PM PDT 24
Finished Jun 28 05:34:20 PM PDT 24
Peak memory 216800 kb
Host smart-abde5c40-c53c-4bb0-a498-220fd66014b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856367966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3856367966
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1134062852
Short name T534
Test name
Test status
Simulation time 34069685 ps
CPU time 0.72 seconds
Started Jun 28 05:33:40 PM PDT 24
Finished Jun 28 05:33:43 PM PDT 24
Peak memory 206188 kb
Host smart-6d3b4fc4-9eb4-41fd-a08b-604fcf47b7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134062852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1134062852
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3464185361
Short name T398
Test name
Test status
Simulation time 653261217 ps
CPU time 2.09 seconds
Started Jun 28 05:33:48 PM PDT 24
Finished Jun 28 05:33:51 PM PDT 24
Peak memory 216772 kb
Host smart-ddf8bed6-01bf-4ebd-b8a9-5bd529685239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464185361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3464185361
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4138231514
Short name T364
Test name
Test status
Simulation time 183550480 ps
CPU time 1.02 seconds
Started Jun 28 05:33:47 PM PDT 24
Finished Jun 28 05:33:49 PM PDT 24
Peak memory 207356 kb
Host smart-2f4ce490-1f36-451e-8edc-1c2b7441033f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138231514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4138231514
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2150910242
Short name T528
Test name
Test status
Simulation time 236857498 ps
CPU time 5.12 seconds
Started Jun 28 05:33:51 PM PDT 24
Finished Jun 28 05:33:57 PM PDT 24
Peak memory 233212 kb
Host smart-de183b7e-bc43-409e-8d07-fe409ee13d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150910242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2150910242
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2714020888
Short name T86
Test name
Test status
Simulation time 24804232 ps
CPU time 0.74 seconds
Started Jun 28 05:33:49 PM PDT 24
Finished Jun 28 05:33:51 PM PDT 24
Peak memory 206288 kb
Host smart-0b2ecaa6-d35e-4a41-a51f-ef4f577fe521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714020888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2714020888
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.4060318486
Short name T463
Test name
Test status
Simulation time 389852935 ps
CPU time 5.37 seconds
Started Jun 28 05:33:49 PM PDT 24
Finished Jun 28 05:33:55 PM PDT 24
Peak memory 224972 kb
Host smart-25e1bf5b-8fad-4a87-a863-17c914b44ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060318486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.4060318486
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2775732594
Short name T396
Test name
Test status
Simulation time 52066713 ps
CPU time 0.82 seconds
Started Jun 28 05:33:57 PM PDT 24
Finished Jun 28 05:33:58 PM PDT 24
Peak memory 206400 kb
Host smart-88e0e9cb-d511-4beb-8748-ada1a25908ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775732594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2775732594
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3073047487
Short name T194
Test name
Test status
Simulation time 13031643293 ps
CPU time 113.59 seconds
Started Jun 28 05:33:47 PM PDT 24
Finished Jun 28 05:35:41 PM PDT 24
Peak memory 239652 kb
Host smart-c462920f-e325-4237-8996-f0a6bf93f553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073047487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3073047487
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1536643871
Short name T688
Test name
Test status
Simulation time 311732895589 ps
CPU time 717.48 seconds
Started Jun 28 05:33:49 PM PDT 24
Finished Jun 28 05:45:47 PM PDT 24
Peak memory 265536 kb
Host smart-09257af5-45fa-450e-aef1-4d0469cf3b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536643871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1536643871
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2659773743
Short name T265
Test name
Test status
Simulation time 34937703911 ps
CPU time 135.47 seconds
Started Jun 28 05:33:50 PM PDT 24
Finished Jun 28 05:36:07 PM PDT 24
Peak memory 257000 kb
Host smart-8f3f2af0-6168-472f-aa1a-d0132cdee065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659773743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2659773743
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3112620312
Short name T280
Test name
Test status
Simulation time 335013065 ps
CPU time 11.87 seconds
Started Jun 28 05:33:54 PM PDT 24
Finished Jun 28 05:34:06 PM PDT 24
Peak memory 251080 kb
Host smart-9147719a-758c-4182-afbf-30af69ba4c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112620312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3112620312
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2653541038
Short name T992
Test name
Test status
Simulation time 9416402991 ps
CPU time 17.92 seconds
Started Jun 28 05:33:54 PM PDT 24
Finished Jun 28 05:34:13 PM PDT 24
Peak memory 238808 kb
Host smart-22437cb7-f0ef-4c8b-b659-c1f9b066b66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653541038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2653541038
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3896637104
Short name T642
Test name
Test status
Simulation time 7504020998 ps
CPU time 20.16 seconds
Started Jun 28 05:33:49 PM PDT 24
Finished Jun 28 05:34:10 PM PDT 24
Peak memory 225080 kb
Host smart-bf3923ef-0446-411d-9120-ccafa490a4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896637104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3896637104
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2968223321
Short name T526
Test name
Test status
Simulation time 737730634 ps
CPU time 8.09 seconds
Started Jun 28 05:33:49 PM PDT 24
Finished Jun 28 05:33:57 PM PDT 24
Peak memory 233160 kb
Host smart-fc6c8c12-971d-46ee-bd88-5f5246042997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968223321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2968223321
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1286585369
Short name T222
Test name
Test status
Simulation time 5193765967 ps
CPU time 14.55 seconds
Started Jun 28 05:33:46 PM PDT 24
Finished Jun 28 05:34:01 PM PDT 24
Peak memory 225080 kb
Host smart-1a35d32c-1f70-4955-b0fe-88e91af553d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286585369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1286585369
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.686051948
Short name T230
Test name
Test status
Simulation time 14581782788 ps
CPU time 15.02 seconds
Started Jun 28 05:33:46 PM PDT 24
Finished Jun 28 05:34:02 PM PDT 24
Peak memory 225152 kb
Host smart-08b81801-5af3-4141-8120-d03025ef0fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686051948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.686051948
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2071273551
Short name T433
Test name
Test status
Simulation time 3044302922 ps
CPU time 10.33 seconds
Started Jun 28 05:33:50 PM PDT 24
Finished Jun 28 05:34:01 PM PDT 24
Peak memory 223296 kb
Host smart-460abbfd-20e8-4755-a92d-2d81b96eaffa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2071273551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2071273551
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.222612085
Short name T18
Test name
Test status
Simulation time 6745539975 ps
CPU time 106.4 seconds
Started Jun 28 05:33:51 PM PDT 24
Finished Jun 28 05:35:38 PM PDT 24
Peak memory 251964 kb
Host smart-294a21a3-e05f-407d-aa77-8736242ec939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222612085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.222612085
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1527579324
Short name T515
Test name
Test status
Simulation time 3401319779 ps
CPU time 7.76 seconds
Started Jun 28 05:33:47 PM PDT 24
Finished Jun 28 05:33:55 PM PDT 24
Peak memory 216936 kb
Host smart-0c77fcb9-12fa-4592-99ba-cb44cdda19c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527579324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1527579324
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1598751689
Short name T787
Test name
Test status
Simulation time 4064955701 ps
CPU time 10.85 seconds
Started Jun 28 05:33:48 PM PDT 24
Finished Jun 28 05:34:00 PM PDT 24
Peak memory 216876 kb
Host smart-6e4e23e9-e935-4c68-a863-54161671a3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598751689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1598751689
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.820335852
Short name T585
Test name
Test status
Simulation time 16700198 ps
CPU time 0.81 seconds
Started Jun 28 05:33:51 PM PDT 24
Finished Jun 28 05:33:53 PM PDT 24
Peak memory 206472 kb
Host smart-f08a14e8-a1d9-459a-a320-8b3d36dde312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820335852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.820335852
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.934448116
Short name T306
Test name
Test status
Simulation time 138886006 ps
CPU time 0.8 seconds
Started Jun 28 05:33:46 PM PDT 24
Finished Jun 28 05:33:47 PM PDT 24
Peak memory 206392 kb
Host smart-0746ddc6-4d0b-4c2f-8027-9911d0154a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934448116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.934448116
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3431293429
Short name T719
Test name
Test status
Simulation time 879289460 ps
CPU time 2.17 seconds
Started Jun 28 05:33:50 PM PDT 24
Finished Jun 28 05:33:54 PM PDT 24
Peak memory 224792 kb
Host smart-c6b8db7e-7337-4a1b-b5a4-c24d905c9c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431293429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3431293429
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3191896526
Short name T341
Test name
Test status
Simulation time 38948935 ps
CPU time 0.74 seconds
Started Jun 28 05:33:59 PM PDT 24
Finished Jun 28 05:34:01 PM PDT 24
Peak memory 206292 kb
Host smart-ed599142-277d-49be-b676-62ee60825ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191896526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3191896526
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1997423921
Short name T438
Test name
Test status
Simulation time 142542043 ps
CPU time 2.65 seconds
Started Jun 28 05:34:01 PM PDT 24
Finished Jun 28 05:34:05 PM PDT 24
Peak memory 233204 kb
Host smart-4bf81ef7-2d52-47d7-85d2-a76915f4a671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997423921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1997423921
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1977606948
Short name T1001
Test name
Test status
Simulation time 55180777 ps
CPU time 0.76 seconds
Started Jun 28 05:33:50 PM PDT 24
Finished Jun 28 05:33:51 PM PDT 24
Peak memory 206396 kb
Host smart-a248c66f-76f3-48da-b31c-015e215ae69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977606948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1977606948
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.378371493
Short name T964
Test name
Test status
Simulation time 43985896197 ps
CPU time 161.25 seconds
Started Jun 28 05:34:02 PM PDT 24
Finished Jun 28 05:36:44 PM PDT 24
Peak memory 250276 kb
Host smart-01defa01-7a4a-4bd7-8ae2-d432a669cf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378371493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.378371493
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3088046323
Short name T204
Test name
Test status
Simulation time 58209345494 ps
CPU time 95.01 seconds
Started Jun 28 05:33:56 PM PDT 24
Finished Jun 28 05:35:31 PM PDT 24
Peak memory 249720 kb
Host smart-554e69e7-c310-460e-9499-b07b3c035ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088046323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3088046323
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2736406808
Short name T208
Test name
Test status
Simulation time 12229841691 ps
CPU time 94.75 seconds
Started Jun 28 05:33:58 PM PDT 24
Finished Jun 28 05:35:34 PM PDT 24
Peak memory 266404 kb
Host smart-77405659-48e3-41fc-b226-def336f287b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736406808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2736406808
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3266870985
Short name T796
Test name
Test status
Simulation time 14485918056 ps
CPU time 52.46 seconds
Started Jun 28 05:33:58 PM PDT 24
Finished Jun 28 05:34:52 PM PDT 24
Peak memory 249740 kb
Host smart-2ca78980-0349-4f39-a8ff-8e5a5745bb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266870985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3266870985
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1038686626
Short name T169
Test name
Test status
Simulation time 4410400784 ps
CPU time 54.02 seconds
Started Jun 28 05:33:58 PM PDT 24
Finished Jun 28 05:34:53 PM PDT 24
Peak memory 246380 kb
Host smart-8f90ac0e-2a5b-4758-8965-12a9af09e3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038686626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1038686626
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.94599334
Short name T219
Test name
Test status
Simulation time 10957275170 ps
CPU time 21.33 seconds
Started Jun 28 05:33:59 PM PDT 24
Finished Jun 28 05:34:22 PM PDT 24
Peak memory 233304 kb
Host smart-f78bf849-24db-4e45-8522-28d1f271798f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94599334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.94599334
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.485429597
Short name T458
Test name
Test status
Simulation time 31207690 ps
CPU time 1.96 seconds
Started Jun 28 05:34:03 PM PDT 24
Finished Jun 28 05:34:06 PM PDT 24
Peak memory 224736 kb
Host smart-6f46bee2-a651-48c8-98f6-05b81a30d798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485429597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.485429597
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2138603479
Short name T239
Test name
Test status
Simulation time 925055059 ps
CPU time 4.26 seconds
Started Jun 28 05:33:58 PM PDT 24
Finished Jun 28 05:34:04 PM PDT 24
Peak memory 224908 kb
Host smart-5e11ea85-9556-4436-a54a-e644c13f4ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138603479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2138603479
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1661375306
Short name T454
Test name
Test status
Simulation time 126639365 ps
CPU time 2.34 seconds
Started Jun 28 05:33:57 PM PDT 24
Finished Jun 28 05:34:00 PM PDT 24
Peak memory 225048 kb
Host smart-0d617de0-de5e-478b-9c02-88f22004bccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661375306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1661375306
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3572290687
Short name T519
Test name
Test status
Simulation time 405501511 ps
CPU time 6.1 seconds
Started Jun 28 05:33:58 PM PDT 24
Finished Jun 28 05:34:05 PM PDT 24
Peak memory 223440 kb
Host smart-e143aa9a-5357-41ea-bc75-c45a0db33aee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3572290687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3572290687
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.120594243
Short name T16
Test name
Test status
Simulation time 43423068 ps
CPU time 0.97 seconds
Started Jun 28 05:33:58 PM PDT 24
Finished Jun 28 05:34:00 PM PDT 24
Peak memory 207464 kb
Host smart-3b4b7e77-1d98-4518-98bc-fcbfea2d35ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120594243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.120594243
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2716900918
Short name T987
Test name
Test status
Simulation time 1269002873 ps
CPU time 21.14 seconds
Started Jun 28 05:33:57 PM PDT 24
Finished Jun 28 05:34:19 PM PDT 24
Peak memory 217220 kb
Host smart-cc9b1dd3-97f3-4116-98b2-67a0b08f8913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716900918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2716900918
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3665830881
Short name T801
Test name
Test status
Simulation time 5176819615 ps
CPU time 14.41 seconds
Started Jun 28 05:33:47 PM PDT 24
Finished Jun 28 05:34:02 PM PDT 24
Peak memory 217028 kb
Host smart-e53dba9a-2603-4f01-ac08-e665826cc2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665830881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3665830881
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.516774714
Short name T544
Test name
Test status
Simulation time 64292144 ps
CPU time 1.16 seconds
Started Jun 28 05:33:53 PM PDT 24
Finished Jun 28 05:33:54 PM PDT 24
Peak memory 216760 kb
Host smart-fd8f7743-746b-4141-ac39-c1e920a6b15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516774714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.516774714
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3364692224
Short name T553
Test name
Test status
Simulation time 79078491 ps
CPU time 1.03 seconds
Started Jun 28 05:33:52 PM PDT 24
Finished Jun 28 05:33:54 PM PDT 24
Peak memory 207412 kb
Host smart-62576b42-9802-4d3f-9cd2-2759e522d7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364692224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3364692224
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1702279031
Short name T609
Test name
Test status
Simulation time 1131494054 ps
CPU time 6.68 seconds
Started Jun 28 05:34:07 PM PDT 24
Finished Jun 28 05:34:15 PM PDT 24
Peak memory 224992 kb
Host smart-9b5e0d7d-6001-4178-a381-b234d676e0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702279031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1702279031
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1913748004
Short name T350
Test name
Test status
Simulation time 21797311 ps
CPU time 0.72 seconds
Started Jun 28 05:31:53 PM PDT 24
Finished Jun 28 05:31:54 PM PDT 24
Peak memory 205968 kb
Host smart-9fb09423-ba38-4503-b214-658879589e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913748004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
913748004
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3927445270
Short name T997
Test name
Test status
Simulation time 153885786 ps
CPU time 3.07 seconds
Started Jun 28 05:31:48 PM PDT 24
Finished Jun 28 05:31:51 PM PDT 24
Peak memory 224956 kb
Host smart-7708ae5b-1d45-4e1d-925b-86ba7b6f1076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927445270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3927445270
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1352181993
Short name T691
Test name
Test status
Simulation time 17753840 ps
CPU time 0.78 seconds
Started Jun 28 05:31:40 PM PDT 24
Finished Jun 28 05:31:42 PM PDT 24
Peak memory 207072 kb
Host smart-cecad897-34a5-4cf3-8fb4-ce191c798547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352181993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1352181993
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2277934584
Short name T435
Test name
Test status
Simulation time 1003462795 ps
CPU time 9.42 seconds
Started Jun 28 05:31:47 PM PDT 24
Finished Jun 28 05:31:57 PM PDT 24
Peak memory 237896 kb
Host smart-ac51fdbf-5476-4d23-9449-c00fb50bb712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277934584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2277934584
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2259753578
Short name T909
Test name
Test status
Simulation time 5513014550 ps
CPU time 78.53 seconds
Started Jun 28 05:31:48 PM PDT 24
Finished Jun 28 05:33:07 PM PDT 24
Peak memory 257908 kb
Host smart-980edda9-7ab5-47a8-872e-cbe0add32fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259753578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2259753578
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1216633900
Short name T862
Test name
Test status
Simulation time 41941723 ps
CPU time 0.79 seconds
Started Jun 28 05:31:50 PM PDT 24
Finished Jun 28 05:31:51 PM PDT 24
Peak memory 217652 kb
Host smart-b054ed34-33b2-43f0-a1c1-7c959412a2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216633900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1216633900
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1041192332
Short name T899
Test name
Test status
Simulation time 267286590 ps
CPU time 6.73 seconds
Started Jun 28 05:31:49 PM PDT 24
Finished Jun 28 05:31:56 PM PDT 24
Peak memory 225020 kb
Host smart-84166f95-96c6-4a54-9c6d-584044081c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041192332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1041192332
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3768778170
Short name T818
Test name
Test status
Simulation time 31523326 ps
CPU time 0.88 seconds
Started Jun 28 05:31:47 PM PDT 24
Finished Jun 28 05:31:48 PM PDT 24
Peak memory 216780 kb
Host smart-c09270e4-3a95-4a1a-9505-0ed65ac9d514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768778170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3768778170
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1070488867
Short name T574
Test name
Test status
Simulation time 2737716783 ps
CPU time 5.9 seconds
Started Jun 28 05:31:51 PM PDT 24
Finished Jun 28 05:31:58 PM PDT 24
Peak memory 225116 kb
Host smart-cbae87b8-9d79-4caa-b410-ac8372904bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070488867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1070488867
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.824419278
Short name T745
Test name
Test status
Simulation time 8714167482 ps
CPU time 22.67 seconds
Started Jun 28 05:31:53 PM PDT 24
Finished Jun 28 05:32:17 PM PDT 24
Peak memory 225084 kb
Host smart-c3ae4677-e2ee-4fef-92c3-17f8c00b5f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824419278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.824419278
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.337511155
Short name T533
Test name
Test status
Simulation time 74337434523 ps
CPU time 20.63 seconds
Started Jun 28 05:31:47 PM PDT 24
Finished Jun 28 05:32:09 PM PDT 24
Peak memory 241432 kb
Host smart-6c7daaea-847d-4767-8cd0-32622f9bbccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337511155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.337511155
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.40165667
Short name T416
Test name
Test status
Simulation time 4392247344 ps
CPU time 9.02 seconds
Started Jun 28 05:31:47 PM PDT 24
Finished Jun 28 05:31:57 PM PDT 24
Peak memory 221136 kb
Host smart-54b72b8e-6fd8-416e-88a4-49085ea34ea0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=40165667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct
.40165667
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.317509312
Short name T79
Test name
Test status
Simulation time 71430644 ps
CPU time 0.99 seconds
Started Jun 28 05:31:48 PM PDT 24
Finished Jun 28 05:31:50 PM PDT 24
Peak memory 236908 kb
Host smart-1a2c0557-79e4-46b7-9dcb-9dae223fc3b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317509312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.317509312
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.652451700
Short name T700
Test name
Test status
Simulation time 82521997 ps
CPU time 0.99 seconds
Started Jun 28 05:31:53 PM PDT 24
Finished Jun 28 05:31:55 PM PDT 24
Peak memory 207304 kb
Host smart-12ccbece-dca5-49d2-b336-44ce94ba2667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652451700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.652451700
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2425256000
Short name T949
Test name
Test status
Simulation time 1434512424 ps
CPU time 7.57 seconds
Started Jun 28 05:31:42 PM PDT 24
Finished Jun 28 05:31:50 PM PDT 24
Peak memory 219688 kb
Host smart-6fb0ac42-7c11-4ac6-a99a-a3278b14aec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425256000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2425256000
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3891952214
Short name T635
Test name
Test status
Simulation time 749665019 ps
CPU time 1.74 seconds
Started Jun 28 05:31:38 PM PDT 24
Finished Jun 28 05:31:41 PM PDT 24
Peak memory 216584 kb
Host smart-c58926ef-6f61-4ecc-ab41-ff263fbc397c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891952214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3891952214
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3752180044
Short name T827
Test name
Test status
Simulation time 600734055 ps
CPU time 1.56 seconds
Started Jun 28 05:31:54 PM PDT 24
Finished Jun 28 05:31:56 PM PDT 24
Peak memory 216680 kb
Host smart-fbf0bd4c-5f1f-410f-b075-d93d4eb5ee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752180044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3752180044
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.614257961
Short name T665
Test name
Test status
Simulation time 27991083 ps
CPU time 0.68 seconds
Started Jun 28 05:31:38 PM PDT 24
Finished Jun 28 05:31:40 PM PDT 24
Peak memory 206140 kb
Host smart-9bf5b5ec-1714-4d1b-8e2e-fb66a325bb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614257961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.614257961
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3911718863
Short name T70
Test name
Test status
Simulation time 28675203452 ps
CPU time 24.73 seconds
Started Jun 28 05:31:46 PM PDT 24
Finished Jun 28 05:32:11 PM PDT 24
Peak memory 225136 kb
Host smart-788e1325-d980-4bd2-90ae-a78491f32dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911718863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3911718863
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.170031725
Short name T465
Test name
Test status
Simulation time 23809058 ps
CPU time 0.73 seconds
Started Jun 28 05:34:01 PM PDT 24
Finished Jun 28 05:34:02 PM PDT 24
Peak memory 205944 kb
Host smart-ee65c1fe-9044-42f5-8b1d-23d3ae6f3be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170031725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.170031725
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2572501834
Short name T347
Test name
Test status
Simulation time 882140876 ps
CPU time 5.42 seconds
Started Jun 28 05:33:59 PM PDT 24
Finished Jun 28 05:34:05 PM PDT 24
Peak memory 233184 kb
Host smart-a14bee47-ee68-48f1-bcf1-1141516ff38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572501834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2572501834
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1131742762
Short name T629
Test name
Test status
Simulation time 19100791 ps
CPU time 0.82 seconds
Started Jun 28 05:33:57 PM PDT 24
Finished Jun 28 05:33:59 PM PDT 24
Peak memory 207060 kb
Host smart-f1deb5f5-4823-43f0-a4d6-19eb7eae4373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131742762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1131742762
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3272244678
Short name T66
Test name
Test status
Simulation time 59833131095 ps
CPU time 24.58 seconds
Started Jun 28 05:34:08 PM PDT 24
Finished Jun 28 05:34:33 PM PDT 24
Peak memory 241508 kb
Host smart-c567c447-714e-4a2b-a788-0d2b0c4df826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272244678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3272244678
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1666928186
Short name T272
Test name
Test status
Simulation time 11406029458 ps
CPU time 44.42 seconds
Started Jun 28 05:33:59 PM PDT 24
Finished Jun 28 05:34:45 PM PDT 24
Peak memory 249724 kb
Host smart-3789cf80-fe76-4b94-a830-c0ce23b3bb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666928186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1666928186
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2237196053
Short name T599
Test name
Test status
Simulation time 21311217893 ps
CPU time 61.36 seconds
Started Jun 28 05:33:59 PM PDT 24
Finished Jun 28 05:35:02 PM PDT 24
Peak memory 238884 kb
Host smart-f8982bab-5ffd-4097-b1c3-78c15fcdbb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237196053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2237196053
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.450353491
Short name T281
Test name
Test status
Simulation time 484755978 ps
CPU time 7.37 seconds
Started Jun 28 05:34:03 PM PDT 24
Finished Jun 28 05:34:12 PM PDT 24
Peak memory 241308 kb
Host smart-931ef827-5712-4bc0-ace7-737460ed21b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450353491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.450353491
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.772792605
Short name T200
Test name
Test status
Simulation time 52943255 ps
CPU time 3.17 seconds
Started Jun 28 05:33:59 PM PDT 24
Finished Jun 28 05:34:03 PM PDT 24
Peak memory 233144 kb
Host smart-0dd6f486-816d-4e30-8e8e-56b95c3952fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772792605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.772792605
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3118484401
Short name T646
Test name
Test status
Simulation time 18191053407 ps
CPU time 38.02 seconds
Started Jun 28 05:33:58 PM PDT 24
Finished Jun 28 05:34:37 PM PDT 24
Peak memory 225080 kb
Host smart-d03df408-9efe-47fa-8aa0-88b8ab626fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118484401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3118484401
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3648530555
Short name T612
Test name
Test status
Simulation time 203303579 ps
CPU time 2.99 seconds
Started Jun 28 05:33:58 PM PDT 24
Finished Jun 28 05:34:02 PM PDT 24
Peak memory 224956 kb
Host smart-9dc004ea-899e-4d85-8a6c-80cf6d78d498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648530555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3648530555
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2471114334
Short name T649
Test name
Test status
Simulation time 24628657851 ps
CPU time 37.43 seconds
Started Jun 28 05:33:58 PM PDT 24
Finished Jun 28 05:34:36 PM PDT 24
Peak memory 251228 kb
Host smart-5ca8144c-ca7f-4135-849a-c1253601a272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471114334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2471114334
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4229608129
Short name T514
Test name
Test status
Simulation time 4139311031 ps
CPU time 9.72 seconds
Started Jun 28 05:34:07 PM PDT 24
Finished Jun 28 05:34:17 PM PDT 24
Peak memory 223900 kb
Host smart-a5855c77-6915-45c1-a52c-9bc90e480a90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4229608129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4229608129
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3624261359
Short name T766
Test name
Test status
Simulation time 33707518599 ps
CPU time 281.35 seconds
Started Jun 28 05:34:07 PM PDT 24
Finished Jun 28 05:38:49 PM PDT 24
Peak memory 249832 kb
Host smart-9432dd5b-9df7-4b61-a917-f4bd7c88db4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624261359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3624261359
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.749168162
Short name T902
Test name
Test status
Simulation time 4700742449 ps
CPU time 14.7 seconds
Started Jun 28 05:33:59 PM PDT 24
Finished Jun 28 05:34:14 PM PDT 24
Peak memory 220556 kb
Host smart-b3eb05fa-cb54-44b0-90ee-17bc58293c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749168162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.749168162
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.306335729
Short name T363
Test name
Test status
Simulation time 470407863 ps
CPU time 2.37 seconds
Started Jun 28 05:33:57 PM PDT 24
Finished Jun 28 05:34:00 PM PDT 24
Peak memory 216684 kb
Host smart-d621261d-5f4e-40d3-829e-76613cb92972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306335729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.306335729
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.219562659
Short name T860
Test name
Test status
Simulation time 43158887 ps
CPU time 0.71 seconds
Started Jun 28 05:34:06 PM PDT 24
Finished Jun 28 05:34:08 PM PDT 24
Peak memory 206104 kb
Host smart-5149871c-d4b8-458e-9626-b33ac0835757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219562659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.219562659
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1208353349
Short name T415
Test name
Test status
Simulation time 76245486 ps
CPU time 1.01 seconds
Started Jun 28 05:33:59 PM PDT 24
Finished Jun 28 05:34:01 PM PDT 24
Peak memory 206712 kb
Host smart-75c82900-284a-427a-be5b-76d836dfb003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208353349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1208353349
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2646948513
Short name T601
Test name
Test status
Simulation time 10304783989 ps
CPU time 29.66 seconds
Started Jun 28 05:33:57 PM PDT 24
Finished Jun 28 05:34:28 PM PDT 24
Peak memory 233336 kb
Host smart-30afaa55-7353-4252-a69b-dda999ea3d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646948513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2646948513
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.80906667
Short name T811
Test name
Test status
Simulation time 114010405 ps
CPU time 0.72 seconds
Started Jun 28 05:34:12 PM PDT 24
Finished Jun 28 05:34:13 PM PDT 24
Peak memory 205384 kb
Host smart-d02a8e14-eab7-48e0-98a1-b3d2f0ee268f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80906667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.80906667
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1347189655
Short name T859
Test name
Test status
Simulation time 3840213975 ps
CPU time 9.43 seconds
Started Jun 28 05:34:07 PM PDT 24
Finished Jun 28 05:34:17 PM PDT 24
Peak memory 233340 kb
Host smart-a2f0053e-1491-4cb2-b360-52b3e0414429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347189655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1347189655
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2592225927
Short name T369
Test name
Test status
Simulation time 49533158 ps
CPU time 0.76 seconds
Started Jun 28 05:34:00 PM PDT 24
Finished Jun 28 05:34:01 PM PDT 24
Peak memory 207028 kb
Host smart-819bf85c-59b8-4b34-aa12-64d72a96225c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592225927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2592225927
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3344738548
Short name T343
Test name
Test status
Simulation time 33167559289 ps
CPU time 74.43 seconds
Started Jun 28 05:34:03 PM PDT 24
Finished Jun 28 05:35:18 PM PDT 24
Peak memory 233332 kb
Host smart-b0be9980-6a7b-4157-b2e4-579e0f0c266a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344738548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3344738548
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1534311246
Short name T210
Test name
Test status
Simulation time 35959833288 ps
CPU time 340.94 seconds
Started Jun 28 05:33:58 PM PDT 24
Finished Jun 28 05:39:40 PM PDT 24
Peak memory 257052 kb
Host smart-b94dff74-f0c1-47eb-86a5-3b78de260329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534311246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1534311246
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.517515658
Short name T174
Test name
Test status
Simulation time 18911853563 ps
CPU time 141.67 seconds
Started Jun 28 05:34:02 PM PDT 24
Finished Jun 28 05:36:25 PM PDT 24
Peak memory 249424 kb
Host smart-504d0691-ef6a-4ebe-b2a0-be6a0fb2751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517515658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.517515658
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4256707581
Short name T92
Test name
Test status
Simulation time 558870025 ps
CPU time 3.71 seconds
Started Jun 28 05:33:59 PM PDT 24
Finished Jun 28 05:34:04 PM PDT 24
Peak memory 233200 kb
Host smart-4d741343-1ef3-49d4-91e4-e32aba50dc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256707581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4256707581
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3329006229
Short name T527
Test name
Test status
Simulation time 13510168 ps
CPU time 0.76 seconds
Started Jun 28 05:34:01 PM PDT 24
Finished Jun 28 05:34:02 PM PDT 24
Peak memory 216372 kb
Host smart-fc92825e-d4e1-4c5b-afce-cc26eadf0bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329006229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3329006229
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4198222402
Short name T409
Test name
Test status
Simulation time 1016453014 ps
CPU time 4.86 seconds
Started Jun 28 05:33:59 PM PDT 24
Finished Jun 28 05:34:05 PM PDT 24
Peak memory 233160 kb
Host smart-1a8413d0-57d6-4de3-a308-37a827020a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198222402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4198222402
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2999332697
Short name T938
Test name
Test status
Simulation time 1921197239 ps
CPU time 21.33 seconds
Started Jun 28 05:34:04 PM PDT 24
Finished Jun 28 05:34:26 PM PDT 24
Peak memory 240088 kb
Host smart-70302dd6-f19f-43cb-bcb6-811165453d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999332697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2999332697
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3027210605
Short name T835
Test name
Test status
Simulation time 54390497 ps
CPU time 2.58 seconds
Started Jun 28 05:33:58 PM PDT 24
Finished Jun 28 05:34:02 PM PDT 24
Peak memory 232960 kb
Host smart-9d5a9c0d-2040-44b3-b5ce-1f0a9e7e9f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027210605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3027210605
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3035147697
Short name T487
Test name
Test status
Simulation time 2724940229 ps
CPU time 7.51 seconds
Started Jun 28 05:34:02 PM PDT 24
Finished Jun 28 05:34:10 PM PDT 24
Peak memory 225116 kb
Host smart-4b133b15-9e90-4827-b142-a0eb3cd23709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035147697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3035147697
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3185671661
Short name T445
Test name
Test status
Simulation time 221920231 ps
CPU time 4.99 seconds
Started Jun 28 05:33:58 PM PDT 24
Finished Jun 28 05:34:04 PM PDT 24
Peak memory 223564 kb
Host smart-19589e07-5322-4c60-a8d9-2c158352f056
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3185671661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3185671661
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2160562030
Short name T548
Test name
Test status
Simulation time 2071419045 ps
CPU time 22.76 seconds
Started Jun 28 05:34:02 PM PDT 24
Finished Jun 28 05:34:25 PM PDT 24
Peak memory 216752 kb
Host smart-a6e5d1b2-ee48-4107-b5cc-ed9bb97b8cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160562030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2160562030
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3386897458
Short name T292
Test name
Test status
Simulation time 13462732 ps
CPU time 0.72 seconds
Started Jun 28 05:33:59 PM PDT 24
Finished Jun 28 05:34:01 PM PDT 24
Peak memory 206188 kb
Host smart-eeeace47-b912-469c-bede-6a456894042d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386897458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3386897458
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3162968150
Short name T839
Test name
Test status
Simulation time 1250203674 ps
CPU time 4.21 seconds
Started Jun 28 05:34:00 PM PDT 24
Finished Jun 28 05:34:05 PM PDT 24
Peak memory 216724 kb
Host smart-e00379e0-7bdb-4b15-85c8-5368afa6c888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162968150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3162968150
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1896156618
Short name T659
Test name
Test status
Simulation time 77820784 ps
CPU time 0.88 seconds
Started Jun 28 05:33:58 PM PDT 24
Finished Jun 28 05:34:00 PM PDT 24
Peak memory 206464 kb
Host smart-7dc6c074-3014-48bf-a064-dca4264aa3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896156618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1896156618
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.707047532
Short name T390
Test name
Test status
Simulation time 1248464343 ps
CPU time 10.81 seconds
Started Jun 28 05:33:59 PM PDT 24
Finished Jun 28 05:34:11 PM PDT 24
Peak memory 241300 kb
Host smart-3cf3890a-4c3c-4c54-b056-1cde977766df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707047532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.707047532
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.665826116
Short name T367
Test name
Test status
Simulation time 18127441 ps
CPU time 0.73 seconds
Started Jun 28 05:34:08 PM PDT 24
Finished Jun 28 05:34:10 PM PDT 24
Peak memory 205332 kb
Host smart-2de3eab9-79be-40ca-a339-342482989f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665826116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.665826116
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2878861128
Short name T954
Test name
Test status
Simulation time 1512782828 ps
CPU time 3.56 seconds
Started Jun 28 05:34:08 PM PDT 24
Finished Jun 28 05:34:13 PM PDT 24
Peak memory 233192 kb
Host smart-45ca2943-b583-4dab-ad41-abbac8b6196e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878861128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2878861128
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1014184065
Short name T300
Test name
Test status
Simulation time 49612392 ps
CPU time 0.73 seconds
Started Jun 28 05:34:10 PM PDT 24
Finished Jun 28 05:34:11 PM PDT 24
Peak memory 206392 kb
Host smart-d8b3e344-1628-4c63-b7eb-121c42fd4f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014184065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1014184065
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2518980823
Short name T771
Test name
Test status
Simulation time 18780532703 ps
CPU time 90.13 seconds
Started Jun 28 05:34:07 PM PDT 24
Finished Jun 28 05:35:38 PM PDT 24
Peak memory 249792 kb
Host smart-a6768d0a-0b45-44ff-abfa-7def83d5e02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518980823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2518980823
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1448996889
Short name T740
Test name
Test status
Simulation time 114180752942 ps
CPU time 232.73 seconds
Started Jun 28 05:34:12 PM PDT 24
Finished Jun 28 05:38:05 PM PDT 24
Peak memory 249840 kb
Host smart-fd5935ff-c2bb-4bb7-873b-d0ecc003588c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448996889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1448996889
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.403599438
Short name T457
Test name
Test status
Simulation time 1258028627 ps
CPU time 20.3 seconds
Started Jun 28 05:34:09 PM PDT 24
Finished Jun 28 05:34:30 PM PDT 24
Peak memory 249620 kb
Host smart-3fe77f0d-be67-452e-b5de-1041e66ef2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403599438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.403599438
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3389630459
Short name T594
Test name
Test status
Simulation time 15657313 ps
CPU time 0.75 seconds
Started Jun 28 05:34:10 PM PDT 24
Finished Jun 28 05:34:11 PM PDT 24
Peak memory 216372 kb
Host smart-ce0313fc-e24b-4f49-afd1-96afd3d5016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389630459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3389630459
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2597243562
Short name T468
Test name
Test status
Simulation time 713794503 ps
CPU time 7.63 seconds
Started Jun 28 05:34:09 PM PDT 24
Finished Jun 28 05:34:18 PM PDT 24
Peak memory 224964 kb
Host smart-11b52d1c-930d-45fa-a052-c057866336c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597243562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2597243562
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1399675536
Short name T87
Test name
Test status
Simulation time 5332099476 ps
CPU time 22.6 seconds
Started Jun 28 05:34:09 PM PDT 24
Finished Jun 28 05:34:33 PM PDT 24
Peak memory 233268 kb
Host smart-52ed822b-45c4-493c-859f-ffd6b7085ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399675536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1399675536
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3051807332
Short name T237
Test name
Test status
Simulation time 21838461863 ps
CPU time 20.86 seconds
Started Jun 28 05:34:08 PM PDT 24
Finished Jun 28 05:34:30 PM PDT 24
Peak memory 225276 kb
Host smart-1670f513-1c92-4007-9956-e813ccd92bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051807332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3051807332
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1460540342
Short name T150
Test name
Test status
Simulation time 1391801079 ps
CPU time 3.84 seconds
Started Jun 28 05:34:08 PM PDT 24
Finished Jun 28 05:34:12 PM PDT 24
Peak memory 233084 kb
Host smart-8f1d2f27-a437-4cef-b2c5-1667cf8f4b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460540342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1460540342
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.754234170
Short name T506
Test name
Test status
Simulation time 2722731717 ps
CPU time 14.49 seconds
Started Jun 28 05:34:09 PM PDT 24
Finished Jun 28 05:34:24 PM PDT 24
Peak memory 223568 kb
Host smart-d58abcff-c73b-4aad-9299-d734ac1c8486
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=754234170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.754234170
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.37342815
Short name T290
Test name
Test status
Simulation time 36887017702 ps
CPU time 44.77 seconds
Started Jun 28 05:34:13 PM PDT 24
Finished Jun 28 05:34:59 PM PDT 24
Peak memory 216928 kb
Host smart-29650edd-ecfb-4d8f-acd0-bb492864213f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37342815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.37342815
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2087265867
Short name T735
Test name
Test status
Simulation time 3026732780 ps
CPU time 13.99 seconds
Started Jun 28 05:34:09 PM PDT 24
Finished Jun 28 05:34:24 PM PDT 24
Peak memory 216964 kb
Host smart-3a6b3ece-1a29-4523-adb9-0f521dd0c117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087265867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2087265867
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4252395497
Short name T530
Test name
Test status
Simulation time 52617456 ps
CPU time 1.65 seconds
Started Jun 28 05:34:10 PM PDT 24
Finished Jun 28 05:34:12 PM PDT 24
Peak memory 216800 kb
Host smart-ab270e01-31a5-4fa0-a060-752385a9d889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252395497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4252395497
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.493479981
Short name T298
Test name
Test status
Simulation time 46751345 ps
CPU time 0.84 seconds
Started Jun 28 05:34:09 PM PDT 24
Finished Jun 28 05:34:11 PM PDT 24
Peak memory 206432 kb
Host smart-9ee8daf9-12bc-43ae-a1a7-18f9c74ad74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493479981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.493479981
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1295447396
Short name T502
Test name
Test status
Simulation time 1514988201 ps
CPU time 7.26 seconds
Started Jun 28 05:34:13 PM PDT 24
Finished Jun 28 05:34:21 PM PDT 24
Peak memory 224932 kb
Host smart-3074e683-3b3d-4c89-9704-0fd4b32265fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295447396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1295447396
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3105565824
Short name T837
Test name
Test status
Simulation time 14157246 ps
CPU time 0.71 seconds
Started Jun 28 05:34:18 PM PDT 24
Finished Jun 28 05:34:20 PM PDT 24
Peak memory 205400 kb
Host smart-5a85a7fc-33e2-4a70-b90c-ee5757dfdef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105565824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3105565824
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.295566666
Short name T437
Test name
Test status
Simulation time 114595389 ps
CPU time 2.96 seconds
Started Jun 28 05:34:08 PM PDT 24
Finished Jun 28 05:34:12 PM PDT 24
Peak memory 233096 kb
Host smart-d1e64873-2b73-4277-8b3c-81f3988e7b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295566666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.295566666
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.853223299
Short name T296
Test name
Test status
Simulation time 49907658 ps
CPU time 0.78 seconds
Started Jun 28 05:34:07 PM PDT 24
Finished Jun 28 05:34:09 PM PDT 24
Peak memory 207388 kb
Host smart-c72c8e1d-f567-417b-95a0-3fa18418912b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853223299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.853223299
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3613562722
Short name T8
Test name
Test status
Simulation time 23543517174 ps
CPU time 181.14 seconds
Started Jun 28 05:34:09 PM PDT 24
Finished Jun 28 05:37:11 PM PDT 24
Peak memory 255272 kb
Host smart-8620f325-791d-40b0-bca7-c47ad1fe9f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613562722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3613562722
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1214633321
Short name T431
Test name
Test status
Simulation time 171201923265 ps
CPU time 242.93 seconds
Started Jun 28 05:34:22 PM PDT 24
Finished Jun 28 05:38:26 PM PDT 24
Peak memory 249948 kb
Host smart-ad7fb553-afd6-433b-be64-06f31f8df753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214633321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1214633321
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.480267529
Short name T999
Test name
Test status
Simulation time 988405109 ps
CPU time 17.52 seconds
Started Jun 28 05:34:09 PM PDT 24
Finished Jun 28 05:34:27 PM PDT 24
Peak memory 225020 kb
Host smart-67f9d35f-2826-478c-92c9-461906246a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480267529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.480267529
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.534167
Short name T221
Test name
Test status
Simulation time 476295906 ps
CPU time 6.97 seconds
Started Jun 28 05:34:10 PM PDT 24
Finished Jun 28 05:34:18 PM PDT 24
Peak memory 224952 kb
Host smart-573cc83a-5971-4545-98b7-4c9cc2d9ae61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.534167
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3045019986
Short name T970
Test name
Test status
Simulation time 12227449680 ps
CPU time 60.73 seconds
Started Jun 28 05:34:11 PM PDT 24
Finished Jun 28 05:35:12 PM PDT 24
Peak memory 233260 kb
Host smart-bdac21d5-d18e-457f-b0fa-04f81f6e80b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045019986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3045019986
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.871622077
Short name T788
Test name
Test status
Simulation time 3544024214 ps
CPU time 10.19 seconds
Started Jun 28 05:34:10 PM PDT 24
Finished Jun 28 05:34:21 PM PDT 24
Peak memory 233332 kb
Host smart-e5d8f116-cb43-49b6-99d9-b83caceabded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871622077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.871622077
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.298767853
Short name T557
Test name
Test status
Simulation time 1291957840 ps
CPU time 2.69 seconds
Started Jun 28 05:34:13 PM PDT 24
Finished Jun 28 05:34:16 PM PDT 24
Peak memory 233224 kb
Host smart-fb3525b2-122f-4e36-903d-f2dc5091ee38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298767853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.298767853
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2131385719
Short name T898
Test name
Test status
Simulation time 116845840 ps
CPU time 4.16 seconds
Started Jun 28 05:34:10 PM PDT 24
Finished Jun 28 05:34:15 PM PDT 24
Peak memory 220036 kb
Host smart-9c4232e2-2fcf-4899-bc6f-2fc94f39c0f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2131385719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2131385719
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3529664737
Short name T139
Test name
Test status
Simulation time 61421801348 ps
CPU time 164.88 seconds
Started Jun 28 05:34:23 PM PDT 24
Finished Jun 28 05:37:08 PM PDT 24
Peak memory 264788 kb
Host smart-9ddd807f-0330-43b1-8526-3271c056d255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529664737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3529664737
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3346635770
Short name T356
Test name
Test status
Simulation time 13559441922 ps
CPU time 22.8 seconds
Started Jun 28 05:34:08 PM PDT 24
Finished Jun 28 05:34:32 PM PDT 24
Peak memory 221040 kb
Host smart-a93c9628-5c7d-47bb-bf27-2b455b06c101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346635770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3346635770
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3641294059
Short name T872
Test name
Test status
Simulation time 13980556 ps
CPU time 0.74 seconds
Started Jun 28 05:34:08 PM PDT 24
Finished Jun 28 05:34:10 PM PDT 24
Peak memory 206188 kb
Host smart-b60acbed-71e6-4bde-a31a-0818cfa88ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641294059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3641294059
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.696845116
Short name T400
Test name
Test status
Simulation time 55787152 ps
CPU time 0.89 seconds
Started Jun 28 05:34:11 PM PDT 24
Finished Jun 28 05:34:12 PM PDT 24
Peak memory 208332 kb
Host smart-ad412eeb-c6b6-4c2c-afb7-3768828d1a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696845116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.696845116
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.992690279
Short name T97
Test name
Test status
Simulation time 37005727 ps
CPU time 0.86 seconds
Started Jun 28 05:34:10 PM PDT 24
Finished Jun 28 05:34:11 PM PDT 24
Peak memory 206640 kb
Host smart-db1eddf8-683f-42d2-882f-9c1659b46d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992690279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.992690279
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.385135680
Short name T880
Test name
Test status
Simulation time 2389867804 ps
CPU time 10.42 seconds
Started Jun 28 05:34:07 PM PDT 24
Finished Jun 28 05:34:18 PM PDT 24
Peak memory 233180 kb
Host smart-b05f0ee5-2866-4e1b-b766-cb56393fbe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385135680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.385135680
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3903731533
Short name T851
Test name
Test status
Simulation time 42644683 ps
CPU time 0.75 seconds
Started Jun 28 05:34:20 PM PDT 24
Finished Jun 28 05:34:21 PM PDT 24
Peak memory 205868 kb
Host smart-e9fbb302-cb93-4da4-b937-86cf821e8603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903731533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3903731533
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2807794531
Short name T26
Test name
Test status
Simulation time 6852691590 ps
CPU time 14.84 seconds
Started Jun 28 05:34:20 PM PDT 24
Finished Jun 28 05:34:36 PM PDT 24
Peak memory 233296 kb
Host smart-defbbd2b-1ea3-447d-ba4d-7a90e9ae3a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807794531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2807794531
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.400160585
Short name T89
Test name
Test status
Simulation time 263922452 ps
CPU time 0.75 seconds
Started Jun 28 05:34:19 PM PDT 24
Finished Jun 28 05:34:20 PM PDT 24
Peak memory 206052 kb
Host smart-03591e93-1f91-45ad-8762-32f5a4ee3e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400160585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.400160585
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.720555620
Short name T345
Test name
Test status
Simulation time 113709460273 ps
CPU time 109.62 seconds
Started Jun 28 05:34:23 PM PDT 24
Finished Jun 28 05:36:13 PM PDT 24
Peak memory 249832 kb
Host smart-fa35451a-c173-4c53-8680-774c819eb407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720555620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.720555620
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1970408765
Short name T251
Test name
Test status
Simulation time 221241352134 ps
CPU time 488.08 seconds
Started Jun 28 05:34:20 PM PDT 24
Finished Jun 28 05:42:29 PM PDT 24
Peak memory 267244 kb
Host smart-184eafda-650d-424c-9771-65c4e7ade1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970408765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1970408765
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.640119754
Short name T393
Test name
Test status
Simulation time 11389911288 ps
CPU time 31.78 seconds
Started Jun 28 05:34:19 PM PDT 24
Finished Jun 28 05:34:51 PM PDT 24
Peak memory 249348 kb
Host smart-ef9a3ff5-ab20-4755-a5fe-ebec6d368784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640119754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.640119754
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.234934595
Short name T542
Test name
Test status
Simulation time 1468653472 ps
CPU time 10.29 seconds
Started Jun 28 05:34:20 PM PDT 24
Finished Jun 28 05:34:32 PM PDT 24
Peak memory 224952 kb
Host smart-5a763cf6-199e-4529-8f44-a5a8db86c92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234934595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.234934595
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1864171743
Short name T664
Test name
Test status
Simulation time 3860632509 ps
CPU time 19.45 seconds
Started Jun 28 05:34:21 PM PDT 24
Finished Jun 28 05:34:41 PM PDT 24
Peak memory 225024 kb
Host smart-00ff67c9-8456-4205-98fe-7d3928486d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864171743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1864171743
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2142871044
Short name T234
Test name
Test status
Simulation time 332622872 ps
CPU time 2.68 seconds
Started Jun 28 05:34:21 PM PDT 24
Finished Jun 28 05:34:25 PM PDT 24
Peak memory 224956 kb
Host smart-7528087d-2cab-4088-a7d3-ecb739341285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142871044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2142871044
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2173275054
Short name T616
Test name
Test status
Simulation time 23170061892 ps
CPU time 34.19 seconds
Started Jun 28 05:34:19 PM PDT 24
Finished Jun 28 05:34:54 PM PDT 24
Peak memory 233340 kb
Host smart-d0cda200-6994-487c-8755-43910ebf0275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173275054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2173275054
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2681469306
Short name T192
Test name
Test status
Simulation time 43904011742 ps
CPU time 32.68 seconds
Started Jun 28 05:34:21 PM PDT 24
Finished Jun 28 05:34:54 PM PDT 24
Peak memory 249472 kb
Host smart-df1c0757-ffde-4d3b-8d05-3f2a1adba314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681469306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2681469306
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.75645953
Short name T677
Test name
Test status
Simulation time 960122099 ps
CPU time 12.55 seconds
Started Jun 28 05:34:20 PM PDT 24
Finished Jun 28 05:34:34 PM PDT 24
Peak memory 220372 kb
Host smart-9d3ce455-9165-4e02-b933-626b6f694f80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=75645953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direc
t.75645953
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1735973757
Short name T157
Test name
Test status
Simulation time 6919689403 ps
CPU time 64.19 seconds
Started Jun 28 05:34:18 PM PDT 24
Finished Jun 28 05:35:23 PM PDT 24
Peak memory 258052 kb
Host smart-f1cac017-22cf-4f94-89de-d3642fef2937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735973757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1735973757
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3063986208
Short name T641
Test name
Test status
Simulation time 2900115382 ps
CPU time 26.34 seconds
Started Jun 28 05:34:20 PM PDT 24
Finished Jun 28 05:34:47 PM PDT 24
Peak memory 216984 kb
Host smart-8f005312-87c6-4a14-b279-4d8a62d1b122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063986208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3063986208
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2589528137
Short name T968
Test name
Test status
Simulation time 23457988149 ps
CPU time 16.01 seconds
Started Jun 28 05:34:20 PM PDT 24
Finished Jun 28 05:34:37 PM PDT 24
Peak memory 217060 kb
Host smart-eafdf3e3-c592-4438-9ff5-627fd595399c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589528137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2589528137
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.642116591
Short name T618
Test name
Test status
Simulation time 337329623 ps
CPU time 8.01 seconds
Started Jun 28 05:34:21 PM PDT 24
Finished Jun 28 05:34:30 PM PDT 24
Peak memory 216768 kb
Host smart-28a85084-e501-4bfd-998d-3dc6ad297bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642116591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.642116591
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.899417237
Short name T760
Test name
Test status
Simulation time 29716662 ps
CPU time 0.85 seconds
Started Jun 28 05:34:21 PM PDT 24
Finished Jun 28 05:34:24 PM PDT 24
Peak memory 206636 kb
Host smart-3d6945ed-6037-4598-8f34-05a5e8f60406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899417237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.899417237
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2435637378
Short name T908
Test name
Test status
Simulation time 3146721689 ps
CPU time 4.23 seconds
Started Jun 28 05:34:19 PM PDT 24
Finished Jun 28 05:34:24 PM PDT 24
Peak memory 225232 kb
Host smart-ee144d00-ca05-48c3-969f-b118fe9f6f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435637378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2435637378
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.279361880
Short name T915
Test name
Test status
Simulation time 17511607 ps
CPU time 0.71 seconds
Started Jun 28 05:34:31 PM PDT 24
Finished Jun 28 05:34:33 PM PDT 24
Peak memory 205944 kb
Host smart-60a28b8d-9b65-4fd6-8a7e-29a52af9bcf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279361880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.279361880
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2231909883
Short name T380
Test name
Test status
Simulation time 1064737370 ps
CPU time 5.59 seconds
Started Jun 28 05:34:19 PM PDT 24
Finished Jun 28 05:34:26 PM PDT 24
Peak memory 224964 kb
Host smart-66649cfa-9fc4-4ece-91ad-4d21a3a69077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231909883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2231909883
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1840838620
Short name T856
Test name
Test status
Simulation time 21098131 ps
CPU time 0.76 seconds
Started Jun 28 05:34:19 PM PDT 24
Finished Jun 28 05:34:20 PM PDT 24
Peak memory 206392 kb
Host smart-8f946878-c2ad-464f-bf89-94334dd55936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840838620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1840838620
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2823483653
Short name T496
Test name
Test status
Simulation time 3570104699 ps
CPU time 61.16 seconds
Started Jun 28 05:34:31 PM PDT 24
Finished Jun 28 05:35:33 PM PDT 24
Peak memory 254792 kb
Host smart-14e2ad8d-1570-4d2f-8f02-3acef81b56d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823483653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2823483653
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.4140529462
Short name T749
Test name
Test status
Simulation time 6726528522 ps
CPU time 146.09 seconds
Started Jun 28 05:34:33 PM PDT 24
Finished Jun 28 05:37:00 PM PDT 24
Peak memory 265124 kb
Host smart-762da420-8c3f-4efe-8d8f-511f4bf7904b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140529462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.4140529462
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.635555985
Short name T538
Test name
Test status
Simulation time 9202407334 ps
CPU time 83.94 seconds
Started Jun 28 05:34:31 PM PDT 24
Finished Jun 28 05:35:56 PM PDT 24
Peak memory 249784 kb
Host smart-3ddaff1f-43c2-4d30-b065-c27447462a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635555985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.635555985
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3223566268
Short name T959
Test name
Test status
Simulation time 31948944 ps
CPU time 2.3 seconds
Started Jun 28 05:34:31 PM PDT 24
Finished Jun 28 05:34:34 PM PDT 24
Peak memory 224724 kb
Host smart-93c8db57-246a-4b94-8106-64ed36009d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223566268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3223566268
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1076160636
Short name T803
Test name
Test status
Simulation time 9083364214 ps
CPU time 117.8 seconds
Started Jun 28 05:34:30 PM PDT 24
Finished Jun 28 05:36:28 PM PDT 24
Peak memory 253272 kb
Host smart-c7f0524b-d778-4200-a98f-61a4f072d601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076160636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1076160636
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2498884682
Short name T785
Test name
Test status
Simulation time 342103640 ps
CPU time 2.57 seconds
Started Jun 28 05:34:19 PM PDT 24
Finished Jun 28 05:34:22 PM PDT 24
Peak memory 224956 kb
Host smart-8dc97f49-cadd-4a74-8f12-0b98f9cfa454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498884682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2498884682
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1852628068
Short name T480
Test name
Test status
Simulation time 1423389702 ps
CPU time 11.73 seconds
Started Jun 28 05:34:19 PM PDT 24
Finished Jun 28 05:34:31 PM PDT 24
Peak memory 241100 kb
Host smart-918dff1b-af76-4bb6-ae2c-4af3bcf1845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852628068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1852628068
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.10328664
Short name T461
Test name
Test status
Simulation time 268253921 ps
CPU time 4.14 seconds
Started Jun 28 05:34:19 PM PDT 24
Finished Jun 28 05:34:23 PM PDT 24
Peak memory 233144 kb
Host smart-1404f009-483d-4859-860d-87f756681cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10328664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.10328664
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1034898694
Short name T497
Test name
Test status
Simulation time 535088942 ps
CPU time 3.01 seconds
Started Jun 28 05:34:20 PM PDT 24
Finished Jun 28 05:34:24 PM PDT 24
Peak memory 225028 kb
Host smart-77825f93-26a0-48bd-a776-440d0bf50fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034898694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1034898694
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4000289822
Short name T13
Test name
Test status
Simulation time 3745739403 ps
CPU time 5.1 seconds
Started Jun 28 05:34:33 PM PDT 24
Finished Jun 28 05:34:40 PM PDT 24
Peak memory 222720 kb
Host smart-c81552db-d838-445c-92f9-169dc27f4675
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4000289822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4000289822
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3645159322
Short name T561
Test name
Test status
Simulation time 6705940409 ps
CPU time 19.25 seconds
Started Jun 28 05:34:20 PM PDT 24
Finished Jun 28 05:34:40 PM PDT 24
Peak memory 220620 kb
Host smart-8af6b1a7-125f-4aab-b614-b87e881ea279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645159322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3645159322
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3641889671
Short name T985
Test name
Test status
Simulation time 572201566 ps
CPU time 3.23 seconds
Started Jun 28 05:34:21 PM PDT 24
Finished Jun 28 05:34:25 PM PDT 24
Peak memory 216768 kb
Host smart-f36f2a32-b37a-49eb-8da8-039438eed949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641889671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3641889671
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.4259694271
Short name T93
Test name
Test status
Simulation time 10873825 ps
CPU time 0.7 seconds
Started Jun 28 05:34:20 PM PDT 24
Finished Jun 28 05:34:22 PM PDT 24
Peak memory 206152 kb
Host smart-befcba84-0478-4a67-92c2-ece6d29c8c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259694271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.4259694271
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3398897718
Short name T825
Test name
Test status
Simulation time 414197575 ps
CPU time 1.03 seconds
Started Jun 28 05:34:21 PM PDT 24
Finished Jun 28 05:34:23 PM PDT 24
Peak memory 206464 kb
Host smart-a7226c25-427d-4ea2-9ea1-2f64402488a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398897718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3398897718
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1749324420
Short name T645
Test name
Test status
Simulation time 4224158873 ps
CPU time 5.33 seconds
Started Jun 28 05:34:21 PM PDT 24
Finished Jun 28 05:34:28 PM PDT 24
Peak memory 225048 kb
Host smart-5817ddad-5f97-4d19-8f57-933cee8b0ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749324420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1749324420
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.614597439
Short name T441
Test name
Test status
Simulation time 12201561 ps
CPU time 0.73 seconds
Started Jun 28 05:34:33 PM PDT 24
Finished Jun 28 05:34:35 PM PDT 24
Peak memory 205272 kb
Host smart-f76c404a-68a0-46d2-9ca7-c62117d46d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614597439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.614597439
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1118092386
Short name T316
Test name
Test status
Simulation time 454843884 ps
CPU time 2.45 seconds
Started Jun 28 05:34:36 PM PDT 24
Finished Jun 28 05:34:39 PM PDT 24
Peak memory 224968 kb
Host smart-c1d154c0-216d-4cd4-9152-6f8a71a06b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118092386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1118092386
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.776120959
Short name T943
Test name
Test status
Simulation time 50960341 ps
CPU time 0.79 seconds
Started Jun 28 05:34:36 PM PDT 24
Finished Jun 28 05:34:37 PM PDT 24
Peak memory 206068 kb
Host smart-f32b1166-f39f-4b1c-aa9a-33de65afe8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776120959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.776120959
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1627449347
Short name T198
Test name
Test status
Simulation time 28675754811 ps
CPU time 244.5 seconds
Started Jun 28 05:34:35 PM PDT 24
Finished Jun 28 05:38:40 PM PDT 24
Peak memory 257084 kb
Host smart-265a8c2d-7b09-48d5-8e3c-b51f1c9c4f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627449347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1627449347
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1242661362
Short name T264
Test name
Test status
Simulation time 6992302851 ps
CPU time 46.51 seconds
Started Jun 28 05:34:32 PM PDT 24
Finished Jun 28 05:35:19 PM PDT 24
Peak memory 249724 kb
Host smart-a990192c-0739-4aab-854f-e984c472b730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242661362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1242661362
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1250218252
Short name T998
Test name
Test status
Simulation time 21081443193 ps
CPU time 54.75 seconds
Started Jun 28 05:34:33 PM PDT 24
Finished Jun 28 05:35:28 PM PDT 24
Peak memory 233464 kb
Host smart-5780d9ba-3c93-474e-84bf-f384044948e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250218252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1250218252
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1360725494
Short name T545
Test name
Test status
Simulation time 438600607 ps
CPU time 9.63 seconds
Started Jun 28 05:34:34 PM PDT 24
Finished Jun 28 05:34:45 PM PDT 24
Peak memory 224868 kb
Host smart-6db7aa9e-eddf-4a2a-a20a-f8d9ba6cc022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360725494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1360725494
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.401944830
Short name T1003
Test name
Test status
Simulation time 17738638743 ps
CPU time 124.11 seconds
Started Jun 28 05:34:34 PM PDT 24
Finished Jun 28 05:36:39 PM PDT 24
Peak memory 256504 kb
Host smart-528c2529-808b-4109-889a-455756953868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401944830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.401944830
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.740127673
Short name T736
Test name
Test status
Simulation time 2684134048 ps
CPU time 10.6 seconds
Started Jun 28 05:34:31 PM PDT 24
Finished Jun 28 05:34:42 PM PDT 24
Peak memory 233284 kb
Host smart-46df0d56-991b-451b-97e6-f25c1dae89ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740127673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.740127673
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3861588449
Short name T30
Test name
Test status
Simulation time 40278334083 ps
CPU time 81.66 seconds
Started Jun 28 05:34:32 PM PDT 24
Finished Jun 28 05:35:55 PM PDT 24
Peak memory 236160 kb
Host smart-b5091390-9ab0-464b-953a-4db93f4bbe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861588449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3861588449
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2306240941
Short name T759
Test name
Test status
Simulation time 57310460753 ps
CPU time 39.58 seconds
Started Jun 28 05:34:33 PM PDT 24
Finished Jun 28 05:35:14 PM PDT 24
Peak memory 249740 kb
Host smart-5fc0fb97-67e8-418d-8bd3-fa118e4488e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306240941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2306240941
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2146384976
Short name T994
Test name
Test status
Simulation time 8977596216 ps
CPU time 25.14 seconds
Started Jun 28 05:34:33 PM PDT 24
Finished Jun 28 05:34:59 PM PDT 24
Peak memory 233184 kb
Host smart-5d0f65cf-761a-4bd5-9e08-593c8096b6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146384976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2146384976
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.577738180
Short name T552
Test name
Test status
Simulation time 754902312 ps
CPU time 4.4 seconds
Started Jun 28 05:34:33 PM PDT 24
Finished Jun 28 05:34:38 PM PDT 24
Peak memory 223568 kb
Host smart-73a8a923-65ef-4b19-ba16-f7a736446b63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=577738180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.577738180
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2704385937
Short name T158
Test name
Test status
Simulation time 116127138661 ps
CPU time 970.63 seconds
Started Jun 28 05:34:31 PM PDT 24
Finished Jun 28 05:50:42 PM PDT 24
Peak memory 307088 kb
Host smart-48a73160-63e1-4700-ad6e-d2db129c80b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704385937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2704385937
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3008049508
Short name T374
Test name
Test status
Simulation time 1324453692 ps
CPU time 14.76 seconds
Started Jun 28 05:34:31 PM PDT 24
Finished Jun 28 05:34:47 PM PDT 24
Peak memory 216740 kb
Host smart-204c4f82-64a1-4dbf-9173-1bb6b0cb8985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008049508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3008049508
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3371910581
Short name T401
Test name
Test status
Simulation time 5399027736 ps
CPU time 4.68 seconds
Started Jun 28 05:34:31 PM PDT 24
Finished Jun 28 05:34:37 PM PDT 24
Peak memory 217876 kb
Host smart-8e30826c-6471-4a52-84ab-f374297a5e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371910581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3371910581
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3133206242
Short name T459
Test name
Test status
Simulation time 145499933 ps
CPU time 0.86 seconds
Started Jun 28 05:34:32 PM PDT 24
Finished Jun 28 05:34:33 PM PDT 24
Peak memory 208184 kb
Host smart-cc2d57f6-6e8a-4865-9417-2f97a04f5955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133206242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3133206242
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3137829467
Short name T762
Test name
Test status
Simulation time 78595881 ps
CPU time 0.88 seconds
Started Jun 28 05:34:34 PM PDT 24
Finished Jun 28 05:34:36 PM PDT 24
Peak memory 206460 kb
Host smart-d5f9a0b7-b89c-40d2-94d0-0d4bf78b538c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137829467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3137829467
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1774053668
Short name T794
Test name
Test status
Simulation time 7827331033 ps
CPU time 14.4 seconds
Started Jun 28 05:34:33 PM PDT 24
Finished Jun 28 05:34:48 PM PDT 24
Peak memory 233280 kb
Host smart-d97f33cc-c0ee-4281-9e3d-c5ebafd60f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774053668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1774053668
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.13068335
Short name T732
Test name
Test status
Simulation time 17707649 ps
CPU time 0.73 seconds
Started Jun 28 05:34:38 PM PDT 24
Finished Jun 28 05:34:39 PM PDT 24
Peak memory 205928 kb
Host smart-a01205c6-8b5d-4f3a-8b89-b478f09350ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13068335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.13068335
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3311547794
Short name T791
Test name
Test status
Simulation time 324753349 ps
CPU time 2.33 seconds
Started Jun 28 05:34:34 PM PDT 24
Finished Jun 28 05:34:37 PM PDT 24
Peak memory 233020 kb
Host smart-cc1e40ff-11fd-44e4-83ad-4f2245c4c6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311547794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3311547794
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3102353626
Short name T38
Test name
Test status
Simulation time 14978977 ps
CPU time 0.8 seconds
Started Jun 28 05:34:34 PM PDT 24
Finished Jun 28 05:34:36 PM PDT 24
Peak memory 207088 kb
Host smart-38c14a7c-0367-49d8-b209-3c55b3f6c8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102353626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3102353626
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.766925427
Short name T703
Test name
Test status
Simulation time 5128539660 ps
CPU time 21.18 seconds
Started Jun 28 05:34:38 PM PDT 24
Finished Jun 28 05:35:00 PM PDT 24
Peak memory 236936 kb
Host smart-f314bfef-8a8e-4b61-abc8-31b40111a5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766925427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.766925427
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2860488149
Short name T1000
Test name
Test status
Simulation time 50288553334 ps
CPU time 120.72 seconds
Started Jun 28 05:34:34 PM PDT 24
Finished Jun 28 05:36:36 PM PDT 24
Peak memory 249448 kb
Host smart-03fe478d-4a5d-43e8-a05d-2f3b78015364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860488149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2860488149
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.820060036
Short name T592
Test name
Test status
Simulation time 3482374717 ps
CPU time 44.01 seconds
Started Jun 28 05:34:33 PM PDT 24
Finished Jun 28 05:35:18 PM PDT 24
Peak memory 249824 kb
Host smart-f0a430a8-b967-40ab-9203-1231ab70c905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820060036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.820060036
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3575130848
Short name T176
Test name
Test status
Simulation time 26043152558 ps
CPU time 72.82 seconds
Started Jun 28 05:34:33 PM PDT 24
Finished Jun 28 05:35:47 PM PDT 24
Peak memory 254144 kb
Host smart-3f8cb92f-8c91-49fc-8632-8507c771fd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575130848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3575130848
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3011401760
Short name T831
Test name
Test status
Simulation time 1954445617 ps
CPU time 5.14 seconds
Started Jun 28 05:34:35 PM PDT 24
Finished Jun 28 05:34:41 PM PDT 24
Peak memory 224956 kb
Host smart-829ccd0b-bae5-4db2-85c5-e4d66d960388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011401760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3011401760
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1213776636
Short name T815
Test name
Test status
Simulation time 1499328063 ps
CPU time 11.11 seconds
Started Jun 28 05:34:33 PM PDT 24
Finished Jun 28 05:34:45 PM PDT 24
Peak memory 233224 kb
Host smart-ba022ade-533d-431c-a714-c41bfeb9d953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213776636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1213776636
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2217971503
Short name T211
Test name
Test status
Simulation time 25560714654 ps
CPU time 35.89 seconds
Started Jun 28 05:34:33 PM PDT 24
Finished Jun 28 05:35:10 PM PDT 24
Peak memory 237872 kb
Host smart-bc6ad065-3a36-4719-99c5-e45dc82585f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217971503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2217971503
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1712048867
Short name T559
Test name
Test status
Simulation time 1085369124 ps
CPU time 6.42 seconds
Started Jun 28 05:34:36 PM PDT 24
Finished Jun 28 05:34:43 PM PDT 24
Peak memory 224956 kb
Host smart-87010e93-b15a-4355-8fc0-c522ceb11602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712048867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1712048867
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.713257036
Short name T489
Test name
Test status
Simulation time 3544620770 ps
CPU time 5.14 seconds
Started Jun 28 05:34:37 PM PDT 24
Finished Jun 28 05:34:43 PM PDT 24
Peak memory 223888 kb
Host smart-5b4a5d15-59e3-4f56-861e-aaefc3461076
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=713257036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.713257036
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1522579457
Short name T481
Test name
Test status
Simulation time 63740326 ps
CPU time 0.96 seconds
Started Jun 28 05:34:31 PM PDT 24
Finished Jun 28 05:34:33 PM PDT 24
Peak memory 207132 kb
Host smart-b3f21455-a1a5-456e-8720-ab98257cbc59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522579457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1522579457
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3231156272
Short name T697
Test name
Test status
Simulation time 5428353842 ps
CPU time 39.07 seconds
Started Jun 28 05:34:32 PM PDT 24
Finished Jun 28 05:35:12 PM PDT 24
Peak memory 216952 kb
Host smart-7c83d293-fc4d-49bc-9a4c-1cba3cf73225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231156272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3231156272
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3346671614
Short name T449
Test name
Test status
Simulation time 3735420502 ps
CPU time 5.64 seconds
Started Jun 28 05:34:34 PM PDT 24
Finished Jun 28 05:34:40 PM PDT 24
Peak memory 216964 kb
Host smart-225f8dc0-592e-471d-9ab7-3cb4e0b03402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346671614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3346671614
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1851309960
Short name T973
Test name
Test status
Simulation time 58894548 ps
CPU time 0.83 seconds
Started Jun 28 05:34:36 PM PDT 24
Finished Jun 28 05:34:37 PM PDT 24
Peak memory 207104 kb
Host smart-85dbbe55-68e3-49de-84e9-a716b10204b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851309960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1851309960
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.4291164120
Short name T303
Test name
Test status
Simulation time 25212358 ps
CPU time 0.81 seconds
Started Jun 28 05:34:33 PM PDT 24
Finished Jun 28 05:34:35 PM PDT 24
Peak memory 206328 kb
Host smart-6e1f6ee9-5d68-4e54-b624-567beb98d1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291164120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4291164120
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.614953770
Short name T2
Test name
Test status
Simulation time 1327678411 ps
CPU time 4.9 seconds
Started Jun 28 05:34:36 PM PDT 24
Finished Jun 28 05:34:42 PM PDT 24
Peak memory 225000 kb
Host smart-e40541b7-1764-484a-9e3c-b4cc243a8cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614953770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.614953770
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.191819375
Short name T472
Test name
Test status
Simulation time 39255964 ps
CPU time 0.74 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:34:46 PM PDT 24
Peak memory 205904 kb
Host smart-e1799e4e-4030-48f4-9db5-39f66d5db9c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191819375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.191819375
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.691805097
Short name T382
Test name
Test status
Simulation time 2724960855 ps
CPU time 6.29 seconds
Started Jun 28 05:34:48 PM PDT 24
Finished Jun 28 05:34:55 PM PDT 24
Peak memory 233260 kb
Host smart-b9b91770-6910-4f44-a05e-bb85b516b0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691805097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.691805097
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3034139893
Short name T686
Test name
Test status
Simulation time 26076764 ps
CPU time 0.75 seconds
Started Jun 28 05:34:34 PM PDT 24
Finished Jun 28 05:34:35 PM PDT 24
Peak memory 207112 kb
Host smart-ed07b26b-33d1-4f06-a969-346df3f6c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034139893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3034139893
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3410519289
Short name T209
Test name
Test status
Simulation time 58080501324 ps
CPU time 306.6 seconds
Started Jun 28 05:34:47 PM PDT 24
Finished Jun 28 05:39:56 PM PDT 24
Peak memory 266120 kb
Host smart-02e6eb7f-ffa0-438a-b5c4-57d74fd92755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410519289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3410519289
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1347455189
Short name T252
Test name
Test status
Simulation time 8366803635 ps
CPU time 116.25 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:36:42 PM PDT 24
Peak memory 261588 kb
Host smart-b091eeb0-cbff-41af-b9d7-537c9ddfad4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347455189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1347455189
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.976777388
Short name T432
Test name
Test status
Simulation time 2313894586 ps
CPU time 35.63 seconds
Started Jun 28 05:34:46 PM PDT 24
Finished Jun 28 05:35:24 PM PDT 24
Peak memory 225260 kb
Host smart-12b3e65b-c684-43c5-a1e9-fb03498501d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976777388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.976777388
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.629838107
Short name T278
Test name
Test status
Simulation time 2472218088 ps
CPU time 41.16 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:35:27 PM PDT 24
Peak memory 235764 kb
Host smart-398c4502-6354-4f7e-adb9-4c4b99710a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629838107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.629838107
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2636193442
Short name T652
Test name
Test status
Simulation time 7599113155 ps
CPU time 50.39 seconds
Started Jun 28 05:34:45 PM PDT 24
Finished Jun 28 05:35:38 PM PDT 24
Peak memory 262228 kb
Host smart-0b782ceb-9584-4342-b1cc-ff3f0c921ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636193442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2636193442
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2997693953
Short name T462
Test name
Test status
Simulation time 65120547 ps
CPU time 2.5 seconds
Started Jun 28 05:34:43 PM PDT 24
Finished Jun 28 05:34:46 PM PDT 24
Peak memory 233224 kb
Host smart-7d4d819b-e3f2-4215-9d77-fae8f3d0133f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997693953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2997693953
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4253064581
Short name T777
Test name
Test status
Simulation time 66701789636 ps
CPU time 54.59 seconds
Started Jun 28 05:34:47 PM PDT 24
Finished Jun 28 05:35:44 PM PDT 24
Peak memory 233272 kb
Host smart-b77fa3a8-420f-4aa2-acc4-75ec8eeeab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253064581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4253064581
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.842977655
Short name T802
Test name
Test status
Simulation time 860952831 ps
CPU time 2.67 seconds
Started Jun 28 05:34:45 PM PDT 24
Finished Jun 28 05:34:50 PM PDT 24
Peak memory 225096 kb
Host smart-a28b5c64-a502-438a-95d7-29f152de7a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842977655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.842977655
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1312518520
Short name T429
Test name
Test status
Simulation time 1247971897 ps
CPU time 2.84 seconds
Started Jun 28 05:34:45 PM PDT 24
Finished Jun 28 05:34:50 PM PDT 24
Peak memory 225028 kb
Host smart-ede27a4e-e353-4b6d-bb9f-a502f544aa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312518520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1312518520
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1790236320
Short name T772
Test name
Test status
Simulation time 2930965449 ps
CPU time 7.63 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:34:54 PM PDT 24
Peak memory 222628 kb
Host smart-f9c34845-d616-4f2b-86c9-4a05ffca68d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1790236320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1790236320
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2103903292
Short name T986
Test name
Test status
Simulation time 39330514 ps
CPU time 0.92 seconds
Started Jun 28 05:34:47 PM PDT 24
Finished Jun 28 05:34:50 PM PDT 24
Peak memory 207424 kb
Host smart-27a73a0b-d432-4c4d-9dd7-89923b6f9d78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103903292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2103903292
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3326126781
Short name T956
Test name
Test status
Simulation time 2097215945 ps
CPU time 21.96 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:35:08 PM PDT 24
Peak memory 217020 kb
Host smart-757e016a-af2c-40c4-bfa6-460b84b2279e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326126781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3326126781
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3071290371
Short name T935
Test name
Test status
Simulation time 33028547255 ps
CPU time 24.34 seconds
Started Jun 28 05:34:38 PM PDT 24
Finished Jun 28 05:35:03 PM PDT 24
Peak memory 217100 kb
Host smart-0e557504-20ee-4ca4-9fcc-d1abf54e7df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071290371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3071290371
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1723131130
Short name T321
Test name
Test status
Simulation time 66585320 ps
CPU time 0.73 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:34:46 PM PDT 24
Peak memory 206104 kb
Host smart-d734691b-4858-4562-a926-52d1636b74b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723131130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1723131130
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1180205084
Short name T679
Test name
Test status
Simulation time 15514774 ps
CPU time 0.74 seconds
Started Jun 28 05:34:43 PM PDT 24
Finished Jun 28 05:34:45 PM PDT 24
Peak memory 206460 kb
Host smart-7ee01e60-066e-404b-9656-fc36de6418fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180205084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1180205084
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3135273261
Short name T727
Test name
Test status
Simulation time 2023126721 ps
CPU time 11.33 seconds
Started Jun 28 05:34:46 PM PDT 24
Finished Jun 28 05:34:59 PM PDT 24
Peak memory 224960 kb
Host smart-55e57868-7df0-4a1a-ae4e-07f557ebefeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135273261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3135273261
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.431210726
Short name T387
Test name
Test status
Simulation time 42618480 ps
CPU time 0.75 seconds
Started Jun 28 05:34:45 PM PDT 24
Finished Jun 28 05:34:48 PM PDT 24
Peak memory 205984 kb
Host smart-9cca617e-2cc3-411f-a744-07f112fa3f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431210726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.431210726
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2815978561
Short name T924
Test name
Test status
Simulation time 243577641 ps
CPU time 2.68 seconds
Started Jun 28 05:34:47 PM PDT 24
Finished Jun 28 05:34:51 PM PDT 24
Peak memory 233132 kb
Host smart-4b7bb021-12d1-454c-85e6-11c3d29ac652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815978561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2815978561
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.224212298
Short name T392
Test name
Test status
Simulation time 17339989 ps
CPU time 0.74 seconds
Started Jun 28 05:34:45 PM PDT 24
Finished Jun 28 05:34:48 PM PDT 24
Peak memory 207400 kb
Host smart-f93893f0-23b5-4b6b-8cc8-e74fe49fdd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224212298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.224212298
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.4060597718
Short name T737
Test name
Test status
Simulation time 39771709144 ps
CPU time 183.78 seconds
Started Jun 28 05:34:45 PM PDT 24
Finished Jun 28 05:37:51 PM PDT 24
Peak memory 255776 kb
Host smart-f89619b8-5072-4c98-9b5d-9a7f171c7eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060597718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4060597718
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.4263808830
Short name T183
Test name
Test status
Simulation time 28651965475 ps
CPU time 131.33 seconds
Started Jun 28 05:34:46 PM PDT 24
Finished Jun 28 05:37:00 PM PDT 24
Peak memory 256520 kb
Host smart-5d6e484c-ba39-4289-b0cf-403909788dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263808830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.4263808830
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3058056619
Short name T85
Test name
Test status
Simulation time 32999732765 ps
CPU time 176.93 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:37:43 PM PDT 24
Peak memory 265144 kb
Host smart-edfd64be-5ded-447e-8ab2-92eff7c9ea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058056619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3058056619
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2784730623
Short name T359
Test name
Test status
Simulation time 3484863043 ps
CPU time 16.98 seconds
Started Jun 28 05:34:47 PM PDT 24
Finished Jun 28 05:35:06 PM PDT 24
Peak memory 233344 kb
Host smart-543a150b-d8d0-4a52-b851-307322c16189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784730623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2784730623
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.771133850
Short name T188
Test name
Test status
Simulation time 4083916112 ps
CPU time 66.25 seconds
Started Jun 28 05:34:46 PM PDT 24
Finished Jun 28 05:35:54 PM PDT 24
Peak memory 236436 kb
Host smart-384c6959-9072-4cee-8309-f7022de8219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771133850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.771133850
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3509844569
Short name T195
Test name
Test status
Simulation time 1047948959 ps
CPU time 3.47 seconds
Started Jun 28 05:34:45 PM PDT 24
Finished Jun 28 05:34:51 PM PDT 24
Peak memory 233340 kb
Host smart-62cfe9ed-0930-41a6-83ac-54f074f6bba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509844569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3509844569
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.336590886
Short name T757
Test name
Test status
Simulation time 10755806206 ps
CPU time 22.07 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:35:08 PM PDT 24
Peak memory 233276 kb
Host smart-b960eb36-2936-4cf9-9470-879f30350b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336590886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.336590886
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3321334925
Short name T518
Test name
Test status
Simulation time 12118284940 ps
CPU time 9.86 seconds
Started Jun 28 05:34:45 PM PDT 24
Finished Jun 28 05:34:57 PM PDT 24
Peak memory 233252 kb
Host smart-2ee11a3b-fd6f-4589-94ca-7b53c858f662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321334925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3321334925
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2129695080
Short name T830
Test name
Test status
Simulation time 771214410 ps
CPU time 4.36 seconds
Started Jun 28 05:34:43 PM PDT 24
Finished Jun 28 05:34:48 PM PDT 24
Peak memory 225028 kb
Host smart-293324b8-7c00-4f8c-b769-bbff9f2e82cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129695080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2129695080
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2418860539
Short name T806
Test name
Test status
Simulation time 2337236895 ps
CPU time 7.31 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:34:53 PM PDT 24
Peak memory 222572 kb
Host smart-1d0d60c4-5a4e-48da-bbc7-d6baaaf3a8ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2418860539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2418860539
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2361775200
Short name T846
Test name
Test status
Simulation time 40168907142 ps
CPU time 382.58 seconds
Started Jun 28 05:34:46 PM PDT 24
Finished Jun 28 05:41:11 PM PDT 24
Peak memory 251356 kb
Host smart-5687b349-aada-43f9-a42c-dc2ff586c822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361775200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2361775200
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.522603179
Short name T471
Test name
Test status
Simulation time 111252190 ps
CPU time 2.26 seconds
Started Jun 28 05:34:43 PM PDT 24
Finished Jun 28 05:34:46 PM PDT 24
Peak memory 218600 kb
Host smart-6e01753a-8495-4607-9846-9ada5ea1bd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522603179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.522603179
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1737551527
Short name T312
Test name
Test status
Simulation time 577677873 ps
CPU time 1.41 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:34:47 PM PDT 24
Peak memory 208184 kb
Host smart-5dca46ab-809b-48e9-8bdd-30dbb1993dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737551527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1737551527
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2820266420
Short name T381
Test name
Test status
Simulation time 21735352 ps
CPU time 0.72 seconds
Started Jun 28 05:34:43 PM PDT 24
Finished Jun 28 05:34:45 PM PDT 24
Peak memory 206116 kb
Host smart-0bf6b1d8-03b8-43c7-8f44-e269798ccfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820266420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2820266420
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2633475110
Short name T71
Test name
Test status
Simulation time 10979870 ps
CPU time 0.7 seconds
Started Jun 28 05:34:47 PM PDT 24
Finished Jun 28 05:34:49 PM PDT 24
Peak memory 206112 kb
Host smart-4c656d86-9620-4301-b1ab-7e12ef3474c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633475110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2633475110
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1871733574
Short name T972
Test name
Test status
Simulation time 8179306905 ps
CPU time 27.88 seconds
Started Jun 28 05:34:46 PM PDT 24
Finished Jun 28 05:35:15 PM PDT 24
Peak memory 237904 kb
Host smart-e923aea8-0dfc-4e26-a0e4-515a84688acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871733574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1871733574
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1438049508
Short name T604
Test name
Test status
Simulation time 22099137 ps
CPU time 0.75 seconds
Started Jun 28 05:32:04 PM PDT 24
Finished Jun 28 05:32:06 PM PDT 24
Peak memory 205960 kb
Host smart-7d3c5899-d3c6-43b5-b716-3ca2ed18b171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438049508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
438049508
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3038426530
Short name T499
Test name
Test status
Simulation time 397701692 ps
CPU time 3.92 seconds
Started Jun 28 05:31:47 PM PDT 24
Finished Jun 28 05:31:51 PM PDT 24
Peak memory 233184 kb
Host smart-852cffa8-0e07-4c4e-8148-5fa97e5e843e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038426530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3038426530
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3844597813
Short name T624
Test name
Test status
Simulation time 26804821 ps
CPU time 0.82 seconds
Started Jun 28 05:31:47 PM PDT 24
Finished Jun 28 05:31:48 PM PDT 24
Peak memory 207404 kb
Host smart-9da3971f-e540-4884-985b-edabf467e27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844597813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3844597813
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2414063126
Short name T887
Test name
Test status
Simulation time 37335768513 ps
CPU time 262.9 seconds
Started Jun 28 05:31:56 PM PDT 24
Finished Jun 28 05:36:19 PM PDT 24
Peak memory 253992 kb
Host smart-1c304104-1b28-456e-bc68-910f244df50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414063126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2414063126
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.4142061410
Short name T226
Test name
Test status
Simulation time 69296308444 ps
CPU time 180.59 seconds
Started Jun 28 05:31:56 PM PDT 24
Finished Jun 28 05:34:57 PM PDT 24
Peak memory 256884 kb
Host smart-b1068f71-6245-4bbe-8eaa-d63f8dd40827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142061410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4142061410
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.619316239
Short name T962
Test name
Test status
Simulation time 66317363738 ps
CPU time 631.89 seconds
Started Jun 28 05:31:58 PM PDT 24
Finished Jun 28 05:42:31 PM PDT 24
Peak memory 269916 kb
Host smart-afbba59a-8e08-4873-9f7f-ac3e015c5325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619316239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
619316239
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3050060200
Short name T611
Test name
Test status
Simulation time 3695022330 ps
CPU time 33.15 seconds
Started Jun 28 05:31:54 PM PDT 24
Finished Jun 28 05:32:27 PM PDT 24
Peak memory 241508 kb
Host smart-f72dd277-e7cb-4fc6-bc2e-5494ebc3eb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050060200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3050060200
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1483830593
Short name T178
Test name
Test status
Simulation time 11904257861 ps
CPU time 163.29 seconds
Started Jun 28 05:31:58 PM PDT 24
Finished Jun 28 05:34:43 PM PDT 24
Peak memory 268420 kb
Host smart-bedf18e1-9d10-4416-a564-32f7859ec427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483830593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1483830593
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1432240799
Short name T414
Test name
Test status
Simulation time 285909396 ps
CPU time 6.14 seconds
Started Jun 28 05:31:47 PM PDT 24
Finished Jun 28 05:31:54 PM PDT 24
Peak memory 233208 kb
Host smart-84877ce5-e64a-4139-81f3-ded691506296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432240799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1432240799
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2852342631
Short name T993
Test name
Test status
Simulation time 441592185 ps
CPU time 8.18 seconds
Started Jun 28 05:31:51 PM PDT 24
Finished Jun 28 05:32:00 PM PDT 24
Peak memory 224936 kb
Host smart-5ef14da7-654d-43e8-bed7-019708a7153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852342631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2852342631
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1111515182
Short name T765
Test name
Test status
Simulation time 18601635926 ps
CPU time 15.5 seconds
Started Jun 28 05:31:48 PM PDT 24
Finished Jun 28 05:32:04 PM PDT 24
Peak memory 249736 kb
Host smart-b08eb844-dd91-4b27-ab61-cfb42fce9904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111515182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1111515182
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.4198514768
Short name T751
Test name
Test status
Simulation time 151652325 ps
CPU time 3.86 seconds
Started Jun 28 05:31:51 PM PDT 24
Finished Jun 28 05:31:55 PM PDT 24
Peak memory 233156 kb
Host smart-4284c17c-6820-4df5-b00f-5aa57138378a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198514768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4198514768
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3928558050
Short name T373
Test name
Test status
Simulation time 1330554998 ps
CPU time 8.67 seconds
Started Jun 28 05:31:57 PM PDT 24
Finished Jun 28 05:32:07 PM PDT 24
Peak memory 219320 kb
Host smart-3eff8f70-30ed-43dd-86f3-19327d380b30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3928558050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3928558050
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.622091078
Short name T83
Test name
Test status
Simulation time 68080654 ps
CPU time 0.99 seconds
Started Jun 28 05:31:56 PM PDT 24
Finished Jun 28 05:31:59 PM PDT 24
Peak memory 236336 kb
Host smart-21675e98-19fb-4580-9dea-1bb623a7a755
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622091078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.622091078
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1227816918
Short name T159
Test name
Test status
Simulation time 206355691 ps
CPU time 0.99 seconds
Started Jun 28 05:31:58 PM PDT 24
Finished Jun 28 05:32:00 PM PDT 24
Peak memory 207436 kb
Host smart-2cf8a393-30d9-4db1-adc5-62d34faeada3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227816918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1227816918
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2393051176
Short name T500
Test name
Test status
Simulation time 65320969 ps
CPU time 0.75 seconds
Started Jun 28 05:31:48 PM PDT 24
Finished Jun 28 05:31:50 PM PDT 24
Peak memory 206124 kb
Host smart-9fb321d9-82ae-4a58-9124-7b62395515a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393051176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2393051176
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3892698960
Short name T335
Test name
Test status
Simulation time 36236572988 ps
CPU time 22.52 seconds
Started Jun 28 05:31:50 PM PDT 24
Finished Jun 28 05:32:13 PM PDT 24
Peak memory 217936 kb
Host smart-cfc5462c-8dad-4efa-84d2-e513210eded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892698960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3892698960
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4130827493
Short name T886
Test name
Test status
Simulation time 363226723 ps
CPU time 1.3 seconds
Started Jun 28 05:31:49 PM PDT 24
Finished Jun 28 05:31:51 PM PDT 24
Peak memory 208460 kb
Host smart-5009ff54-34c6-4cd9-b032-7f718e62dd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130827493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4130827493
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1805803621
Short name T813
Test name
Test status
Simulation time 118789797 ps
CPU time 1.05 seconds
Started Jun 28 05:31:46 PM PDT 24
Finished Jun 28 05:31:47 PM PDT 24
Peak memory 207380 kb
Host smart-794316eb-e88f-464c-8d9d-f563b8a35dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805803621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1805803621
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2822615659
Short name T384
Test name
Test status
Simulation time 95390195 ps
CPU time 2.3 seconds
Started Jun 28 05:31:50 PM PDT 24
Finished Jun 28 05:31:52 PM PDT 24
Peak memory 225016 kb
Host smart-9870d212-7cfc-452e-a73b-817d66eecdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822615659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2822615659
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2295367806
Short name T951
Test name
Test status
Simulation time 14518458 ps
CPU time 0.76 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:34:46 PM PDT 24
Peak memory 206292 kb
Host smart-490c2c67-c7de-469c-8769-37fb14e9d79e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295367806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2295367806
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2713168559
Short name T564
Test name
Test status
Simulation time 160825151 ps
CPU time 2.98 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:34:49 PM PDT 24
Peak memory 224916 kb
Host smart-f7807648-c7de-4a7d-80a8-319e4b155a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713168559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2713168559
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1763389853
Short name T293
Test name
Test status
Simulation time 50727225 ps
CPU time 0.76 seconds
Started Jun 28 05:34:45 PM PDT 24
Finished Jun 28 05:34:48 PM PDT 24
Peak memory 207088 kb
Host smart-b26ce003-c4b9-4d84-be31-b57c18715ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763389853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1763389853
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2821801924
Short name T543
Test name
Test status
Simulation time 25966362 ps
CPU time 0.77 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:34:47 PM PDT 24
Peak memory 216380 kb
Host smart-89ab3a2b-75bf-41d3-8efc-04fad54ea6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821801924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2821801924
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3508181317
Short name T240
Test name
Test status
Simulation time 69950470327 ps
CPU time 370.16 seconds
Started Jun 28 05:34:46 PM PDT 24
Finished Jun 28 05:40:58 PM PDT 24
Peak memory 263588 kb
Host smart-8141ee99-76d7-4abf-9f13-8528dd337e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508181317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3508181317
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3530368109
Short name T922
Test name
Test status
Simulation time 196116452 ps
CPU time 3.74 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:34:48 PM PDT 24
Peak memory 233056 kb
Host smart-3364a3c8-7b41-4bee-a1ce-c054e65340a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530368109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3530368109
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3889061222
Short name T903
Test name
Test status
Simulation time 6215752455 ps
CPU time 109.49 seconds
Started Jun 28 05:34:46 PM PDT 24
Finished Jun 28 05:36:38 PM PDT 24
Peak memory 253388 kb
Host smart-60109699-6259-429b-a044-9873546cfe00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889061222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3889061222
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3206843854
Short name T512
Test name
Test status
Simulation time 4198892229 ps
CPU time 8.67 seconds
Started Jun 28 05:34:47 PM PDT 24
Finished Jun 28 05:34:57 PM PDT 24
Peak memory 230672 kb
Host smart-9ea0525e-923e-4d47-9763-ef2551e8e1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206843854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3206843854
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2322822361
Short name T816
Test name
Test status
Simulation time 5482024348 ps
CPU time 17.44 seconds
Started Jun 28 05:34:46 PM PDT 24
Finished Jun 28 05:35:06 PM PDT 24
Peak memory 225152 kb
Host smart-62773ede-75d9-4ef8-b3cd-14f1bee0b925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322822361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2322822361
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4052261846
Short name T800
Test name
Test status
Simulation time 46702210345 ps
CPU time 24.11 seconds
Started Jun 28 05:34:47 PM PDT 24
Finished Jun 28 05:35:13 PM PDT 24
Peak memory 241540 kb
Host smart-2cff4ee6-2ead-4588-bb3f-95f9be3e16c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052261846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4052261846
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1606095589
Short name T572
Test name
Test status
Simulation time 459695935 ps
CPU time 2.7 seconds
Started Jun 28 05:34:45 PM PDT 24
Finished Jun 28 05:34:50 PM PDT 24
Peak memory 225012 kb
Host smart-631f4252-149d-44cc-8008-72afe067bc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606095589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1606095589
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1783866793
Short name T314
Test name
Test status
Simulation time 1414488491 ps
CPU time 9.83 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:34:55 PM PDT 24
Peak memory 224100 kb
Host smart-b7291379-2d03-4418-8861-21de7853a252
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1783866793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1783866793
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3238361382
Short name T467
Test name
Test status
Simulation time 3789098634 ps
CPU time 19.19 seconds
Started Jun 28 05:34:43 PM PDT 24
Finished Jun 28 05:35:03 PM PDT 24
Peak memory 217112 kb
Host smart-bd11db1a-732c-435a-bc85-39d780bf2668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238361382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3238361382
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4222120987
Short name T453
Test name
Test status
Simulation time 5816846067 ps
CPU time 15.17 seconds
Started Jun 28 05:34:47 PM PDT 24
Finished Jun 28 05:35:04 PM PDT 24
Peak memory 216908 kb
Host smart-35a832ad-081b-4d3c-90de-9e04655f285a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222120987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4222120987
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1265934547
Short name T742
Test name
Test status
Simulation time 30459096 ps
CPU time 0.72 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:34:47 PM PDT 24
Peak memory 206092 kb
Host smart-dd4c4885-9bdf-4ac8-b1c4-b4efd87aba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265934547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1265934547
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3837082093
Short name T333
Test name
Test status
Simulation time 331183087 ps
CPU time 0.81 seconds
Started Jun 28 05:34:44 PM PDT 24
Finished Jun 28 05:34:47 PM PDT 24
Peak memory 206456 kb
Host smart-27ce0dfe-ebb8-4604-bd0c-2fd315e0bd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837082093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3837082093
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.921142374
Short name T54
Test name
Test status
Simulation time 214247488 ps
CPU time 2.96 seconds
Started Jun 28 05:34:46 PM PDT 24
Finished Jun 28 05:34:51 PM PDT 24
Peak memory 225152 kb
Host smart-73e31222-b6ed-4782-8adb-5494419aa588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921142374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.921142374
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.376827028
Short name T627
Test name
Test status
Simulation time 17893216 ps
CPU time 0.73 seconds
Started Jun 28 05:35:00 PM PDT 24
Finished Jun 28 05:35:01 PM PDT 24
Peak memory 205404 kb
Host smart-0e3c85aa-d985-4924-92b9-659bee35e96e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376827028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.376827028
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1615468759
Short name T861
Test name
Test status
Simulation time 3440058543 ps
CPU time 14.9 seconds
Started Jun 28 05:34:54 PM PDT 24
Finished Jun 28 05:35:10 PM PDT 24
Peak memory 233284 kb
Host smart-8f8a5dd6-055f-45f2-b8e6-ee6574f03d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615468759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1615468759
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3944675412
Short name T63
Test name
Test status
Simulation time 17037839 ps
CPU time 0.79 seconds
Started Jun 28 05:34:48 PM PDT 24
Finished Jun 28 05:34:50 PM PDT 24
Peak memory 206392 kb
Host smart-6ee0c9c2-c1ca-4476-b135-be2a651190cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944675412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3944675412
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2574182136
Short name T187
Test name
Test status
Simulation time 49378301782 ps
CPU time 109.02 seconds
Started Jun 28 05:34:55 PM PDT 24
Finished Jun 28 05:36:45 PM PDT 24
Peak memory 249716 kb
Host smart-532cb666-0ff8-4d5a-88d1-754aeb6c010d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574182136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2574182136
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2856079917
Short name T622
Test name
Test status
Simulation time 4889745694 ps
CPU time 24.99 seconds
Started Jun 28 05:34:53 PM PDT 24
Finished Jun 28 05:35:19 PM PDT 24
Peak memory 249736 kb
Host smart-275b57a8-ddb9-4ef3-8c29-e9bf085a7e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856079917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2856079917
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2776874331
Short name T584
Test name
Test status
Simulation time 12760925680 ps
CPU time 57.19 seconds
Started Jun 28 05:34:55 PM PDT 24
Finished Jun 28 05:35:54 PM PDT 24
Peak memory 250868 kb
Host smart-a7c8d3fb-d5db-493a-8551-bbe0e96fe260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776874331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2776874331
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2773249650
Short name T613
Test name
Test status
Simulation time 19260538177 ps
CPU time 55.7 seconds
Started Jun 28 05:34:58 PM PDT 24
Finished Jun 28 05:35:55 PM PDT 24
Peak memory 251192 kb
Host smart-93013e29-6b6e-4fdb-893a-d90a08e1c95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773249650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2773249650
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.570771581
Short name T179
Test name
Test status
Simulation time 100582714180 ps
CPU time 208.15 seconds
Started Jun 28 05:34:57 PM PDT 24
Finished Jun 28 05:38:27 PM PDT 24
Peak memory 249724 kb
Host smart-aa94da6e-a47f-480e-b96b-40f2ab12820c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570771581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.570771581
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1518636391
Short name T610
Test name
Test status
Simulation time 3975448567 ps
CPU time 16.72 seconds
Started Jun 28 05:34:57 PM PDT 24
Finished Jun 28 05:35:15 PM PDT 24
Peak memory 233248 kb
Host smart-1d7ef5d0-dd6a-45ca-8e5a-4091bba2e220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518636391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1518636391
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1361611280
Short name T330
Test name
Test status
Simulation time 52112993 ps
CPU time 2.39 seconds
Started Jun 28 05:34:57 PM PDT 24
Finished Jun 28 05:35:01 PM PDT 24
Peak memory 233032 kb
Host smart-3d13389f-a697-4b38-a288-fb9bb13ec070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361611280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1361611280
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1474875975
Short name T357
Test name
Test status
Simulation time 739096540 ps
CPU time 4.57 seconds
Started Jun 28 05:34:57 PM PDT 24
Finished Jun 28 05:35:03 PM PDT 24
Peak memory 224924 kb
Host smart-436ef62a-cfaa-4853-a8fe-9afcb3d17533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474875975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1474875975
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.87761984
Short name T670
Test name
Test status
Simulation time 514394593 ps
CPU time 4.57 seconds
Started Jun 28 05:34:56 PM PDT 24
Finished Jun 28 05:35:01 PM PDT 24
Peak memory 233136 kb
Host smart-8a39440f-c3a6-4caa-a146-c4003cbe4295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87761984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.87761984
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.793741061
Short name T597
Test name
Test status
Simulation time 132652627 ps
CPU time 3.41 seconds
Started Jun 28 05:34:54 PM PDT 24
Finished Jun 28 05:34:58 PM PDT 24
Peak memory 219408 kb
Host smart-da1205b0-c951-4287-b5de-99346cb80771
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=793741061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.793741061
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.473695978
Short name T140
Test name
Test status
Simulation time 15230442932 ps
CPU time 166.83 seconds
Started Jun 28 05:34:58 PM PDT 24
Finished Jun 28 05:37:47 PM PDT 24
Peak memory 264536 kb
Host smart-773e5c3a-5355-4449-b9f1-f018ba228f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473695978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.473695978
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.784363758
Short name T689
Test name
Test status
Simulation time 1794034972 ps
CPU time 17.02 seconds
Started Jun 28 05:34:47 PM PDT 24
Finished Jun 28 05:35:06 PM PDT 24
Peak memory 216772 kb
Host smart-b69b1992-be56-410f-8c69-781e408ea449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784363758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.784363758
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2062907389
Short name T753
Test name
Test status
Simulation time 334464165 ps
CPU time 2.14 seconds
Started Jun 28 05:34:45 PM PDT 24
Finished Jun 28 05:34:49 PM PDT 24
Peak memory 216796 kb
Host smart-1ae8147e-622e-43af-a837-b3f2ee4d845f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062907389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2062907389
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3064439831
Short name T448
Test name
Test status
Simulation time 478464281 ps
CPU time 1.27 seconds
Started Jun 28 05:34:58 PM PDT 24
Finished Jun 28 05:35:01 PM PDT 24
Peak memory 208368 kb
Host smart-a75652d5-b4df-4cf1-a5a4-c0f581ac7876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064439831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3064439831
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3236029949
Short name T965
Test name
Test status
Simulation time 70559097 ps
CPU time 0.82 seconds
Started Jun 28 05:34:57 PM PDT 24
Finished Jun 28 05:34:59 PM PDT 24
Peak memory 206600 kb
Host smart-9a2929a8-f4f0-48c0-af06-7099ed1d9dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236029949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3236029949
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3940877198
Short name T990
Test name
Test status
Simulation time 1158777737 ps
CPU time 5.9 seconds
Started Jun 28 05:34:58 PM PDT 24
Finished Jun 28 05:35:06 PM PDT 24
Peak memory 224952 kb
Host smart-6bcd2097-53a4-46c2-92cc-764b3d9595b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940877198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3940877198
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2231699050
Short name T340
Test name
Test status
Simulation time 113684776 ps
CPU time 0.71 seconds
Started Jun 28 05:34:56 PM PDT 24
Finished Jun 28 05:34:59 PM PDT 24
Peak memory 205928 kb
Host smart-0860ab36-a26f-4abd-94da-5651c7fcfd7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231699050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2231699050
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2618856124
Short name T675
Test name
Test status
Simulation time 31616045 ps
CPU time 2.65 seconds
Started Jun 28 05:34:56 PM PDT 24
Finished Jun 28 05:35:01 PM PDT 24
Peak memory 232924 kb
Host smart-c125988e-d2ae-4cbf-b3fb-b3ae27cfa516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618856124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2618856124
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2237262182
Short name T640
Test name
Test status
Simulation time 86499441 ps
CPU time 0.73 seconds
Started Jun 28 05:34:54 PM PDT 24
Finished Jun 28 05:34:56 PM PDT 24
Peak memory 206000 kb
Host smart-c6289685-87f5-42b5-8080-f2d442d96434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237262182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2237262182
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1747409790
Short name T256
Test name
Test status
Simulation time 30896178599 ps
CPU time 186.66 seconds
Started Jun 28 05:34:58 PM PDT 24
Finished Jun 28 05:38:06 PM PDT 24
Peak memory 250748 kb
Host smart-bdf7b118-bc41-4967-a095-d673f8fbdd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747409790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1747409790
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3175725344
Short name T482
Test name
Test status
Simulation time 997415855 ps
CPU time 10.52 seconds
Started Jun 28 05:34:59 PM PDT 24
Finished Jun 28 05:35:11 PM PDT 24
Peak memory 237112 kb
Host smart-1c494b8b-d64d-4d59-86a0-345c5c86752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175725344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3175725344
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3835105768
Short name T593
Test name
Test status
Simulation time 71787941 ps
CPU time 3.32 seconds
Started Jun 28 05:34:55 PM PDT 24
Finished Jun 28 05:34:59 PM PDT 24
Peak memory 233092 kb
Host smart-ef47915e-6860-400d-ac17-a0bccb872b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835105768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3835105768
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1513565165
Short name T722
Test name
Test status
Simulation time 213645892176 ps
CPU time 380.59 seconds
Started Jun 28 05:34:56 PM PDT 24
Finished Jun 28 05:41:18 PM PDT 24
Peak memory 255100 kb
Host smart-1e372699-840e-413a-8bb4-4f57f959e307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513565165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1513565165
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.83091584
Short name T668
Test name
Test status
Simulation time 489934275 ps
CPU time 5.8 seconds
Started Jun 28 05:34:57 PM PDT 24
Finished Jun 28 05:35:05 PM PDT 24
Peak memory 233088 kb
Host smart-935c7762-1b72-4591-be96-feb357c4e9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83091584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.83091584
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3015488631
Short name T199
Test name
Test status
Simulation time 1547423280 ps
CPU time 10.94 seconds
Started Jun 28 05:34:56 PM PDT 24
Finished Jun 28 05:35:09 PM PDT 24
Peak memory 249608 kb
Host smart-7eebb4ad-74c6-4e0e-be67-6198e46b58ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015488631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3015488631
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2673337705
Short name T790
Test name
Test status
Simulation time 30078201 ps
CPU time 2.56 seconds
Started Jun 28 05:34:58 PM PDT 24
Finished Jun 28 05:35:02 PM PDT 24
Peak memory 233032 kb
Host smart-9d2f8ad1-b1c0-4d11-8761-d163ef59ac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673337705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2673337705
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.957535944
Short name T768
Test name
Test status
Simulation time 1375404514 ps
CPU time 10.27 seconds
Started Jun 28 05:34:54 PM PDT 24
Finished Jun 28 05:35:05 PM PDT 24
Peak memory 233124 kb
Host smart-e6c7318c-9a80-42d8-a636-70570ae6b33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957535944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.957535944
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1174968286
Short name T738
Test name
Test status
Simulation time 3916273004 ps
CPU time 12.74 seconds
Started Jun 28 05:34:56 PM PDT 24
Finished Jun 28 05:35:10 PM PDT 24
Peak memory 221332 kb
Host smart-8348a2dc-7be0-4923-8244-35a64cdce22f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1174968286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1174968286
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.320263686
Short name T725
Test name
Test status
Simulation time 34565120 ps
CPU time 0.88 seconds
Started Jun 28 05:34:59 PM PDT 24
Finished Jun 28 05:35:01 PM PDT 24
Peak memory 206420 kb
Host smart-0594a19a-c172-42d2-b6be-7eba5419eb3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320263686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.320263686
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4109569224
Short name T99
Test name
Test status
Simulation time 5941449425 ps
CPU time 33.57 seconds
Started Jun 28 05:34:54 PM PDT 24
Finished Jun 28 05:35:29 PM PDT 24
Peak memory 217008 kb
Host smart-00a09634-2236-4f7e-a0d1-4d920ef287fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109569224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4109569224
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3395429478
Short name T535
Test name
Test status
Simulation time 10298290750 ps
CPU time 23.32 seconds
Started Jun 28 05:34:53 PM PDT 24
Finished Jun 28 05:35:18 PM PDT 24
Peak memory 216964 kb
Host smart-69c9f805-02bd-422a-ae03-05d48618872e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395429478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3395429478
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3317733857
Short name T776
Test name
Test status
Simulation time 15318453 ps
CPU time 0.97 seconds
Started Jun 28 05:34:55 PM PDT 24
Finished Jun 28 05:34:57 PM PDT 24
Peak memory 207908 kb
Host smart-e1711cdc-7b74-48c9-bf90-82ae00804804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317733857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3317733857
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2173946793
Short name T576
Test name
Test status
Simulation time 64202440 ps
CPU time 0.87 seconds
Started Jun 28 05:34:57 PM PDT 24
Finished Jun 28 05:34:59 PM PDT 24
Peak memory 206448 kb
Host smart-515df850-ad41-461a-a264-e3b513656a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173946793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2173946793
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1845307239
Short name T508
Test name
Test status
Simulation time 4840133552 ps
CPU time 16.85 seconds
Started Jun 28 05:34:59 PM PDT 24
Finished Jun 28 05:35:17 PM PDT 24
Peak memory 233184 kb
Host smart-ff66ba10-ae4e-45bf-9b99-3c531128ab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845307239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1845307239
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2966870152
Short name T352
Test name
Test status
Simulation time 11412014 ps
CPU time 0.75 seconds
Started Jun 28 05:35:06 PM PDT 24
Finished Jun 28 05:35:08 PM PDT 24
Peak memory 205584 kb
Host smart-ebdf71db-82c7-4f4c-b3da-211462fd3765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966870152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2966870152
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1513530901
Short name T822
Test name
Test status
Simulation time 144951042 ps
CPU time 2.72 seconds
Started Jun 28 05:34:55 PM PDT 24
Finished Jun 28 05:34:59 PM PDT 24
Peak memory 224940 kb
Host smart-c82da024-a6b7-48b8-900f-91b3952fd3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513530901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1513530901
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.788118881
Short name T326
Test name
Test status
Simulation time 20156783 ps
CPU time 0.83 seconds
Started Jun 28 05:34:56 PM PDT 24
Finished Jun 28 05:34:59 PM PDT 24
Peak memory 207108 kb
Host smart-152771a4-fde9-4c2c-a11d-5fc4cbf4928b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788118881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.788118881
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2670442866
Short name T582
Test name
Test status
Simulation time 32431401569 ps
CPU time 114.26 seconds
Started Jun 28 05:35:03 PM PDT 24
Finished Jun 28 05:36:58 PM PDT 24
Peak memory 251720 kb
Host smart-da19864e-7189-4e34-b5f4-641de539c772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670442866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2670442866
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3036383927
Short name T741
Test name
Test status
Simulation time 8270078870 ps
CPU time 48.99 seconds
Started Jun 28 05:35:04 PM PDT 24
Finished Jun 28 05:35:55 PM PDT 24
Peak memory 241648 kb
Host smart-cf9280ff-7c30-4b98-a129-908ea5aea87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036383927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3036383927
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1953349016
Short name T733
Test name
Test status
Simulation time 576678753 ps
CPU time 3.79 seconds
Started Jun 28 05:35:03 PM PDT 24
Finished Jun 28 05:35:09 PM PDT 24
Peak memory 225012 kb
Host smart-5708fb5d-882b-4a29-b6d6-e8eea69463d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953349016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1953349016
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2506337713
Short name T975
Test name
Test status
Simulation time 86159247085 ps
CPU time 68.19 seconds
Started Jun 28 05:35:04 PM PDT 24
Finished Jun 28 05:36:14 PM PDT 24
Peak memory 249724 kb
Host smart-5280267a-f81d-4813-88c3-3f0de5c04d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506337713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2506337713
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3596617256
Short name T110
Test name
Test status
Simulation time 1709218191 ps
CPU time 9.01 seconds
Started Jun 28 05:34:54 PM PDT 24
Finished Jun 28 05:35:04 PM PDT 24
Peak memory 224964 kb
Host smart-4fc3d0bb-3971-4da0-acfd-e869342ee4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596617256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3596617256
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.277366530
Short name T213
Test name
Test status
Simulation time 974438237 ps
CPU time 9.41 seconds
Started Jun 28 05:34:54 PM PDT 24
Finished Jun 28 05:35:05 PM PDT 24
Peak memory 224956 kb
Host smart-2b65c3af-8138-415e-94ab-a231ad40549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277366530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.277366530
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1170438902
Short name T586
Test name
Test status
Simulation time 4556346150 ps
CPU time 4.74 seconds
Started Jun 28 05:34:58 PM PDT 24
Finished Jun 28 05:35:05 PM PDT 24
Peak memory 225068 kb
Host smart-151851c6-3807-4e13-b80e-51244cb6947e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170438902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1170438902
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3202690719
Short name T476
Test name
Test status
Simulation time 1173715726 ps
CPU time 8.28 seconds
Started Jun 28 05:34:59 PM PDT 24
Finished Jun 28 05:35:09 PM PDT 24
Peak memory 233044 kb
Host smart-b24e1e90-154c-46a0-b4c9-3c1ab6b305eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202690719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3202690719
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2923116184
Short name T869
Test name
Test status
Simulation time 5058054029 ps
CPU time 5.45 seconds
Started Jun 28 05:35:03 PM PDT 24
Finished Jun 28 05:35:09 PM PDT 24
Peak memory 221716 kb
Host smart-b10a1e94-6074-4d31-9cd7-c140c95a0a4e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2923116184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2923116184
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1390442228
Short name T945
Test name
Test status
Simulation time 2436476080 ps
CPU time 17.14 seconds
Started Jun 28 05:34:54 PM PDT 24
Finished Jun 28 05:35:12 PM PDT 24
Peak memory 220804 kb
Host smart-90056a27-5741-435d-bbd4-9b8a6f529c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390442228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1390442228
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3301881377
Short name T498
Test name
Test status
Simulation time 29440907748 ps
CPU time 20.61 seconds
Started Jun 28 05:34:57 PM PDT 24
Finished Jun 28 05:35:19 PM PDT 24
Peak memory 217024 kb
Host smart-7842fe22-1d77-4f39-b3df-f37c6a6acd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301881377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3301881377
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2680896277
Short name T521
Test name
Test status
Simulation time 68919837 ps
CPU time 1.01 seconds
Started Jun 28 05:34:56 PM PDT 24
Finished Jun 28 05:34:58 PM PDT 24
Peak memory 207936 kb
Host smart-22cda805-cf0c-43f1-a441-ce878b9438f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680896277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2680896277
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1374702354
Short name T989
Test name
Test status
Simulation time 79389175 ps
CPU time 0.76 seconds
Started Jun 28 05:34:59 PM PDT 24
Finished Jun 28 05:35:01 PM PDT 24
Peak memory 206380 kb
Host smart-aa58d2cf-9c9a-484a-9adb-c451fdefb894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374702354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1374702354
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.638765549
Short name T362
Test name
Test status
Simulation time 3204501083 ps
CPU time 5.04 seconds
Started Jun 28 05:34:57 PM PDT 24
Finished Jun 28 05:35:03 PM PDT 24
Peak memory 225128 kb
Host smart-3e03447f-c2ab-46a2-a0c1-4d3e29f8f485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638765549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.638765549
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3018527624
Short name T72
Test name
Test status
Simulation time 15103824 ps
CPU time 0.73 seconds
Started Jun 28 05:35:04 PM PDT 24
Finished Jun 28 05:35:07 PM PDT 24
Peak memory 205404 kb
Host smart-3621b027-0580-4287-90ed-996051b7d884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018527624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3018527624
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2528169123
Short name T426
Test name
Test status
Simulation time 35751282116 ps
CPU time 27.11 seconds
Started Jun 28 05:35:10 PM PDT 24
Finished Jun 28 05:35:38 PM PDT 24
Peak memory 225064 kb
Host smart-9176c357-926d-4058-bed9-078a10148b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528169123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2528169123
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.894319301
Short name T307
Test name
Test status
Simulation time 21585594 ps
CPU time 0.91 seconds
Started Jun 28 05:35:04 PM PDT 24
Finished Jun 28 05:35:07 PM PDT 24
Peak memory 207028 kb
Host smart-da3df15c-f90c-4321-8293-d53868fe7f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894319301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.894319301
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3332206714
Short name T223
Test name
Test status
Simulation time 1238270294 ps
CPU time 15.2 seconds
Started Jun 28 05:35:10 PM PDT 24
Finished Jun 28 05:35:26 PM PDT 24
Peak memory 225028 kb
Host smart-ec52b41d-9670-4944-b3ad-ea166af7d751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332206714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3332206714
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.4149371204
Short name T614
Test name
Test status
Simulation time 581560546547 ps
CPU time 387.27 seconds
Started Jun 28 05:35:04 PM PDT 24
Finished Jun 28 05:41:33 PM PDT 24
Peak memory 249996 kb
Host smart-df3b766c-1639-4961-b221-732f637e0463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149371204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4149371204
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1676248263
Short name T847
Test name
Test status
Simulation time 19710889349 ps
CPU time 103 seconds
Started Jun 28 05:35:06 PM PDT 24
Finished Jun 28 05:36:50 PM PDT 24
Peak memory 257864 kb
Host smart-60420393-217b-4afb-b8c4-f9ff484a5259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676248263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1676248263
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2784997698
Short name T874
Test name
Test status
Simulation time 5681525242 ps
CPU time 63.84 seconds
Started Jun 28 05:35:07 PM PDT 24
Finished Jun 28 05:36:12 PM PDT 24
Peak memory 233340 kb
Host smart-496099b9-d38d-4953-b144-15e48fde61b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784997698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2784997698
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2539692018
Short name T718
Test name
Test status
Simulation time 77580547345 ps
CPU time 171.63 seconds
Started Jun 28 05:35:07 PM PDT 24
Finished Jun 28 05:38:00 PM PDT 24
Peak memory 255572 kb
Host smart-9f8c53f3-b320-450a-bc85-d54b6e7aa064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539692018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2539692018
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1056651607
Short name T744
Test name
Test status
Simulation time 3967533220 ps
CPU time 18.71 seconds
Started Jun 28 05:35:05 PM PDT 24
Finished Jun 28 05:35:26 PM PDT 24
Peak memory 233352 kb
Host smart-707b8751-17a8-4ce7-8513-8895bb68d241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056651607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1056651607
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4188735744
Short name T626
Test name
Test status
Simulation time 3933526795 ps
CPU time 11.7 seconds
Started Jun 28 05:35:04 PM PDT 24
Finished Jun 28 05:35:18 PM PDT 24
Peak memory 231004 kb
Host smart-236fa365-4f0c-43df-a252-a9b6fb6e1de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188735744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4188735744
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3360491505
Short name T88
Test name
Test status
Simulation time 1435437185 ps
CPU time 12.19 seconds
Started Jun 28 05:35:04 PM PDT 24
Finished Jun 28 05:35:19 PM PDT 24
Peak memory 249268 kb
Host smart-bbaecdd2-660f-496b-9d5a-80836212fda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360491505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3360491505
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2599316846
Short name T7
Test name
Test status
Simulation time 510712737 ps
CPU time 5.17 seconds
Started Jun 28 05:35:09 PM PDT 24
Finished Jun 28 05:35:14 PM PDT 24
Peak memory 225028 kb
Host smart-584718aa-33a2-4c6f-b97c-f2227a58e833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599316846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2599316846
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.287301252
Short name T941
Test name
Test status
Simulation time 71128672 ps
CPU time 4.01 seconds
Started Jun 28 05:35:04 PM PDT 24
Finished Jun 28 05:35:10 PM PDT 24
Peak memory 224100 kb
Host smart-8b713bf4-0e13-4a52-ba6b-e6ad1d30dcb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=287301252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.287301252
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3629451089
Short name T376
Test name
Test status
Simulation time 47866870903 ps
CPU time 116.17 seconds
Started Jun 28 05:35:04 PM PDT 24
Finished Jun 28 05:37:03 PM PDT 24
Peak memory 256356 kb
Host smart-9ddf518a-7f50-44c8-babe-8c083474f3e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629451089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3629451089
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.387719310
Short name T286
Test name
Test status
Simulation time 11106042462 ps
CPU time 32.08 seconds
Started Jun 28 05:35:10 PM PDT 24
Finished Jun 28 05:35:43 PM PDT 24
Peak memory 216824 kb
Host smart-a93b178b-9894-43b6-885e-784df023b3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387719310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.387719310
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1109000750
Short name T906
Test name
Test status
Simulation time 287976799 ps
CPU time 2.59 seconds
Started Jun 28 05:35:05 PM PDT 24
Finished Jun 28 05:35:10 PM PDT 24
Peak memory 216768 kb
Host smart-4f6b89d0-9b97-4f18-9259-a885a4b3d91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109000750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1109000750
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2180520839
Short name T960
Test name
Test status
Simulation time 40273607 ps
CPU time 1.25 seconds
Started Jun 28 05:35:05 PM PDT 24
Finished Jun 28 05:35:08 PM PDT 24
Peak memory 208376 kb
Host smart-b27c1502-e535-4581-a1d1-6ef970dc45c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180520839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2180520839
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1919383873
Short name T588
Test name
Test status
Simulation time 32322988 ps
CPU time 0.83 seconds
Started Jun 28 05:35:07 PM PDT 24
Finished Jun 28 05:35:09 PM PDT 24
Peak memory 206456 kb
Host smart-6de452a5-8907-4f26-ad59-08263f914bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919383873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1919383873
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3861389634
Short name T328
Test name
Test status
Simulation time 13676472492 ps
CPU time 10.02 seconds
Started Jun 28 05:35:04 PM PDT 24
Finished Jun 28 05:35:17 PM PDT 24
Peak memory 233240 kb
Host smart-71e07c6d-e540-4781-b32d-e32081b1739c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861389634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3861389634
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3889921896
Short name T963
Test name
Test status
Simulation time 30110803 ps
CPU time 0.72 seconds
Started Jun 28 05:35:15 PM PDT 24
Finished Jun 28 05:35:17 PM PDT 24
Peak memory 205948 kb
Host smart-d9a91633-2d7c-47c1-b36a-23af32246276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889921896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3889921896
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.393585260
Short name T294
Test name
Test status
Simulation time 1814395966 ps
CPU time 18.19 seconds
Started Jun 28 05:35:04 PM PDT 24
Finished Jun 28 05:35:24 PM PDT 24
Peak memory 224940 kb
Host smart-e1e5ab7e-7246-4e47-bae0-8dead9deecd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393585260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.393585260
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.553301018
Short name T676
Test name
Test status
Simulation time 48359207 ps
CPU time 0.86 seconds
Started Jun 28 05:35:06 PM PDT 24
Finished Jun 28 05:35:08 PM PDT 24
Peak memory 207364 kb
Host smart-11a43ee6-f484-40c0-8fdd-e662ed850363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553301018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.553301018
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.296559875
Short name T850
Test name
Test status
Simulation time 21579255209 ps
CPU time 61.76 seconds
Started Jun 28 05:35:16 PM PDT 24
Finished Jun 28 05:36:19 PM PDT 24
Peak memory 249728 kb
Host smart-d033921b-8bea-4b29-8848-77ac19d91ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296559875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.296559875
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.526357240
Short name T540
Test name
Test status
Simulation time 64412189115 ps
CPU time 147.13 seconds
Started Jun 28 05:35:16 PM PDT 24
Finished Jun 28 05:37:45 PM PDT 24
Peak memory 274204 kb
Host smart-e8642cf1-1337-4e87-b9d5-b9f4f4f10b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526357240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.526357240
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3522627544
Short name T277
Test name
Test status
Simulation time 1415868927 ps
CPU time 14.43 seconds
Started Jun 28 05:35:15 PM PDT 24
Finished Jun 28 05:35:30 PM PDT 24
Peak memory 233372 kb
Host smart-fc794efd-eef2-4398-a147-61c8a30b2960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522627544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3522627544
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1476945425
Short name T44
Test name
Test status
Simulation time 36297341006 ps
CPU time 53.67 seconds
Started Jun 28 05:35:15 PM PDT 24
Finished Jun 28 05:36:10 PM PDT 24
Peak memory 251628 kb
Host smart-89cdaa73-be79-41b7-802e-632eaa163f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476945425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1476945425
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1466793718
Short name T509
Test name
Test status
Simulation time 209803509 ps
CPU time 3.82 seconds
Started Jun 28 05:35:04 PM PDT 24
Finished Jun 28 05:35:10 PM PDT 24
Peak memory 233160 kb
Host smart-b3574521-fa11-4e56-907c-e61fa706d321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466793718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1466793718
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2689674624
Short name T889
Test name
Test status
Simulation time 31897821464 ps
CPU time 65.74 seconds
Started Jun 28 05:35:12 PM PDT 24
Finished Jun 28 05:36:18 PM PDT 24
Peak memory 225080 kb
Host smart-5ddab324-c7e1-442c-bd10-4363088531c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689674624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2689674624
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2645402441
Short name T238
Test name
Test status
Simulation time 206336026 ps
CPU time 2.49 seconds
Started Jun 28 05:35:04 PM PDT 24
Finished Jun 28 05:35:08 PM PDT 24
Peak memory 224900 kb
Host smart-09d0e000-d0be-4627-a2e5-8de1b5117168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645402441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2645402441
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2467500745
Short name T334
Test name
Test status
Simulation time 490894182 ps
CPU time 2.91 seconds
Started Jun 28 05:35:10 PM PDT 24
Finished Jun 28 05:35:14 PM PDT 24
Peak memory 233144 kb
Host smart-763caf38-3c8b-41e1-862e-99c6c6bd0cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467500745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2467500745
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2559622801
Short name T857
Test name
Test status
Simulation time 1629055214 ps
CPU time 12.48 seconds
Started Jun 28 05:35:17 PM PDT 24
Finished Jun 28 05:35:31 PM PDT 24
Peak memory 219380 kb
Host smart-25ed99ca-07ca-4bda-a770-37f62119c04b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2559622801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2559622801
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2092878818
Short name T21
Test name
Test status
Simulation time 18108913571 ps
CPU time 243.26 seconds
Started Jun 28 05:35:18 PM PDT 24
Finished Jun 28 05:39:22 PM PDT 24
Peak memory 266868 kb
Host smart-243d54b8-ce1d-4d1f-8ae9-200beb0efd35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092878818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2092878818
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1832590698
Short name T338
Test name
Test status
Simulation time 18919924159 ps
CPU time 23.98 seconds
Started Jun 28 05:35:10 PM PDT 24
Finished Jun 28 05:35:35 PM PDT 24
Peak memory 218268 kb
Host smart-d3a21d18-a7a3-4b0c-a37b-708cea5f3b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832590698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1832590698
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.768088581
Short name T590
Test name
Test status
Simulation time 1048449658 ps
CPU time 2.67 seconds
Started Jun 28 05:35:07 PM PDT 24
Finished Jun 28 05:35:11 PM PDT 24
Peak memory 216772 kb
Host smart-eae62aa0-9261-4c90-bcd7-54ac6b84a88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768088581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.768088581
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2114365207
Short name T692
Test name
Test status
Simulation time 110098437 ps
CPU time 0.83 seconds
Started Jun 28 05:35:10 PM PDT 24
Finished Jun 28 05:35:12 PM PDT 24
Peak memory 206480 kb
Host smart-7b0bf0d7-9c9a-41b2-81b4-c4aceb372939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114365207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2114365207
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.967448578
Short name T360
Test name
Test status
Simulation time 117901331 ps
CPU time 0.84 seconds
Started Jun 28 05:35:06 PM PDT 24
Finished Jun 28 05:35:08 PM PDT 24
Peak memory 206692 kb
Host smart-69d736ac-e33a-4a70-bb90-b4cf21fff6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967448578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.967448578
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3322458579
Short name T248
Test name
Test status
Simulation time 3138569715 ps
CPU time 3.57 seconds
Started Jun 28 05:35:06 PM PDT 24
Finished Jun 28 05:35:11 PM PDT 24
Peak memory 225076 kb
Host smart-945676ea-bc37-453e-8556-a1de5e95231a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322458579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3322458579
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1147490858
Short name T501
Test name
Test status
Simulation time 25870904 ps
CPU time 0.76 seconds
Started Jun 28 05:35:18 PM PDT 24
Finished Jun 28 05:35:19 PM PDT 24
Peak memory 205384 kb
Host smart-4b55657d-29f8-43bc-bed5-76ad8979c982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147490858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1147490858
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3259155670
Short name T967
Test name
Test status
Simulation time 8752542264 ps
CPU time 33.77 seconds
Started Jun 28 05:35:17 PM PDT 24
Finished Jun 28 05:35:52 PM PDT 24
Peak memory 225080 kb
Host smart-4c34213d-af8b-4353-be30-70a6de7e4b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259155670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3259155670
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1379865522
Short name T440
Test name
Test status
Simulation time 13984031 ps
CPU time 0.8 seconds
Started Jun 28 05:35:17 PM PDT 24
Finished Jun 28 05:35:19 PM PDT 24
Peak memory 207416 kb
Host smart-52d1ce12-2b74-4c96-8ee9-afd5afd75c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379865522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1379865522
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3555757266
Short name T353
Test name
Test status
Simulation time 30377385292 ps
CPU time 125.55 seconds
Started Jun 28 05:35:16 PM PDT 24
Finished Jun 28 05:37:22 PM PDT 24
Peak memory 251064 kb
Host smart-bc5cc462-1e23-49db-8344-27206011ed6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555757266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3555757266
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2798972530
Short name T936
Test name
Test status
Simulation time 36413418055 ps
CPU time 141.18 seconds
Started Jun 28 05:35:17 PM PDT 24
Finished Jun 28 05:37:39 PM PDT 24
Peak memory 241636 kb
Host smart-879e439f-9995-4556-ab2e-2e4253cbb666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798972530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2798972530
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4275863661
Short name T388
Test name
Test status
Simulation time 12193354952 ps
CPU time 35.85 seconds
Started Jun 28 05:35:16 PM PDT 24
Finished Jun 28 05:35:53 PM PDT 24
Peak memory 233332 kb
Host smart-ddf01908-f729-4b03-8c1e-2c14a748a2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275863661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4275863661
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.560636775
Short name T220
Test name
Test status
Simulation time 4018632228 ps
CPU time 45.54 seconds
Started Jun 28 05:35:17 PM PDT 24
Finished Jun 28 05:36:04 PM PDT 24
Peak memory 241524 kb
Host smart-f4d59797-10e0-425a-a29a-0e0c2527091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560636775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.560636775
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2005432452
Short name T797
Test name
Test status
Simulation time 873877716 ps
CPU time 4.27 seconds
Started Jun 28 05:35:17 PM PDT 24
Finished Jun 28 05:35:23 PM PDT 24
Peak memory 233160 kb
Host smart-06370b9f-28df-4436-bca5-0a0031a85c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005432452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2005432452
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3340879829
Short name T867
Test name
Test status
Simulation time 489729296 ps
CPU time 9.77 seconds
Started Jun 28 05:35:16 PM PDT 24
Finished Jun 28 05:35:27 PM PDT 24
Peak memory 239628 kb
Host smart-bb2c8d29-05e1-4b87-a9f1-749148b242d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340879829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3340879829
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2938852178
Short name T444
Test name
Test status
Simulation time 1083958649 ps
CPU time 7.17 seconds
Started Jun 28 05:35:16 PM PDT 24
Finished Jun 28 05:35:25 PM PDT 24
Peak memory 224960 kb
Host smart-549052c8-19be-453c-9286-976079a4ec1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938852178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2938852178
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3613423691
Short name T662
Test name
Test status
Simulation time 229636351 ps
CPU time 2.08 seconds
Started Jun 28 05:35:15 PM PDT 24
Finished Jun 28 05:35:18 PM PDT 24
Peak memory 224928 kb
Host smart-cdb2dee0-e9ff-4893-bc34-51d4700a2ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613423691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3613423691
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3633845532
Short name T147
Test name
Test status
Simulation time 119270998 ps
CPU time 4.38 seconds
Started Jun 28 05:35:16 PM PDT 24
Finished Jun 28 05:35:22 PM PDT 24
Peak memory 220636 kb
Host smart-b8b79e42-d837-44f4-b669-fad2e6b9a176
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3633845532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3633845532
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4057289635
Short name T258
Test name
Test status
Simulation time 78315686145 ps
CPU time 543.95 seconds
Started Jun 28 05:35:15 PM PDT 24
Finished Jun 28 05:44:20 PM PDT 24
Peak memory 270312 kb
Host smart-bfb15458-b190-4a07-9895-7a9ae40449e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057289635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4057289635
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3587606851
Short name T658
Test name
Test status
Simulation time 2837650102 ps
CPU time 15.77 seconds
Started Jun 28 05:35:18 PM PDT 24
Finished Jun 28 05:35:34 PM PDT 24
Peak memory 216896 kb
Host smart-418623bd-c0ff-4da7-aa7d-2067bcac2e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587606851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3587606851
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2490270807
Short name T371
Test name
Test status
Simulation time 4317041236 ps
CPU time 5.81 seconds
Started Jun 28 05:35:16 PM PDT 24
Finished Jun 28 05:35:23 PM PDT 24
Peak memory 216884 kb
Host smart-12275a5c-dde7-4dee-a746-055ddd2f897d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490270807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2490270807
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.462975119
Short name T921
Test name
Test status
Simulation time 713064701 ps
CPU time 1.05 seconds
Started Jun 28 05:35:18 PM PDT 24
Finished Jun 28 05:35:20 PM PDT 24
Peak memory 208368 kb
Host smart-899a18f2-3ef0-4fd1-a4bb-f768e90803f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462975119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.462975119
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2617659880
Short name T828
Test name
Test status
Simulation time 10409886 ps
CPU time 0.69 seconds
Started Jun 28 05:35:16 PM PDT 24
Finished Jun 28 05:35:17 PM PDT 24
Peak memory 206124 kb
Host smart-9e3ea7e4-8a5f-4e2d-876f-a1eaccfc0902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617659880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2617659880
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3304461934
Short name T246
Test name
Test status
Simulation time 30810749593 ps
CPU time 24.43 seconds
Started Jun 28 05:35:17 PM PDT 24
Finished Jun 28 05:35:43 PM PDT 24
Peak memory 233260 kb
Host smart-210021c9-55eb-49f5-b0ee-1ca2e121f799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304461934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3304461934
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3148977880
Short name T824
Test name
Test status
Simulation time 11335414 ps
CPU time 0.72 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:35:29 PM PDT 24
Peak memory 205908 kb
Host smart-b933d06d-41af-47bd-9c98-aaa3445bc808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148977880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3148977880
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3017070622
Short name T466
Test name
Test status
Simulation time 174641851 ps
CPU time 2.37 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:35:30 PM PDT 24
Peak memory 224988 kb
Host smart-1c0ad0ee-a909-46d7-90de-efd175baa68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017070622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3017070622
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4113914575
Short name T580
Test name
Test status
Simulation time 108646015 ps
CPU time 0.78 seconds
Started Jun 28 05:35:29 PM PDT 24
Finished Jun 28 05:35:32 PM PDT 24
Peak memory 207084 kb
Host smart-629f410e-9b56-4aa6-a55a-4f74349722b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113914575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4113914575
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2279475507
Short name T849
Test name
Test status
Simulation time 72307232978 ps
CPU time 506.78 seconds
Started Jun 28 05:35:28 PM PDT 24
Finished Jun 28 05:43:56 PM PDT 24
Peak memory 272804 kb
Host smart-dd1c1065-0615-41b8-92ad-1fe917f2542d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279475507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2279475507
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.333574032
Short name T587
Test name
Test status
Simulation time 79715135396 ps
CPU time 116.04 seconds
Started Jun 28 05:35:29 PM PDT 24
Finished Jun 28 05:37:28 PM PDT 24
Peak memory 250280 kb
Host smart-56e5226a-632a-4357-8476-7b6d6149b28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333574032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.333574032
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2527941085
Short name T672
Test name
Test status
Simulation time 42228241191 ps
CPU time 110.07 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:37:18 PM PDT 24
Peak memory 255620 kb
Host smart-94a71872-87ba-40a1-a28c-dc25dfa6e207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527941085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2527941085
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3335283348
Short name T470
Test name
Test status
Simulation time 57105717 ps
CPU time 2.45 seconds
Started Jun 28 05:35:29 PM PDT 24
Finished Jun 28 05:35:34 PM PDT 24
Peak memory 233236 kb
Host smart-d93e1e75-a866-4ecf-a6da-c984d6472d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335283348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3335283348
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2011184237
Short name T180
Test name
Test status
Simulation time 5652206865 ps
CPU time 9.94 seconds
Started Jun 28 05:35:34 PM PDT 24
Finished Jun 28 05:35:45 PM PDT 24
Peak memory 233312 kb
Host smart-6727849e-73f0-40a4-9724-592f4e809daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011184237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2011184237
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.109060653
Short name T532
Test name
Test status
Simulation time 470905253 ps
CPU time 3 seconds
Started Jun 28 05:35:35 PM PDT 24
Finished Jun 28 05:35:39 PM PDT 24
Peak memory 224932 kb
Host smart-646866c2-964e-41f8-b884-4a1bfbc98bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109060653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.109060653
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3414828015
Short name T560
Test name
Test status
Simulation time 1216954877 ps
CPU time 15.06 seconds
Started Jun 28 05:35:28 PM PDT 24
Finished Jun 28 05:35:46 PM PDT 24
Peak memory 224936 kb
Host smart-f90503ec-dc82-4f97-90ee-c1d5376dde0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414828015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3414828015
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3015628931
Short name T884
Test name
Test status
Simulation time 5101413388 ps
CPU time 12.57 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:35:41 PM PDT 24
Peak memory 238676 kb
Host smart-f6c9a9f7-9248-4588-810b-28d211411ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015628931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3015628931
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.565817025
Short name T782
Test name
Test status
Simulation time 3203202594 ps
CPU time 7.97 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:35:37 PM PDT 24
Peak memory 241244 kb
Host smart-71231bf3-86b5-4a0b-8495-078f5adb0aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565817025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.565817025
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.989634411
Short name T591
Test name
Test status
Simulation time 326932790 ps
CPU time 3.94 seconds
Started Jun 28 05:35:30 PM PDT 24
Finished Jun 28 05:35:36 PM PDT 24
Peak memory 223116 kb
Host smart-457b73cf-f8fe-4674-a968-38008fe6415b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=989634411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.989634411
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3666344749
Short name T573
Test name
Test status
Simulation time 5403976734 ps
CPU time 58.19 seconds
Started Jun 28 05:35:28 PM PDT 24
Finished Jun 28 05:36:29 PM PDT 24
Peak memory 241668 kb
Host smart-04c82636-2ad9-438e-b949-0a052649fc41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666344749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3666344749
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.847476575
Short name T739
Test name
Test status
Simulation time 1458882694 ps
CPU time 8.45 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:35:36 PM PDT 24
Peak memory 219760 kb
Host smart-13c7c3e6-7e51-470e-a63e-28f74dd4a3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847476575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.847476575
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.580382129
Short name T893
Test name
Test status
Simulation time 2268549389 ps
CPU time 9.46 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:35:38 PM PDT 24
Peak memory 216888 kb
Host smart-e0761d06-ae49-4e53-aaeb-56633caf7f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580382129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.580382129
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.203635660
Short name T881
Test name
Test status
Simulation time 106128734 ps
CPU time 1.85 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:35:30 PM PDT 24
Peak memory 208568 kb
Host smart-fbb78e07-fa27-4848-9294-0b079788bb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203635660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.203635660
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.986812743
Short name T882
Test name
Test status
Simulation time 35706740 ps
CPU time 0.83 seconds
Started Jun 28 05:35:28 PM PDT 24
Finished Jun 28 05:35:31 PM PDT 24
Peak memory 206464 kb
Host smart-8149bdb2-e26a-4eeb-9d35-1eab783d828c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986812743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.986812743
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.89451661
Short name T865
Test name
Test status
Simulation time 33659127529 ps
CPU time 29.42 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:35:58 PM PDT 24
Peak memory 233248 kb
Host smart-753be190-6291-490e-9a68-6624cae1e27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89451661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.89451661
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.792123341
Short name T517
Test name
Test status
Simulation time 18196669 ps
CPU time 0.79 seconds
Started Jun 28 05:35:26 PM PDT 24
Finished Jun 28 05:35:28 PM PDT 24
Peak memory 205376 kb
Host smart-8aa94072-2169-4aa9-8586-e9b64ae01ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792123341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.792123341
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3287209155
Short name T892
Test name
Test status
Simulation time 960321838 ps
CPU time 4.49 seconds
Started Jun 28 05:35:26 PM PDT 24
Finished Jun 28 05:35:31 PM PDT 24
Peak memory 233192 kb
Host smart-8ce84e64-0d28-40fe-bcfa-b4a923623e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287209155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3287209155
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2942185938
Short name T607
Test name
Test status
Simulation time 24728918 ps
CPU time 0.78 seconds
Started Jun 28 05:35:30 PM PDT 24
Finished Jun 28 05:35:33 PM PDT 24
Peak memory 207080 kb
Host smart-54cec85e-a9a1-4586-830b-649d5fe43871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942185938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2942185938
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3270233876
Short name T891
Test name
Test status
Simulation time 107245230776 ps
CPU time 404.51 seconds
Started Jun 28 05:35:31 PM PDT 24
Finished Jun 28 05:42:17 PM PDT 24
Peak memory 268764 kb
Host smart-9649778f-b6fa-4fba-a934-447a898f695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270233876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3270233876
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1854490463
Short name T491
Test name
Test status
Simulation time 51690671994 ps
CPU time 311.98 seconds
Started Jun 28 05:35:29 PM PDT 24
Finished Jun 28 05:40:44 PM PDT 24
Peak memory 258040 kb
Host smart-dd9a407f-4296-42ea-958b-bfc2acdb21ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854490463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1854490463
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1784580050
Short name T378
Test name
Test status
Simulation time 14070801963 ps
CPU time 38.44 seconds
Started Jun 28 05:35:28 PM PDT 24
Finished Jun 28 05:36:09 PM PDT 24
Peak memory 233288 kb
Host smart-3bc45de4-0aa8-4f33-ac61-7f1f5d598c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784580050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1784580050
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.64005018
Short name T203
Test name
Test status
Simulation time 6044365706 ps
CPU time 11.81 seconds
Started Jun 28 05:35:28 PM PDT 24
Finished Jun 28 05:35:43 PM PDT 24
Peak memory 225092 kb
Host smart-15ff0179-8487-4e53-890f-964dd69a12fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64005018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.64005018
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.208267954
Short name T206
Test name
Test status
Simulation time 1891885820 ps
CPU time 19.75 seconds
Started Jun 28 05:35:30 PM PDT 24
Finished Jun 28 05:35:52 PM PDT 24
Peak memory 233152 kb
Host smart-46945102-54c7-47b4-965d-6718852a05ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208267954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.208267954
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1707480311
Short name T57
Test name
Test status
Simulation time 27914782456 ps
CPU time 19.61 seconds
Started Jun 28 05:35:30 PM PDT 24
Finished Jun 28 05:35:52 PM PDT 24
Peak memory 233252 kb
Host smart-c5351687-9216-4bb3-bee9-592351fed379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707480311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1707480311
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2708324935
Short name T758
Test name
Test status
Simulation time 5215768204 ps
CPU time 15.79 seconds
Started Jun 28 05:35:28 PM PDT 24
Finished Jun 28 05:35:47 PM PDT 24
Peak memory 233272 kb
Host smart-1d8358d4-7ea4-4e49-ab94-fcd22b60e177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708324935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2708324935
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.797721540
Short name T331
Test name
Test status
Simulation time 1066185155 ps
CPU time 11.48 seconds
Started Jun 28 05:35:29 PM PDT 24
Finished Jun 28 05:35:43 PM PDT 24
Peak memory 221120 kb
Host smart-154df9ba-07ba-492f-8be6-399738fcb2e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=797721540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.797721540
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2396074912
Short name T267
Test name
Test status
Simulation time 19607879441 ps
CPU time 184.75 seconds
Started Jun 28 05:35:28 PM PDT 24
Finished Jun 28 05:38:35 PM PDT 24
Peak memory 266272 kb
Host smart-ffc78ee1-1b95-4f77-b8d4-c201db4329ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396074912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2396074912
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4112335815
Short name T413
Test name
Test status
Simulation time 8471801739 ps
CPU time 15.54 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:35:45 PM PDT 24
Peak memory 220380 kb
Host smart-93aa4d0a-d39c-40e3-97f6-c06065bf6d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112335815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4112335815
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.845224480
Short name T493
Test name
Test status
Simulation time 504604778 ps
CPU time 2.65 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:35:32 PM PDT 24
Peak memory 216768 kb
Host smart-dc20212d-1767-4e46-b3e0-8ad21209050e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845224480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.845224480
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3132612249
Short name T370
Test name
Test status
Simulation time 835221057 ps
CPU time 2.94 seconds
Started Jun 28 05:35:28 PM PDT 24
Finished Jun 28 05:35:33 PM PDT 24
Peak memory 216724 kb
Host smart-d4803ef8-435d-46fe-973b-ee4c8b6fa2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132612249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3132612249
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2279192451
Short name T699
Test name
Test status
Simulation time 27259653 ps
CPU time 0.89 seconds
Started Jun 28 05:35:35 PM PDT 24
Finished Jun 28 05:35:37 PM PDT 24
Peak memory 206420 kb
Host smart-c1d47d7c-b382-4faf-a9dc-b06bbb96feac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279192451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2279192451
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.210370949
Short name T225
Test name
Test status
Simulation time 289174754 ps
CPU time 5 seconds
Started Jun 28 05:35:29 PM PDT 24
Finished Jun 28 05:35:37 PM PDT 24
Peak memory 233132 kb
Host smart-bab62cf8-969e-4b8b-928a-b34a79628b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210370949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.210370949
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3901540665
Short name T598
Test name
Test status
Simulation time 16357768 ps
CPU time 0.77 seconds
Started Jun 28 05:35:41 PM PDT 24
Finished Jun 28 05:35:42 PM PDT 24
Peak memory 205928 kb
Host smart-efb71b6f-5636-41d2-9152-8fdf5ea7b6bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901540665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3901540665
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.237222647
Short name T804
Test name
Test status
Simulation time 592017702 ps
CPU time 3.25 seconds
Started Jun 28 05:35:28 PM PDT 24
Finished Jun 28 05:35:34 PM PDT 24
Peak memory 225012 kb
Host smart-49e25ee7-c41d-49a8-86b3-7b9ede942cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237222647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.237222647
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3083456557
Short name T456
Test name
Test status
Simulation time 11763695 ps
CPU time 0.77 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:35:29 PM PDT 24
Peak memory 206064 kb
Host smart-4df416c3-2e25-4562-b1ec-3eafd57d6c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083456557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3083456557
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2072949370
Short name T236
Test name
Test status
Simulation time 5702705633 ps
CPU time 63.61 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:36:32 PM PDT 24
Peak memory 264172 kb
Host smart-d9eb96e7-3c17-4023-b1d9-d6ea6eb820eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072949370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2072949370
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2423061403
Short name T930
Test name
Test status
Simulation time 9581126445 ps
CPU time 76.46 seconds
Started Jun 28 05:35:29 PM PDT 24
Finished Jun 28 05:36:48 PM PDT 24
Peak memory 241568 kb
Host smart-b11850c8-25d1-4753-9d33-96f57afcf14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423061403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2423061403
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.273036687
Short name T952
Test name
Test status
Simulation time 8625100309 ps
CPU time 89.7 seconds
Started Jun 28 05:35:40 PM PDT 24
Finished Jun 28 05:37:11 PM PDT 24
Peak memory 249812 kb
Host smart-64174e0e-0b78-4943-8627-317792bf0a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273036687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.273036687
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2464742330
Short name T291
Test name
Test status
Simulation time 203475358 ps
CPU time 3.52 seconds
Started Jun 28 05:35:26 PM PDT 24
Finished Jun 28 05:35:30 PM PDT 24
Peak memory 233220 kb
Host smart-f097a287-a9cf-4e7f-b3e7-3a5e8e67fc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464742330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2464742330
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1740202581
Short name T170
Test name
Test status
Simulation time 328569784525 ps
CPU time 248.69 seconds
Started Jun 28 05:35:29 PM PDT 24
Finished Jun 28 05:39:40 PM PDT 24
Peak memory 255924 kb
Host smart-404f992f-912e-440b-9ff9-618ed757d4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740202581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1740202581
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.19005914
Short name T190
Test name
Test status
Simulation time 1874640043 ps
CPU time 10.85 seconds
Started Jun 28 05:35:35 PM PDT 24
Finished Jun 28 05:35:46 PM PDT 24
Peak memory 224980 kb
Host smart-e80441c1-c3ef-40c0-91e2-c1f086e29aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19005914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.19005914
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1233383200
Short name T667
Test name
Test status
Simulation time 2582048309 ps
CPU time 9.55 seconds
Started Jun 28 05:35:29 PM PDT 24
Finished Jun 28 05:35:41 PM PDT 24
Peak memory 225008 kb
Host smart-eeb60d4f-c276-46fd-bf6f-6199a47f9c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233383200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1233383200
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3655208988
Short name T907
Test name
Test status
Simulation time 158858903 ps
CPU time 3.17 seconds
Started Jun 28 05:35:29 PM PDT 24
Finished Jun 28 05:35:35 PM PDT 24
Peak memory 224960 kb
Host smart-fdad3dbb-323c-41f3-9f5e-0f1a0ee77740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655208988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3655208988
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1569009078
Short name T969
Test name
Test status
Simulation time 885517312 ps
CPU time 8.28 seconds
Started Jun 28 05:35:28 PM PDT 24
Finished Jun 28 05:35:39 PM PDT 24
Peak memory 241660 kb
Host smart-eec0889d-f951-49ef-9a6c-bda80f7bc02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569009078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1569009078
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3384196426
Short name T148
Test name
Test status
Simulation time 2737016765 ps
CPU time 14.39 seconds
Started Jun 28 05:35:29 PM PDT 24
Finished Jun 28 05:35:46 PM PDT 24
Peak memory 219380 kb
Host smart-3f975d12-5665-4ada-ac29-e3a1898ac1b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3384196426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3384196426
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.927592384
Short name T56
Test name
Test status
Simulation time 3558731331 ps
CPU time 18.06 seconds
Started Jun 28 05:35:29 PM PDT 24
Finished Jun 28 05:35:50 PM PDT 24
Peak memory 216884 kb
Host smart-1561173b-1f45-476e-90ac-ea84c9449ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927592384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.927592384
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.832082740
Short name T578
Test name
Test status
Simulation time 675710812 ps
CPU time 4.23 seconds
Started Jun 28 05:35:30 PM PDT 24
Finished Jun 28 05:35:36 PM PDT 24
Peak memory 216696 kb
Host smart-9eb76e85-bb43-4bb3-a433-58ade27e003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832082740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.832082740
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4123602820
Short name T671
Test name
Test status
Simulation time 13737415 ps
CPU time 0.71 seconds
Started Jun 28 05:35:29 PM PDT 24
Finished Jun 28 05:35:33 PM PDT 24
Peak memory 206044 kb
Host smart-bd77af58-3a74-4413-8a67-778742ad42e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123602820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4123602820
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.509813800
Short name T421
Test name
Test status
Simulation time 46542615 ps
CPU time 0.74 seconds
Started Jun 28 05:35:30 PM PDT 24
Finished Jun 28 05:35:33 PM PDT 24
Peak memory 206456 kb
Host smart-e01869fa-3872-4bb1-8e38-b4ead2525dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509813800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.509813800
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2877358220
Short name T996
Test name
Test status
Simulation time 1483113877 ps
CPU time 7.06 seconds
Started Jun 28 05:35:27 PM PDT 24
Finished Jun 28 05:35:36 PM PDT 24
Peak memory 233096 kb
Host smart-13333604-5d74-42ae-8396-b88fdb84cae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877358220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2877358220
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3605807967
Short name T651
Test name
Test status
Simulation time 42891349 ps
CPU time 0.73 seconds
Started Jun 28 05:31:57 PM PDT 24
Finished Jun 28 05:32:00 PM PDT 24
Peak memory 205920 kb
Host smart-19ffa068-5cbf-4087-bee6-a61f8f893ac6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605807967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
605807967
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.486289006
Short name T229
Test name
Test status
Simulation time 136458413 ps
CPU time 2.1 seconds
Started Jun 28 05:31:58 PM PDT 24
Finished Jun 28 05:32:02 PM PDT 24
Peak memory 224932 kb
Host smart-50a0c04b-afca-42c5-a9ec-3ba7a5ea019c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486289006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.486289006
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2304648464
Short name T494
Test name
Test status
Simulation time 224377431 ps
CPU time 0.76 seconds
Started Jun 28 05:31:57 PM PDT 24
Finished Jun 28 05:31:59 PM PDT 24
Peak memory 207092 kb
Host smart-0e4fca53-1b49-4200-bbbe-6fa472d9b528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304648464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2304648464
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2012433010
Short name T841
Test name
Test status
Simulation time 36964970824 ps
CPU time 296.34 seconds
Started Jun 28 05:31:59 PM PDT 24
Finished Jun 28 05:36:56 PM PDT 24
Peak memory 266068 kb
Host smart-8acc0aa7-87f6-44b8-b6d5-e3fd4f37356d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012433010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2012433010
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1845884355
Short name T615
Test name
Test status
Simulation time 5411726328 ps
CPU time 76.44 seconds
Started Jun 28 05:31:57 PM PDT 24
Finished Jun 28 05:33:15 PM PDT 24
Peak memory 253848 kb
Host smart-2d8ee064-d37a-4c88-a17c-d5f11d724672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845884355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1845884355
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.280239873
Short name T138
Test name
Test status
Simulation time 1478378230 ps
CPU time 20.3 seconds
Started Jun 28 05:32:02 PM PDT 24
Finished Jun 28 05:32:22 PM PDT 24
Peak memory 233352 kb
Host smart-5b8ceab8-6a52-40b1-bd20-b7f839a9c115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280239873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
280239873
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2229977964
Short name T721
Test name
Test status
Simulation time 589340164 ps
CPU time 13.52 seconds
Started Jun 28 05:31:56 PM PDT 24
Finished Jun 28 05:32:11 PM PDT 24
Peak memory 224940 kb
Host smart-43b60d02-35a5-4431-b36c-621e6e91cfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229977964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2229977964
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1449125682
Short name T958
Test name
Test status
Simulation time 1137506821 ps
CPU time 14.46 seconds
Started Jun 28 05:31:57 PM PDT 24
Finished Jun 28 05:32:13 PM PDT 24
Peak memory 225012 kb
Host smart-31e7af82-5329-40ea-ae02-a8dde6c8116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449125682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1449125682
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3308333698
Short name T224
Test name
Test status
Simulation time 246967064 ps
CPU time 3.11 seconds
Started Jun 28 05:31:53 PM PDT 24
Finished Jun 28 05:31:57 PM PDT 24
Peak memory 233232 kb
Host smart-a252dde5-7661-4cb6-a444-7e30e35189cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308333698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3308333698
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3684416564
Short name T683
Test name
Test status
Simulation time 69062614840 ps
CPU time 25.26 seconds
Started Jun 28 05:31:59 PM PDT 24
Finished Jun 28 05:32:25 PM PDT 24
Peak memory 237852 kb
Host smart-97f99c17-6b90-4ce7-8bbb-977e317dce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684416564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3684416564
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2334464406
Short name T50
Test name
Test status
Simulation time 16121616808 ps
CPU time 26.79 seconds
Started Jun 28 05:31:56 PM PDT 24
Finished Jun 28 05:32:24 PM PDT 24
Peak memory 250640 kb
Host smart-97197be5-4aff-4b65-80a6-69f8043d339e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334464406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2334464406
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3939221783
Short name T714
Test name
Test status
Simulation time 3155156533 ps
CPU time 5.22 seconds
Started Jun 28 05:31:56 PM PDT 24
Finished Jun 28 05:32:02 PM PDT 24
Peak memory 220484 kb
Host smart-67b67fe2-bcf6-4b86-b3bb-1e05529692c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939221783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3939221783
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1903567938
Short name T67
Test name
Test status
Simulation time 93396835 ps
CPU time 4.67 seconds
Started Jun 28 05:31:57 PM PDT 24
Finished Jun 28 05:32:03 PM PDT 24
Peak memory 223496 kb
Host smart-ba8e2061-278d-48ae-89de-e2555084047b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1903567938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1903567938
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.700546396
Short name T20
Test name
Test status
Simulation time 5307089257 ps
CPU time 127.5 seconds
Started Jun 28 05:31:58 PM PDT 24
Finished Jun 28 05:34:07 PM PDT 24
Peak memory 271212 kb
Host smart-01c072c7-434a-4c7e-9f9f-bd161efbe228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700546396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.700546396
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2002163225
Short name T858
Test name
Test status
Simulation time 624220153 ps
CPU time 7.73 seconds
Started Jun 28 05:31:57 PM PDT 24
Finished Jun 28 05:32:07 PM PDT 24
Peak memory 216884 kb
Host smart-28f63420-3836-48ca-8265-9573dc497b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002163225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2002163225
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1912437416
Short name T98
Test name
Test status
Simulation time 63083921410 ps
CPU time 18.53 seconds
Started Jun 28 05:31:57 PM PDT 24
Finished Jun 28 05:32:17 PM PDT 24
Peak memory 217032 kb
Host smart-d70bf9b1-0ad1-482c-8759-630bdc577b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912437416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1912437416
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2492482538
Short name T422
Test name
Test status
Simulation time 74574503 ps
CPU time 1.28 seconds
Started Jun 28 05:31:56 PM PDT 24
Finished Jun 28 05:31:57 PM PDT 24
Peak memory 216824 kb
Host smart-a1318a6b-e34f-4621-9344-757ab8f16c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492482538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2492482538
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.735189446
Short name T947
Test name
Test status
Simulation time 20406498 ps
CPU time 0.68 seconds
Started Jun 28 05:31:56 PM PDT 24
Finished Jun 28 05:31:58 PM PDT 24
Peak memory 206124 kb
Host smart-772fe135-a91e-4158-8f35-0a59d65a8482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735189446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.735189446
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2868039558
Short name T705
Test name
Test status
Simulation time 567257106 ps
CPU time 6.07 seconds
Started Jun 28 05:31:56 PM PDT 24
Finished Jun 28 05:32:03 PM PDT 24
Peak memory 233260 kb
Host smart-7b08ea41-0f71-4f53-98bd-0ce6b52adcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868039558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2868039558
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3242373325
Short name T474
Test name
Test status
Simulation time 26830546 ps
CPU time 0.75 seconds
Started Jun 28 05:32:09 PM PDT 24
Finished Jun 28 05:32:10 PM PDT 24
Peak memory 205940 kb
Host smart-1e68f1e3-6514-40dc-a1f0-371dec65f0b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242373325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
242373325
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3289455122
Short name T233
Test name
Test status
Simulation time 134878657 ps
CPU time 3.38 seconds
Started Jun 28 05:32:04 PM PDT 24
Finished Jun 28 05:32:08 PM PDT 24
Peak memory 233156 kb
Host smart-64673463-8cab-4356-87fe-a5779a455057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289455122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3289455122
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2727303267
Short name T567
Test name
Test status
Simulation time 23001414 ps
CPU time 0.87 seconds
Started Jun 28 05:31:57 PM PDT 24
Finished Jun 28 05:31:59 PM PDT 24
Peak memory 207420 kb
Host smart-659d3ff7-2ea3-4ed2-b53b-644163ab4f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727303267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2727303267
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.950328707
Short name T724
Test name
Test status
Simulation time 22172490635 ps
CPU time 79.95 seconds
Started Jun 28 05:32:13 PM PDT 24
Finished Jun 28 05:33:34 PM PDT 24
Peak memory 241520 kb
Host smart-800eef4d-860c-4222-9f0c-5473dc084829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950328707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.950328707
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1238326702
Short name T643
Test name
Test status
Simulation time 53893693536 ps
CPU time 272.63 seconds
Started Jun 28 05:32:09 PM PDT 24
Finished Jun 28 05:36:42 PM PDT 24
Peak memory 256568 kb
Host smart-037c6cfd-64bf-4de2-8002-7cbe9107c90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238326702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1238326702
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4192512027
Short name T568
Test name
Test status
Simulation time 630164732 ps
CPU time 9.39 seconds
Started Jun 28 05:32:01 PM PDT 24
Finished Jun 28 05:32:10 PM PDT 24
Peak memory 224944 kb
Host smart-5ff39056-0580-49cc-bd37-0c930da21d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192512027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4192512027
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3829445481
Short name T661
Test name
Test status
Simulation time 12504760 ps
CPU time 0.78 seconds
Started Jun 28 05:31:58 PM PDT 24
Finished Jun 28 05:32:00 PM PDT 24
Peak memory 216544 kb
Host smart-7f34c941-ac26-4f25-ab25-5d99467e420c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829445481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3829445481
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1952424031
Short name T565
Test name
Test status
Simulation time 3882204906 ps
CPU time 8.91 seconds
Started Jun 28 05:32:03 PM PDT 24
Finished Jun 28 05:32:12 PM PDT 24
Peak memory 225140 kb
Host smart-c20de675-ab4f-4ce7-aa89-1ebd17ec28bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952424031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1952424031
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.867625165
Short name T843
Test name
Test status
Simulation time 41717286521 ps
CPU time 29.89 seconds
Started Jun 28 05:32:04 PM PDT 24
Finished Jun 28 05:32:35 PM PDT 24
Peak memory 233272 kb
Host smart-bd524bf3-2e7d-47b9-af3c-128055ae41c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867625165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.867625165
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.67545054
Short name T257
Test name
Test status
Simulation time 17339875529 ps
CPU time 12.41 seconds
Started Jun 28 05:32:04 PM PDT 24
Finished Jun 28 05:32:17 PM PDT 24
Peak memory 240960 kb
Host smart-479b240c-84e5-4329-a2eb-c8ed337f44a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67545054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.67545054
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3378274903
Short name T243
Test name
Test status
Simulation time 1587927947 ps
CPU time 8.74 seconds
Started Jun 28 05:31:57 PM PDT 24
Finished Jun 28 05:32:07 PM PDT 24
Peak memory 233208 kb
Host smart-c0aefef3-6ad0-445f-88cf-bbc528aed32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378274903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3378274903
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1391105627
Short name T405
Test name
Test status
Simulation time 7905496761 ps
CPU time 6.85 seconds
Started Jun 28 05:32:07 PM PDT 24
Finished Jun 28 05:32:15 PM PDT 24
Peak memory 222728 kb
Host smart-07cdce4b-abc6-4f38-a6c7-1235a69b8fe5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1391105627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1391105627
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1599944117
Short name T995
Test name
Test status
Simulation time 6935880676 ps
CPU time 109.87 seconds
Started Jun 28 05:32:09 PM PDT 24
Finished Jun 28 05:34:00 PM PDT 24
Peak memory 256856 kb
Host smart-3e6aeaee-7f3f-46a9-a84c-d7118f12de9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599944117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1599944117
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1920185967
Short name T853
Test name
Test status
Simulation time 2962356035 ps
CPU time 9.57 seconds
Started Jun 28 05:31:59 PM PDT 24
Finished Jun 28 05:32:09 PM PDT 24
Peak memory 216908 kb
Host smart-b5d1d9a6-f309-419f-8d0a-3840687c93b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920185967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1920185967
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1351134918
Short name T485
Test name
Test status
Simulation time 11904476999 ps
CPU time 9.59 seconds
Started Jun 28 05:32:01 PM PDT 24
Finished Jun 28 05:32:12 PM PDT 24
Peak memory 216924 kb
Host smart-ad9fa1fd-244e-4f51-9a63-c7b2e78d828d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351134918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1351134918
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.291160051
Short name T775
Test name
Test status
Simulation time 12687355 ps
CPU time 0.68 seconds
Started Jun 28 05:31:59 PM PDT 24
Finished Jun 28 05:32:01 PM PDT 24
Peak memory 206108 kb
Host smart-d9f97896-3d5d-4309-ad05-5ad0bdee220e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291160051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.291160051
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.731394251
Short name T1002
Test name
Test status
Simulation time 96146246 ps
CPU time 0.85 seconds
Started Jun 28 05:31:59 PM PDT 24
Finished Jun 28 05:32:01 PM PDT 24
Peak memory 206436 kb
Host smart-898a7899-7a48-46ac-a58c-4e3f7cbb6206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731394251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.731394251
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3678329462
Short name T29
Test name
Test status
Simulation time 54668455019 ps
CPU time 41.07 seconds
Started Jun 28 05:31:58 PM PDT 24
Finished Jun 28 05:32:40 PM PDT 24
Peak memory 250360 kb
Host smart-083d3f43-d5a1-4ec2-97e6-6dcac79f4dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678329462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3678329462
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.787588236
Short name T73
Test name
Test status
Simulation time 45662329 ps
CPU time 0.74 seconds
Started Jun 28 05:32:12 PM PDT 24
Finished Jun 28 05:32:14 PM PDT 24
Peak memory 206288 kb
Host smart-a9ecef05-bc22-477b-9f1b-8bbd29de39d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787588236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.787588236
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.16859792
Short name T942
Test name
Test status
Simulation time 199871028 ps
CPU time 4.75 seconds
Started Jun 28 05:32:11 PM PDT 24
Finished Jun 28 05:32:16 PM PDT 24
Peak memory 233120 kb
Host smart-5835aeb0-ed5e-4d40-8c44-7fbd8776b5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16859792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.16859792
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.199938524
Short name T709
Test name
Test status
Simulation time 18234760 ps
CPU time 0.74 seconds
Started Jun 28 05:32:11 PM PDT 24
Finished Jun 28 05:32:12 PM PDT 24
Peak memory 207364 kb
Host smart-7c03aaf7-ef35-4146-b594-c0306ad12d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199938524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.199938524
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3044329399
Short name T901
Test name
Test status
Simulation time 3834926811 ps
CPU time 70.87 seconds
Started Jun 28 05:32:13 PM PDT 24
Finished Jun 28 05:33:25 PM PDT 24
Peak memory 254904 kb
Host smart-d1107266-6531-43ec-b624-06cf242b4ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044329399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3044329399
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.231128582
Short name T37
Test name
Test status
Simulation time 80093581274 ps
CPU time 344.26 seconds
Started Jun 28 05:32:12 PM PDT 24
Finished Jun 28 05:37:57 PM PDT 24
Peak memory 257940 kb
Host smart-6ab549b2-64be-4e77-bd50-aa6c92625aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231128582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.231128582
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3439708463
Short name T984
Test name
Test status
Simulation time 14880806338 ps
CPU time 89.22 seconds
Started Jun 28 05:32:08 PM PDT 24
Finished Jun 28 05:33:39 PM PDT 24
Peak memory 267156 kb
Host smart-3ee02c2f-9840-4a6c-9800-07b2a4945011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439708463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3439708463
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1959659377
Short name T821
Test name
Test status
Simulation time 116411242 ps
CPU time 3.73 seconds
Started Jun 28 05:32:08 PM PDT 24
Finished Jun 28 05:32:12 PM PDT 24
Peak memory 224984 kb
Host smart-fd2c326d-db59-41fd-a420-35016289dbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959659377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1959659377
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1347286801
Short name T228
Test name
Test status
Simulation time 52166155741 ps
CPU time 392.68 seconds
Started Jun 28 05:32:12 PM PDT 24
Finished Jun 28 05:38:46 PM PDT 24
Peak memory 269060 kb
Host smart-27339437-08cd-4807-bc56-2a5683827270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347286801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1347286801
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2300500897
Short name T439
Test name
Test status
Simulation time 57958869 ps
CPU time 2.62 seconds
Started Jun 28 05:32:12 PM PDT 24
Finished Jun 28 05:32:15 PM PDT 24
Peak memory 233040 kb
Host smart-0257cd14-b5e4-4299-a2be-fd975763afb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300500897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2300500897
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.843404602
Short name T783
Test name
Test status
Simulation time 337992553 ps
CPU time 6.19 seconds
Started Jun 28 05:32:09 PM PDT 24
Finished Jun 28 05:32:16 PM PDT 24
Peak memory 233208 kb
Host smart-25be02e6-a7a8-4329-ac31-4447ba42ae10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843404602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.843404602
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1704095687
Short name T389
Test name
Test status
Simulation time 2183353501 ps
CPU time 6.24 seconds
Started Jun 28 05:32:09 PM PDT 24
Finished Jun 28 05:32:17 PM PDT 24
Peak memory 225136 kb
Host smart-9b95acb1-c481-4877-96d1-f9cb16506eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704095687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1704095687
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2873024073
Short name T379
Test name
Test status
Simulation time 755119665 ps
CPU time 2.33 seconds
Started Jun 28 05:32:12 PM PDT 24
Finished Jun 28 05:32:15 PM PDT 24
Peak memory 224384 kb
Host smart-cda991ec-42cb-4219-a1fc-827079b0e540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873024073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2873024073
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2357954460
Short name T596
Test name
Test status
Simulation time 419143029 ps
CPU time 5.35 seconds
Started Jun 28 05:32:09 PM PDT 24
Finished Jun 28 05:32:15 PM PDT 24
Peak memory 221056 kb
Host smart-a6c9fecd-e277-4030-a39f-3f861cb264b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2357954460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2357954460
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1569642739
Short name T988
Test name
Test status
Simulation time 122769331036 ps
CPU time 270.55 seconds
Started Jun 28 05:32:12 PM PDT 24
Finished Jun 28 05:36:44 PM PDT 24
Peak memory 249800 kb
Host smart-5e15f3e0-f417-4c25-9fd1-9195f1215717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569642739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1569642739
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1802716981
Short name T288
Test name
Test status
Simulation time 9408246380 ps
CPU time 52.12 seconds
Started Jun 28 05:32:09 PM PDT 24
Finished Jun 28 05:33:02 PM PDT 24
Peak memory 216860 kb
Host smart-96092f9d-56e6-4d09-913c-1ad83dc973b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802716981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1802716981
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2424077980
Short name T716
Test name
Test status
Simulation time 4523649817 ps
CPU time 16.3 seconds
Started Jun 28 05:32:10 PM PDT 24
Finished Jun 28 05:32:27 PM PDT 24
Peak memory 216876 kb
Host smart-129b8dfa-6646-47ba-af2a-82ee4ef3467d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424077980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2424077980
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2216863839
Short name T905
Test name
Test status
Simulation time 18289045 ps
CPU time 0.87 seconds
Started Jun 28 05:32:08 PM PDT 24
Finished Jun 28 05:32:10 PM PDT 24
Peak memory 207024 kb
Host smart-86a68cfd-0e59-4534-bbae-26e3a92c1956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216863839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2216863839
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4259078093
Short name T460
Test name
Test status
Simulation time 416968066 ps
CPU time 1.01 seconds
Started Jun 28 05:32:09 PM PDT 24
Finished Jun 28 05:32:11 PM PDT 24
Peak memory 206932 kb
Host smart-57d23ce8-c002-4195-b214-b15cce92766d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259078093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4259078093
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2824549892
Short name T215
Test name
Test status
Simulation time 6181957462 ps
CPU time 11.43 seconds
Started Jun 28 05:32:12 PM PDT 24
Finished Jun 28 05:32:25 PM PDT 24
Peak memory 233316 kb
Host smart-227b3fef-39c2-4b37-86fc-a31e92529a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824549892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2824549892
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3002897480
Short name T820
Test name
Test status
Simulation time 33165890 ps
CPU time 0.73 seconds
Started Jun 28 05:32:30 PM PDT 24
Finished Jun 28 05:32:31 PM PDT 24
Peak memory 206288 kb
Host smart-e53e6d75-640b-4c8b-992c-ba6e0eef3240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002897480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
002897480
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2636766598
Short name T182
Test name
Test status
Simulation time 64849538 ps
CPU time 2.49 seconds
Started Jun 28 05:32:20 PM PDT 24
Finished Jun 28 05:32:24 PM PDT 24
Peak memory 233184 kb
Host smart-1bb694a6-a1dc-4ae0-b2ee-418ece812e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636766598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2636766598
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2024623939
Short name T919
Test name
Test status
Simulation time 60953822 ps
CPU time 0.78 seconds
Started Jun 28 05:32:28 PM PDT 24
Finished Jun 28 05:32:29 PM PDT 24
Peak memory 206068 kb
Host smart-0882b0b1-48a1-4115-808c-cb7e1f426ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024623939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2024623939
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.4186769139
Short name T876
Test name
Test status
Simulation time 91613472213 ps
CPU time 154.89 seconds
Started Jun 28 05:32:20 PM PDT 24
Finished Jun 28 05:34:56 PM PDT 24
Peak memory 249724 kb
Host smart-4f0c2fb6-cae6-4a01-9f46-234e0abb8d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186769139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4186769139
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3750550408
Short name T196
Test name
Test status
Simulation time 12125663474 ps
CPU time 151.59 seconds
Started Jun 28 05:32:28 PM PDT 24
Finished Jun 28 05:35:00 PM PDT 24
Peak memory 262864 kb
Host smart-7466eb67-ef9f-4858-88e8-b5ed05d999f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750550408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3750550408
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1056792192
Short name T897
Test name
Test status
Simulation time 4288017528 ps
CPU time 106.64 seconds
Started Jun 28 05:32:21 PM PDT 24
Finished Jun 28 05:34:09 PM PDT 24
Peak memory 265604 kb
Host smart-8b1e8ede-9db9-42b3-8897-972716e595ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056792192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1056792192
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2998141615
Short name T65
Test name
Test status
Simulation time 514968668 ps
CPU time 10.24 seconds
Started Jun 28 05:32:19 PM PDT 24
Finished Jun 28 05:32:30 PM PDT 24
Peak memory 224988 kb
Host smart-b7db52f3-168b-4993-b07f-0dda8eda9375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998141615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2998141615
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.500645036
Short name T704
Test name
Test status
Simulation time 22791151858 ps
CPU time 23.51 seconds
Started Jun 28 05:32:20 PM PDT 24
Finished Jun 28 05:32:44 PM PDT 24
Peak memory 225080 kb
Host smart-b30599dc-7620-46dc-8371-aca1e4a21510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500645036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
500645036
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3541893670
Short name T404
Test name
Test status
Simulation time 356641336 ps
CPU time 4.94 seconds
Started Jun 28 05:32:20 PM PDT 24
Finished Jun 28 05:32:26 PM PDT 24
Peak memory 224960 kb
Host smart-80de4760-137f-4232-849c-cee7476ee269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541893670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3541893670
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2112608827
Short name T541
Test name
Test status
Simulation time 11429136196 ps
CPU time 11.65 seconds
Started Jun 28 05:32:19 PM PDT 24
Finished Jun 28 05:32:31 PM PDT 24
Peak memory 233296 kb
Host smart-47bf527b-1ab5-414e-abb6-4f8195b889a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112608827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2112608827
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1185881463
Short name T746
Test name
Test status
Simulation time 97033288 ps
CPU time 2.32 seconds
Started Jun 28 05:32:21 PM PDT 24
Finished Jun 28 05:32:24 PM PDT 24
Peak memory 224364 kb
Host smart-ae4309ee-6fdb-44ad-89e2-155cff1b5f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185881463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1185881463
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1716586142
Short name T522
Test name
Test status
Simulation time 497273119 ps
CPU time 6.5 seconds
Started Jun 28 05:32:20 PM PDT 24
Finished Jun 28 05:32:28 PM PDT 24
Peak memory 234188 kb
Host smart-b800d211-ad1c-4504-85c7-b7657084b122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716586142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1716586142
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2445293851
Short name T563
Test name
Test status
Simulation time 193847522 ps
CPU time 4.03 seconds
Started Jun 28 05:32:22 PM PDT 24
Finished Jun 28 05:32:27 PM PDT 24
Peak memory 219892 kb
Host smart-7affb770-8dc8-4525-8b53-f3af05b5dcd1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2445293851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2445293851
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1003286681
Short name T730
Test name
Test status
Simulation time 50610097605 ps
CPU time 394.74 seconds
Started Jun 28 05:32:22 PM PDT 24
Finished Jun 28 05:38:58 PM PDT 24
Peak memory 264624 kb
Host smart-6c1c8195-7fc9-402e-9831-dd0f828fbb18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003286681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1003286681
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.72774483
Short name T285
Test name
Test status
Simulation time 7011490638 ps
CPU time 38.96 seconds
Started Jun 28 05:32:20 PM PDT 24
Finished Jun 28 05:33:00 PM PDT 24
Peak memory 220688 kb
Host smart-1cfe39d0-8b73-457f-8bf7-d73a9dc8b6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72774483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.72774483
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.4213417352
Short name T770
Test name
Test status
Simulation time 19393374566 ps
CPU time 5.86 seconds
Started Jun 28 05:32:23 PM PDT 24
Finished Jun 28 05:32:29 PM PDT 24
Peak memory 216896 kb
Host smart-f9840eb9-a586-4987-8011-3e1c70e7c0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213417352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.4213417352
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3283318010
Short name T317
Test name
Test status
Simulation time 17779508 ps
CPU time 0.82 seconds
Started Jun 28 05:32:20 PM PDT 24
Finished Jun 28 05:32:22 PM PDT 24
Peak memory 206504 kb
Host smart-7065b123-69b2-42c8-9424-0ecbf6a6b165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283318010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3283318010
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.448694386
Short name T695
Test name
Test status
Simulation time 157250075 ps
CPU time 0.84 seconds
Started Jun 28 05:32:18 PM PDT 24
Finished Jun 28 05:32:20 PM PDT 24
Peak memory 206456 kb
Host smart-77c7102e-7c02-42bd-8663-c771b4ad2764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448694386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.448694386
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1683627009
Short name T623
Test name
Test status
Simulation time 3403940783 ps
CPU time 8.21 seconds
Started Jun 28 05:32:22 PM PDT 24
Finished Jun 28 05:32:31 PM PDT 24
Peak memory 233336 kb
Host smart-776d900d-19e2-4d48-a46d-51923fc1e80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683627009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1683627009
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.458877009
Short name T305
Test name
Test status
Simulation time 17504892 ps
CPU time 0.76 seconds
Started Jun 28 05:32:21 PM PDT 24
Finished Jun 28 05:32:23 PM PDT 24
Peak memory 205404 kb
Host smart-131c2a35-d6a3-462f-aee4-f66df1ca829b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458877009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.458877009
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1987280606
Short name T555
Test name
Test status
Simulation time 941493967 ps
CPU time 13.26 seconds
Started Jun 28 05:32:27 PM PDT 24
Finished Jun 28 05:32:41 PM PDT 24
Peak memory 225024 kb
Host smart-0a5d773c-84fb-4919-834a-d3ad7eb1f725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987280606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1987280606
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.658965917
Short name T946
Test name
Test status
Simulation time 40228803 ps
CPU time 0.82 seconds
Started Jun 28 05:32:27 PM PDT 24
Finished Jun 28 05:32:28 PM PDT 24
Peak memory 206212 kb
Host smart-c8fd6fcb-c06f-4973-8465-54d78b2e06d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658965917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.658965917
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3836963564
Short name T707
Test name
Test status
Simulation time 39194420524 ps
CPU time 74.82 seconds
Started Jun 28 05:32:21 PM PDT 24
Finished Jun 28 05:33:37 PM PDT 24
Peak memory 241524 kb
Host smart-58d8c51f-b417-4128-9da0-232a063adec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836963564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3836963564
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2106290225
Short name T42
Test name
Test status
Simulation time 4625631399 ps
CPU time 105.07 seconds
Started Jun 28 05:32:20 PM PDT 24
Finished Jun 28 05:34:06 PM PDT 24
Peak memory 258392 kb
Host smart-51bb18c8-f58b-45c2-b00b-f421046a3c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106290225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2106290225
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.701162709
Short name T34
Test name
Test status
Simulation time 67000402612 ps
CPU time 99.94 seconds
Started Jun 28 05:32:21 PM PDT 24
Finished Jun 28 05:34:02 PM PDT 24
Peak memory 240488 kb
Host smart-64d13aad-d729-417f-8912-0c166054a700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701162709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
701162709
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1792375398
Short name T673
Test name
Test status
Simulation time 62587137 ps
CPU time 2.83 seconds
Started Jun 28 05:32:21 PM PDT 24
Finished Jun 28 05:32:25 PM PDT 24
Peak memory 233144 kb
Host smart-4d81129c-186c-4c0a-8f3e-26e23dcc6ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792375398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1792375398
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1133029495
Short name T69
Test name
Test status
Simulation time 2352026124 ps
CPU time 29.98 seconds
Started Jun 28 05:32:29 PM PDT 24
Finished Jun 28 05:32:59 PM PDT 24
Peak memory 249724 kb
Host smart-e7041e25-a03d-4d62-af3d-c3b51686eb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133029495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1133029495
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3716788930
Short name T125
Test name
Test status
Simulation time 9737025387 ps
CPU time 9.8 seconds
Started Jun 28 05:32:20 PM PDT 24
Finished Jun 28 05:32:32 PM PDT 24
Peak memory 233352 kb
Host smart-641b16a1-1cd7-4f3f-b44f-85fcdc6ca1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716788930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3716788930
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2591517792
Short name T227
Test name
Test status
Simulation time 1570412726 ps
CPU time 10.12 seconds
Started Jun 28 05:32:19 PM PDT 24
Finished Jun 28 05:32:29 PM PDT 24
Peak memory 241400 kb
Host smart-2e5cdb83-a765-4967-9ba1-a0631b3a88f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591517792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2591517792
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.477232814
Short name T90
Test name
Test status
Simulation time 992687050 ps
CPU time 4.38 seconds
Started Jun 28 05:32:22 PM PDT 24
Finished Jun 28 05:32:27 PM PDT 24
Peak memory 224984 kb
Host smart-20bd43ad-af15-4150-b325-88936ce9ec94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477232814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
477232814
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3448575271
Short name T754
Test name
Test status
Simulation time 103283352 ps
CPU time 2.36 seconds
Started Jun 28 05:32:20 PM PDT 24
Finished Jun 28 05:32:24 PM PDT 24
Peak memory 224504 kb
Host smart-5d439637-1f81-4acf-abed-3e0cdc844e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448575271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3448575271
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1959110723
Short name T693
Test name
Test status
Simulation time 1187871144 ps
CPU time 11.16 seconds
Started Jun 28 05:32:22 PM PDT 24
Finished Jun 28 05:32:34 PM PDT 24
Peak memory 221408 kb
Host smart-84dea2ef-d8c6-4d16-b074-f581cb03ad6c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1959110723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1959110723
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.82752569
Short name T948
Test name
Test status
Simulation time 7219226070 ps
CPU time 95.04 seconds
Started Jun 28 05:32:21 PM PDT 24
Finished Jun 28 05:33:57 PM PDT 24
Peak memory 257908 kb
Host smart-4bd3a74f-3a32-41df-b3ac-79feaf315d41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82752569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_
all.82752569
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3129915176
Short name T656
Test name
Test status
Simulation time 379871848 ps
CPU time 3.66 seconds
Started Jun 28 05:32:21 PM PDT 24
Finished Jun 28 05:32:26 PM PDT 24
Peak memory 219652 kb
Host smart-6fe3b3fe-aa4f-4335-9ba9-35a99c11b2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129915176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3129915176
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2406027532
Short name T513
Test name
Test status
Simulation time 4671446385 ps
CPU time 14 seconds
Started Jun 28 05:32:22 PM PDT 24
Finished Jun 28 05:32:37 PM PDT 24
Peak memory 216764 kb
Host smart-982acbcc-77a0-4483-884f-8ff04e409305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406027532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2406027532
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2333663704
Short name T639
Test name
Test status
Simulation time 390201234 ps
CPU time 1.57 seconds
Started Jun 28 05:32:30 PM PDT 24
Finished Jun 28 05:32:32 PM PDT 24
Peak memory 216772 kb
Host smart-82e61d5f-af06-473c-9dbf-70ba569d7096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333663704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2333663704
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2213178276
Short name T31
Test name
Test status
Simulation time 25473344 ps
CPU time 0.82 seconds
Started Jun 28 05:32:22 PM PDT 24
Finished Jun 28 05:32:24 PM PDT 24
Peak memory 206432 kb
Host smart-8dcd2a91-3154-4e4a-8dd1-272708ea907d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213178276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2213178276
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.146878443
Short name T957
Test name
Test status
Simulation time 5860536842 ps
CPU time 22.95 seconds
Started Jun 28 05:32:21 PM PDT 24
Finished Jun 28 05:32:45 PM PDT 24
Peak memory 240548 kb
Host smart-6baa1b2e-bfa7-481d-a915-11f23e9adfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146878443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.146878443
Directory /workspace/9.spi_device_upload/latest
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