Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2359354	1			T1	1		T2	1		T4	13
all_values[1]	2359354	1			T1	1		T2	1		T4	13
all_values[2]	2359354	1			T1	1		T2	1		T4	13
all_values[3]	2359354	1			T1	1		T2	1		T4	13
all_values[4]	2359354	1			T1	1		T2	1		T4	13
all_values[5]	2359354	1			T1	1		T2	1		T4	13
all_values[6]	2359354	1			T1	1		T2	1		T4	13
all_values[7]	2359354	1			T1	1		T2	1		T4	13

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18220044

1

T1

8

T2

8

T4

104

auto[1]

654788

1

T13

70

T65

29

T15

71

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18850179

1

T1

8

T2

8

T4

104

auto[1]

24653

1

T6

531

T13

52

T14

404

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2279766	1			T1	1		T2	1		T4	13
all_values[0]	auto[0]	auto[1]	11344	1			T6	357		T13	2		T14	235
all_values[0]	auto[1]	auto[0]	67646	1			T13	8		T65	4		T15	8
all_values[0]	auto[1]	auto[1]	598	1			T13	3		T65	3		T15	6
all_values[1]	auto[0]	auto[0]	2237147	1			T1	1		T2	1		T4	13
all_values[1]	auto[0]	auto[1]	7442	1			T6	139		T13	5		T14	114
all_values[1]	auto[1]	auto[0]	114453	1			T13	3		T65	5		T15	5
all_values[1]	auto[1]	auto[1]	312	1			T13	3		T15	6		T16	4
all_values[2]	auto[0]	auto[0]	2230159	1			T1	1		T2	1		T4	13
all_values[2]	auto[0]	auto[1]	2807	1			T6	35		T13	4		T14	55
all_values[2]	auto[1]	auto[0]	126096	1			T13	4		T15	2		T16	2
all_values[2]	auto[1]	auto[1]	292	1			T13	4		T65	2		T15	4
all_values[3]	auto[0]	auto[0]	2281892	1			T1	1		T2	1		T4	13
all_values[3]	auto[0]	auto[1]	196	1			T13	5		T15	5		T16	2
all_values[3]	auto[1]	auto[0]	77072	1			T13	2		T65	1		T15	3
all_values[3]	auto[1]	auto[1]	194	1			T13	4		T15	4		T16	6
all_values[4]	auto[0]	auto[0]	2278509	1			T1	1		T2	1		T4	13
all_values[4]	auto[0]	auto[1]	206	1			T13	5		T65	4		T15	6
all_values[4]	auto[1]	auto[0]	80452	1			T13	2		T15	1		T16	6
all_values[4]	auto[1]	auto[1]	187	1			T13	1		T15	5		T18	2
all_values[5]	auto[0]	auto[0]	2288009	1			T1	1		T2	1		T4	13
all_values[5]	auto[0]	auto[1]	163	1			T13	2		T15	5		T16	1
all_values[5]	auto[1]	auto[0]	71003	1			T13	10		T65	4		T15	1
all_values[5]	auto[1]	auto[1]	179	1			T13	2		T65	3		T15	3
all_values[6]	auto[0]	auto[0]	2246152	1			T1	1		T2	1		T4	13
all_values[6]	auto[0]	auto[1]	170	1			T13	3		T15	6		T18	2
all_values[6]	auto[1]	auto[0]	112842	1			T13	5		T15	2		T16	9
all_values[6]	auto[1]	auto[1]	190	1			T13	6		T65	1		T15	10
all_values[7]	auto[0]	auto[0]	2355891	1			T1	1		T2	1		T4	13
all_values[7]	auto[0]	auto[1]	191	1			T65	1		T15	5		T16	2
all_values[7]	auto[1]	auto[0]	3090	1			T13	10		T65	3		T15	7
all_values[7]	auto[1]	auto[1]	182	1			T13	3		T65	3		T15	4