Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34065	1			T1	2		T6	290		T8	10
auto[SpiFlashAddrCfg]	7766	1			T6	59		T7	4		T10	2
auto[SpiFlashAddr3b]	9286	1			T2	2		T6	89		T7	2
auto[SpiFlashAddr4b]	7759	1			T2	2		T6	73		T14	32

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32956

1

T1

2

T2

4

T6

270

auto[1]

25920

1

T6

241

T8

12

T14

105

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31608

1

T2

4

T6

295

T7

2

auto[1]

27268

1

T1

2

T6

216

T7

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38823	1			T1	2		T6	333		T8	6
values[1]	1091	1			T6	9		T14	7		T24	4
values[2]	1408	1			T6	11		T8	4		T14	7
values[3]	1479	1			T6	10		T7	2		T14	10
values[4]	1495	1			T2	2		T6	14		T14	5
values[5]	1482	1			T6	13		T14	10		T24	8
values[6]	1574	1			T6	16		T14	9		T24	20
values[7]	1481	1			T6	13		T7	2		T10	2
values[8]	10043	1			T2	2		T6	92		T7	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33707

1

T1

2

T7

6

T8

12

auto[1]

25169

1

T2

4

T6

511

T43

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55621

1

T1

2

T2

4

T6

490

write

3255

1

T6

21

T14

10

T24

15

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19725

1

T2

4

T6

218

T7

6

valids[0x1]

39151

1

T1

2

T6

293

T8

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1555	1			T6	16		T10	2		T12	2
internal_process_ops[0x5a]	1595	1			T6	20		T14	5		T24	8
internal_process_ops[0x05]	19963	1			T6	129		T8	2		T14	77
internal_process_ops[0x35]	1575	1			T1	2		T6	15		T14	3
internal_process_ops[0x15]	1581	1			T6	20		T8	4		T14	3
internal_process_ops[0x03]	1081	1			T6	7		T14	8		T24	13
internal_process_ops[0x0b]	1137	1			T6	5		T14	5		T24	9
internal_process_ops[0x3b]	1183	1			T2	2		T6	8		T7	2
internal_process_ops[0x6b]	1095	1			T2	2		T6	4		T7	2
internal_process_ops[0xbb]	1182	1			T6	9		T8	2		T14	9
internal_process_ops[0xeb]	1114	1			T6	4		T7	2		T14	7

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57168

1

T1

2

T2

4

T6

501

auto[1]

1708

1

T6

10

T14

6

T24

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56443

1

T1

2

T2

4

T6

483

auto[1]

2433

1

T6

28

T14

18

T24

14

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11181

1

T1

2

T9

18

T12

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7187

1

T8

10

T14

53

T24

32

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2298

1

T7

4

T10

2

T14

17

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1919

1

T14

18

T24

26

T36

19

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2705

1

T7

2

T14

16

T24

33

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2415

1

T8

2

T14

20

T24

28

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2171

1

T14

21

T24

36

T36

25

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2088

1

T14

10

T24

29

T36

23

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

123

1

T14

1

T45

2

T49

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

87

1

T24

1

T49

4

T51

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

103

1

T24

3

T37

1

T38

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

123

1

T38

3

T49

6

T50

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

120

1

T14

2

T27

1

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

116

1

T14

2

T49

1

T50

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T14

1

T36

1

T51

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

116

1

T36

3

T27

1

T37

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

117

1

T27

2

T98

2

T37

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

100

1

T36

3

T38

1

T50

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

81

1

T24

5

T36

2

T27

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

121

1

T14

3

T36

2

T37

7

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

133

1

T24

2

T37

1

T174

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

109

1

T14

1

T24

1

T27

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

84

1

T36

1

T27

1

T37

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

115

1

T24

3

T36

1

T38

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8454

1

T6

153

T15

141

T42

81

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6369

1

T6

125

T15

106

T42

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1431

1

T6

40

T43

1

T15

27

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1316

1

T6

18

T15

17

T42

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1708

1

T2

2

T6

40

T39

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1674

1

T6

42

T15

22

T42

7

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1352

1

T2

2

T6

32

T43

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1353

1

T6

40

T15

34

T42

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

94

1

T15

1

T87

2

T80

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

114

1

T6

2

T15

2

T16

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

112

1

T6

7

T15

7

T87

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

118

1

T6

3

T15

2

T16

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

106

1

T42

1

T16

1

T96

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

76

1

T42

2

T175

1

T97

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

83

1

T42

4

T87

3

T81

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

90

1

T6

1

T15

1

T42

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

65

1

T6

1

T15

1

T96

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

116

1

T6

2

T15

3

T80

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

80

1

T6

2

T15

2

T16

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

104

1

T6

2

T15

2

T16

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

80

1

T87

3

T80

1

T81

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

100

1

T15

2

T87

1

T96

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

71

1

T6

1

T16

2

T80

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

103

1

T15

3

T80

8

T175

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4169	1			T9	18		T12	2		T14	36
auto[0]	values[0]	valids[0x1]	17423	1			T1	2		T8	6		T12	2
auto[0]	values[1]	valids[0x1]	634	1			T14	7		T24	4		T36	8
auto[0]	values[2]	valids[0x0]	531	1			T14	3		T24	8		T36	3
auto[0]	values[2]	valids[0x1]	324	1			T8	4		T14	4		T24	2
auto[0]	values[3]	valids[0x0]	597	1			T7	2		T14	6		T24	5
auto[0]	values[3]	valids[0x1]	326	1			T14	4		T24	4		T36	4
auto[0]	values[4]	valids[0x0]	606	1			T14	4		T24	8		T36	4
auto[0]	values[4]	valids[0x1]	288	1			T14	1		T24	4		T36	7
auto[0]	values[5]	valids[0x0]	600	1			T14	6		T24	4		T36	8
auto[0]	values[5]	valids[0x1]	313	1			T14	4		T24	4		T45	2
auto[0]	values[6]	valids[0x0]	630	1			T14	7		T24	13		T36	2
auto[0]	values[6]	valids[0x1]	341	1			T14	2		T24	7		T36	2
auto[0]	values[7]	valids[0x0]	558	1			T7	2		T10	2		T14	5
auto[0]	values[7]	valids[0x1]	332	1			T24	6		T36	3		T27	1
auto[0]	values[8]	valids[0x0]	3800	1			T7	2		T8	2		T14	23
auto[0]	values[8]	valids[0x1]	2235	1			T14	14		T46	2		T24	32
auto[1]	values[0]	valids[0x0]	3716	1			T6	110		T15	60		T42	10
auto[1]	values[0]	valids[0x1]	13515	1			T6	223		T15	219		T155	1
auto[1]	values[1]	valids[0x1]	457	1			T6	9		T15	11		T42	4
auto[1]	values[2]	valids[0x0]	358	1			T6	5		T43	1		T15	13
auto[1]	values[2]	valids[0x1]	195	1			T6	6		T42	2		T87	1
auto[1]	values[3]	valids[0x0]	314	1			T6	4		T15	4		T42	2
auto[1]	values[3]	valids[0x1]	242	1			T6	6		T15	5		T42	1
auto[1]	values[4]	valids[0x0]	343	1			T2	2		T6	12		T39	3
auto[1]	values[4]	valids[0x1]	258	1			T6	2		T80	9		T96	1
auto[1]	values[5]	valids[0x0]	362	1			T6	11		T15	8		T16	2
auto[1]	values[5]	valids[0x1]	207	1			T6	2		T15	6		T42	1
auto[1]	values[6]	valids[0x0]	389	1			T6	9		T15	7		T42	3
auto[1]	values[6]	valids[0x1]	214	1			T6	7		T43	1		T15	3
auto[1]	values[7]	valids[0x0]	369	1			T6	12		T15	12		T87	4
auto[1]	values[7]	valids[0x1]	222	1			T6	1		T15	5		T87	2
auto[1]	values[8]	valids[0x0]	2383	1			T2	2		T6	55		T41	2
auto[1]	values[8]	valids[0x1]	1625	1			T6	37		T15	33		T42	2