Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3542868

1

T1

8585

T2

2103

T6

17347

auto[1]

28702

1

T6

111

T14

71

T24

29

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

978391

1

T1

3489

T2

2103

T6

124

auto[1]

2593179

1

T1

5096

T6

17334

T14

11354

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	677514	1			T1	2540		T2	464		T6	583
auto[524288:1048575]	441849	1			T1	6040		T6	2788		T9	3
auto[1048576:1572863]	435922	1			T6	2849		T7	394		T9	1
auto[1572864:2097151]	455820	1			T1	3		T2	3		T6	85
auto[2097152:2621439]	422468	1			T2	526		T6	5423		T7	5538
auto[2621440:3145727]	372833	1			T2	916		T6	1895		T14	153
auto[3145728:3670015]	391564	1			T2	58		T6	2235		T7	1
auto[3670016:4194303]	373600	1			T1	2		T2	136		T6	1600

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2628602

1

T1

5103

T2

13

T6

17456

auto[1]

942968

1

T1

3482

T2

2090

T6

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3040914

1

T1

8585

T2

2103

T6

13867

auto[1]

530656

1

T6

3591

T9

76

T14

1207

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	198975	1			T1	1		T2	464		T6	6
auto[0]	auto[0]	auto[0:524287]	auto[1]	396677	1			T1	2539		T6	569		T14	3194
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	97424	1			T1	3484		T6	11		T14	16
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	272881	1			T1	2556		T6	2770		T14	3257
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	91751	1			T6	9		T7	394		T9	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	257397	1			T6	2831		T24	3358		T36	7119
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	146444	1			T1	2		T2	3		T6	11
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	240939	1			T1	1		T6	6		T14	2207
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	137028	1			T2	526		T6	11		T7	5538
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	225151	1			T6	3842		T24	2875		T52	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	96207	1			T2	916		T6	7		T14	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	223301	1			T6	976		T14	130		T24	501
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	117442	1			T2	58		T6	13		T7	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	215829	1			T6	1160		T14	1		T24	6651
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	78944	1			T1	2		T2	136		T6	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	220487	1			T6	1587		T14	1326		T24	768
auto[0]	auto[1]	auto[0:524287]	auto[0]	1185	1			T9	4		T36	4		T15	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	76681	1			T36	513		T15	60		T42	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1607	1			T6	1		T9	3		T14	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	66794	1			T14	927		T36	383		T37	512
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	657	1			T6	1		T14	3		T24	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	81266	1			T14	258		T24	1		T36	129
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	3473	1			T6	9		T24	1		T15	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	61753	1			T6	43		T38	1		T16	1908
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	735	1			T6	5		T24	7		T36	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	54870	1			T6	1524		T24	1		T36	301
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	831	1			T6	4		T14	5		T24	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	49577	1			T6	902		T14	1		T27	768
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	781	1			T6	4		T9	69		T24	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	54481	1			T6	1041		T24	1		T49	131
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	730	1			T6	1		T24	3		T37	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	70570	1			T24	1		T37	1729		T15	4
auto[1]	auto[0]	auto[0:524287]	auto[0]	534	1			T6	2		T14	1		T24	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2903	1			T6	6		T14	1		T24	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	408	1			T6	4		T14	6		T37	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2319	1			T6	2		T14	25		T37	7
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	397	1			T6	4		T24	1		T37	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3564	1			T6	4		T24	3		T37	25
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	436	1			T6	1		T14	2		T24	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2131	1			T14	4		T36	14		T15	38
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	444	1			T6	3		T24	2		T27	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3494	1			T6	5		T24	2		T37	33
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	417	1			T6	1		T14	2		T24	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2128	1			T6	2		T14	12		T24	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	376	1			T6	3		T14	1		T24	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2183	1			T6	9		T14	1		T24	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	391	1			T6	2		T14	3		T36	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1912	1			T6	7		T14	2		T36	29
auto[1]	auto[1]	auto[0:524287]	auto[0]	95	1			T36	1		T42	1		T49	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	464	1			T36	16		T42	11		T49	4
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	120	1			T14	1		T51	6		T81	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	296	1			T14	4		T81	3		T189	8
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	105	1			T14	2		T24	1		T36	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	785	1			T14	4		T24	1		T36	30
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	105	1			T6	3		T38	1		T16	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	539	1			T6	12		T38	3		T80	14
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	130	1			T6	2		T24	1		T97	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	616	1			T6	31		T24	2		T19	11
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	56	1			T6	2		T37	1		T87	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	316	1			T6	1		T37	6		T87	11
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	70	1			T6	1		T24	1		T49	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	402	1			T6	4		T49	5		T21	5
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	93	1			T24	1		T15	2		T245	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	473	1			T24	1		T15	3		T245	6

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2078920	1			T1	5103		T2	13		T6	13812
auto[0]	auto[0]	auto[1]	937957	1			T1	3482		T2	2090		T7	17354
auto[0]	auto[1]	auto[0]	521716	1			T6	3535		T9	73		T14	1196
auto[0]	auto[1]	auto[1]	4275	1			T9	3		T36	1		T37	2
auto[1]	auto[0]	auto[0]	23443	1			T6	55		T14	60		T24	20
auto[1]	auto[0]	auto[1]	594	1			T24	1		T36	3		T37	6
auto[1]	auto[1]	auto[0]	4523	1			T6	54		T14	10		T24	7
auto[1]	auto[1]	auto[1]	142	1			T6	2		T14	1		T24	1