Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2359354	1			T1	1		T2	1		T4	13
all_pins[1]	2359354	1			T1	1		T2	1		T4	13
all_pins[2]	2359354	1			T1	1		T2	1		T4	13
all_pins[3]	2359354	1			T1	1		T2	1		T4	13
all_pins[4]	2359354	1			T1	1		T2	1		T4	13
all_pins[5]	2359354	1			T1	1		T2	1		T4	13
all_pins[6]	2359354	1			T1	1		T2	1		T4	13
all_pins[7]	2359354	1			T1	1		T2	1		T4	13

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18758457	1			T1	8		T2	8		T4	104
values[0x1]	116375	1			T13	26		T65	12		T15	42
transitions[0x0=>0x1]	114851	1			T13	19		T65	8		T15	31
transitions[0x1=>0x0]	114866	1			T13	19		T65	8		T15	31

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2358674	1			T1	1		T2	1		T4	13
all_pins[0]	values[0x1]	680	1			T13	3		T65	3		T15	6
all_pins[0]	transitions[0x0=>0x1]	523	1			T13	3		T65	3		T15	3
all_pins[0]	transitions[0x1=>0x0]	194	1			T13	3		T15	3		T16	1
all_pins[1]	values[0x0]	2359003	1			T1	1		T2	1		T4	13
all_pins[1]	values[0x1]	351	1			T13	3		T15	6		T16	4
all_pins[1]	transitions[0x0=>0x1]	249	1			T13	3		T15	6		T16	1
all_pins[1]	transitions[0x1=>0x0]	203	1			T13	4		T65	2		T15	4
all_pins[2]	values[0x0]	2359049	1			T1	1		T2	1		T4	13
all_pins[2]	values[0x1]	305	1			T13	4		T65	2		T15	4
all_pins[2]	transitions[0x0=>0x1]	249	1			T13	2		T65	2		T15	2
all_pins[2]	transitions[0x1=>0x0]	138	1			T13	2		T15	2		T16	2
all_pins[3]	values[0x0]	2359160	1			T1	1		T2	1		T4	13
all_pins[3]	values[0x1]	194	1			T13	4		T15	4		T16	6
all_pins[3]	transitions[0x0=>0x1]	147	1			T13	3		T15	3		T16	6
all_pins[3]	transitions[0x1=>0x0]	140	1			T15	4		T18	2		T20	3
all_pins[4]	values[0x0]	2359167	1			T1	1		T2	1		T4	13
all_pins[4]	values[0x1]	187	1			T13	1		T15	5		T18	2
all_pins[4]	transitions[0x0=>0x1]	144	1			T13	1		T15	5		T18	2
all_pins[4]	transitions[0x1=>0x0]	1771	1			T13	2		T65	3		T15	3
all_pins[5]	values[0x0]	2357540	1			T1	1		T2	1		T4	13
all_pins[5]	values[0x1]	1814	1			T13	2		T65	3		T15	3
all_pins[5]	transitions[0x0=>0x1]	789	1			T13	2		T65	2		T15	1
all_pins[5]	transitions[0x1=>0x0]	111637	1			T13	6		T15	8		T16	3
all_pins[6]	values[0x0]	2246692	1			T1	1		T2	1		T4	13
all_pins[6]	values[0x1]	112662	1			T13	6		T65	1		T15	10
all_pins[6]	transitions[0x0=>0x1]	112616	1			T13	3		T15	7		T16	5
all_pins[6]	transitions[0x1=>0x0]	136	1			T65	2		T15	1		T16	4
all_pins[7]	values[0x0]	2359172	1			T1	1		T2	1		T4	13
all_pins[7]	values[0x1]	182	1			T13	3		T65	3		T15	4
all_pins[7]	transitions[0x0=>0x1]	134	1			T13	2		T65	1		T15	4
all_pins[7]	transitions[0x1=>0x0]	647	1			T13	2		T65	1		T15	6