Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19260

1

T1

2

T7

6

T9

18

auto[1]

14447

1

T8

12

T14

105

T24

126

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4190	1			T14	52		T24	20		T36	117
values[1]	3874	1			T7	6		T10	2		T14	40
values[2]	4540	1			T1	2		T8	12		T14	20
values[3]	4052	1			T9	18		T12	4		T14	39
values[4]	3917	1			T24	20		T36	20		T44	14
values[5]	4326	1			T14	46		T24	71		T36	44
values[6]	4274	1			T14	34		T24	60		T36	91
values[7]	4534	1			T24	66		T241	6		T37	55

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3776	1			T44	14		T38	72		T246	24
values[1]	4414	1			T8	12		T14	34		T24	40
values[2]	4447	1			T1	2		T14	118		T46	4
values[3]	4605	1			T9	18		T14	40		T24	26
values[4]	4059	1			T24	68		T52	8		T36	50
values[5]	4419	1			T10	2		T24	40		T36	79
values[6]	4040	1			T7	6		T12	4		T24	47
values[7]	3947	1			T14	39		T24	44		T36	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	358	1			T38	7		T19	24		T247	13
auto[0]	values[0]	values[1]	237	1			T213	11		T219	14		T248	15
auto[0]	values[0]	values[2]	152	1			T14	9		T36	9		T50	7
auto[0]	values[0]	values[3]	206	1			T249	14		T51	13		T242	12
auto[0]	values[0]	values[4]	371	1			T36	4		T38	8		T224	12
auto[0]	values[0]	values[5]	345	1			T50	13		T250	6		T211	9
auto[0]	values[0]	values[6]	548	1			T24	17		T36	12		T204	10
auto[0]	values[0]	values[7]	290	1			T229	13		T21	25		T242	14
auto[0]	values[1]	values[0]	329	1			T209	10		T204	24		T30	14
auto[0]	values[1]	values[1]	257	1			T36	9		T50	13		T19	45
auto[0]	values[1]	values[2]	379	1			T14	12		T251	2		T50	18
auto[0]	values[1]	values[3]	295	1			T14	6		T49	19		T252	2
auto[0]	values[1]	values[4]	268	1			T24	13		T27	13		T37	9
auto[0]	values[1]	values[5]	304	1			T10	2		T36	16		T187	4
auto[0]	values[1]	values[6]	314	1			T7	6		T37	12		T51	12
auto[0]	values[1]	values[7]	149	1			T229	19		T209	10		T253	10
auto[0]	values[2]	values[0]	265	1			T49	5		T50	16		T207	8
auto[0]	values[2]	values[1]	526	1			T98	24		T37	26		T204	78
auto[0]	values[2]	values[2]	228	1			T1	2		T14	17		T46	4
auto[0]	values[2]	values[3]	570	1			T238	2		T20	10		T196	12
auto[0]	values[2]	values[4]	187	1			T51	10		T75	11		T254	6
auto[0]	values[2]	values[5]	341	1			T24	13		T255	22		T20	9
auto[0]	values[2]	values[6]	303	1			T27	16		T37	20		T49	5
auto[0]	values[2]	values[7]	216	1			T256	16		T213	11		T216	6
auto[0]	values[3]	values[0]	304	1			T257	20		T19	12		T196	17
auto[0]	values[3]	values[1]	286	1			T50	31		T229	10		T166	11
auto[0]	values[3]	values[2]	194	1			T36	26		T258	2		T259	2
auto[0]	values[3]	values[3]	252	1			T9	18		T24	10		T49	9
auto[0]	values[3]	values[4]	336	1			T52	8		T38	8		T51	10
auto[0]	values[3]	values[5]	228	1			T37	11		T49	9		T51	11
auto[0]	values[3]	values[6]	298	1			T12	4		T213	10		T219	68
auto[0]	values[3]	values[7]	284	1			T14	33		T49	11		T209	15
auto[0]	values[4]	values[0]	207	1			T44	14		T38	12		T51	10
auto[0]	values[4]	values[1]	278	1			T21	11		T190	8		T237	18
auto[0]	values[4]	values[2]	310	1			T49	17		T207	15		T213	10
auto[0]	values[4]	values[3]	265	1			T27	14		T30	7		T166	13
auto[0]	values[4]	values[4]	142	1			T207	6		T21	13		T219	8
auto[0]	values[4]	values[5]	545	1			T49	15		T79	14		T260	195
auto[0]	values[4]	values[6]	274	1			T36	8		T227	18		T204	12
auto[0]	values[4]	values[7]	232	1			T24	11		T27	15		T229	7
auto[0]	values[5]	values[0]	328	1			T50	7		T198	10		T261	6
auto[0]	values[5]	values[1]	224	1			T37	8		T38	17		T196	13
auto[0]	values[5]	values[2]	358	1			T14	10		T24	27		T19	25
auto[0]	values[5]	values[3]	352	1			T14	12		T27	11		T37	10
auto[0]	values[5]	values[4]	259	1			T209	15		T213	12		T262	13
auto[0]	values[5]	values[5]	273	1			T36	12		T51	12		T263	18
auto[0]	values[5]	values[6]	180	1			T24	14		T37	11		T38	14
auto[0]	values[5]	values[7]	243	1			T38	13		T20	17		T264	2
auto[0]	values[6]	values[0]	161	1			T225	14		T50	10		T265	35
auto[0]	values[6]	values[1]	427	1			T14	27		T24	29		T36	16
auto[0]	values[6]	values[2]	384	1			T223	22		T51	10		T75	21
auto[0]	values[6]	values[3]	340	1			T49	12		T266	2		T229	16
auto[0]	values[6]	values[4]	307	1			T24	12		T45	6		T244	8
auto[0]	values[6]	values[5]	316	1			T49	13		T75	13		T21	20
auto[0]	values[6]	values[6]	162	1			T36	48		T174	8		T38	7
auto[0]	values[6]	values[7]	297	1			T36	10		T38	9		T49	31
auto[0]	values[7]	values[0]	347	1			T50	10		T51	8		T192	9
auto[0]	values[7]	values[1]	198	1			T77	16		T207	14		T19	10
auto[0]	values[7]	values[2]	388	1			T241	6		T37	24		T58	165
auto[0]	values[7]	values[3]	448	1			T51	11		T231	12		T20	44
auto[0]	values[7]	values[4]	411	1			T24	15		T213	8		T219	56
auto[0]	values[7]	values[5]	231	1			T24	12		T49	14		T207	44
auto[0]	values[7]	values[6]	373	1			T37	12		T119	6		T21	12
auto[0]	values[7]	values[7]	380	1			T24	10		T231	15		T194	38
auto[1]	values[0]	values[0]	152	1			T38	45		T19	7		T247	7
auto[1]	values[0]	values[1]	195	1			T203	22		T213	22		T219	7
auto[1]	values[0]	values[2]	296	1			T14	43		T36	38		T50	44
auto[1]	values[0]	values[3]	160	1			T51	7		T242	8		T195	33
auto[1]	values[0]	values[4]	179	1			T36	46		T38	12		T267	2
auto[1]	values[0]	values[5]	133	1			T50	7		T211	16		T199	7
auto[1]	values[0]	values[6]	309	1			T24	3		T36	8		T48	6
auto[1]	values[0]	values[7]	259	1			T229	7		T21	10		T242	6
auto[1]	values[1]	values[0]	150	1			T246	24		T209	14		T204	10
auto[1]	values[1]	values[1]	212	1			T36	11		T50	7		T19	4
auto[1]	values[1]	values[2]	136	1			T14	8		T50	2		T75	9
auto[1]	values[1]	values[3]	263	1			T14	14		T49	14		T204	10
auto[1]	values[1]	values[4]	128	1			T24	13		T27	7		T37	11
auto[1]	values[1]	values[5]	296	1			T36	19		T213	10		T191	18
auto[1]	values[1]	values[6]	298	1			T37	27		T51	8		T19	13
auto[1]	values[1]	values[7]	96	1			T229	5		T209	10		T230	12
auto[1]	values[2]	values[0]	293	1			T49	15		T50	26		T207	12
auto[1]	values[2]	values[1]	319	1			T8	12		T37	46		T204	14
auto[1]	values[2]	values[2]	152	1			T14	3		T36	2		T75	6
auto[1]	values[2]	values[3]	279	1			T20	10		T196	16		T213	17
auto[1]	values[2]	values[4]	192	1			T51	10		T75	9		T268	16
auto[1]	values[2]	values[5]	363	1			T24	7		T20	11		T197	33
auto[1]	values[2]	values[6]	207	1			T27	5		T37	11		T49	15
auto[1]	values[2]	values[7]	99	1			T213	9		T216	14		T253	6
auto[1]	values[3]	values[0]	240	1			T19	8		T196	3		T21	8
auto[1]	values[3]	values[1]	274	1			T50	10		T229	10		T166	9
auto[1]	values[3]	values[2]	307	1			T36	11		T191	9		T269	168
auto[1]	values[3]	values[3]	225	1			T24	16		T49	11		T197	14
auto[1]	values[3]	values[4]	187	1			T38	33		T51	10		T21	41
auto[1]	values[3]	values[5]	139	1			T37	9		T49	11		T51	9
auto[1]	values[3]	values[6]	116	1			T270	4		T213	10		T219	4
auto[1]	values[3]	values[7]	382	1			T14	6		T49	9		T209	5
auto[1]	values[4]	values[0]	88	1			T38	8		T51	10		T229	10
auto[1]	values[4]	values[1]	274	1			T21	16		T190	19		T30	4
auto[1]	values[4]	values[2]	331	1			T49	3		T207	71		T213	10
auto[1]	values[4]	values[3]	124	1			T27	6		T30	15		T166	11
auto[1]	values[4]	values[4]	132	1			T207	14		T21	7		T219	17
auto[1]	values[4]	values[5]	271	1			T49	8		T219	8		T192	7
auto[1]	values[4]	values[6]	203	1			T36	12		T204	8		T213	26
auto[1]	values[4]	values[7]	241	1			T24	9		T27	9		T226	12
auto[1]	values[5]	values[0]	196	1			T50	13		T219	4		T248	5
auto[1]	values[5]	values[1]	164	1			T37	12		T38	7		T196	8
auto[1]	values[5]	values[2]	249	1			T14	16		T24	17		T19	7
auto[1]	values[5]	values[3]	419	1			T14	8		T27	9		T37	69
auto[1]	values[5]	values[4]	360	1			T209	7		T213	8		T262	13
auto[1]	values[5]	values[5]	327	1			T36	32		T51	8		T263	3
auto[1]	values[5]	values[6]	149	1			T24	13		T37	17		T38	45
auto[1]	values[5]	values[7]	245	1			T38	31		T20	3		T137	15
auto[1]	values[6]	values[0]	105	1			T50	50		T271	4		T272	13
auto[1]	values[6]	values[1]	302	1			T14	7		T24	11		T36	4
auto[1]	values[6]	values[2]	308	1			T51	10		T75	9		T207	9
auto[1]	values[6]	values[3]	242	1			T49	8		T233	18		T229	5
auto[1]	values[6]	values[4]	370	1			T24	8		T50	8		T19	33
auto[1]	values[6]	values[5]	174	1			T49	7		T75	9		T21	3
auto[1]	values[6]	values[6]	133	1			T36	3		T38	13		T190	9
auto[1]	values[6]	values[7]	246	1			T36	10		T38	11		T49	30
auto[1]	values[7]	values[0]	253	1			T50	37		T51	12		T192	11
auto[1]	values[7]	values[1]	241	1			T207	10		T19	37		T204	14
auto[1]	values[7]	values[2]	275	1			T37	11		T229	9		T19	73
auto[1]	values[7]	values[3]	165	1			T51	9		T231	8		T20	4
auto[1]	values[7]	values[4]	230	1			T24	7		T213	12		T219	13
auto[1]	values[7]	values[5]	133	1			T24	8		T49	8		T207	4
auto[1]	values[7]	values[6]	173	1			T37	8		T21	14		T219	5
auto[1]	values[7]	values[7]	288	1			T24	14		T231	7		T194	66