Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	431	1			T7	2		T14	3		T24	1
auto[ReadAddrCrossIntoMailbox]	331	1			T7	2		T14	4		T36	4
auto[ReadAddrCrossOutOfMailbox]	331	1			T14	2		T24	3		T36	6
auto[ReadAddrCrossAllMailbox]	222	1			T7	2		T14	4		T24	1
auto[ReadAddrOutsideMailbox]	3950	1			T8	2		T14	22		T24	69

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2579

1

T7

3

T8

1

T14

15

auto[1]

2686

1

T7

3

T8

1

T14

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	843	1			T14	8		T24	13		T36	11
read_ops[0x0b]	880	1			T14	5		T24	9		T36	11
read_ops[0x3b]	922	1			T7	2		T14	5		T24	16
read_ops[0x6b]	849	1			T7	2		T14	1		T24	10
read_ops[0xbb]	904	1			T8	2		T14	9		T24	14
read_ops[0xeb]	867	1			T7	2		T14	7		T24	12

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T227	2		T196	1		T204	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T14	1		T227	2		T21	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T37	3		T51	1		T242	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T14	2		T36	1		T38	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T37	2		T51	1		T197	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T36	1		T49	1		T50	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T36	1		T204	1		T166	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T37	1		T49	1		T20	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T14	1		T24	3		T36	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	329	1			T14	4		T24	10		T36	6
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T36	1		T38	2		T50	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T14	1		T227	2		T51	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T20	1		T204	1		T213	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T14	2		T50	1		T21	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T14	1		T27	1		T21	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T24	1		T36	1		T19	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T24	1		T36	1		T38	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T20	2		T168	1		T273	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	329	1			T24	5		T36	5		T27	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	330	1			T14	1		T24	2		T36	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T51	1		T19	1		T20	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T24	1		T36	1		T37	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T7	1		T38	1		T219	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T7	1		T36	1		T49	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	38	1			T27	1		T38	1		T49	3
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T24	2		T50	1		T229	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T14	1		T36	1		T38	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T14	1		T36	2		T19	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	341	1			T14	3		T24	4		T36	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	352	1			T24	9		T36	1		T37	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T251	1		T75	1		T19	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T36	1		T251	1		T50	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T27	1		T19	1		T21	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T36	1		T38	1		T50	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T229	2		T196	1		T190	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T49	1		T75	1		T209	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T7	1		T229	1		T250	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T7	1		T38	1		T49	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T14	1		T24	4		T36	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	351	1			T24	6		T36	1		T27	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T36	2		T37	1		T49	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T49	1		T50	2		T204	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T36	1		T38	1		T49	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T209	1		T204	1		T194	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T36	1		T50	1		T197	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T50	1		T229	1		T196	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T209	1		T20	1		T274	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T38	1		T21	1		T242	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	321	1			T8	1		T14	6		T24	6
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	373	1			T8	1		T14	3		T24	8
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T7	1		T36	1		T51	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T7	1		T14	1		T51	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T213	1		T250	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T38	2		T51	1		T21	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T36	3		T50	1		T21	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T14	1		T49	1		T51	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T213	1		T193	1		T265	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T14	2		T27	1		T229	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	333	1			T14	2		T24	6		T36	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	301	1			T14	1		T24	6		T36	2