Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4081	1			T8	12		T10	2		T24	90
values[1]	4181	1			T24	82		T36	72		T27	20
values[2]	3841	1			T14	40		T241	6		T38	59
values[3]	4559	1			T1	2		T14	52		T24	27
values[4]	4471	1			T14	54		T46	4		T24	50
values[5]	4602	1			T7	6		T9	18		T49	58
values[6]	4599	1			T14	59		T24	40		T187	4
values[7]	3373	1			T12	4		T14	26		T24	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3782	1			T12	4		T14	54		T24	46
values[1]	3931	1			T14	39		T46	4		T36	101
values[2]	4192	1			T1	2		T24	69		T48	6
values[3]	4579	1			T9	18		T10	2		T14	26
values[4]	3885	1			T24	20		T52	8		T27	24
values[5]	3873	1			T7	6		T24	24		T36	102
values[6]	4486	1			T14	60		T24	20		T36	70
values[7]	4979	1			T8	12		T14	52		T24	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32820

1

T1

2

T7

6

T8

12

auto[1]

887

1

T14

6

T24

5

T36

9

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	368	1			T24	25		T50	20		T231	19
auto[0]	values[0]	values[1]	670	1			T36	19		T45	6		T27	21
auto[0]	values[0]	values[2]	573	1			T49	22		T275	6		T276	6
auto[0]	values[0]	values[3]	394	1			T10	2		T50	18		T238	2
auto[0]	values[0]	values[4]	539	1			T24	19		T50	19		T77	16
auto[0]	values[0]	values[5]	449	1			T24	23		T36	65		T37	20
auto[0]	values[0]	values[6]	569	1			T44	14		T37	76		T99	4
auto[0]	values[0]	values[7]	411	1			T8	12		T24	20		T27	20
auto[0]	values[1]	values[0]	422	1			T24	20		T49	20		T236	68
auto[0]	values[1]	values[1]	520	1			T36	37		T75	27		T229	20
auto[0]	values[1]	values[2]	569	1			T24	41		T213	19		T190	20
auto[0]	values[1]	values[3]	838	1			T24	20		T37	20		T277	6
auto[0]	values[1]	values[4]	232	1			T229	27		T242	30		T204	17
auto[0]	values[1]	values[5]	507	1			T36	34		T50	20		T223	22
auto[0]	values[1]	values[6]	407	1			T51	19		T229	24		T278	6
auto[0]	values[1]	values[7]	579	1			T27	19		T204	29		T213	28
auto[0]	values[2]	values[0]	405	1			T14	20		T49	20		T19	47
auto[0]	values[2]	values[1]	449	1			T38	56		T51	18		T204	25
auto[0]	values[2]	values[2]	364	1			T51	38		T21	26		T191	17
auto[0]	values[2]	values[3]	411	1			T205	18		T207	48		T209	20
auto[0]	values[2]	values[4]	395	1			T192	63		T191	21		T141	2
auto[0]	values[2]	values[5]	591	1			T266	2		T20	48		T194	19
auto[0]	values[2]	values[6]	484	1			T14	20		T207	85		T231	22
auto[0]	values[2]	values[7]	643	1			T241	6		T50	42		T209	20
auto[0]	values[3]	values[0]	334	1			T36	18		T37	28		T49	20
auto[0]	values[3]	values[1]	749	1			T257	20		T203	22		T209	20
auto[0]	values[3]	values[2]	537	1			T1	2		T24	27		T49	19
auto[0]	values[3]	values[3]	718	1			T36	20		T244	8		T192	43
auto[0]	values[3]	values[4]	549	1			T52	8		T38	20		T196	28
auto[0]	values[3]	values[5]	372	1			T37	59		T19	20		T20	20
auto[0]	values[3]	values[6]	652	1			T36	20		T27	20		T37	20
auto[0]	values[3]	values[7]	545	1			T14	52		T36	51		T246	24
auto[0]	values[4]	values[0]	597	1			T14	32		T207	43		T229	19
auto[0]	values[4]	values[1]	423	1			T46	4		T36	42		T37	29
auto[0]	values[4]	values[2]	624	1			T21	47		T93	10		T137	26
auto[0]	values[4]	values[3]	388	1			T24	49		T50	45		T252	2
auto[0]	values[4]	values[4]	673	1			T58	165		T50	107		T192	26
auto[0]	values[4]	values[5]	130	1			T49	20		T251	2		T20	20
auto[0]	values[4]	values[6]	756	1			T14	19		T47	20		T75	144
auto[0]	values[4]	values[7]	757	1			T37	70		T49	19		T79	14
auto[0]	values[5]	values[0]	507	1			T49	24		T192	19		T274	8
auto[0]	values[5]	values[1]	351	1			T242	20		T213	17		T192	24
auto[0]	values[5]	values[2]	358	1			T192	23		T191	21		T202	16
auto[0]	values[5]	values[3]	449	1			T9	18		T209	20		T21	22
auto[0]	values[5]	values[4]	649	1			T207	24		T19	70		T248	100
auto[0]	values[5]	values[5]	827	1			T7	6		T49	29		T75	19
auto[0]	values[5]	values[6]	488	1			T196	20		T261	6		T219	16
auto[0]	values[5]	values[7]	833	1			T226	12		T50	38		T215	71
auto[0]	values[6]	values[0]	571	1			T187	4		T233	16		T229	20
auto[0]	values[6]	values[1]	357	1			T14	38		T204	26		T197	20
auto[0]	values[6]	values[2]	522	1			T48	4		T38	44		T270	4
auto[0]	values[6]	values[3]	866	1			T24	20		T49	20		T51	18
auto[0]	values[6]	values[4]	376	1			T37	30		T38	39		T229	20
auto[0]	values[6]	values[5]	674	1			T50	41		T75	21		T209	23
auto[0]	values[6]	values[6]	542	1			T14	20		T24	20		T279	4
auto[0]	values[6]	values[7]	575	1			T49	20		T229	29		T19	19
auto[0]	values[7]	values[0]	449	1			T12	4		T38	41		T49	17
auto[0]	values[7]	values[1]	301	1			T51	20		T280	29		T281	14
auto[0]	values[7]	values[2]	552	1			T50	21		T19	47		T30	21
auto[0]	values[7]	values[3]	418	1			T14	24		T24	20		T36	20
auto[0]	values[7]	values[4]	365	1			T27	23		T174	8		T227	18
auto[0]	values[7]	values[5]	207	1			T224	12		T282	6		T21	21
auto[0]	values[7]	values[6]	476	1			T36	49		T38	50		T196	20
auto[0]	values[7]	values[7]	514	1			T38	24		T229	21		T210	10
auto[1]	values[0]	values[0]	9	1			T24	1		T231	1		T283	2
auto[1]	values[0]	values[1]	16	1			T36	1		T197	2		T213	2
auto[1]	values[0]	values[2]	16	1			T199	2		T168	5		T169	1
auto[1]	values[0]	values[3]	7	1			T50	2		T191	2		T199	1
auto[1]	values[0]	values[4]	10	1			T24	1		T50	1		T284	3
auto[1]	values[0]	values[5]	11	1			T24	1		T36	2		T209	1
auto[1]	values[0]	values[6]	21	1			T37	3		T38	3		T217	1
auto[1]	values[0]	values[7]	18	1			T49	1		T204	5		T195	1
auto[1]	values[1]	values[0]	7	1			T253	1		T285	4		T286	1
auto[1]	values[1]	values[1]	16	1			T75	3		T21	2		T247	1
auto[1]	values[1]	values[2]	11	1			T24	1		T213	1		T194	4
auto[1]	values[1]	values[3]	23	1			T287	5		T288	4		T283	3
auto[1]	values[1]	values[4]	7	1			T204	3		T219	1		T289	3
auto[1]	values[1]	values[5]	11	1			T36	1		T236	4		T290	1
auto[1]	values[1]	values[6]	11	1			T51	1		T278	6		T137	1
auto[1]	values[1]	values[7]	21	1			T27	1		T204	2		T194	2
auto[1]	values[2]	values[0]	12	1			T191	3		T137	1		T195	1
auto[1]	values[2]	values[1]	9	1			T38	3		T51	2		T204	1
auto[1]	values[2]	values[2]	20	1			T51	2		T191	3		T216	1
auto[1]	values[2]	values[3]	8	1			T193	6		T194	1		T291	1
auto[1]	values[2]	values[4]	12	1			T192	3		T292	2		T293	1
auto[1]	values[2]	values[5]	18	1			T194	2		T280	1		T168	1
auto[1]	values[2]	values[6]	10	1			T207	1		T19	1		T280	6
auto[1]	values[2]	values[7]	10	1			T191	1		T294	3		T273	1
auto[1]	values[3]	values[0]	10	1			T36	2		T166	1		T295	2
auto[1]	values[3]	values[1]	20	1			T204	2		T191	5		T217	1
auto[1]	values[3]	values[2]	6	1			T49	1		T168	4		T283	1
auto[1]	values[3]	values[3]	16	1			T192	2		T265	3		T294	1
auto[1]	values[3]	values[4]	12	1			T204	1		T248	3		T273	5
auto[1]	values[3]	values[5]	9	1			T21	1		T284	3		T200	1
auto[1]	values[3]	values[6]	13	1			T166	1		T137	2		T269	1
auto[1]	values[3]	values[7]	17	1			T271	4		T221	1		T290	2
auto[1]	values[4]	values[0]	40	1			T14	2		T207	1		T229	1
auto[1]	values[4]	values[1]	20	1			T36	2		T37	6		T49	1
auto[1]	values[4]	values[2]	8	1			T21	5		T212	1		T147	2
auto[1]	values[4]	values[3]	5	1			T24	1		T50	2		T296	1
auto[1]	values[4]	values[4]	17	1			T50	4		T192	1		T269	1
auto[1]	values[4]	values[5]	1	1			T297	1		-	-		-	-
auto[1]	values[4]	values[6]	14	1			T14	1		T75	1		T190	1
auto[1]	values[4]	values[7]	18	1			T37	2		T49	1		T207	3
auto[1]	values[5]	values[0]	20	1			T49	1		T192	1		T287	1
auto[1]	values[5]	values[1]	13	1			T213	3		T192	2		T57	5
auto[1]	values[5]	values[2]	6	1			T192	1		T298	1		T200	1
auto[1]	values[5]	values[3]	7	1			T21	1		T269	2		T33	2
auto[1]	values[5]	values[4]	25	1			T248	5		T216	3		T168	3
auto[1]	values[5]	values[5]	36	1			T49	4		T75	1		T213	3
auto[1]	values[5]	values[6]	13	1			T219	4		T193	1		T295	3
auto[1]	values[5]	values[7]	20	1			T50	1		T204	2		T219	2
auto[1]	values[6]	values[0]	22	1			T233	2		T19	2		T213	1
auto[1]	values[6]	values[1]	7	1			T14	1		T204	1		T213	2
auto[1]	values[6]	values[2]	10	1			T48	2		T248	1		T137	2
auto[1]	values[6]	values[3]	18	1			T51	2		T236	3		T217	1
auto[1]	values[6]	values[4]	11	1			T37	1		T38	1		T21	2
auto[1]	values[6]	values[5]	22	1			T75	1		T209	1		T213	2
auto[1]	values[6]	values[6]	20	1			T299	1		T221	5		T300	2
auto[1]	values[6]	values[7]	6	1			T19	1		T280	1		T301	1
auto[1]	values[7]	values[0]	9	1			T49	3		T204	2		T191	3
auto[1]	values[7]	values[1]	10	1			T212	3		T273	1		T302	3
auto[1]	values[7]	values[2]	16	1			T50	1		T30	1		T269	3
auto[1]	values[7]	values[3]	13	1			T14	2		T269	6		T32	1
auto[1]	values[7]	values[4]	13	1			T27	1		T263	1		T195	7
auto[1]	values[7]	values[5]	8	1			T21	1		T192	1		T168	3
auto[1]	values[7]	values[6]	10	1			T36	1		T38	2		T147	2
auto[1]	values[7]	values[7]	12	1			T190	2		T191	3		T33	1