Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	785	1			T13	11		T65	4		T15	17
all_values[1]	785	1			T13	11		T65	4		T15	17
all_values[2]	785	1			T13	11		T65	4		T15	17
all_values[3]	785	1			T13	11		T65	4		T15	17
all_values[4]	785	1			T13	11		T65	4		T15	17
all_values[5]	785	1			T13	11		T65	4		T15	17
all_values[6]	785	1			T13	11		T65	4		T15	17
all_values[7]	785	1			T13	11		T65	4		T15	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3416

1

T13

39

T65

21

T15

77

auto[1]

2864

1

T13

49

T65

11

T15

59

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2503

1

T13

31

T65

11

T15

44

auto[1]

3777

1

T13

57

T65

21

T15

92

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3590

1

T13

55

T65

18

T15

73

auto[1]

2690

1

T13

33

T65

14

T15

63

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	173	1			T65	1		T15	4		T16	1
all_values[0]	auto[0]	auto[0]	auto[1]	87	1			T13	1		T15	1		T16	2
all_values[0]	auto[0]	auto[1]	auto[0]	127	1			T13	6		T15	3		T16	2
all_values[0]	auto[0]	auto[1]	auto[1]	69	1			T13	2		T65	1		T15	2
all_values[0]	auto[1]	auto[0]	auto[1]	179	1			T15	3		T16	2		T18	2
all_values[0]	auto[1]	auto[1]	auto[1]	150	1			T13	2		T65	2		T15	4
all_values[1]	auto[0]	auto[0]	auto[0]	174	1			T13	1		T65	1		T15	6
all_values[1]	auto[0]	auto[0]	auto[1]	75	1			T13	1		T15	2		T16	3
all_values[1]	auto[0]	auto[1]	auto[0]	116	1			T13	1		T65	1		T15	1
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T13	3		T65	1		T15	2
all_values[1]	auto[1]	auto[0]	auto[1]	204	1			T13	5		T65	1		T15	4
all_values[1]	auto[1]	auto[1]	auto[1]	136	1			T15	2		T16	1		T18	3
all_values[2]	auto[0]	auto[0]	auto[0]	159	1			T65	1		T15	2		T16	3
all_values[2]	auto[0]	auto[0]	auto[1]	88	1			T13	3		T65	1		T15	1
all_values[2]	auto[0]	auto[1]	auto[0]	123	1			T13	2		T15	1		T18	2
all_values[2]	auto[0]	auto[1]	auto[1]	84	1			T13	2		T15	4		T16	3
all_values[2]	auto[1]	auto[0]	auto[1]	192	1			T13	3		T65	1		T15	6
all_values[2]	auto[1]	auto[1]	auto[1]	139	1			T13	1		T65	1		T15	3
all_values[3]	auto[0]	auto[0]	auto[0]	162	1			T13	2		T65	3		T15	2
all_values[3]	auto[0]	auto[0]	auto[1]	78	1			T13	1		T15	1		T16	1
all_values[3]	auto[0]	auto[1]	auto[0]	126	1			T15	3		T16	1		T18	2
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T13	1		T15	1		T16	3
all_values[3]	auto[1]	auto[0]	auto[1]	184	1			T13	5		T65	1		T15	8
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T13	2		T15	2		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	140	1			T13	3		T15	4		T16	5
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T13	3		T65	2		T15	2
all_values[4]	auto[0]	auto[1]	auto[0]	143	1			T13	1		T16	5		T18	1
all_values[4]	auto[0]	auto[1]	auto[1]	69	1			T13	1		T15	3		T18	1
all_values[4]	auto[1]	auto[0]	auto[1]	196	1			T13	2		T65	2		T15	3
all_values[4]	auto[1]	auto[1]	auto[1]	163	1			T13	1		T15	5		T18	1
all_values[5]	auto[0]	auto[0]	auto[0]	256	1			T13	2		T15	8		T16	3
all_values[5]	auto[0]	auto[1]	auto[0]	187	1			T13	5		T65	1		T15	1
all_values[5]	auto[1]	auto[0]	auto[1]	175	1			T13	1		T65	1		T15	7
all_values[5]	auto[1]	auto[1]	auto[1]	167	1			T13	3		T65	2		T15	1
all_values[6]	auto[0]	auto[0]	auto[0]	172	1			T65	3		T15	1		T16	2
all_values[6]	auto[0]	auto[0]	auto[1]	63	1			T13	2		T15	2		T21	1
all_values[6]	auto[0]	auto[1]	auto[0]	139	1			T16	3		T18	2		T19	4
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T13	3		T15	5		T16	3
all_values[6]	auto[1]	auto[0]	auto[1]	172	1			T13	2		T65	1		T15	3
all_values[6]	auto[1]	auto[1]	auto[1]	157	1			T13	4		T15	6		T16	3
all_values[7]	auto[0]	auto[0]	auto[0]	160	1			T13	2		T15	3		T16	3
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T65	1		T15	3		T19	1
all_values[7]	auto[0]	auto[1]	auto[0]	146	1			T13	6		T15	5		T16	1
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T13	1		T65	1		T16	1
all_values[7]	auto[1]	auto[0]	auto[1]	175	1			T65	1		T15	1		T16	3
all_values[7]	auto[1]	auto[1]	auto[1]	151	1			T13	2		T65	1		T15	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal