Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1809

1

T6

8

T11

1

T23

19

auto[1]

1727

1

T6

9

T11

3

T23

18

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1888

1

T6

17

T14

9

T24

25

auto[1]

1648

1

T11

4

T23

37

T14

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2851

1

T6

14

T11

4

T23

37

auto[1]

685

1

T6

3

T14

5

T24

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	750	1			T6	2		T23	14		T14	2
valid[1]	689	1			T6	7		T11	1		T23	4
valid[2]	680	1			T6	3		T11	1		T23	9
valid[3]	734	1			T6	3		T11	1		T23	5
valid[4]	683	1			T6	2		T11	1		T23	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	133	1			T24	1		T25	1		T27	3
auto[0]	auto[0]	valid[0]	auto[1]	174	1			T23	8		T14	1		T88	3
auto[0]	auto[0]	valid[1]	auto[0]	124	1			T6	4		T14	1		T24	2
auto[0]	auto[0]	valid[1]	auto[1]	166	1			T23	3		T89	1		T92	2
auto[0]	auto[0]	valid[2]	auto[0]	118	1			T24	2		T25	2		T15	1
auto[0]	auto[0]	valid[2]	auto[1]	155	1			T23	3		T29	4		T88	1
auto[0]	auto[0]	valid[3]	auto[0]	140	1			T6	2		T25	2		T172	1
auto[0]	auto[0]	valid[3]	auto[1]	152	1			T23	3		T91	2		T92	2
auto[0]	auto[0]	valid[4]	auto[0]	115	1			T6	1		T24	1		T25	2
auto[0]	auto[0]	valid[4]	auto[1]	182	1			T11	1		T23	2		T14	1
auto[0]	auto[1]	valid[0]	auto[0]	114	1			T6	1		T24	2		T38	1
auto[0]	auto[1]	valid[0]	auto[1]	180	1			T23	6		T14	1		T29	3
auto[0]	auto[1]	valid[1]	auto[0]	115	1			T6	2		T24	2		T27	1
auto[0]	auto[1]	valid[1]	auto[1]	125	1			T11	1		T23	1		T14	1
auto[0]	auto[1]	valid[2]	auto[0]	119	1			T6	2		T14	2		T24	4
auto[0]	auto[1]	valid[2]	auto[1]	162	1			T11	1		T23	6		T14	1
auto[0]	auto[1]	valid[3]	auto[0]	106	1			T6	1		T14	1		T24	4
auto[0]	auto[1]	valid[3]	auto[1]	198	1			T11	1		T23	2		T29	1
auto[0]	auto[1]	valid[4]	auto[0]	119	1			T6	1		T24	1		T15	2
auto[0]	auto[1]	valid[4]	auto[1]	154	1			T23	3		T29	1		T92	1
auto[1]	auto[0]	valid[0]	auto[0]	82	1			T34	1		T38	1		T49	1
auto[1]	auto[0]	valid[1]	auto[0]	83	1			T24	2		T25	1		T15	1
auto[1]	auto[0]	valid[2]	auto[0]	59	1			T6	1		T49	1		T329	1
auto[1]	auto[0]	valid[3]	auto[0]	67	1			T14	1		T245	1		T321	1
auto[1]	auto[0]	valid[4]	auto[0]	59	1			T14	1		T15	1		T38	1
auto[1]	auto[1]	valid[0]	auto[0]	67	1			T6	1		T25	2		T49	1
auto[1]	auto[1]	valid[1]	auto[0]	76	1			T6	1		T14	2		T24	2
auto[1]	auto[1]	valid[2]	auto[0]	67	1			T14	1		T24	2		T75	1
auto[1]	auto[1]	valid[3]	auto[0]	71	1			T15	1		T75	2		T318	1
auto[1]	auto[1]	valid[4]	auto[0]	54	1			T25	1		T15	1		T318	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal