Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47043

1

T4

2

T6

389

T14

187

auto[1]

16978

1

T11

4

T23

495

T14

55

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47038

1

T4

2

T6

275

T11

4

auto[1]

16983

1

T6

114

T14

90

T24

165

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33105	1			T4	1		T6	214		T11	4
others[1]	5383	1			T6	26		T23	28		T14	25
others[2]	5432	1			T6	29		T23	30		T14	26
others[3]	6140	1			T4	1		T6	40		T23	58
interest[1]	3399	1			T6	25		T23	25		T14	14
interest[4]	21666	1			T6	144		T11	4		T23	158
interest[64]	10562	1			T6	55		T23	101		T14	47

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15512	1			T4	1		T6	150		T14	39
auto[0]	auto[0]	others[1]	2581	1			T6	19		T14	10		T24	38
auto[0]	auto[0]	others[2]	2575	1			T6	23		T14	9		T24	36
auto[0]	auto[0]	others[3]	2868	1			T4	1		T6	32		T14	11
auto[0]	auto[0]	interest[1]	1588	1			T6	16		T14	7		T24	28
auto[0]	auto[0]	interest[4]	10121	1			T6	104		T14	26		T24	127
auto[0]	auto[0]	interest[64]	4936	1			T6	35		T14	21		T24	49
auto[0]	auto[1]	others[0]	8906	1			T11	4		T23	253		T14	23
auto[0]	auto[1]	others[1]	1361	1			T23	28		T14	5		T34	1
auto[0]	auto[1]	others[2]	1433	1			T23	30		T14	9		T37	1
auto[0]	auto[1]	others[3]	1623	1			T23	58		T14	6		T37	1
auto[0]	auto[1]	interest[1]	893	1			T23	25		T14	2		T37	1
auto[0]	auto[1]	interest[4]	5936	1			T11	4		T23	158		T14	14
auto[0]	auto[1]	interest[64]	2762	1			T23	101		T14	10		T34	1
auto[1]	auto[0]	others[0]	8687	1			T6	64		T14	47		T24	81
auto[1]	auto[0]	others[1]	1441	1			T6	7		T14	10		T24	13
auto[1]	auto[0]	others[2]	1424	1			T6	6		T14	8		T24	15
auto[1]	auto[0]	others[3]	1649	1			T6	8		T14	4		T24	17
auto[1]	auto[0]	interest[1]	918	1			T6	9		T14	5		T24	9
auto[1]	auto[0]	interest[4]	5609	1			T6	40		T14	34		T24	45
auto[1]	auto[0]	interest[64]	2864	1			T6	20		T14	16		T24	30

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal