Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 94.01 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1034 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1892403643 Jun 29 05:26:28 PM PDT 24 Jun 29 05:26:32 PM PDT 24 209547574 ps
T1035 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2694347484 Jun 29 05:26:22 PM PDT 24 Jun 29 05:26:23 PM PDT 24 109136284 ps
T1036 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2362649387 Jun 29 05:26:37 PM PDT 24 Jun 29 05:26:44 PM PDT 24 207190725 ps
T1037 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2640329160 Jun 29 05:26:54 PM PDT 24 Jun 29 05:26:56 PM PDT 24 14578635 ps
T108 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3125910495 Jun 29 05:26:24 PM PDT 24 Jun 29 05:26:27 PM PDT 24 262217568 ps
T1038 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.123244868 Jun 29 05:26:15 PM PDT 24 Jun 29 05:26:18 PM PDT 24 50055702 ps
T1039 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1396209449 Jun 29 05:26:23 PM PDT 24 Jun 29 05:26:24 PM PDT 24 16787232 ps
T1040 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2812555898 Jun 29 05:26:27 PM PDT 24 Jun 29 05:26:29 PM PDT 24 41552378 ps
T183 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.509831442 Jun 29 05:26:14 PM PDT 24 Jun 29 05:26:26 PM PDT 24 159938999 ps
T126 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.950701642 Jun 29 05:26:12 PM PDT 24 Jun 29 05:26:15 PM PDT 24 361750209 ps
T1041 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1180874816 Jun 29 05:26:24 PM PDT 24 Jun 29 05:26:27 PM PDT 24 147795153 ps
T1042 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2820078598 Jun 29 05:26:29 PM PDT 24 Jun 29 05:26:31 PM PDT 24 38958721 ps
T127 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.445043343 Jun 29 05:26:17 PM PDT 24 Jun 29 05:26:20 PM PDT 24 47271342 ps
T1043 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3247439158 Jun 29 05:26:39 PM PDT 24 Jun 29 05:26:40 PM PDT 24 40232084 ps
T181 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1357962910 Jun 29 05:26:28 PM PDT 24 Jun 29 05:26:36 PM PDT 24 1032332420 ps
T113 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.180508003 Jun 29 05:26:21 PM PDT 24 Jun 29 05:26:26 PM PDT 24 326902079 ps
T1044 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2458608825 Jun 29 05:26:17 PM PDT 24 Jun 29 05:26:20 PM PDT 24 89516834 ps
T1045 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.283258041 Jun 29 05:26:30 PM PDT 24 Jun 29 05:26:32 PM PDT 24 28202159 ps
T163 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2185400437 Jun 29 05:26:38 PM PDT 24 Jun 29 05:26:46 PM PDT 24 112983867 ps
T1046 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.44123159 Jun 29 05:26:16 PM PDT 24 Jun 29 05:26:21 PM PDT 24 227650994 ps
T112 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3925979036 Jun 29 05:26:15 PM PDT 24 Jun 29 05:26:19 PM PDT 24 505208639 ps
T1047 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.482055533 Jun 29 05:26:21 PM PDT 24 Jun 29 05:26:23 PM PDT 24 57285341 ps
T114 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1228525680 Jun 29 05:26:35 PM PDT 24 Jun 29 05:26:38 PM PDT 24 35751453 ps
T1048 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4258300587 Jun 29 05:26:29 PM PDT 24 Jun 29 05:26:30 PM PDT 24 19925889 ps
T1049 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.138261645 Jun 29 05:26:20 PM PDT 24 Jun 29 05:26:23 PM PDT 24 77450783 ps
T128 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1993763538 Jun 29 05:26:19 PM PDT 24 Jun 29 05:26:27 PM PDT 24 736090054 ps
T1050 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2415224783 Jun 29 05:26:29 PM PDT 24 Jun 29 05:26:31 PM PDT 24 18107159 ps
T1051 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4009012943 Jun 29 05:26:14 PM PDT 24 Jun 29 05:26:15 PM PDT 24 12716086 ps
T1052 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3068763645 Jun 29 05:26:22 PM PDT 24 Jun 29 05:26:23 PM PDT 24 13828071 ps
T129 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1620916732 Jun 29 05:26:21 PM PDT 24 Jun 29 05:26:23 PM PDT 24 40993604 ps
T130 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.831177618 Jun 29 05:26:13 PM PDT 24 Jun 29 05:26:40 PM PDT 24 2800760223 ps
T1053 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2473389350 Jun 29 05:26:28 PM PDT 24 Jun 29 05:26:30 PM PDT 24 14779806 ps
T1054 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2415909956 Jun 29 05:26:14 PM PDT 24 Jun 29 05:26:17 PM PDT 24 101084589 ps
T1055 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3277061412 Jun 29 05:26:32 PM PDT 24 Jun 29 05:26:36 PM PDT 24 491050053 ps
T1056 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3166487921 Jun 29 05:26:20 PM PDT 24 Jun 29 05:26:22 PM PDT 24 139070504 ps
T110 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1347537890 Jun 29 05:26:22 PM PDT 24 Jun 29 05:26:27 PM PDT 24 211982220 ps
T1057 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2586206679 Jun 29 05:26:24 PM PDT 24 Jun 29 05:26:25 PM PDT 24 40841129 ps
T1058 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4232446907 Jun 29 05:26:54 PM PDT 24 Jun 29 05:26:56 PM PDT 24 35094781 ps
T1059 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1033856798 Jun 29 05:26:26 PM PDT 24 Jun 29 05:26:50 PM PDT 24 371891055 ps
T1060 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.393683267 Jun 29 05:26:29 PM PDT 24 Jun 29 05:26:31 PM PDT 24 56997714 ps
T1061 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1785151433 Jun 29 05:26:27 PM PDT 24 Jun 29 05:26:29 PM PDT 24 13082242 ps
T1062 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1592494175 Jun 29 05:26:24 PM PDT 24 Jun 29 05:26:25 PM PDT 24 22846070 ps
T179 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1546951881 Jun 29 05:26:21 PM PDT 24 Jun 29 05:26:41 PM PDT 24 301962069 ps
T164 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.689481593 Jun 29 05:26:29 PM PDT 24 Jun 29 05:26:32 PM PDT 24 278439447 ps
T1063 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2399693967 Jun 29 05:26:41 PM PDT 24 Jun 29 05:26:43 PM PDT 24 35663897 ps
T116 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2611354249 Jun 29 05:26:27 PM PDT 24 Jun 29 05:26:33 PM PDT 24 200899157 ps
T132 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3464474095 Jun 29 05:26:09 PM PDT 24 Jun 29 05:26:13 PM PDT 24 84774242 ps
T133 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2956299044 Jun 29 05:26:19 PM PDT 24 Jun 29 05:26:21 PM PDT 24 26691233 ps
T131 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.107212309 Jun 29 05:26:24 PM PDT 24 Jun 29 05:26:28 PM PDT 24 457650782 ps
T1064 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.316302164 Jun 29 05:26:09 PM PDT 24 Jun 29 05:26:12 PM PDT 24 13644190 ps
T134 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2229852633 Jun 29 05:26:27 PM PDT 24 Jun 29 05:26:30 PM PDT 24 265681505 ps
T1065 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1933275505 Jun 29 05:26:34 PM PDT 24 Jun 29 05:26:36 PM PDT 24 11839662 ps
T165 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.363955383 Jun 29 05:26:28 PM PDT 24 Jun 29 05:26:31 PM PDT 24 68791280 ps
T1066 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3216652337 Jun 29 05:26:22 PM PDT 24 Jun 29 05:26:26 PM PDT 24 47074121 ps
T1067 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3120615050 Jun 29 05:26:16 PM PDT 24 Jun 29 05:26:21 PM PDT 24 162261812 ps
T115 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1813888268 Jun 29 05:26:32 PM PDT 24 Jun 29 05:26:36 PM PDT 24 138717731 ps
T1068 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1228041356 Jun 29 05:26:14 PM PDT 24 Jun 29 05:26:21 PM PDT 24 119485381 ps
T1069 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.756512702 Jun 29 05:26:43 PM PDT 24 Jun 29 05:26:45 PM PDT 24 24888110 ps
T173 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.335214841 Jun 29 05:26:16 PM PDT 24 Jun 29 05:26:31 PM PDT 24 2827313318 ps
T1070 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1642939478 Jun 29 05:26:20 PM PDT 24 Jun 29 05:26:24 PM PDT 24 1520392751 ps
T1071 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4253780965 Jun 29 05:26:29 PM PDT 24 Jun 29 05:26:31 PM PDT 24 24462447 ps
T135 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1138247620 Jun 29 05:26:21 PM PDT 24 Jun 29 05:26:24 PM PDT 24 334113805 ps
T1072 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1994853956 Jun 29 05:26:17 PM PDT 24 Jun 29 05:26:20 PM PDT 24 92896618 ps
T1073 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2711035694 Jun 29 05:26:34 PM PDT 24 Jun 29 05:26:36 PM PDT 24 66947850 ps
T1074 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3315627325 Jun 29 05:26:17 PM PDT 24 Jun 29 05:26:19 PM PDT 24 55746253 ps
T1075 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2473820858 Jun 29 05:26:14 PM PDT 24 Jun 29 05:26:16 PM PDT 24 220096031 ps
T1076 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3723227998 Jun 29 05:26:32 PM PDT 24 Jun 29 05:26:35 PM PDT 24 107871112 ps
T111 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1508731973 Jun 29 05:26:20 PM PDT 24 Jun 29 05:26:24 PM PDT 24 502525254 ps
T1077 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.467656113 Jun 29 05:26:30 PM PDT 24 Jun 29 05:26:33 PM PDT 24 78467314 ps
T84 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.538157315 Jun 29 05:26:18 PM PDT 24 Jun 29 05:26:19 PM PDT 24 15510768 ps
T136 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2676520362 Jun 29 05:26:39 PM PDT 24 Jun 29 05:27:13 PM PDT 24 3762339826 ps
T1078 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3407723900 Jun 29 05:26:33 PM PDT 24 Jun 29 05:26:37 PM PDT 24 743949588 ps
T1079 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.898093130 Jun 29 05:26:50 PM PDT 24 Jun 29 05:26:53 PM PDT 24 232344724 ps
T1080 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3127428291 Jun 29 05:26:19 PM PDT 24 Jun 29 05:26:21 PM PDT 24 20448572 ps
T1081 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3625218544 Jun 29 05:26:53 PM PDT 24 Jun 29 05:27:00 PM PDT 24 272782294 ps
T1082 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2140374579 Jun 29 05:26:53 PM PDT 24 Jun 29 05:26:55 PM PDT 24 80472384 ps
T1083 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1606998422 Jun 29 05:26:30 PM PDT 24 Jun 29 05:26:32 PM PDT 24 12874242 ps
T1084 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1612556287 Jun 29 05:26:53 PM PDT 24 Jun 29 05:26:54 PM PDT 24 13266211 ps
T1085 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1673990348 Jun 29 05:26:27 PM PDT 24 Jun 29 05:26:29 PM PDT 24 14805222 ps
T1086 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3717159910 Jun 29 05:26:34 PM PDT 24 Jun 29 05:26:35 PM PDT 24 16846230 ps
T1087 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1064750630 Jun 29 05:26:34 PM PDT 24 Jun 29 05:26:39 PM PDT 24 63802887 ps
T1088 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2787953363 Jun 29 05:26:35 PM PDT 24 Jun 29 05:26:37 PM PDT 24 14728618 ps
T1089 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4274371474 Jun 29 05:26:16 PM PDT 24 Jun 29 05:26:17 PM PDT 24 11782658 ps
T1090 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.177082172 Jun 29 05:26:28 PM PDT 24 Jun 29 05:26:30 PM PDT 24 18752005 ps
T85 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3453797239 Jun 29 05:26:26 PM PDT 24 Jun 29 05:26:28 PM PDT 24 29915918 ps
T1091 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2658084234 Jun 29 05:26:26 PM PDT 24 Jun 29 05:26:28 PM PDT 24 52008687 ps
T1092 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3223636095 Jun 29 05:26:29 PM PDT 24 Jun 29 05:26:31 PM PDT 24 32545969 ps
T1093 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1215793288 Jun 29 05:26:21 PM PDT 24 Jun 29 05:26:23 PM PDT 24 73139673 ps
T1094 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1138108009 Jun 29 05:26:13 PM PDT 24 Jun 29 05:26:16 PM PDT 24 437598043 ps
T1095 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.52954726 Jun 29 05:26:22 PM PDT 24 Jun 29 05:26:25 PM PDT 24 134023391 ps
T1096 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2221439855 Jun 29 05:26:42 PM PDT 24 Jun 29 05:26:47 PM PDT 24 571403276 ps
T1097 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3780894486 Jun 29 05:26:22 PM PDT 24 Jun 29 05:26:27 PM PDT 24 900620604 ps
T1098 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3103497799 Jun 29 05:26:32 PM PDT 24 Jun 29 05:26:34 PM PDT 24 59535307 ps
T1099 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1582202838 Jun 29 05:26:28 PM PDT 24 Jun 29 05:26:30 PM PDT 24 92790731 ps
T1100 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.389494153 Jun 29 05:26:32 PM PDT 24 Jun 29 05:26:34 PM PDT 24 23669528 ps
T1101 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.691943143 Jun 29 05:26:20 PM PDT 24 Jun 29 05:26:42 PM PDT 24 624691362 ps
T1102 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2419647353 Jun 29 05:26:28 PM PDT 24 Jun 29 05:26:34 PM PDT 24 812757098 ps
T1103 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1806607612 Jun 29 05:26:18 PM PDT 24 Jun 29 05:26:21 PM PDT 24 416256202 ps
T1104 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.117620546 Jun 29 05:26:25 PM PDT 24 Jun 29 05:26:27 PM PDT 24 152486284 ps
T1105 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2507244075 Jun 29 05:26:52 PM PDT 24 Jun 29 05:26:55 PM PDT 24 26010380 ps
T1106 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2606622480 Jun 29 05:26:08 PM PDT 24 Jun 29 05:26:13 PM PDT 24 154610606 ps
T1107 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2742361583 Jun 29 05:26:12 PM PDT 24 Jun 29 05:26:48 PM PDT 24 2183471191 ps
T1108 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2534126273 Jun 29 05:26:18 PM PDT 24 Jun 29 05:26:44 PM PDT 24 4220966116 ps
T1109 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3573482075 Jun 29 05:26:53 PM PDT 24 Jun 29 05:27:01 PM PDT 24 231791178 ps
T1110 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.12292656 Jun 29 05:26:07 PM PDT 24 Jun 29 05:26:12 PM PDT 24 890792196 ps
T1111 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1229272824 Jun 29 05:26:38 PM PDT 24 Jun 29 05:26:41 PM PDT 24 304818130 ps
T1112 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1545197128 Jun 29 05:26:52 PM PDT 24 Jun 29 05:26:54 PM PDT 24 13218649 ps
T1113 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1299148034 Jun 29 05:26:43 PM PDT 24 Jun 29 05:26:46 PM PDT 24 314025532 ps
T1114 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2819816356 Jun 29 05:26:07 PM PDT 24 Jun 29 05:26:31 PM PDT 24 3979901580 ps
T1115 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4069750083 Jun 29 05:26:30 PM PDT 24 Jun 29 05:26:35 PM PDT 24 1377744746 ps
T1116 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2332939460 Jun 29 05:26:21 PM PDT 24 Jun 29 05:26:26 PM PDT 24 230175253 ps
T86 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.765039082 Jun 29 05:26:23 PM PDT 24 Jun 29 05:26:25 PM PDT 24 87674734 ps
T1117 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4289493867 Jun 29 05:26:33 PM PDT 24 Jun 29 05:26:37 PM PDT 24 270134916 ps
T182 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1081809706 Jun 29 05:26:17 PM PDT 24 Jun 29 05:26:32 PM PDT 24 3879330336 ps
T1118 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.168691508 Jun 29 05:26:45 PM PDT 24 Jun 29 05:26:49 PM PDT 24 86760346 ps
T1119 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4203049812 Jun 29 05:26:27 PM PDT 24 Jun 29 05:26:30 PM PDT 24 122401628 ps
T1120 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3967200275 Jun 29 05:26:21 PM PDT 24 Jun 29 05:26:25 PM PDT 24 118690275 ps
T180 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.930905204 Jun 29 05:26:31 PM PDT 24 Jun 29 05:26:45 PM PDT 24 2240031565 ps
T1121 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3428042593 Jun 29 05:26:09 PM PDT 24 Jun 29 05:26:11 PM PDT 24 22214437 ps
T177 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1764728566 Jun 29 05:26:27 PM PDT 24 Jun 29 05:26:46 PM PDT 24 1132383044 ps
T1122 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.517632333 Jun 29 05:26:29 PM PDT 24 Jun 29 05:26:33 PM PDT 24 87891469 ps
T1123 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3963159004 Jun 29 05:26:45 PM PDT 24 Jun 29 05:26:46 PM PDT 24 36688346 ps
T176 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1292812514 Jun 29 05:26:22 PM PDT 24 Jun 29 05:26:26 PM PDT 24 777411896 ps
T1124 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3633919421 Jun 29 05:26:22 PM PDT 24 Jun 29 05:26:25 PM PDT 24 314614237 ps
T1125 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.36718542 Jun 29 05:26:28 PM PDT 24 Jun 29 05:26:30 PM PDT 24 53093660 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3935512502 Jun 29 05:26:09 PM PDT 24 Jun 29 05:26:12 PM PDT 24 45404430 ps
T1127 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.272364507 Jun 29 05:26:22 PM PDT 24 Jun 29 05:26:35 PM PDT 24 786694735 ps
T1128 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.718207420 Jun 29 05:26:40 PM PDT 24 Jun 29 05:26:41 PM PDT 24 13967489 ps
T1129 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2216306401 Jun 29 05:26:27 PM PDT 24 Jun 29 05:26:28 PM PDT 24 55300099 ps
T1130 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1552390711 Jun 29 05:26:20 PM PDT 24 Jun 29 05:26:22 PM PDT 24 90828976 ps

Test location /workspace/coverage/default/20.spi_device_stress_all.1548117516
Short name T6
Test name
Test status
Simulation time 653025839460 ps
CPU time 348.75 seconds
Started Jun 29 05:28:18 PM PDT 24
Finished Jun 29 05:34:07 PM PDT 24
Peak memory 266264 kb
Host smart-a3664d33-ba1e-4071-8895-5576b2bc087b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548117516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1548117516
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1375267930
Short name T14
Test name
Test status
Simulation time 12106639635 ps
CPU time 166.08 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:31:26 PM PDT 24
Peak memory 253252 kb
Host smart-23b20d8d-7637-4f4c-86f2-3df2587ece1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375267930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1375267930
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.183524044
Short name T21
Test name
Test status
Simulation time 17124652844 ps
CPU time 123.47 seconds
Started Jun 29 05:27:46 PM PDT 24
Finished Jun 29 05:29:51 PM PDT 24
Peak memory 266272 kb
Host smart-8ade9e4a-f17d-4b51-b0eb-601392d92cf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183524044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.183524044
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3695497141
Short name T106
Test name
Test status
Simulation time 9528746281 ps
CPU time 17.02 seconds
Started Jun 29 05:26:17 PM PDT 24
Finished Jun 29 05:26:35 PM PDT 24
Peak memory 223568 kb
Host smart-0ba1f5fc-bbdb-4e8a-a1d0-b5d2936a7edb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695497141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3695497141
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2885684383
Short name T24
Test name
Test status
Simulation time 148454859383 ps
CPU time 718.13 seconds
Started Jun 29 05:29:19 PM PDT 24
Finished Jun 29 05:41:18 PM PDT 24
Peak memory 254368 kb
Host smart-3161b712-86d3-420a-a427-21782125ef0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885684383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2885684383
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.4293400618
Short name T66
Test name
Test status
Simulation time 18865465 ps
CPU time 0.79 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:07 PM PDT 24
Peak memory 216340 kb
Host smart-9db9328d-3254-4c59-b3b6-524466859688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293400618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4293400618
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1839528073
Short name T191
Test name
Test status
Simulation time 64128488140 ps
CPU time 754.1 seconds
Started Jun 29 05:29:05 PM PDT 24
Finished Jun 29 05:41:41 PM PDT 24
Peak memory 298952 kb
Host smart-9e73caad-14a6-4ab9-916c-3cb41a82d7fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839528073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1839528073
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1021562049
Short name T49
Test name
Test status
Simulation time 101733371572 ps
CPU time 350.07 seconds
Started Jun 29 05:29:17 PM PDT 24
Finished Jun 29 05:35:08 PM PDT 24
Peak memory 266092 kb
Host smart-7e6a047f-e3b0-48ec-8616-6a9a1b5fe18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021562049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1021562049
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.233106591
Short name T38
Test name
Test status
Simulation time 12349895690 ps
CPU time 75.31 seconds
Started Jun 29 05:27:46 PM PDT 24
Finished Jun 29 05:29:03 PM PDT 24
Peak memory 257212 kb
Host smart-2157000a-4634-4535-90e4-6bc144f0a74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233106591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.233106591
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4002140161
Short name T194
Test name
Test status
Simulation time 20948203572 ps
CPU time 258.52 seconds
Started Jun 29 05:29:43 PM PDT 24
Finished Jun 29 05:34:03 PM PDT 24
Peak memory 258012 kb
Host smart-bfdf02cd-eebc-4b56-8f1e-45936eb37999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002140161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4002140161
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2025725917
Short name T17
Test name
Test status
Simulation time 304311362 ps
CPU time 1.18 seconds
Started Jun 29 05:27:02 PM PDT 24
Finished Jun 29 05:27:04 PM PDT 24
Peak memory 236356 kb
Host smart-56f5520c-4718-4b04-b835-70ce1dd8f708
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025725917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2025725917
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3094903606
Short name T51
Test name
Test status
Simulation time 3521840071 ps
CPU time 74.53 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:29:30 PM PDT 24
Peak memory 253712 kb
Host smart-bad8e879-4c2f-4160-ad8f-77e39f2e6c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094903606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3094903606
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3558647526
Short name T39
Test name
Test status
Simulation time 1915947046 ps
CPU time 11.22 seconds
Started Jun 29 05:29:04 PM PDT 24
Finished Jun 29 05:29:15 PM PDT 24
Peak memory 241392 kb
Host smart-8354c1c9-a2a3-4d05-9b8f-4ef393d6a408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558647526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3558647526
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1773815192
Short name T104
Test name
Test status
Simulation time 91477541 ps
CPU time 3.35 seconds
Started Jun 29 05:26:23 PM PDT 24
Finished Jun 29 05:26:27 PM PDT 24
Peak memory 215616 kb
Host smart-cbcdfc6d-5a45-46bb-a6ef-b7155b81c9d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773815192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1773815192
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1631155534
Short name T219
Test name
Test status
Simulation time 9109199801 ps
CPU time 113.21 seconds
Started Jun 29 05:27:52 PM PDT 24
Finished Jun 29 05:29:48 PM PDT 24
Peak memory 266200 kb
Host smart-c12f56a8-9856-42be-b5ef-71e3814f08dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631155534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1631155534
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3073826551
Short name T192
Test name
Test status
Simulation time 61044973374 ps
CPU time 453.8 seconds
Started Jun 29 05:29:53 PM PDT 24
Finished Jun 29 05:37:27 PM PDT 24
Peak memory 259200 kb
Host smart-dfd9dd5c-9be2-4376-817e-a606cdcf1d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073826551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3073826551
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4025566366
Short name T124
Test name
Test status
Simulation time 203700079 ps
CPU time 12.6 seconds
Started Jun 29 05:26:09 PM PDT 24
Finished Jun 29 05:26:23 PM PDT 24
Peak memory 215400 kb
Host smart-3a9a75aa-5d37-462e-a15c-de6447af4040
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025566366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.4025566366
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.925072862
Short name T168
Test name
Test status
Simulation time 131352954350 ps
CPU time 314.35 seconds
Started Jun 29 05:29:22 PM PDT 24
Finished Jun 29 05:34:37 PM PDT 24
Peak memory 273716 kb
Host smart-a6f43f3c-c5f6-4595-a4fe-301679df79d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925072862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.925072862
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1801269347
Short name T231
Test name
Test status
Simulation time 25178580488 ps
CPU time 228.61 seconds
Started Jun 29 05:29:29 PM PDT 24
Finished Jun 29 05:33:18 PM PDT 24
Peak memory 250800 kb
Host smart-1865b770-5849-4bff-b9a0-67c731a465b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801269347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1801269347
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.646662008
Short name T19
Test name
Test status
Simulation time 72084636049 ps
CPU time 517.16 seconds
Started Jun 29 05:27:59 PM PDT 24
Finished Jun 29 05:36:37 PM PDT 24
Peak memory 254580 kb
Host smart-24aadf0d-836a-4c46-a689-819a99899009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646662008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.646662008
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3067433238
Short name T36
Test name
Test status
Simulation time 19815051298 ps
CPU time 198.29 seconds
Started Jun 29 05:27:21 PM PDT 24
Finished Jun 29 05:30:40 PM PDT 24
Peak memory 255336 kb
Host smart-1dba50bc-5a36-451e-96af-eda20387ac55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067433238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3067433238
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2646786257
Short name T137
Test name
Test status
Simulation time 12432759436 ps
CPU time 208.55 seconds
Started Jun 29 05:27:16 PM PDT 24
Finished Jun 29 05:30:46 PM PDT 24
Peak memory 264840 kb
Host smart-710cd877-19f7-4048-8f93-43387deb2125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646786257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2646786257
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3210816961
Short name T253
Test name
Test status
Simulation time 4495347283 ps
CPU time 62.54 seconds
Started Jun 29 05:28:50 PM PDT 24
Finished Jun 29 05:29:53 PM PDT 24
Peak memory 257504 kb
Host smart-3e1a1635-853a-4d5d-ab29-75d23d6e4c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210816961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3210816961
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2822097605
Short name T50
Test name
Test status
Simulation time 288551616899 ps
CPU time 444.55 seconds
Started Jun 29 05:29:47 PM PDT 24
Finished Jun 29 05:37:12 PM PDT 24
Peak memory 255528 kb
Host smart-84011dca-5e14-4c1d-ab33-d8040d7e147c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822097605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2822097605
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1620582678
Short name T175
Test name
Test status
Simulation time 104133712430 ps
CPU time 267.68 seconds
Started Jun 29 05:29:49 PM PDT 24
Finished Jun 29 05:34:18 PM PDT 24
Peak memory 249864 kb
Host smart-ba8c03e7-0d8b-42db-b7a0-a7ee8290a689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620582678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1620582678
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4287011280
Short name T59
Test name
Test status
Simulation time 40213928 ps
CPU time 0.74 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:27:50 PM PDT 24
Peak memory 205960 kb
Host smart-c1384b11-27da-45e7-8b23-83e82471a30b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287011280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4287011280
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2263607032
Short name T64
Test name
Test status
Simulation time 500299516 ps
CPU time 13.02 seconds
Started Jun 29 05:26:23 PM PDT 24
Finished Jun 29 05:26:37 PM PDT 24
Peak memory 215676 kb
Host smart-2bd23bee-0682-4ef8-b075-173ea2578428
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263607032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2263607032
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1944303749
Short name T289
Test name
Test status
Simulation time 16657441710 ps
CPU time 107.36 seconds
Started Jun 29 05:28:32 PM PDT 24
Finished Jun 29 05:30:19 PM PDT 24
Peak memory 257796 kb
Host smart-cab7a643-9a5c-4deb-a941-ace828247c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944303749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1944303749
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2215922573
Short name T217
Test name
Test status
Simulation time 47063488932 ps
CPU time 218.44 seconds
Started Jun 29 05:27:16 PM PDT 24
Finished Jun 29 05:30:55 PM PDT 24
Peak memory 265604 kb
Host smart-6f847474-9175-4ebc-b693-cca43250474b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215922573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2215922573
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1003633203
Short name T82
Test name
Test status
Simulation time 57843733423 ps
CPU time 178.83 seconds
Started Jun 29 05:27:23 PM PDT 24
Finished Jun 29 05:30:22 PM PDT 24
Peak memory 273796 kb
Host smart-4603ed09-8c90-49c6-876f-8046eda39657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003633203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1003633203
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1813888268
Short name T115
Test name
Test status
Simulation time 138717731 ps
CPU time 3.92 seconds
Started Jun 29 05:26:32 PM PDT 24
Finished Jun 29 05:26:36 PM PDT 24
Peak memory 215532 kb
Host smart-7af40ee9-ebd5-42a7-9642-9a3cd4edc494
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813888268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1813888268
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3865793810
Short name T304
Test name
Test status
Simulation time 329302599 ps
CPU time 11.82 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:28:02 PM PDT 24
Peak memory 235272 kb
Host smart-0016c42a-e2bf-4fdd-ad8d-ec6a9a44e2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865793810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3865793810
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.493898111
Short name T23
Test name
Test status
Simulation time 62099346385 ps
CPU time 27.22 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:28:18 PM PDT 24
Peak memory 216948 kb
Host smart-62637c22-c72a-423c-9096-b2a00ddbfbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493898111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.493898111
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.929627483
Short name T751
Test name
Test status
Simulation time 194976194625 ps
CPU time 352.92 seconds
Started Jun 29 05:29:01 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 268172 kb
Host smart-a1101d5c-8ecc-4e14-9218-68c7f4147e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929627483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.929627483
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1186644284
Short name T178
Test name
Test status
Simulation time 572990604 ps
CPU time 13.96 seconds
Started Jun 29 05:26:50 PM PDT 24
Finished Jun 29 05:27:05 PM PDT 24
Peak memory 215228 kb
Host smart-49d3f102-fbb8-4445-97c8-794f2dc644db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186644284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1186644284
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.296042023
Short name T305
Test name
Test status
Simulation time 296402258 ps
CPU time 9.42 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:28:01 PM PDT 24
Peak memory 236916 kb
Host smart-78d2cebf-9cb2-4eb5-b129-87f0ee2f4325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296042023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.296042023
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.105669789
Short name T20
Test name
Test status
Simulation time 594258361626 ps
CPU time 595.59 seconds
Started Jun 29 05:28:29 PM PDT 24
Finished Jun 29 05:38:25 PM PDT 24
Peak memory 282632 kb
Host smart-44ee4155-09d7-4578-ac2a-885853c30df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105669789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.105669789
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1796193732
Short name T160
Test name
Test status
Simulation time 14164348265 ps
CPU time 35.61 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:28:25 PM PDT 24
Peak memory 241468 kb
Host smart-a326b714-389d-4f92-800d-a7a8df78b8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796193732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1796193732
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.48596578
Short name T103
Test name
Test status
Simulation time 1932320697 ps
CPU time 18.28 seconds
Started Jun 29 05:26:23 PM PDT 24
Finished Jun 29 05:26:42 PM PDT 24
Peak memory 215396 kb
Host smart-d26d96d5-fe9b-42a4-9181-6c75271b8024
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48596578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_
tl_intg_err.48596578
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.15516289
Short name T33
Test name
Test status
Simulation time 24865503515 ps
CPU time 199.47 seconds
Started Jun 29 05:27:17 PM PDT 24
Finished Jun 29 05:30:39 PM PDT 24
Peak memory 241584 kb
Host smart-33b43a41-5e6e-499e-94e6-de4a94a09e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15516289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.15516289
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2895169510
Short name T700
Test name
Test status
Simulation time 10928996510 ps
CPU time 47.47 seconds
Started Jun 29 05:27:42 PM PDT 24
Finished Jun 29 05:28:30 PM PDT 24
Peak memory 241528 kb
Host smart-395885be-cb42-4cca-be4b-05ed27fec699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895169510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2895169510
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_upload.2473370663
Short name T187
Test name
Test status
Simulation time 887612923 ps
CPU time 4.43 seconds
Started Jun 29 05:27:55 PM PDT 24
Finished Jun 29 05:28:00 PM PDT 24
Peak memory 224964 kb
Host smart-6210653d-5982-4636-b358-6d5a6929d4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473370663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2473370663
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1318970001
Short name T297
Test name
Test status
Simulation time 9683443587 ps
CPU time 64.79 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:28:57 PM PDT 24
Peak memory 253488 kb
Host smart-15a9f594-e927-4126-baff-f3ad97014942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318970001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1318970001
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3067531576
Short name T206
Test name
Test status
Simulation time 630745147 ps
CPU time 6.1 seconds
Started Jun 29 05:28:12 PM PDT 24
Finished Jun 29 05:28:20 PM PDT 24
Peak memory 224964 kb
Host smart-b6a99e03-fa67-4d42-8142-87f93aff6a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067531576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3067531576
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1347537890
Short name T110
Test name
Test status
Simulation time 211982220 ps
CPU time 4.21 seconds
Started Jun 29 05:26:22 PM PDT 24
Finished Jun 29 05:26:27 PM PDT 24
Peak memory 215556 kb
Host smart-e3cd3a0b-89b6-423f-96ed-708286103c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347537890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1347537890
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2318863832
Short name T226
Test name
Test status
Simulation time 1101871411 ps
CPU time 5.52 seconds
Started Jun 29 05:27:51 PM PDT 24
Finished Jun 29 05:28:00 PM PDT 24
Peak memory 224884 kb
Host smart-6cf35af4-453d-4ce7-b87c-aa6791d7ec83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318863832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2318863832
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3935512502
Short name T1126
Test name
Test status
Simulation time 45404430 ps
CPU time 1.52 seconds
Started Jun 29 05:26:09 PM PDT 24
Finished Jun 29 05:26:12 PM PDT 24
Peak memory 207136 kb
Host smart-2ff9e327-be13-42cf-9a17-92533ca2cd5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935512502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3935512502
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2217948620
Short name T34
Test name
Test status
Simulation time 108557372 ps
CPU time 1.76 seconds
Started Jun 29 05:27:12 PM PDT 24
Finished Jun 29 05:27:14 PM PDT 24
Peak memory 216920 kb
Host smart-7b26c0d9-0991-4efc-87fb-124b04ae7275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217948620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2217948620
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2819816356
Short name T1114
Test name
Test status
Simulation time 3979901580 ps
CPU time 22.16 seconds
Started Jun 29 05:26:07 PM PDT 24
Finished Jun 29 05:26:31 PM PDT 24
Peak memory 207188 kb
Host smart-0ba4bb74-5622-4cb0-8faf-02c5654c85e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819816356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2819816356
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2742361583
Short name T1107
Test name
Test status
Simulation time 2183471191 ps
CPU time 35.05 seconds
Started Jun 29 05:26:12 PM PDT 24
Finished Jun 29 05:26:48 PM PDT 24
Peak memory 207088 kb
Host smart-26a34a11-e67b-4dd2-8049-a1d93ccc196f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742361583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2742361583
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.538157315
Short name T84
Test name
Test status
Simulation time 15510768 ps
CPU time 0.94 seconds
Started Jun 29 05:26:18 PM PDT 24
Finished Jun 29 05:26:19 PM PDT 24
Peak memory 206876 kb
Host smart-456c614f-22e1-4a4c-b6c6-638bdbfca111
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538157315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.538157315
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2606622480
Short name T1106
Test name
Test status
Simulation time 154610606 ps
CPU time 3.75 seconds
Started Jun 29 05:26:08 PM PDT 24
Finished Jun 29 05:26:13 PM PDT 24
Peak memory 218140 kb
Host smart-71e033d3-51ba-497c-b67d-ab81afcd56b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606622480 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2606622480
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3127897593
Short name T122
Test name
Test status
Simulation time 138574164 ps
CPU time 2.08 seconds
Started Jun 29 05:26:14 PM PDT 24
Finished Jun 29 05:26:17 PM PDT 24
Peak memory 207200 kb
Host smart-a00e5f86-af8d-4152-995c-0d10a40c1ab6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127897593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
127897593
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.316302164
Short name T1064
Test name
Test status
Simulation time 13644190 ps
CPU time 0.73 seconds
Started Jun 29 05:26:09 PM PDT 24
Finished Jun 29 05:26:12 PM PDT 24
Peak memory 203808 kb
Host smart-152d56f1-1b57-48bb-9f47-f089b44d75d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316302164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.316302164
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3464474095
Short name T132
Test name
Test status
Simulation time 84774242 ps
CPU time 1.77 seconds
Started Jun 29 05:26:09 PM PDT 24
Finished Jun 29 05:26:13 PM PDT 24
Peak memory 215400 kb
Host smart-e16a4a1e-0513-428b-8f16-5015a42b7808
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464474095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3464474095
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3046353637
Short name T1020
Test name
Test status
Simulation time 15518366 ps
CPU time 0.65 seconds
Started Jun 29 05:26:21 PM PDT 24
Finished Jun 29 05:26:23 PM PDT 24
Peak memory 203780 kb
Host smart-578d0cbf-0224-49c2-a102-7962f9db4795
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046353637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3046353637
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3974852488
Short name T152
Test name
Test status
Simulation time 236093771 ps
CPU time 1.97 seconds
Started Jun 29 05:26:10 PM PDT 24
Finished Jun 29 05:26:13 PM PDT 24
Peak memory 207216 kb
Host smart-ed1f9435-4cf4-4fb5-9874-a01242da45ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974852488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3974852488
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3925979036
Short name T112
Test name
Test status
Simulation time 505208639 ps
CPU time 3.33 seconds
Started Jun 29 05:26:15 PM PDT 24
Finished Jun 29 05:26:19 PM PDT 24
Peak memory 220212 kb
Host smart-779946af-da73-42f4-a3ff-c6ac13fe58c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925979036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
925979036
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1877166410
Short name T63
Test name
Test status
Simulation time 6970175230 ps
CPU time 16.94 seconds
Started Jun 29 05:26:08 PM PDT 24
Finished Jun 29 05:26:27 PM PDT 24
Peak memory 215720 kb
Host smart-ac32ed80-ac7a-4430-ae70-c1c21c5a5996
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877166410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1877166410
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2534126273
Short name T1108
Test name
Test status
Simulation time 4220966116 ps
CPU time 25.09 seconds
Started Jun 29 05:26:18 PM PDT 24
Finished Jun 29 05:26:44 PM PDT 24
Peak memory 215364 kb
Host smart-07da19db-c2d0-42bb-815e-7b817ff3d4db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534126273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2534126273
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3780894486
Short name T1097
Test name
Test status
Simulation time 900620604 ps
CPU time 3.71 seconds
Started Jun 29 05:26:22 PM PDT 24
Finished Jun 29 05:26:27 PM PDT 24
Peak memory 218344 kb
Host smart-6a2ed13f-9a0f-4ac9-908f-9bf61b72d729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780894486 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3780894486
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.950701642
Short name T126
Test name
Test status
Simulation time 361750209 ps
CPU time 2.63 seconds
Started Jun 29 05:26:12 PM PDT 24
Finished Jun 29 05:26:15 PM PDT 24
Peak memory 215404 kb
Host smart-a7805020-4bad-4ed6-ba38-ab779a389426
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950701642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.950701642
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3428042593
Short name T1121
Test name
Test status
Simulation time 22214437 ps
CPU time 0.8 seconds
Started Jun 29 05:26:09 PM PDT 24
Finished Jun 29 05:26:11 PM PDT 24
Peak memory 203860 kb
Host smart-afc5c06a-cc27-4041-aa28-a2a09b2fc624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428042593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
428042593
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1620916732
Short name T129
Test name
Test status
Simulation time 40993604 ps
CPU time 1.4 seconds
Started Jun 29 05:26:21 PM PDT 24
Finished Jun 29 05:26:23 PM PDT 24
Peak memory 215396 kb
Host smart-86c8dfc0-6e8c-45e9-97bd-c0524ccc6a6b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620916732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1620916732
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4274371474
Short name T1089
Test name
Test status
Simulation time 11782658 ps
CPU time 0.67 seconds
Started Jun 29 05:26:16 PM PDT 24
Finished Jun 29 05:26:17 PM PDT 24
Peak memory 203776 kb
Host smart-ee3f33c3-0bde-4bb5-8a84-b0cb1caf87db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274371474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4274371474
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2282637158
Short name T154
Test name
Test status
Simulation time 410566828 ps
CPU time 3.12 seconds
Started Jun 29 05:26:20 PM PDT 24
Finished Jun 29 05:26:24 PM PDT 24
Peak memory 215396 kb
Host smart-f742a6d8-2c96-4ecb-9e22-b591eff3d813
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282637158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2282637158
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.12292656
Short name T1110
Test name
Test status
Simulation time 890792196 ps
CPU time 3.17 seconds
Started Jun 29 05:26:07 PM PDT 24
Finished Jun 29 05:26:12 PM PDT 24
Peak memory 215524 kb
Host smart-d4a5210b-493d-4f9a-b5f0-98901e2059c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12292656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.12292656
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.509831442
Short name T183
Test name
Test status
Simulation time 159938999 ps
CPU time 6.26 seconds
Started Jun 29 05:26:14 PM PDT 24
Finished Jun 29 05:26:26 PM PDT 24
Peak memory 215360 kb
Host smart-ee5b2e25-cac5-49ea-8735-1d1e0cf3c711
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509831442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.509831442
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2185400437
Short name T163
Test name
Test status
Simulation time 112983867 ps
CPU time 2.68 seconds
Started Jun 29 05:26:38 PM PDT 24
Finished Jun 29 05:26:46 PM PDT 24
Peak memory 216844 kb
Host smart-10c17af2-333d-4cb3-a699-c4475155febf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185400437 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2185400437
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3967200275
Short name T1120
Test name
Test status
Simulation time 118690275 ps
CPU time 2.82 seconds
Started Jun 29 05:26:21 PM PDT 24
Finished Jun 29 05:26:25 PM PDT 24
Peak memory 207132 kb
Host smart-33b3a6b8-b833-4a3e-b9e0-fd54a5bd5fe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967200275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3967200275
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1396209449
Short name T1039
Test name
Test status
Simulation time 16787232 ps
CPU time 0.75 seconds
Started Jun 29 05:26:23 PM PDT 24
Finished Jun 29 05:26:24 PM PDT 24
Peak memory 203800 kb
Host smart-cbf7adef-06cb-45b6-afa5-62cb8cdb94c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396209449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1396209449
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.898093130
Short name T1079
Test name
Test status
Simulation time 232344724 ps
CPU time 3.13 seconds
Started Jun 29 05:26:50 PM PDT 24
Finished Jun 29 05:26:53 PM PDT 24
Peak memory 215268 kb
Host smart-067f93d0-be99-4a33-b23d-66cc70b08cbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898093130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.898093130
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4203049812
Short name T1119
Test name
Test status
Simulation time 122401628 ps
CPU time 2.09 seconds
Started Jun 29 05:26:27 PM PDT 24
Finished Jun 29 05:26:30 PM PDT 24
Peak memory 215644 kb
Host smart-6b8d00f1-0a77-484b-bbad-1e203b4d4d73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203049812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4203049812
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3365894413
Short name T161
Test name
Test status
Simulation time 1336365058 ps
CPU time 7.83 seconds
Started Jun 29 05:26:26 PM PDT 24
Finished Jun 29 05:26:34 PM PDT 24
Peak memory 215400 kb
Host smart-47539e3a-f29b-4b09-9eef-2a900e78a3d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365894413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3365894413
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1229272824
Short name T1111
Test name
Test status
Simulation time 304818130 ps
CPU time 2.63 seconds
Started Jun 29 05:26:38 PM PDT 24
Finished Jun 29 05:26:41 PM PDT 24
Peak memory 217104 kb
Host smart-f806c8ab-0008-4004-a2e7-cddfe7fe63c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229272824 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1229272824
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.482055533
Short name T1047
Test name
Test status
Simulation time 57285341 ps
CPU time 1.24 seconds
Started Jun 29 05:26:21 PM PDT 24
Finished Jun 29 05:26:23 PM PDT 24
Peak memory 207080 kb
Host smart-ab061207-d7f4-4ce2-9deb-d26669ce8aac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482055533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.482055533
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2711035694
Short name T1073
Test name
Test status
Simulation time 66947850 ps
CPU time 0.71 seconds
Started Jun 29 05:26:34 PM PDT 24
Finished Jun 29 05:26:36 PM PDT 24
Peak memory 203812 kb
Host smart-92cc4156-4ec0-47d8-97e0-0ed22aa73bab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711035694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2711035694
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.467656113
Short name T1077
Test name
Test status
Simulation time 78467314 ps
CPU time 1.74 seconds
Started Jun 29 05:26:30 PM PDT 24
Finished Jun 29 05:26:33 PM PDT 24
Peak memory 215292 kb
Host smart-829a530b-5ca8-4a34-9387-051e75d9560a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467656113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.467656113
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.180508003
Short name T113
Test name
Test status
Simulation time 326902079 ps
CPU time 4.31 seconds
Started Jun 29 05:26:21 PM PDT 24
Finished Jun 29 05:26:26 PM PDT 24
Peak memory 215676 kb
Host smart-041e0128-f8d0-408a-bed1-270dcc7e5974
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180508003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.180508003
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2245234430
Short name T101
Test name
Test status
Simulation time 131176553 ps
CPU time 3.73 seconds
Started Jun 29 05:26:29 PM PDT 24
Finished Jun 29 05:26:34 PM PDT 24
Peak memory 216764 kb
Host smart-903378da-ab47-4e5c-960e-c35bb980faa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245234430 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2245234430
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1552390711
Short name T1130
Test name
Test status
Simulation time 90828976 ps
CPU time 2.28 seconds
Started Jun 29 05:26:20 PM PDT 24
Finished Jun 29 05:26:22 PM PDT 24
Peak memory 215416 kb
Host smart-9cdce103-751d-4d00-b907-ac960f21591d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552390711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1552390711
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2415224783
Short name T1050
Test name
Test status
Simulation time 18107159 ps
CPU time 0.79 seconds
Started Jun 29 05:26:29 PM PDT 24
Finished Jun 29 05:26:31 PM PDT 24
Peak memory 204144 kb
Host smart-f08833af-84de-4d5f-8ad7-7e5c77a563a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415224783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2415224783
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2415909956
Short name T1054
Test name
Test status
Simulation time 101084589 ps
CPU time 2.82 seconds
Started Jun 29 05:26:14 PM PDT 24
Finished Jun 29 05:26:17 PM PDT 24
Peak memory 215280 kb
Host smart-1a260993-bb30-47d1-a3e3-7336aa94f6fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415909956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2415909956
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1357962910
Short name T181
Test name
Test status
Simulation time 1032332420 ps
CPU time 7.56 seconds
Started Jun 29 05:26:28 PM PDT 24
Finished Jun 29 05:26:36 PM PDT 24
Peak memory 215420 kb
Host smart-b2625106-ea99-4267-b098-238d3d247cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357962910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1357962910
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1180874816
Short name T1041
Test name
Test status
Simulation time 147795153 ps
CPU time 2.27 seconds
Started Jun 29 05:26:24 PM PDT 24
Finished Jun 29 05:26:27 PM PDT 24
Peak memory 215624 kb
Host smart-7e562b6e-b5da-47e7-850f-be164996a6b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180874816 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1180874816
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2399693967
Short name T1063
Test name
Test status
Simulation time 35663897 ps
CPU time 1.31 seconds
Started Jun 29 05:26:41 PM PDT 24
Finished Jun 29 05:26:43 PM PDT 24
Peak memory 215396 kb
Host smart-563cc506-8bcb-4adb-a204-2a74441dc0c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399693967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2399693967
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2787953363
Short name T1088
Test name
Test status
Simulation time 14728618 ps
CPU time 0.76 seconds
Started Jun 29 05:26:35 PM PDT 24
Finished Jun 29 05:26:37 PM PDT 24
Peak memory 203856 kb
Host smart-039eb2af-8fcd-435f-88ef-fe3540ee2487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787953363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2787953363
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1064750630
Short name T1087
Test name
Test status
Simulation time 63802887 ps
CPU time 4.23 seconds
Started Jun 29 05:26:34 PM PDT 24
Finished Jun 29 05:26:39 PM PDT 24
Peak memory 215368 kb
Host smart-2f9948ef-376c-45dc-be04-3443c9841aad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064750630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1064750630
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1299148034
Short name T1113
Test name
Test status
Simulation time 314025532 ps
CPU time 3.13 seconds
Started Jun 29 05:26:43 PM PDT 24
Finished Jun 29 05:26:46 PM PDT 24
Peak memory 215492 kb
Host smart-40f52228-6407-4507-9a8b-ccde4f87c2e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299148034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1299148034
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2362649387
Short name T1036
Test name
Test status
Simulation time 207190725 ps
CPU time 6.9 seconds
Started Jun 29 05:26:37 PM PDT 24
Finished Jun 29 05:26:44 PM PDT 24
Peak memory 215416 kb
Host smart-ff55b33c-c2cf-4831-b30c-90d76d071a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362649387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2362649387
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2221439855
Short name T1096
Test name
Test status
Simulation time 571403276 ps
CPU time 3.83 seconds
Started Jun 29 05:26:42 PM PDT 24
Finished Jun 29 05:26:47 PM PDT 24
Peak memory 217660 kb
Host smart-4e2b2ecc-0379-443b-9d29-f353ffc30c8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221439855 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2221439855
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.97270966
Short name T121
Test name
Test status
Simulation time 42852944 ps
CPU time 1.45 seconds
Started Jun 29 05:26:28 PM PDT 24
Finished Jun 29 05:26:31 PM PDT 24
Peak memory 215404 kb
Host smart-9844ad29-e010-4025-9170-e56a2bc0c723
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97270966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.97270966
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.177082172
Short name T1090
Test name
Test status
Simulation time 18752005 ps
CPU time 0.7 seconds
Started Jun 29 05:26:28 PM PDT 24
Finished Jun 29 05:26:30 PM PDT 24
Peak memory 203856 kb
Host smart-3f252880-e62e-4de4-b809-5139454d84cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177082172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.177082172
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1884760582
Short name T1023
Test name
Test status
Simulation time 224692033 ps
CPU time 3.89 seconds
Started Jun 29 05:26:54 PM PDT 24
Finished Jun 29 05:26:59 PM PDT 24
Peak memory 214892 kb
Host smart-545feaa3-af80-424f-bc6d-bb7f1b1cb094
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884760582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1884760582
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3625218544
Short name T1081
Test name
Test status
Simulation time 272782294 ps
CPU time 6.4 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:27:00 PM PDT 24
Peak memory 215300 kb
Host smart-561aa79e-e340-4a48-858e-5ed9163a999c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625218544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3625218544
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.168691508
Short name T1118
Test name
Test status
Simulation time 86760346 ps
CPU time 2.95 seconds
Started Jun 29 05:26:45 PM PDT 24
Finished Jun 29 05:26:49 PM PDT 24
Peak memory 216420 kb
Host smart-0a4c573b-f582-457d-986c-54b00771d3ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168691508 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.168691508
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1138247620
Short name T135
Test name
Test status
Simulation time 334113805 ps
CPU time 1.82 seconds
Started Jun 29 05:26:21 PM PDT 24
Finished Jun 29 05:26:24 PM PDT 24
Peak memory 215396 kb
Host smart-14379703-e2cc-4bd3-bc1c-8cabbc81cac7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138247620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1138247620
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.718207420
Short name T1128
Test name
Test status
Simulation time 13967489 ps
CPU time 0.71 seconds
Started Jun 29 05:26:40 PM PDT 24
Finished Jun 29 05:26:41 PM PDT 24
Peak memory 203864 kb
Host smart-ca92b477-a352-4463-9b24-6f1fd4524f88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718207420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.718207420
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3216652337
Short name T1066
Test name
Test status
Simulation time 47074121 ps
CPU time 2.94 seconds
Started Jun 29 05:26:22 PM PDT 24
Finished Jun 29 05:26:26 PM PDT 24
Peak memory 215368 kb
Host smart-ffe03b85-0e18-4d3d-839c-f132bd2fbbe4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216652337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3216652337
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2306303035
Short name T109
Test name
Test status
Simulation time 178187501 ps
CPU time 4.41 seconds
Started Jun 29 05:26:33 PM PDT 24
Finished Jun 29 05:26:38 PM PDT 24
Peak memory 215464 kb
Host smart-eff09c36-efcc-4239-bb79-e01ec6a5bb73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306303035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2306303035
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3393424488
Short name T62
Test name
Test status
Simulation time 206946732 ps
CPU time 12.37 seconds
Started Jun 29 05:26:29 PM PDT 24
Finished Jun 29 05:26:42 PM PDT 24
Peak memory 215404 kb
Host smart-33256f45-2820-47f0-b87b-40a0c439aa20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393424488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3393424488
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1892403643
Short name T1034
Test name
Test status
Simulation time 209547574 ps
CPU time 3.67 seconds
Started Jun 29 05:26:28 PM PDT 24
Finished Jun 29 05:26:32 PM PDT 24
Peak memory 217784 kb
Host smart-0451a4ea-0b82-4900-a1ef-7daeef467a59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892403643 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1892403643
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1582202838
Short name T1099
Test name
Test status
Simulation time 92790731 ps
CPU time 1.59 seconds
Started Jun 29 05:26:28 PM PDT 24
Finished Jun 29 05:26:30 PM PDT 24
Peak memory 215376 kb
Host smart-19bc0247-da1d-4084-a7ae-e4c81d57400d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582202838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1582202838
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3397735700
Short name T1032
Test name
Test status
Simulation time 167775552 ps
CPU time 0.71 seconds
Started Jun 29 05:26:22 PM PDT 24
Finished Jun 29 05:26:23 PM PDT 24
Peak memory 204116 kb
Host smart-32d0597d-3e26-428c-b5a7-507ee0b1fc11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397735700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3397735700
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1642939478
Short name T1070
Test name
Test status
Simulation time 1520392751 ps
CPU time 3.07 seconds
Started Jun 29 05:26:20 PM PDT 24
Finished Jun 29 05:26:24 PM PDT 24
Peak memory 215808 kb
Host smart-558496d6-063d-4b81-a621-0b68218b22e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642939478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1642939478
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3125910495
Short name T108
Test name
Test status
Simulation time 262217568 ps
CPU time 2.04 seconds
Started Jun 29 05:26:24 PM PDT 24
Finished Jun 29 05:26:27 PM PDT 24
Peak memory 215560 kb
Host smart-042b1231-22ee-4684-87d4-cf5af7627dc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125910495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3125910495
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2507244075
Short name T1105
Test name
Test status
Simulation time 26010380 ps
CPU time 1.64 seconds
Started Jun 29 05:26:52 PM PDT 24
Finished Jun 29 05:26:55 PM PDT 24
Peak memory 216356 kb
Host smart-7cdf780f-5c82-472d-96e7-b5419809e297
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507244075 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2507244075
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.689481593
Short name T164
Test name
Test status
Simulation time 278439447 ps
CPU time 1.84 seconds
Started Jun 29 05:26:29 PM PDT 24
Finished Jun 29 05:26:32 PM PDT 24
Peak memory 215452 kb
Host smart-3b2197fc-8dd4-438e-8782-d30c71bfef41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689481593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.689481593
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3068763645
Short name T1052
Test name
Test status
Simulation time 13828071 ps
CPU time 0.73 seconds
Started Jun 29 05:26:22 PM PDT 24
Finished Jun 29 05:26:23 PM PDT 24
Peak memory 203856 kb
Host smart-9f71e650-fad5-49c9-b0de-781bd56741ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068763645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3068763645
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.363955383
Short name T165
Test name
Test status
Simulation time 68791280 ps
CPU time 1.78 seconds
Started Jun 29 05:26:28 PM PDT 24
Finished Jun 29 05:26:31 PM PDT 24
Peak memory 215316 kb
Host smart-1d07a687-6a14-436b-aaf8-40384dc9bff1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363955383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.363955383
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4289493867
Short name T1117
Test name
Test status
Simulation time 270134916 ps
CPU time 3.09 seconds
Started Jun 29 05:26:33 PM PDT 24
Finished Jun 29 05:26:37 PM PDT 24
Peak memory 215684 kb
Host smart-db0ee101-de77-4cc2-addd-354703d677f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289493867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
4289493867
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3573482075
Short name T1109
Test name
Test status
Simulation time 231791178 ps
CPU time 6.77 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:27:01 PM PDT 24
Peak memory 215752 kb
Host smart-bec699a0-e107-41ff-9258-c0fb77574052
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573482075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3573482075
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3277061412
Short name T1055
Test name
Test status
Simulation time 491050053 ps
CPU time 3.76 seconds
Started Jun 29 05:26:32 PM PDT 24
Finished Jun 29 05:26:36 PM PDT 24
Peak memory 217204 kb
Host smart-5d4dc633-649b-47fe-a1ca-4f83d785c6d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277061412 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3277061412
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.117620546
Short name T1104
Test name
Test status
Simulation time 152486284 ps
CPU time 1.52 seconds
Started Jun 29 05:26:25 PM PDT 24
Finished Jun 29 05:26:27 PM PDT 24
Peak memory 215336 kb
Host smart-7fe51f08-015a-404d-9052-0dfd847830d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117620546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.117620546
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.36718542
Short name T1125
Test name
Test status
Simulation time 53093660 ps
CPU time 0.76 seconds
Started Jun 29 05:26:28 PM PDT 24
Finished Jun 29 05:26:30 PM PDT 24
Peak memory 203864 kb
Host smart-0d397d0c-57c4-4749-9228-3e4dcfe87015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36718542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.36718542
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3723227998
Short name T1076
Test name
Test status
Simulation time 107871112 ps
CPU time 1.85 seconds
Started Jun 29 05:26:32 PM PDT 24
Finished Jun 29 05:26:35 PM PDT 24
Peak memory 215400 kb
Host smart-db105cf2-8482-43dd-a109-586b1adeefc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723227998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3723227998
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2419647353
Short name T1102
Test name
Test status
Simulation time 812757098 ps
CPU time 4.59 seconds
Started Jun 29 05:26:28 PM PDT 24
Finished Jun 29 05:26:34 PM PDT 24
Peak memory 215576 kb
Host smart-5ac42343-ec10-45e5-9ed4-5c5f761b3beb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419647353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2419647353
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1546951881
Short name T179
Test name
Test status
Simulation time 301962069 ps
CPU time 18.95 seconds
Started Jun 29 05:26:21 PM PDT 24
Finished Jun 29 05:26:41 PM PDT 24
Peak memory 215612 kb
Host smart-7f8ab5b2-0961-423c-b941-ae1ff144df88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546951881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1546951881
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3135017006
Short name T162
Test name
Test status
Simulation time 59775546 ps
CPU time 1.76 seconds
Started Jun 29 05:26:24 PM PDT 24
Finished Jun 29 05:26:27 PM PDT 24
Peak memory 215364 kb
Host smart-ac2f4fdc-4544-4c4e-ba77-eb66823a9246
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135017006 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3135017006
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.107212309
Short name T131
Test name
Test status
Simulation time 457650782 ps
CPU time 2.57 seconds
Started Jun 29 05:26:24 PM PDT 24
Finished Jun 29 05:26:28 PM PDT 24
Peak memory 215316 kb
Host smart-01e97344-d636-4199-80e6-f389d7025ebb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107212309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.107212309
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1673990348
Short name T1085
Test name
Test status
Simulation time 14805222 ps
CPU time 0.71 seconds
Started Jun 29 05:26:27 PM PDT 24
Finished Jun 29 05:26:29 PM PDT 24
Peak memory 203856 kb
Host smart-d7ea018d-aad2-4f67-9eef-31d14ebee0c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673990348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1673990348
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.52954726
Short name T1095
Test name
Test status
Simulation time 134023391 ps
CPU time 3.15 seconds
Started Jun 29 05:26:22 PM PDT 24
Finished Jun 29 05:26:25 PM PDT 24
Peak memory 215280 kb
Host smart-19462d27-b965-4ef7-9baa-00a1694c608f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52954726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sp
i_device_same_csr_outstanding.52954726
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.691943143
Short name T1101
Test name
Test status
Simulation time 624691362 ps
CPU time 21.2 seconds
Started Jun 29 05:26:20 PM PDT 24
Finished Jun 29 05:26:42 PM PDT 24
Peak memory 215332 kb
Host smart-a93f1100-3c1d-42ec-b324-aa3f6e2c3e0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691943143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.691943143
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1033856798
Short name T1059
Test name
Test status
Simulation time 371891055 ps
CPU time 23.95 seconds
Started Jun 29 05:26:26 PM PDT 24
Finished Jun 29 05:26:50 PM PDT 24
Peak memory 207064 kb
Host smart-4099ff06-621f-432f-b149-a0ac14daf5c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033856798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1033856798
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3453797239
Short name T85
Test name
Test status
Simulation time 29915918 ps
CPU time 1.29 seconds
Started Jun 29 05:26:26 PM PDT 24
Finished Jun 29 05:26:28 PM PDT 24
Peak memory 207164 kb
Host smart-ade1948a-ef1e-498f-ac9a-726d8edba663
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453797239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3453797239
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.138261645
Short name T1049
Test name
Test status
Simulation time 77450783 ps
CPU time 2.83 seconds
Started Jun 29 05:26:20 PM PDT 24
Finished Jun 29 05:26:23 PM PDT 24
Peak memory 216544 kb
Host smart-96b0615f-f2e4-4e56-bc9c-8ef21a56b7df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138261645 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.138261645
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2458608825
Short name T1044
Test name
Test status
Simulation time 89516834 ps
CPU time 1.88 seconds
Started Jun 29 05:26:17 PM PDT 24
Finished Jun 29 05:26:20 PM PDT 24
Peak memory 207264 kb
Host smart-1a14fd2e-e060-4507-889a-1659a1ef4470
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458608825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
458608825
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1785151433
Short name T1061
Test name
Test status
Simulation time 13082242 ps
CPU time 0.69 seconds
Started Jun 29 05:26:27 PM PDT 24
Finished Jun 29 05:26:29 PM PDT 24
Peak memory 203864 kb
Host smart-8997588e-4bf5-45c0-abe1-f9155112fec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785151433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
785151433
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3997645442
Short name T120
Test name
Test status
Simulation time 71308171 ps
CPU time 2.29 seconds
Started Jun 29 05:26:23 PM PDT 24
Finished Jun 29 05:26:26 PM PDT 24
Peak memory 215320 kb
Host smart-9002758f-741e-424e-9a52-aa9a3b535fd9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997645442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3997645442
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3247439158
Short name T1043
Test name
Test status
Simulation time 40232084 ps
CPU time 0.68 seconds
Started Jun 29 05:26:39 PM PDT 24
Finished Jun 29 05:26:40 PM PDT 24
Peak memory 204108 kb
Host smart-bb9d477a-7e6b-4e13-94d6-e838b4ccdcbb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247439158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3247439158
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1247663467
Short name T1025
Test name
Test status
Simulation time 158810448 ps
CPU time 3.01 seconds
Started Jun 29 05:26:17 PM PDT 24
Finished Jun 29 05:26:21 PM PDT 24
Peak memory 215324 kb
Host smart-4f20c8a9-8791-49d3-b1c8-1f021386e79a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247663467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1247663467
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1292812514
Short name T176
Test name
Test status
Simulation time 777411896 ps
CPU time 2.97 seconds
Started Jun 29 05:26:22 PM PDT 24
Finished Jun 29 05:26:26 PM PDT 24
Peak memory 215672 kb
Host smart-cacb9731-5373-4c9d-beab-8dbc406de091
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292812514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
292812514
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.930905204
Short name T180
Test name
Test status
Simulation time 2240031565 ps
CPU time 13.61 seconds
Started Jun 29 05:26:31 PM PDT 24
Finished Jun 29 05:26:45 PM PDT 24
Peak memory 215604 kb
Host smart-91d071e8-56c0-432a-9af1-db6823ad30ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930905204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.930905204
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2140374579
Short name T1082
Test name
Test status
Simulation time 80472384 ps
CPU time 0.73 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:26:55 PM PDT 24
Peak memory 203976 kb
Host smart-7aaa7e44-114f-4244-adea-65e0c1e7e135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140374579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2140374579
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3963159004
Short name T1123
Test name
Test status
Simulation time 36688346 ps
CPU time 0.73 seconds
Started Jun 29 05:26:45 PM PDT 24
Finished Jun 29 05:26:46 PM PDT 24
Peak memory 203828 kb
Host smart-31b22822-b26d-433f-bd17-578a2c12e266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963159004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3963159004
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.573021331
Short name T1033
Test name
Test status
Simulation time 21609162 ps
CPU time 0.74 seconds
Started Jun 29 05:26:43 PM PDT 24
Finished Jun 29 05:26:45 PM PDT 24
Peak memory 203760 kb
Host smart-1d2aa82c-2770-4386-8222-ac8351c89e21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573021331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.573021331
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2508552946
Short name T1019
Test name
Test status
Simulation time 17964807 ps
CPU time 0.75 seconds
Started Jun 29 05:26:48 PM PDT 24
Finished Jun 29 05:26:49 PM PDT 24
Peak memory 204164 kb
Host smart-ee1546f1-1337-464f-b29f-01d445605699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508552946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2508552946
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1933275505
Short name T1065
Test name
Test status
Simulation time 11839662 ps
CPU time 0.72 seconds
Started Jun 29 05:26:34 PM PDT 24
Finished Jun 29 05:26:36 PM PDT 24
Peak memory 204164 kb
Host smart-7314d9ba-12de-4d1e-b5fc-4c73a455254a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933275505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1933275505
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1612556287
Short name T1084
Test name
Test status
Simulation time 13266211 ps
CPU time 0.74 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:26:54 PM PDT 24
Peak memory 203660 kb
Host smart-153f555d-7e13-47d2-8226-65ef263ce57b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612556287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1612556287
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2658084234
Short name T1091
Test name
Test status
Simulation time 52008687 ps
CPU time 0.71 seconds
Started Jun 29 05:26:26 PM PDT 24
Finished Jun 29 05:26:28 PM PDT 24
Peak memory 203860 kb
Host smart-a3ce76ff-b198-4ebb-9174-c28862af8e8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658084234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2658084234
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.344252908
Short name T1028
Test name
Test status
Simulation time 24240693 ps
CPU time 0.78 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:26:55 PM PDT 24
Peak memory 204172 kb
Host smart-1bbc99eb-3a5f-434e-96d6-0a17531d796b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344252908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.344252908
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2586206679
Short name T1057
Test name
Test status
Simulation time 40841129 ps
CPU time 0.79 seconds
Started Jun 29 05:26:24 PM PDT 24
Finished Jun 29 05:26:25 PM PDT 24
Peak memory 203788 kb
Host smart-c90cae04-04b3-4051-b706-13cc0c806e72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586206679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2586206679
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.393683267
Short name T1060
Test name
Test status
Simulation time 56997714 ps
CPU time 0.76 seconds
Started Jun 29 05:26:29 PM PDT 24
Finished Jun 29 05:26:31 PM PDT 24
Peak memory 203832 kb
Host smart-6f2dc3ca-1d46-4b11-ae32-1a714428f0da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393683267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.393683267
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2676520362
Short name T136
Test name
Test status
Simulation time 3762339826 ps
CPU time 23.88 seconds
Started Jun 29 05:26:39 PM PDT 24
Finished Jun 29 05:27:13 PM PDT 24
Peak memory 215476 kb
Host smart-3db843e6-4487-4b68-8215-97c8485a27cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676520362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2676520362
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.831177618
Short name T130
Test name
Test status
Simulation time 2800760223 ps
CPU time 26.34 seconds
Started Jun 29 05:26:13 PM PDT 24
Finished Jun 29 05:26:40 PM PDT 24
Peak memory 207268 kb
Host smart-b4e6c2b7-9c3a-4066-a7d6-bbb1b84d038d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831177618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.831177618
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.765039082
Short name T86
Test name
Test status
Simulation time 87674734 ps
CPU time 1.4 seconds
Started Jun 29 05:26:23 PM PDT 24
Finished Jun 29 05:26:25 PM PDT 24
Peak memory 216348 kb
Host smart-3d3dae7c-f9fe-4fda-a410-8117fe6fcd3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765039082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.765039082
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1503775079
Short name T102
Test name
Test status
Simulation time 362115361 ps
CPU time 2.75 seconds
Started Jun 29 05:26:13 PM PDT 24
Finished Jun 29 05:26:17 PM PDT 24
Peak memory 216796 kb
Host smart-9a0b3a91-3da9-4180-9f49-badb598d3268
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503775079 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1503775079
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4280444908
Short name T123
Test name
Test status
Simulation time 87568651 ps
CPU time 2.41 seconds
Started Jun 29 05:26:26 PM PDT 24
Finished Jun 29 05:26:29 PM PDT 24
Peak memory 215404 kb
Host smart-d5fecf88-c53d-42c2-a9b9-708b721a853a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280444908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
280444908
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.470145115
Short name T1029
Test name
Test status
Simulation time 24857665 ps
CPU time 0.73 seconds
Started Jun 29 05:26:26 PM PDT 24
Finished Jun 29 05:26:27 PM PDT 24
Peak memory 203768 kb
Host smart-e3ea841a-ca13-4093-8503-000e1a2bd4c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470145115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.470145115
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2956299044
Short name T133
Test name
Test status
Simulation time 26691233 ps
CPU time 1.96 seconds
Started Jun 29 05:26:19 PM PDT 24
Finished Jun 29 05:26:21 PM PDT 24
Peak memory 215388 kb
Host smart-e3c94215-c11d-42ca-89b7-177167648097
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956299044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2956299044
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1592494175
Short name T1062
Test name
Test status
Simulation time 22846070 ps
CPU time 0.67 seconds
Started Jun 29 05:26:24 PM PDT 24
Finished Jun 29 05:26:25 PM PDT 24
Peak memory 204112 kb
Host smart-184343d4-aab4-472d-9c3c-bec2b834f087
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592494175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1592494175
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.635289195
Short name T1031
Test name
Test status
Simulation time 51434410 ps
CPU time 1.83 seconds
Started Jun 29 05:26:25 PM PDT 24
Finished Jun 29 05:26:27 PM PDT 24
Peak memory 215392 kb
Host smart-31e7746d-8a21-492c-a66a-9bace43b0483
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635289195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.635289195
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.170004098
Short name T105
Test name
Test status
Simulation time 75690103 ps
CPU time 2.09 seconds
Started Jun 29 05:26:28 PM PDT 24
Finished Jun 29 05:26:31 PM PDT 24
Peak memory 215560 kb
Host smart-ec00012f-160d-432a-afdd-a2f4cb13830c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170004098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.170004098
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3800537999
Short name T117
Test name
Test status
Simulation time 651856293 ps
CPU time 13.86 seconds
Started Jun 29 05:26:17 PM PDT 24
Finished Jun 29 05:26:31 PM PDT 24
Peak memory 215320 kb
Host smart-217aca08-54f3-4ba9-a2ec-de7e205e0ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800537999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3800537999
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4258300587
Short name T1048
Test name
Test status
Simulation time 19925889 ps
CPU time 0.76 seconds
Started Jun 29 05:26:29 PM PDT 24
Finished Jun 29 05:26:30 PM PDT 24
Peak memory 203848 kb
Host smart-4fefe06a-b41c-4586-84bb-15ba9076b793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258300587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
4258300587
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4232446907
Short name T1058
Test name
Test status
Simulation time 35094781 ps
CPU time 0.75 seconds
Started Jun 29 05:26:54 PM PDT 24
Finished Jun 29 05:26:56 PM PDT 24
Peak memory 203588 kb
Host smart-ffa4cc98-132d-437f-b114-dafb3969b71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232446907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4232446907
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3103497799
Short name T1098
Test name
Test status
Simulation time 59535307 ps
CPU time 0.8 seconds
Started Jun 29 05:26:32 PM PDT 24
Finished Jun 29 05:26:34 PM PDT 24
Peak memory 204136 kb
Host smart-60609be5-0b28-48ef-b9d6-080509147824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103497799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3103497799
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3223636095
Short name T1092
Test name
Test status
Simulation time 32545969 ps
CPU time 0.76 seconds
Started Jun 29 05:26:29 PM PDT 24
Finished Jun 29 05:26:31 PM PDT 24
Peak memory 204140 kb
Host smart-ecf366c6-adcf-4d75-ab76-2ee11cff5991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223636095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3223636095
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1145929385
Short name T1027
Test name
Test status
Simulation time 12642752 ps
CPU time 0.68 seconds
Started Jun 29 05:26:53 PM PDT 24
Finished Jun 29 05:26:55 PM PDT 24
Peak memory 203984 kb
Host smart-cdb73e50-9e86-4087-8cbe-14fcbcb78b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145929385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1145929385
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2820078598
Short name T1042
Test name
Test status
Simulation time 38958721 ps
CPU time 0.73 seconds
Started Jun 29 05:26:29 PM PDT 24
Finished Jun 29 05:26:31 PM PDT 24
Peak memory 203824 kb
Host smart-f04a88e9-9b73-45df-871d-f3edb6712d0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820078598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2820078598
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2640329160
Short name T1037
Test name
Test status
Simulation time 14578635 ps
CPU time 0.73 seconds
Started Jun 29 05:26:54 PM PDT 24
Finished Jun 29 05:26:56 PM PDT 24
Peak memory 203880 kb
Host smart-47deea86-749e-4703-9f68-b0be782319d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640329160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2640329160
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3247456091
Short name T1018
Test name
Test status
Simulation time 14201669 ps
CPU time 0.73 seconds
Started Jun 29 05:26:32 PM PDT 24
Finished Jun 29 05:26:34 PM PDT 24
Peak memory 204132 kb
Host smart-a83a9f60-11cb-4a05-92b3-9078a116ab58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247456091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3247456091
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3710354230
Short name T1026
Test name
Test status
Simulation time 17533559 ps
CPU time 0.74 seconds
Started Jun 29 05:26:28 PM PDT 24
Finished Jun 29 05:26:30 PM PDT 24
Peak memory 203860 kb
Host smart-1ddef7bd-5c35-4e55-ace7-741e4f510a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710354230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3710354230
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2812555898
Short name T1040
Test name
Test status
Simulation time 41552378 ps
CPU time 0.71 seconds
Started Jun 29 05:26:27 PM PDT 24
Finished Jun 29 05:26:29 PM PDT 24
Peak memory 203864 kb
Host smart-14047c2a-1943-48ab-ba61-73171225f065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812555898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2812555898
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1993763538
Short name T128
Test name
Test status
Simulation time 736090054 ps
CPU time 7.49 seconds
Started Jun 29 05:26:19 PM PDT 24
Finished Jun 29 05:26:27 PM PDT 24
Peak memory 215392 kb
Host smart-0e6c88c3-7006-476e-8471-4e0000f78d82
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993763538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1993763538
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.335214841
Short name T173
Test name
Test status
Simulation time 2827313318 ps
CPU time 13.93 seconds
Started Jun 29 05:26:16 PM PDT 24
Finished Jun 29 05:26:31 PM PDT 24
Peak memory 215388 kb
Host smart-7d18dbb7-596e-4911-92a1-a59aa713c6eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335214841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.335214841
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1980014626
Short name T83
Test name
Test status
Simulation time 47087430 ps
CPU time 1.48 seconds
Started Jun 29 05:26:20 PM PDT 24
Finished Jun 29 05:26:23 PM PDT 24
Peak memory 207196 kb
Host smart-2f928f9f-12dd-4da0-899d-7cbe218af4a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980014626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1980014626
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3633919421
Short name T1124
Test name
Test status
Simulation time 314614237 ps
CPU time 1.76 seconds
Started Jun 29 05:26:22 PM PDT 24
Finished Jun 29 05:26:25 PM PDT 24
Peak memory 215592 kb
Host smart-0c67a252-4408-49f7-a0a0-fb07fb7f45f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633919421 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3633919421
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1806607612
Short name T1103
Test name
Test status
Simulation time 416256202 ps
CPU time 2.85 seconds
Started Jun 29 05:26:18 PM PDT 24
Finished Jun 29 05:26:21 PM PDT 24
Peak memory 215392 kb
Host smart-a8d26422-d3bc-41a5-8a17-cb9b6fc598c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806607612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
806607612
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4009012943
Short name T1051
Test name
Test status
Simulation time 12716086 ps
CPU time 0.7 seconds
Started Jun 29 05:26:14 PM PDT 24
Finished Jun 29 05:26:15 PM PDT 24
Peak memory 203844 kb
Host smart-fb615c94-ae50-4659-9285-b1f0edf606c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009012943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4
009012943
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2229852633
Short name T134
Test name
Test status
Simulation time 265681505 ps
CPU time 2.17 seconds
Started Jun 29 05:26:27 PM PDT 24
Finished Jun 29 05:26:30 PM PDT 24
Peak memory 215336 kb
Host smart-5f76ab7e-08d3-406b-98ce-aec065bf4c0c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229852633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2229852633
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3842763748
Short name T1021
Test name
Test status
Simulation time 11064058 ps
CPU time 0.67 seconds
Started Jun 29 05:26:16 PM PDT 24
Finished Jun 29 05:26:17 PM PDT 24
Peak memory 204004 kb
Host smart-788ba596-e43c-4af0-a142-b12337ea10fa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842763748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3842763748
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4095371747
Short name T153
Test name
Test status
Simulation time 373083850 ps
CPU time 3.22 seconds
Started Jun 29 05:26:26 PM PDT 24
Finished Jun 29 05:26:30 PM PDT 24
Peak memory 215392 kb
Host smart-4298eece-13e2-4b27-8692-c3249e0bbc15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095371747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.4095371747
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2332939460
Short name T1116
Test name
Test status
Simulation time 230175253 ps
CPU time 4.71 seconds
Started Jun 29 05:26:21 PM PDT 24
Finished Jun 29 05:26:26 PM PDT 24
Peak memory 215564 kb
Host smart-58fbebea-fb48-4bcf-8eaa-8a713bb8dd72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332939460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
332939460
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2216306401
Short name T1129
Test name
Test status
Simulation time 55300099 ps
CPU time 0.76 seconds
Started Jun 29 05:26:27 PM PDT 24
Finished Jun 29 05:26:28 PM PDT 24
Peak memory 203860 kb
Host smart-9cb7b523-dfc7-41c4-b988-1c2e18125a8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216306401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2216306401
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3827604197
Short name T1030
Test name
Test status
Simulation time 28102278 ps
CPU time 0.73 seconds
Started Jun 29 05:26:44 PM PDT 24
Finished Jun 29 05:26:45 PM PDT 24
Peak memory 204168 kb
Host smart-7db9a61b-958a-4b41-a4cd-7fd15cb29f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827604197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3827604197
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4253780965
Short name T1071
Test name
Test status
Simulation time 24462447 ps
CPU time 0.76 seconds
Started Jun 29 05:26:29 PM PDT 24
Finished Jun 29 05:26:31 PM PDT 24
Peak memory 204156 kb
Host smart-adb14e58-73f5-49e1-aac1-df887c0c5814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253780965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4253780965
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.6362923
Short name T1022
Test name
Test status
Simulation time 18768897 ps
CPU time 0.76 seconds
Started Jun 29 05:26:33 PM PDT 24
Finished Jun 29 05:26:34 PM PDT 24
Peak memory 203832 kb
Host smart-be7056c1-057d-48c3-a05c-2a76433129bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6362923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.6362923
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1545197128
Short name T1112
Test name
Test status
Simulation time 13218649 ps
CPU time 0.8 seconds
Started Jun 29 05:26:52 PM PDT 24
Finished Jun 29 05:26:54 PM PDT 24
Peak memory 203848 kb
Host smart-1b88b1b7-4bb7-4f42-be61-b3cc47193f9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545197128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1545197128
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3625173653
Short name T1017
Test name
Test status
Simulation time 11898022 ps
CPU time 0.75 seconds
Started Jun 29 05:26:29 PM PDT 24
Finished Jun 29 05:26:31 PM PDT 24
Peak memory 203836 kb
Host smart-b75a2640-0bce-4016-b8b7-4d765e8e76ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625173653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3625173653
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1606998422
Short name T1083
Test name
Test status
Simulation time 12874242 ps
CPU time 0.77 seconds
Started Jun 29 05:26:30 PM PDT 24
Finished Jun 29 05:26:32 PM PDT 24
Peak memory 203864 kb
Host smart-e539d9ef-bb26-4e9f-856a-fbbd600e0f92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606998422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1606998422
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.756512702
Short name T1069
Test name
Test status
Simulation time 24888110 ps
CPU time 0.74 seconds
Started Jun 29 05:26:43 PM PDT 24
Finished Jun 29 05:26:45 PM PDT 24
Peak memory 203816 kb
Host smart-2a7a845f-cbdd-401c-bf2f-9ed3055bf426
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756512702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.756512702
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3717159910
Short name T1086
Test name
Test status
Simulation time 16846230 ps
CPU time 0.71 seconds
Started Jun 29 05:26:34 PM PDT 24
Finished Jun 29 05:26:35 PM PDT 24
Peak memory 203856 kb
Host smart-25cecb7b-8f77-4f24-835a-f879f0c35f55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717159910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3717159910
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.389494153
Short name T1100
Test name
Test status
Simulation time 23669528 ps
CPU time 0.74 seconds
Started Jun 29 05:26:32 PM PDT 24
Finished Jun 29 05:26:34 PM PDT 24
Peak memory 204172 kb
Host smart-5b2cde01-dd0f-475c-8a9e-4cfc20aad193
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389494153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.389494153
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2772494016
Short name T107
Test name
Test status
Simulation time 161450757 ps
CPU time 2.76 seconds
Started Jun 29 05:26:20 PM PDT 24
Finished Jun 29 05:26:23 PM PDT 24
Peak memory 217048 kb
Host smart-d13a9302-201c-4f1f-9d1b-fd406775c8b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772494016 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2772494016
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3127428291
Short name T1080
Test name
Test status
Simulation time 20448572 ps
CPU time 1.41 seconds
Started Jun 29 05:26:19 PM PDT 24
Finished Jun 29 05:26:21 PM PDT 24
Peak memory 207192 kb
Host smart-51be149d-047a-49a1-a101-e59ddd653b77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127428291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
127428291
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4183981858
Short name T1024
Test name
Test status
Simulation time 42171426 ps
CPU time 0.77 seconds
Started Jun 29 05:26:36 PM PDT 24
Finished Jun 29 05:26:37 PM PDT 24
Peak memory 203852 kb
Host smart-41a443e5-ed0a-467b-92b2-45a4c8fd47a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183981858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.4
183981858
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2473820858
Short name T1075
Test name
Test status
Simulation time 220096031 ps
CPU time 1.9 seconds
Started Jun 29 05:26:14 PM PDT 24
Finished Jun 29 05:26:16 PM PDT 24
Peak memory 207200 kb
Host smart-751c2815-1b1e-4e51-937e-5e356ea2bcac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473820858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2473820858
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2611354249
Short name T116
Test name
Test status
Simulation time 200899157 ps
CPU time 5.35 seconds
Started Jun 29 05:26:27 PM PDT 24
Finished Jun 29 05:26:33 PM PDT 24
Peak memory 215676 kb
Host smart-7876e165-b752-43ea-bf29-215c80d5d400
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611354249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
611354249
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1081809706
Short name T182
Test name
Test status
Simulation time 3879330336 ps
CPU time 13.63 seconds
Started Jun 29 05:26:17 PM PDT 24
Finished Jun 29 05:26:32 PM PDT 24
Peak memory 215432 kb
Host smart-b12e281c-81bc-4099-80af-683d88607cfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081809706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1081809706
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.44123159
Short name T1046
Test name
Test status
Simulation time 227650994 ps
CPU time 3.79 seconds
Started Jun 29 05:26:16 PM PDT 24
Finished Jun 29 05:26:21 PM PDT 24
Peak memory 217848 kb
Host smart-0fdeb45e-062b-46fc-90d4-60450d422967
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44123159 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.44123159
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3665459705
Short name T125
Test name
Test status
Simulation time 288180381 ps
CPU time 1.95 seconds
Started Jun 29 05:26:16 PM PDT 24
Finished Jun 29 05:26:19 PM PDT 24
Peak memory 215336 kb
Host smart-861508f8-5af8-4a70-8114-929e93e50c35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665459705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
665459705
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2694347484
Short name T1035
Test name
Test status
Simulation time 109136284 ps
CPU time 0.7 seconds
Started Jun 29 05:26:22 PM PDT 24
Finished Jun 29 05:26:23 PM PDT 24
Peak memory 204144 kb
Host smart-e589aa98-0115-40c4-a11b-03dc0f4572e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694347484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
694347484
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1138108009
Short name T1094
Test name
Test status
Simulation time 437598043 ps
CPU time 1.87 seconds
Started Jun 29 05:26:13 PM PDT 24
Finished Jun 29 05:26:16 PM PDT 24
Peak memory 215388 kb
Host smart-c00d208e-0474-447c-8c98-a859c0741433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138108009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1138108009
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.517632333
Short name T1122
Test name
Test status
Simulation time 87891469 ps
CPU time 2.4 seconds
Started Jun 29 05:26:29 PM PDT 24
Finished Jun 29 05:26:33 PM PDT 24
Peak memory 215880 kb
Host smart-18b186c8-c780-4b12-9589-a79b9ab14d64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517632333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.517632333
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1228041356
Short name T1068
Test name
Test status
Simulation time 119485381 ps
CPU time 6.66 seconds
Started Jun 29 05:26:14 PM PDT 24
Finished Jun 29 05:26:21 PM PDT 24
Peak memory 215404 kb
Host smart-f4f88935-40a0-4539-8776-04dd11fa1a04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228041356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1228041356
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3324227771
Short name T100
Test name
Test status
Simulation time 143654585 ps
CPU time 2.82 seconds
Started Jun 29 05:26:16 PM PDT 24
Finished Jun 29 05:26:20 PM PDT 24
Peak memory 215872 kb
Host smart-3db4ccbb-89fa-4d64-a442-c7a629910611
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324227771 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3324227771
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.445043343
Short name T127
Test name
Test status
Simulation time 47271342 ps
CPU time 1.84 seconds
Started Jun 29 05:26:17 PM PDT 24
Finished Jun 29 05:26:20 PM PDT 24
Peak memory 215404 kb
Host smart-12972d05-782a-4cd4-ba66-256e08feabf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445043343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.445043343
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3315627325
Short name T1074
Test name
Test status
Simulation time 55746253 ps
CPU time 0.75 seconds
Started Jun 29 05:26:17 PM PDT 24
Finished Jun 29 05:26:19 PM PDT 24
Peak memory 203852 kb
Host smart-04d604c6-ca83-481c-9c49-963d74da375a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315627325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
315627325
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1994853956
Short name T1072
Test name
Test status
Simulation time 92896618 ps
CPU time 1.98 seconds
Started Jun 29 05:26:17 PM PDT 24
Finished Jun 29 05:26:20 PM PDT 24
Peak memory 215360 kb
Host smart-7b812f05-3b6d-4c79-8148-fd20372fc2ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994853956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1994853956
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1228525680
Short name T114
Test name
Test status
Simulation time 35751453 ps
CPU time 2.19 seconds
Started Jun 29 05:26:35 PM PDT 24
Finished Jun 29 05:26:38 PM PDT 24
Peak memory 215552 kb
Host smart-0f22d280-8ae4-41d3-9377-d77d3f2e1046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228525680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
228525680
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1764728566
Short name T177
Test name
Test status
Simulation time 1132383044 ps
CPU time 18.66 seconds
Started Jun 29 05:26:27 PM PDT 24
Finished Jun 29 05:26:46 PM PDT 24
Peak memory 215356 kb
Host smart-5cd0f829-0022-490c-bef9-9fcd7af10640
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764728566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1764728566
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4069750083
Short name T1115
Test name
Test status
Simulation time 1377744746 ps
CPU time 3.83 seconds
Started Jun 29 05:26:30 PM PDT 24
Finished Jun 29 05:26:35 PM PDT 24
Peak memory 218076 kb
Host smart-fe7537c2-2917-4e79-bc78-35db9d869d36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069750083 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4069750083
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3166487921
Short name T1056
Test name
Test status
Simulation time 139070504 ps
CPU time 1.39 seconds
Started Jun 29 05:26:20 PM PDT 24
Finished Jun 29 05:26:22 PM PDT 24
Peak memory 207200 kb
Host smart-3ae62843-6a3d-42b6-8a57-14016fcd0ba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166487921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
166487921
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.283258041
Short name T1045
Test name
Test status
Simulation time 28202159 ps
CPU time 0.78 seconds
Started Jun 29 05:26:30 PM PDT 24
Finished Jun 29 05:26:32 PM PDT 24
Peak memory 204088 kb
Host smart-afa662b0-569d-4e7f-9ef1-db94c238c7d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283258041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.283258041
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2919780316
Short name T151
Test name
Test status
Simulation time 67136765 ps
CPU time 2.06 seconds
Started Jun 29 05:26:22 PM PDT 24
Finished Jun 29 05:26:25 PM PDT 24
Peak memory 215380 kb
Host smart-0d327341-944d-4c78-8362-d714de957d01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919780316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2919780316
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3120615050
Short name T1067
Test name
Test status
Simulation time 162261812 ps
CPU time 3.93 seconds
Started Jun 29 05:26:16 PM PDT 24
Finished Jun 29 05:26:21 PM PDT 24
Peak memory 216572 kb
Host smart-d5afc9f1-58c6-4227-8878-2c24e6f4fd5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120615050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
120615050
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3477097408
Short name T118
Test name
Test status
Simulation time 110853401 ps
CPU time 6.55 seconds
Started Jun 29 05:26:22 PM PDT 24
Finished Jun 29 05:26:29 PM PDT 24
Peak memory 216888 kb
Host smart-ebbb41a1-f135-4890-8b46-900658bd1310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477097408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3477097408
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3407723900
Short name T1078
Test name
Test status
Simulation time 743949588 ps
CPU time 3.71 seconds
Started Jun 29 05:26:33 PM PDT 24
Finished Jun 29 05:26:37 PM PDT 24
Peak memory 218120 kb
Host smart-39ec8eb8-cae0-45af-ae03-e0c88f8301cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407723900 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3407723900
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1215793288
Short name T1093
Test name
Test status
Simulation time 73139673 ps
CPU time 1.29 seconds
Started Jun 29 05:26:21 PM PDT 24
Finished Jun 29 05:26:23 PM PDT 24
Peak memory 215324 kb
Host smart-e4a7e92c-0410-43e1-9ad1-5e47f25825cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215793288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
215793288
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2473389350
Short name T1053
Test name
Test status
Simulation time 14779806 ps
CPU time 0.73 seconds
Started Jun 29 05:26:28 PM PDT 24
Finished Jun 29 05:26:30 PM PDT 24
Peak memory 203800 kb
Host smart-b94ebc13-011d-4fd7-b137-f24b9ab77066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473389350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
473389350
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.123244868
Short name T1038
Test name
Test status
Simulation time 50055702 ps
CPU time 1.82 seconds
Started Jun 29 05:26:15 PM PDT 24
Finished Jun 29 05:26:18 PM PDT 24
Peak memory 215980 kb
Host smart-0c88a13a-569f-4110-ac12-d5b0a09fa702
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123244868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.123244868
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1508731973
Short name T111
Test name
Test status
Simulation time 502525254 ps
CPU time 3.42 seconds
Started Jun 29 05:26:20 PM PDT 24
Finished Jun 29 05:26:24 PM PDT 24
Peak memory 215556 kb
Host smart-bc3e85e5-c218-494f-af6a-d6ea99df0599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508731973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
508731973
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.272364507
Short name T1127
Test name
Test status
Simulation time 786694735 ps
CPU time 11.64 seconds
Started Jun 29 05:26:22 PM PDT 24
Finished Jun 29 05:26:35 PM PDT 24
Peak memory 215672 kb
Host smart-29123838-2892-4acc-826b-5757c2da33af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272364507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.272364507
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3427987102
Short name T519
Test name
Test status
Simulation time 37198336 ps
CPU time 0.77 seconds
Started Jun 29 05:27:03 PM PDT 24
Finished Jun 29 05:27:05 PM PDT 24
Peak memory 205952 kb
Host smart-4421e415-92c3-41fc-bdc1-77ed09d3c456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427987102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
427987102
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.4272754104
Short name T448
Test name
Test status
Simulation time 1532446261 ps
CPU time 7.54 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:14 PM PDT 24
Peak memory 224708 kb
Host smart-f0e4dc20-ca5e-4bcc-bfe0-181f8c7f323b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272754104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.4272754104
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3021043897
Short name T512
Test name
Test status
Simulation time 17938804 ps
CPU time 0.8 seconds
Started Jun 29 05:27:03 PM PDT 24
Finished Jun 29 05:27:04 PM PDT 24
Peak memory 205976 kb
Host smart-78e89708-0a86-4f21-b5be-babf6aaa45f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021043897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3021043897
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1258386783
Short name T953
Test name
Test status
Simulation time 3439587755 ps
CPU time 27.71 seconds
Started Jun 29 05:27:06 PM PDT 24
Finished Jun 29 05:27:35 PM PDT 24
Peak memory 253112 kb
Host smart-2449f535-cabf-4cf5-bc8c-b64b1727dfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258386783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1258386783
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2203013567
Short name T543
Test name
Test status
Simulation time 43661433367 ps
CPU time 124.15 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:29:10 PM PDT 24
Peak memory 257996 kb
Host smart-a24e1dcf-4ac0-4731-848d-e2a111dcb53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203013567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2203013567
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.632742586
Short name T736
Test name
Test status
Simulation time 644722060 ps
CPU time 3.32 seconds
Started Jun 29 05:27:04 PM PDT 24
Finished Jun 29 05:27:08 PM PDT 24
Peak memory 218264 kb
Host smart-25bb2336-c7de-4b71-90c3-c4cfb80557e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632742586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
632742586
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1075200664
Short name T508
Test name
Test status
Simulation time 1329480910 ps
CPU time 3.77 seconds
Started Jun 29 05:27:08 PM PDT 24
Finished Jun 29 05:27:13 PM PDT 24
Peak memory 233232 kb
Host smart-641f8731-d4ac-438a-a4c7-947a3395a901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075200664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1075200664
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.674652673
Short name T283
Test name
Test status
Simulation time 46934162712 ps
CPU time 340.87 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:32:47 PM PDT 24
Peak memory 262776 kb
Host smart-28bdfe79-0cb4-4377-9550-cb7b8f717747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674652673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
674652673
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1445330806
Short name T595
Test name
Test status
Simulation time 180174619 ps
CPU time 3.13 seconds
Started Jun 29 05:27:09 PM PDT 24
Finished Jun 29 05:27:13 PM PDT 24
Peak memory 233164 kb
Host smart-83334fe6-e2da-45e3-aa3a-912b4f1e20b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445330806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1445330806
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4032975359
Short name T514
Test name
Test status
Simulation time 31538465735 ps
CPU time 81.03 seconds
Started Jun 29 05:27:04 PM PDT 24
Finished Jun 29 05:28:26 PM PDT 24
Peak memory 239956 kb
Host smart-d4904d39-765a-4eb6-9929-93c9ca779510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032975359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4032975359
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3584928080
Short name T698
Test name
Test status
Simulation time 6845181199 ps
CPU time 7.67 seconds
Started Jun 29 05:27:23 PM PDT 24
Finished Jun 29 05:27:31 PM PDT 24
Peak memory 234224 kb
Host smart-2999973c-e5e1-4a1b-a01d-a314cbd8fcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584928080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3584928080
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4046360513
Short name T939
Test name
Test status
Simulation time 31580118 ps
CPU time 2.25 seconds
Started Jun 29 05:27:02 PM PDT 24
Finished Jun 29 05:27:05 PM PDT 24
Peak memory 233044 kb
Host smart-c6b8148b-050f-4ac9-aab0-ad754c2923ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046360513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4046360513
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3816893638
Short name T156
Test name
Test status
Simulation time 3870718648 ps
CPU time 11.29 seconds
Started Jun 29 05:27:08 PM PDT 24
Finished Jun 29 05:27:20 PM PDT 24
Peak memory 221444 kb
Host smart-c5c1d8bf-8a56-493a-8da6-936403592c4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3816893638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3816893638
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4033777790
Short name T928
Test name
Test status
Simulation time 72655267 ps
CPU time 1.22 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:08 PM PDT 24
Peak memory 207700 kb
Host smart-ce1a4bb6-b2c3-4f86-9dca-244ad771dc4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033777790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4033777790
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.709185153
Short name T864
Test name
Test status
Simulation time 22137645 ps
CPU time 0.7 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:08 PM PDT 24
Peak memory 206164 kb
Host smart-60707e62-17d0-4dfc-8176-4171329bab4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709185153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.709185153
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1309962451
Short name T657
Test name
Test status
Simulation time 10062122 ps
CPU time 0.7 seconds
Started Jun 29 05:27:11 PM PDT 24
Finished Jun 29 05:27:13 PM PDT 24
Peak memory 206072 kb
Host smart-1509401f-1d87-4fe4-a876-aa12e0ded70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309962451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1309962451
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.4020354912
Short name T29
Test name
Test status
Simulation time 62336247 ps
CPU time 0.91 seconds
Started Jun 29 05:27:04 PM PDT 24
Finished Jun 29 05:27:07 PM PDT 24
Peak memory 206732 kb
Host smart-551ca8d7-dd12-4827-988c-d6e971efa9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020354912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.4020354912
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3441386053
Short name T12
Test name
Test status
Simulation time 94738338 ps
CPU time 2.39 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:09 PM PDT 24
Peak memory 225028 kb
Host smart-ed28099a-8872-4be0-9831-5847ab6b4e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441386053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3441386053
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.948927741
Short name T651
Test name
Test status
Simulation time 13753032 ps
CPU time 0.73 seconds
Started Jun 29 05:26:58 PM PDT 24
Finished Jun 29 05:26:59 PM PDT 24
Peak memory 206280 kb
Host smart-485f8338-cc72-4582-b6ca-b386226fb1b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948927741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.948927741
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2916227064
Short name T277
Test name
Test status
Simulation time 313937623 ps
CPU time 3.92 seconds
Started Jun 29 05:27:17 PM PDT 24
Finished Jun 29 05:27:22 PM PDT 24
Peak memory 224932 kb
Host smart-6b15c314-d127-47f8-ade4-395ad68d5eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916227064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2916227064
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3680663006
Short name T372
Test name
Test status
Simulation time 180941121 ps
CPU time 0.8 seconds
Started Jun 29 05:27:10 PM PDT 24
Finished Jun 29 05:27:11 PM PDT 24
Peak memory 207092 kb
Host smart-55997fde-b9f1-4fdc-8fa1-859e950a908b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680663006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3680663006
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3714121520
Short name T1014
Test name
Test status
Simulation time 202179310826 ps
CPU time 365.5 seconds
Started Jun 29 05:27:03 PM PDT 24
Finished Jun 29 05:33:10 PM PDT 24
Peak memory 265696 kb
Host smart-135bdbcd-3114-4c01-939f-a614d2ca821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714121520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3714121520
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.261439795
Short name T756
Test name
Test status
Simulation time 80511630596 ps
CPU time 204.19 seconds
Started Jun 29 05:27:22 PM PDT 24
Finished Jun 29 05:30:47 PM PDT 24
Peak memory 258036 kb
Host smart-5683734b-7ef1-4268-91db-1171f64d2c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261439795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.261439795
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.679078549
Short name T200
Test name
Test status
Simulation time 125064322904 ps
CPU time 450.98 seconds
Started Jun 29 05:27:02 PM PDT 24
Finished Jun 29 05:34:33 PM PDT 24
Peak memory 252456 kb
Host smart-1b3b82e3-b25f-4c6f-8257-2d4441ba48da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679078549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
679078549
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.821753955
Short name T138
Test name
Test status
Simulation time 4002234718 ps
CPU time 14.79 seconds
Started Jun 29 05:27:13 PM PDT 24
Finished Jun 29 05:27:29 PM PDT 24
Peak memory 233296 kb
Host smart-6cf4a33c-7912-4f9f-b1ce-5961675b3ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821753955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.821753955
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1954752924
Short name T867
Test name
Test status
Simulation time 126988759478 ps
CPU time 426.14 seconds
Started Jun 29 05:27:08 PM PDT 24
Finished Jun 29 05:34:15 PM PDT 24
Peak memory 249608 kb
Host smart-cc23f18e-e20c-47f8-966e-c9ca125cfc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954752924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1954752924
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.712127003
Short name T741
Test name
Test status
Simulation time 35179932 ps
CPU time 2.52 seconds
Started Jun 29 05:27:05 PM PDT 24
Finished Jun 29 05:27:09 PM PDT 24
Peak memory 227412 kb
Host smart-28ba7e9a-5b31-4b91-8917-3ccab6beda0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712127003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.712127003
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3806276128
Short name T522
Test name
Test status
Simulation time 6303848106 ps
CPU time 16.06 seconds
Started Jun 29 05:27:03 PM PDT 24
Finished Jun 29 05:27:20 PM PDT 24
Peak memory 233260 kb
Host smart-9feacaf2-16e3-42df-8bc8-692804a5a8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806276128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3806276128
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3451950302
Short name T270
Test name
Test status
Simulation time 1532334281 ps
CPU time 3 seconds
Started Jun 29 05:27:06 PM PDT 24
Finished Jun 29 05:27:11 PM PDT 24
Peak memory 224892 kb
Host smart-41cdd501-927e-49ff-974e-b991a8f5c801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451950302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3451950302
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3145283414
Short name T517
Test name
Test status
Simulation time 23437603280 ps
CPU time 19.78 seconds
Started Jun 29 05:27:12 PM PDT 24
Finished Jun 29 05:27:33 PM PDT 24
Peak memory 233332 kb
Host smart-3a343f6c-3770-4014-8462-d27c2826045f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145283414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3145283414
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.697864224
Short name T40
Test name
Test status
Simulation time 154098423 ps
CPU time 3.8 seconds
Started Jun 29 05:27:01 PM PDT 24
Finished Jun 29 05:27:06 PM PDT 24
Peak memory 223632 kb
Host smart-f58b7411-49a0-4439-aed3-b448282a35e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=697864224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.697864224
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3790460617
Short name T68
Test name
Test status
Simulation time 151887736 ps
CPU time 1.24 seconds
Started Jun 29 05:27:15 PM PDT 24
Finished Jun 29 05:27:16 PM PDT 24
Peak memory 237184 kb
Host smart-d5b7c621-9b1d-4902-a315-72ad76362aeb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790460617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3790460617
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.883478804
Short name T849
Test name
Test status
Simulation time 11131892259 ps
CPU time 63.29 seconds
Started Jun 29 05:26:59 PM PDT 24
Finished Jun 29 05:28:03 PM PDT 24
Peak memory 249836 kb
Host smart-354a9e24-5d04-4035-a8fb-b4a69167b622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883478804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.883478804
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3551172382
Short name T323
Test name
Test status
Simulation time 13334663189 ps
CPU time 30.14 seconds
Started Jun 29 05:27:06 PM PDT 24
Finished Jun 29 05:27:38 PM PDT 24
Peak memory 216952 kb
Host smart-9ad7a3d3-d9ac-4271-9df9-b2518bc8a19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551172382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3551172382
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2506152917
Short name T959
Test name
Test status
Simulation time 107843904 ps
CPU time 0.69 seconds
Started Jun 29 05:27:07 PM PDT 24
Finished Jun 29 05:27:09 PM PDT 24
Peak memory 206084 kb
Host smart-3d0b7aa7-84e6-4df4-b599-a006e2a63e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506152917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2506152917
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3758674754
Short name T737
Test name
Test status
Simulation time 140128533 ps
CPU time 1.11 seconds
Started Jun 29 05:27:17 PM PDT 24
Finished Jun 29 05:27:19 PM PDT 24
Peak memory 208376 kb
Host smart-e532d46c-897d-4a20-9ac7-6cf55ffa3a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758674754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3758674754
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2144963910
Short name T386
Test name
Test status
Simulation time 54592349 ps
CPU time 0.81 seconds
Started Jun 29 05:27:02 PM PDT 24
Finished Jun 29 05:27:04 PM PDT 24
Peak memory 206452 kb
Host smart-0eb4f878-c122-4765-9068-ffc6c64161a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144963910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2144963910
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1603545583
Short name T58
Test name
Test status
Simulation time 529277718 ps
CPU time 8.96 seconds
Started Jun 29 05:27:02 PM PDT 24
Finished Jun 29 05:27:12 PM PDT 24
Peak memory 249596 kb
Host smart-9f981974-8749-4ac3-8f0d-f9dfbab1336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603545583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1603545583
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4279855421
Short name T443
Test name
Test status
Simulation time 45876286 ps
CPU time 0.76 seconds
Started Jun 29 05:27:35 PM PDT 24
Finished Jun 29 05:27:36 PM PDT 24
Peak memory 205376 kb
Host smart-627e2986-f326-4f1c-a59d-e0684fe9ea81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279855421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4279855421
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3107648026
Short name T630
Test name
Test status
Simulation time 112069100 ps
CPU time 4.18 seconds
Started Jun 29 05:27:51 PM PDT 24
Finished Jun 29 05:27:58 PM PDT 24
Peak memory 233152 kb
Host smart-07c1b0f6-9512-48b7-a11b-21d1d5467155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107648026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3107648026
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1486952192
Short name T142
Test name
Test status
Simulation time 46084413 ps
CPU time 0.81 seconds
Started Jun 29 05:27:46 PM PDT 24
Finished Jun 29 05:27:48 PM PDT 24
Peak memory 207380 kb
Host smart-bd31b92c-dbdb-4283-afc9-2ee59026114e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486952192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1486952192
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3632488490
Short name T869
Test name
Test status
Simulation time 62756709605 ps
CPU time 140.51 seconds
Started Jun 29 05:27:39 PM PDT 24
Finished Jun 29 05:30:00 PM PDT 24
Peak memory 255364 kb
Host smart-875afe1e-92db-4e32-a5b4-c6b22372ea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632488490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3632488490
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1029241627
Short name T31
Test name
Test status
Simulation time 16184538958 ps
CPU time 115.47 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:29:45 PM PDT 24
Peak memory 253164 kb
Host smart-84276dbd-6a3e-4fe3-9777-888f64a698d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029241627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1029241627
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.942265985
Short name T315
Test name
Test status
Simulation time 90832952250 ps
CPU time 138.9 seconds
Started Jun 29 05:27:50 PM PDT 24
Finished Jun 29 05:30:12 PM PDT 24
Peak memory 250064 kb
Host smart-2ab85222-dc9c-4985-8d16-6ee536628010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942265985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.942265985
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.416779810
Short name T285
Test name
Test status
Simulation time 15652367616 ps
CPU time 161.19 seconds
Started Jun 29 05:27:42 PM PDT 24
Finished Jun 29 05:30:24 PM PDT 24
Peak memory 249676 kb
Host smart-592072b2-1b9a-4e9e-a518-e650385db417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416779810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.416779810
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3102042435
Short name T569
Test name
Test status
Simulation time 1318554922 ps
CPU time 7.53 seconds
Started Jun 29 05:27:39 PM PDT 24
Finished Jun 29 05:27:47 PM PDT 24
Peak memory 233064 kb
Host smart-1f001b36-a916-47eb-9757-44c2d7495176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102042435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3102042435
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2398343564
Short name T932
Test name
Test status
Simulation time 66221042223 ps
CPU time 126.42 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:29:59 PM PDT 24
Peak memory 250776 kb
Host smart-389c3e9b-2256-4a62-8412-292f1474c6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398343564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2398343564
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2233196731
Short name T268
Test name
Test status
Simulation time 3753608429 ps
CPU time 12.96 seconds
Started Jun 29 05:27:44 PM PDT 24
Finished Jun 29 05:27:57 PM PDT 24
Peak memory 233328 kb
Host smart-893dcbc7-9890-435a-bcf5-bff40371ff32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233196731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2233196731
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2272640539
Short name T649
Test name
Test status
Simulation time 1782937550 ps
CPU time 5.83 seconds
Started Jun 29 05:27:44 PM PDT 24
Finished Jun 29 05:27:50 PM PDT 24
Peak memory 233228 kb
Host smart-5da8fbd1-c52c-460a-aa85-a011383200a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272640539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2272640539
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1454045406
Short name T157
Test name
Test status
Simulation time 17619109888 ps
CPU time 13.71 seconds
Started Jun 29 05:27:45 PM PDT 24
Finished Jun 29 05:27:59 PM PDT 24
Peak memory 222240 kb
Host smart-ecb699aa-6f48-419a-be38-3ce3795b011e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1454045406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1454045406
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.416983832
Short name T580
Test name
Test status
Simulation time 59848458 ps
CPU time 0.96 seconds
Started Jun 29 05:27:46 PM PDT 24
Finished Jun 29 05:27:47 PM PDT 24
Peak memory 207252 kb
Host smart-88e6f4ef-5ce1-4504-8641-ff4932c3c9ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416983832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.416983832
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3475345058
Short name T673
Test name
Test status
Simulation time 2176558690 ps
CPU time 21.71 seconds
Started Jun 29 05:27:51 PM PDT 24
Finished Jun 29 05:28:15 PM PDT 24
Peak memory 216816 kb
Host smart-1c687c57-14b1-440d-9e94-4b34378ccf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475345058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3475345058
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2826630035
Short name T524
Test name
Test status
Simulation time 976180607 ps
CPU time 7.24 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:27:56 PM PDT 24
Peak memory 216760 kb
Host smart-8c94a125-ca01-459d-9c9c-dfc02f58b1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826630035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2826630035
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.152063300
Short name T835
Test name
Test status
Simulation time 122421328 ps
CPU time 1.41 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:27:54 PM PDT 24
Peak memory 216784 kb
Host smart-9d36c11e-89c0-414a-8a65-28b3d34ac189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152063300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.152063300
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1944470885
Short name T410
Test name
Test status
Simulation time 131161978 ps
CPU time 0.96 seconds
Started Jun 29 05:27:42 PM PDT 24
Finished Jun 29 05:27:44 PM PDT 24
Peak memory 207476 kb
Host smart-cce06770-6d60-4e62-8eb3-0cf7001d4bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944470885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1944470885
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1830005174
Short name T400
Test name
Test status
Simulation time 5107415752 ps
CPU time 23.37 seconds
Started Jun 29 05:27:36 PM PDT 24
Finished Jun 29 05:27:59 PM PDT 24
Peak memory 249688 kb
Host smart-cd865f26-2a40-48c6-95e3-bea13e69b90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830005174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1830005174
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.394731693
Short name T872
Test name
Test status
Simulation time 13083526 ps
CPU time 0.76 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:27:49 PM PDT 24
Peak memory 205956 kb
Host smart-abdc0073-ea22-4d86-a0d6-93b2bb7f5c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394731693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.394731693
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3451707127
Short name T621
Test name
Test status
Simulation time 31995759 ps
CPU time 2.53 seconds
Started Jun 29 05:27:46 PM PDT 24
Finished Jun 29 05:27:50 PM PDT 24
Peak memory 232948 kb
Host smart-c7365260-51bb-4642-89ba-cbdfdde40c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451707127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3451707127
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.230931036
Short name T954
Test name
Test status
Simulation time 14884991 ps
CPU time 0.81 seconds
Started Jun 29 05:27:40 PM PDT 24
Finished Jun 29 05:27:41 PM PDT 24
Peak memory 207080 kb
Host smart-ec2fd016-fb1a-4e66-aad5-2a550ba4b209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230931036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.230931036
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.572727314
Short name T717
Test name
Test status
Simulation time 10061889962 ps
CPU time 60.37 seconds
Started Jun 29 05:27:45 PM PDT 24
Finished Jun 29 05:28:46 PM PDT 24
Peak memory 238768 kb
Host smart-634c8538-45e3-4da4-8cce-e6d5ecaaa667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572727314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.572727314
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2004751830
Short name T773
Test name
Test status
Simulation time 1851118572 ps
CPU time 26.81 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:28:18 PM PDT 24
Peak memory 249580 kb
Host smart-94c660a1-ee95-41bd-95df-22d2f48a6eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004751830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2004751830
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3775118978
Short name T660
Test name
Test status
Simulation time 3020981775 ps
CPU time 50.94 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:28:40 PM PDT 24
Peak memory 251052 kb
Host smart-43aca540-ba36-402e-a1a4-33fb6b8f195a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775118978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3775118978
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.444026651
Short name T767
Test name
Test status
Simulation time 1935081173 ps
CPU time 6.57 seconds
Started Jun 29 05:27:50 PM PDT 24
Finished Jun 29 05:28:00 PM PDT 24
Peak memory 233116 kb
Host smart-689145f0-c9c9-4cbc-a861-ff8f8cdd4dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444026651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.444026651
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.892724062
Short name T680
Test name
Test status
Simulation time 15049972920 ps
CPU time 46.95 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:28:35 PM PDT 24
Peak memory 233296 kb
Host smart-c5eaa2a7-e94c-4fae-9e9b-cf9a37994708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892724062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.892724062
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1847399216
Short name T902
Test name
Test status
Simulation time 35510615093 ps
CPU time 28.65 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:28:20 PM PDT 24
Peak memory 249644 kb
Host smart-3e0b97d9-a569-40c9-9db9-0add32490c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847399216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1847399216
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.4250531585
Short name T851
Test name
Test status
Simulation time 2138187919 ps
CPU time 6.17 seconds
Started Jun 29 05:27:52 PM PDT 24
Finished Jun 29 05:28:01 PM PDT 24
Peak memory 224988 kb
Host smart-418f02d6-5e12-4dc9-85cc-d3eb12dcfada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250531585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.4250531585
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3222595829
Short name T379
Test name
Test status
Simulation time 2877274349 ps
CPU time 7.64 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:27:58 PM PDT 24
Peak memory 220052 kb
Host smart-5760404d-b663-4af6-92cf-3c42922dd373
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3222595829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3222595829
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.856507672
Short name T757
Test name
Test status
Simulation time 23965532231 ps
CPU time 76.64 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:29:05 PM PDT 24
Peak memory 225176 kb
Host smart-56d337dd-a91f-4024-9f5f-678cb9b24eed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856507672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.856507672
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3760423107
Short name T322
Test name
Test status
Simulation time 1956213274 ps
CPU time 5.9 seconds
Started Jun 29 05:27:31 PM PDT 24
Finished Jun 29 05:27:39 PM PDT 24
Peak memory 216696 kb
Host smart-94cefd46-d30d-43dd-b52e-20e640103f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760423107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3760423107
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.781529319
Short name T387
Test name
Test status
Simulation time 2352713895 ps
CPU time 4.89 seconds
Started Jun 29 05:27:42 PM PDT 24
Finished Jun 29 05:27:47 PM PDT 24
Peak memory 216948 kb
Host smart-a2c29d15-4f05-400e-9b91-c5492ed1b6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781529319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.781529319
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3835866405
Short name T879
Test name
Test status
Simulation time 23318683 ps
CPU time 1.01 seconds
Started Jun 29 05:27:39 PM PDT 24
Finished Jun 29 05:27:41 PM PDT 24
Peak memory 207872 kb
Host smart-6379208a-e177-4656-995f-e66c5e7d4039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835866405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3835866405
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3001728795
Short name T675
Test name
Test status
Simulation time 84634839 ps
CPU time 0.94 seconds
Started Jun 29 05:27:54 PM PDT 24
Finished Jun 29 05:27:56 PM PDT 24
Peak memory 206932 kb
Host smart-f94ca4f6-d2a1-418a-981e-7ad1d6e1d03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001728795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3001728795
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3344441081
Short name T235
Test name
Test status
Simulation time 148265716 ps
CPU time 2.31 seconds
Started Jun 29 05:27:40 PM PDT 24
Finished Jun 29 05:27:43 PM PDT 24
Peak memory 225012 kb
Host smart-1128b775-e499-4cb6-b02e-97aa600cf9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344441081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3344441081
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.666052062
Short name T988
Test name
Test status
Simulation time 107867508 ps
CPU time 2.1 seconds
Started Jun 29 05:27:45 PM PDT 24
Finished Jun 29 05:27:47 PM PDT 24
Peak memory 224864 kb
Host smart-77d3e4e7-0f64-4f92-9c03-e24d2be368a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666052062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.666052062
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2335577462
Short name T832
Test name
Test status
Simulation time 15910342 ps
CPU time 0.77 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:27:53 PM PDT 24
Peak memory 207424 kb
Host smart-658efa03-1d66-4584-bddc-43db3ec518bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335577462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2335577462
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2983135717
Short name T449
Test name
Test status
Simulation time 8942331909 ps
CPU time 38.62 seconds
Started Jun 29 05:27:50 PM PDT 24
Finished Jun 29 05:28:32 PM PDT 24
Peak memory 250132 kb
Host smart-dfa4efdf-e776-438c-a5e9-65d577a4e416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983135717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2983135717
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3362419086
Short name T799
Test name
Test status
Simulation time 3239208060 ps
CPU time 72.55 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:29:04 PM PDT 24
Peak memory 249808 kb
Host smart-210a8094-1a04-4e44-9cae-005388f758c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362419086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3362419086
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3096312037
Short name T242
Test name
Test status
Simulation time 37870272431 ps
CPU time 94.82 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:29:25 PM PDT 24
Peak memory 252192 kb
Host smart-73bcff36-d5b0-4e9f-9952-d94f012b654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096312037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3096312037
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1462673890
Short name T935
Test name
Test status
Simulation time 475614178 ps
CPU time 12.47 seconds
Started Jun 29 05:27:42 PM PDT 24
Finished Jun 29 05:27:55 PM PDT 24
Peak memory 249560 kb
Host smart-7ae391d5-6cff-4acc-9014-1a1f67529554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462673890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1462673890
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2681080204
Short name T701
Test name
Test status
Simulation time 1929219481 ps
CPU time 20.93 seconds
Started Jun 29 05:27:50 PM PDT 24
Finished Jun 29 05:28:14 PM PDT 24
Peak memory 236628 kb
Host smart-1575e04f-5d0c-4c4a-8ab1-be3c570cb686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681080204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2681080204
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3610490516
Short name T482
Test name
Test status
Simulation time 1623505325 ps
CPU time 5.07 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:27:56 PM PDT 24
Peak memory 233212 kb
Host smart-e2bfda12-aadf-443f-b2d9-a802eba6608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610490516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3610490516
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.259600154
Short name T472
Test name
Test status
Simulation time 301636333 ps
CPU time 7.25 seconds
Started Jun 29 05:27:46 PM PDT 24
Finished Jun 29 05:27:54 PM PDT 24
Peak memory 233156 kb
Host smart-12d8f243-ad54-439c-bf17-dd6b1b0e2bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259600154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.259600154
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.78656146
Short name T1001
Test name
Test status
Simulation time 1000822241 ps
CPU time 4.44 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:27:56 PM PDT 24
Peak memory 233216 kb
Host smart-1b763942-5c6a-441c-906a-78d9d3a5febb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78656146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.78656146
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3113926578
Short name T642
Test name
Test status
Simulation time 1479415409 ps
CPU time 8.17 seconds
Started Jun 29 05:27:46 PM PDT 24
Finished Jun 29 05:27:55 PM PDT 24
Peak memory 233224 kb
Host smart-b3a74dc5-69d4-4c6d-9a7c-83cb239f3542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113926578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3113926578
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4013061831
Short name T644
Test name
Test status
Simulation time 1326186293 ps
CPU time 7.37 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:27:57 PM PDT 24
Peak memory 220784 kb
Host smart-41b639d3-f325-44de-802c-b3eef7530e88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4013061831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4013061831
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.106528690
Short name T15
Test name
Test status
Simulation time 122457229772 ps
CPU time 281.47 seconds
Started Jun 29 05:27:52 PM PDT 24
Finished Jun 29 05:32:36 PM PDT 24
Peak memory 270856 kb
Host smart-ba8498f1-ab3e-4c40-a23a-80ed1ce8b786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106528690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.106528690
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3696049518
Short name T731
Test name
Test status
Simulation time 7696929842 ps
CPU time 43.76 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:28:33 PM PDT 24
Peak memory 216948 kb
Host smart-7aa83669-70af-4d07-94bc-670d4c677118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696049518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3696049518
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1853864220
Short name T577
Test name
Test status
Simulation time 1602979238 ps
CPU time 9.34 seconds
Started Jun 29 05:27:45 PM PDT 24
Finished Jun 29 05:27:54 PM PDT 24
Peak memory 216820 kb
Host smart-fa17057c-5563-42d6-9e07-59ad56500e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853864220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1853864220
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1667525491
Short name T350
Test name
Test status
Simulation time 78168527 ps
CPU time 0.9 seconds
Started Jun 29 05:27:45 PM PDT 24
Finished Jun 29 05:27:47 PM PDT 24
Peak memory 207068 kb
Host smart-0bb610ed-9df9-45c8-a5da-4b746bf49015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667525491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1667525491
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2419257601
Short name T11
Test name
Test status
Simulation time 43848961 ps
CPU time 0.79 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:27:51 PM PDT 24
Peak memory 206456 kb
Host smart-d7ee5435-dad4-4acd-a13d-f66f7ff14776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419257601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2419257601
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3072537063
Short name T639
Test name
Test status
Simulation time 14373383423 ps
CPU time 13.39 seconds
Started Jun 29 05:27:44 PM PDT 24
Finished Jun 29 05:27:58 PM PDT 24
Peak memory 233300 kb
Host smart-0671b0d3-38c9-4ca8-96d9-2ac2b2d33eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072537063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3072537063
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3197501545
Short name T720
Test name
Test status
Simulation time 12058122 ps
CPU time 0.74 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:27:50 PM PDT 24
Peak memory 205976 kb
Host smart-d0dfac34-16b5-41ee-aedc-26dadf57ac02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197501545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3197501545
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.282013927
Short name T402
Test name
Test status
Simulation time 423781085 ps
CPU time 2.44 seconds
Started Jun 29 05:27:51 PM PDT 24
Finished Jun 29 05:27:57 PM PDT 24
Peak memory 224964 kb
Host smart-bfb5954b-ed17-42ee-9c7d-98cc332409b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282013927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.282013927
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2930417013
Short name T805
Test name
Test status
Simulation time 32059407 ps
CPU time 0.77 seconds
Started Jun 29 05:27:44 PM PDT 24
Finished Jun 29 05:27:45 PM PDT 24
Peak memory 207096 kb
Host smart-f0f4bcae-ed9a-4c94-b4ed-c09cdbb6766b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930417013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2930417013
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.870363035
Short name T784
Test name
Test status
Simulation time 848832124 ps
CPU time 11.19 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:28:02 PM PDT 24
Peak memory 234748 kb
Host smart-f35a9234-f330-4dff-974c-153ee7e162fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870363035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.870363035
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.464739457
Short name T318
Test name
Test status
Simulation time 1275418626 ps
CPU time 18.32 seconds
Started Jun 29 05:27:50 PM PDT 24
Finished Jun 29 05:28:12 PM PDT 24
Peak memory 233256 kb
Host smart-6862225b-fb58-4ada-8300-773f127a1b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464739457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.464739457
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1569031682
Short name T997
Test name
Test status
Simulation time 19231442575 ps
CPU time 78.8 seconds
Started Jun 29 05:27:44 PM PDT 24
Finished Jun 29 05:29:03 PM PDT 24
Peak memory 249668 kb
Host smart-7ca8cd1b-09d8-4d0d-82d8-d006d2cca330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569031682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1569031682
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1813975455
Short name T667
Test name
Test status
Simulation time 246978597 ps
CPU time 4.91 seconds
Started Jun 29 05:27:51 PM PDT 24
Finished Jun 29 05:27:59 PM PDT 24
Peak memory 233108 kb
Host smart-5d8d713f-3829-4c3a-9eb4-1f792ed1c640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813975455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1813975455
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2377493371
Short name T591
Test name
Test status
Simulation time 4278067462 ps
CPU time 9.56 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:28:00 PM PDT 24
Peak memory 236652 kb
Host smart-897b1dc3-e5ae-44a3-82e8-7ebd4a791c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377493371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2377493371
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1254782560
Short name T230
Test name
Test status
Simulation time 82829555 ps
CPU time 2.3 seconds
Started Jun 29 05:28:01 PM PDT 24
Finished Jun 29 05:28:04 PM PDT 24
Peak memory 224852 kb
Host smart-a489d308-a1ee-4dbb-882d-5b13fcd2c0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254782560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1254782560
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3530363071
Short name T77
Test name
Test status
Simulation time 2860346305 ps
CPU time 4.6 seconds
Started Jun 29 05:27:43 PM PDT 24
Finished Jun 29 05:27:49 PM PDT 24
Peak memory 233276 kb
Host smart-e68c9c0c-4ebd-4920-894d-dcf180cd09ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530363071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3530363071
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3709637365
Short name T383
Test name
Test status
Simulation time 893714723 ps
CPU time 7.4 seconds
Started Jun 29 05:27:50 PM PDT 24
Finished Jun 29 05:28:00 PM PDT 24
Peak memory 219264 kb
Host smart-4cb1c023-d52d-4201-a3b8-efc53b59eb75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3709637365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3709637365
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3873408799
Short name T319
Test name
Test status
Simulation time 57167610485 ps
CPU time 31.03 seconds
Started Jun 29 05:27:44 PM PDT 24
Finished Jun 29 05:28:16 PM PDT 24
Peak memory 216828 kb
Host smart-0ea17f2d-9baf-421a-abb3-5ed1898e82bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873408799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3873408799
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2575747196
Short name T554
Test name
Test status
Simulation time 133161447 ps
CPU time 2.73 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:27:54 PM PDT 24
Peak memory 216752 kb
Host smart-123e348e-828b-4fbc-9f88-1e9807db66f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575747196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2575747196
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3796757298
Short name T381
Test name
Test status
Simulation time 15389696 ps
CPU time 0.76 seconds
Started Jun 29 05:27:46 PM PDT 24
Finished Jun 29 05:27:48 PM PDT 24
Peak memory 206456 kb
Host smart-0ad1a4f6-c2cf-4ff8-83e5-1cdab43e5381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796757298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3796757298
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.530293854
Short name T693
Test name
Test status
Simulation time 124704535 ps
CPU time 3.74 seconds
Started Jun 29 05:27:50 PM PDT 24
Finished Jun 29 05:27:57 PM PDT 24
Peak memory 233152 kb
Host smart-25d13ca8-f2ac-410d-9f36-39ef5ccddae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530293854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.530293854
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2329332448
Short name T445
Test name
Test status
Simulation time 13261246 ps
CPU time 0.8 seconds
Started Jun 29 05:27:53 PM PDT 24
Finished Jun 29 05:27:56 PM PDT 24
Peak memory 205980 kb
Host smart-5bf91ba1-14c9-4e3a-a058-b620fc758914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329332448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2329332448
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.799957577
Short name T434
Test name
Test status
Simulation time 42649167 ps
CPU time 2.58 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:27:52 PM PDT 24
Peak memory 233232 kb
Host smart-dbbe427d-237b-42da-801a-ddb82e8929a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799957577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.799957577
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.762894982
Short name T476
Test name
Test status
Simulation time 47939464 ps
CPU time 0.76 seconds
Started Jun 29 05:27:43 PM PDT 24
Finished Jun 29 05:27:44 PM PDT 24
Peak memory 207424 kb
Host smart-6da57a63-f663-4b55-8ca4-56b1597696a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762894982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.762894982
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.4136342501
Short name T204
Test name
Test status
Simulation time 68963002189 ps
CPU time 140.46 seconds
Started Jun 29 05:28:01 PM PDT 24
Finished Jun 29 05:30:22 PM PDT 24
Peak memory 262616 kb
Host smart-70ff91fc-1df3-47f7-8447-e45a34005855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136342501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4136342501
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2074512685
Short name T810
Test name
Test status
Simulation time 13415998352 ps
CPU time 26.14 seconds
Started Jun 29 05:27:50 PM PDT 24
Finished Jun 29 05:28:19 PM PDT 24
Peak memory 225252 kb
Host smart-fd368e3d-4e18-427e-80a8-274f1bda1356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074512685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2074512685
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.298119206
Short name T56
Test name
Test status
Simulation time 38069886737 ps
CPU time 354.57 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:33:46 PM PDT 24
Peak memory 253816 kb
Host smart-510f264d-ca38-4ebf-b020-5d437ea1b55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298119206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.298119206
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1470561570
Short name T542
Test name
Test status
Simulation time 27766413714 ps
CPU time 48.89 seconds
Started Jun 29 05:27:50 PM PDT 24
Finished Jun 29 05:28:42 PM PDT 24
Peak memory 250268 kb
Host smart-a8e55f90-12cb-4638-99bd-7a073d4b369c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470561570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1470561570
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4212083087
Short name T489
Test name
Test status
Simulation time 501860564 ps
CPU time 6.71 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:27:57 PM PDT 24
Peak memory 233116 kb
Host smart-066d2cc7-0516-4cd5-858e-b461c58acc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212083087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4212083087
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3796931746
Short name T441
Test name
Test status
Simulation time 3721281354 ps
CPU time 32.4 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:28:22 PM PDT 24
Peak memory 250784 kb
Host smart-953737e5-05e5-4534-a419-114a7529a82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796931746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3796931746
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1866021853
Short name T896
Test name
Test status
Simulation time 10272100387 ps
CPU time 14.89 seconds
Started Jun 29 05:27:53 PM PDT 24
Finished Jun 29 05:28:10 PM PDT 24
Peak memory 225092 kb
Host smart-f78b2215-f315-41e5-83e2-43a87ff88b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866021853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1866021853
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1987089290
Short name T848
Test name
Test status
Simulation time 1493696556 ps
CPU time 12.36 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:28:02 PM PDT 24
Peak memory 219212 kb
Host smart-0c38958a-aadd-4cb1-a4a5-926a14acdd73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1987089290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1987089290
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3682520508
Short name T895
Test name
Test status
Simulation time 18572294113 ps
CPU time 23.13 seconds
Started Jun 29 05:27:58 PM PDT 24
Finished Jun 29 05:28:22 PM PDT 24
Peak memory 241568 kb
Host smart-4787c0bd-4045-4325-953d-2bfd88da3c11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682520508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3682520508
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1680454299
Short name T321
Test name
Test status
Simulation time 4685416672 ps
CPU time 24.01 seconds
Started Jun 29 05:27:46 PM PDT 24
Finished Jun 29 05:28:11 PM PDT 24
Peak memory 217100 kb
Host smart-e5721410-cd3b-4465-b82c-d83f2a93aea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680454299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1680454299
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.4154196179
Short name T883
Test name
Test status
Simulation time 13188783 ps
CPU time 0.73 seconds
Started Jun 29 05:27:40 PM PDT 24
Finished Jun 29 05:27:41 PM PDT 24
Peak memory 206196 kb
Host smart-711c1041-c79a-444b-b019-e8f079e9c770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154196179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.4154196179
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3343192597
Short name T640
Test name
Test status
Simulation time 963831282 ps
CPU time 3.19 seconds
Started Jun 29 05:27:53 PM PDT 24
Finished Jun 29 05:27:58 PM PDT 24
Peak memory 216732 kb
Host smart-f8df83ee-ef72-4ffc-ae33-b66c26d0d224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343192597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3343192597
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.58497096
Short name T474
Test name
Test status
Simulation time 23857589 ps
CPU time 0.75 seconds
Started Jun 29 05:27:46 PM PDT 24
Finished Jun 29 05:27:49 PM PDT 24
Peak memory 206056 kb
Host smart-fddbfba9-7b0c-413f-b0d5-21fca4a527f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58497096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.58497096
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.746295827
Short name T938
Test name
Test status
Simulation time 457685956 ps
CPU time 2.1 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:27:52 PM PDT 24
Peak memory 224800 kb
Host smart-1140e119-b25c-4784-b381-01a86ed85ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746295827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.746295827
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.4088186419
Short name T967
Test name
Test status
Simulation time 39921097 ps
CPU time 0.7 seconds
Started Jun 29 05:28:15 PM PDT 24
Finished Jun 29 05:28:17 PM PDT 24
Peak memory 205400 kb
Host smart-2b2013c3-fe03-4579-853e-ad8ab0b3098b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088186419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
4088186419
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2167142385
Short name T803
Test name
Test status
Simulation time 1712992818 ps
CPU time 7.99 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:27:59 PM PDT 24
Peak memory 224956 kb
Host smart-c3fb63f5-4006-4dfe-a875-4f54e919d6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167142385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2167142385
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1064549464
Short name T1009
Test name
Test status
Simulation time 51720182 ps
CPU time 0.79 seconds
Started Jun 29 05:27:53 PM PDT 24
Finished Jun 29 05:27:56 PM PDT 24
Peak memory 207096 kb
Host smart-cdd65719-6b28-4878-a60d-bbf0e88585af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064549464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1064549464
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2357979341
Short name T493
Test name
Test status
Simulation time 11115089831 ps
CPU time 78.13 seconds
Started Jun 29 05:28:03 PM PDT 24
Finished Jun 29 05:29:22 PM PDT 24
Peak memory 249668 kb
Host smart-027d33bf-96a9-4d18-a2f1-b2466ec81b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357979341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2357979341
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3714435852
Short name T300
Test name
Test status
Simulation time 2516105270 ps
CPU time 41.2 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:28:33 PM PDT 24
Peak memory 234444 kb
Host smart-8ff7c545-8f94-481c-a240-075246b6db4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714435852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3714435852
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1759686542
Short name T827
Test name
Test status
Simulation time 19536044673 ps
CPU time 142.26 seconds
Started Jun 29 05:28:14 PM PDT 24
Finished Jun 29 05:30:38 PM PDT 24
Peak memory 256728 kb
Host smart-0dba7c01-3aef-4feb-a3fb-4f73728a7b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759686542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1759686542
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2611754179
Short name T765
Test name
Test status
Simulation time 2569982550 ps
CPU time 15.9 seconds
Started Jun 29 05:27:56 PM PDT 24
Finished Jun 29 05:28:12 PM PDT 24
Peak memory 233336 kb
Host smart-c187eb0a-107c-4214-841e-a88c33336cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611754179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2611754179
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1125953674
Short name T950
Test name
Test status
Simulation time 1164212115939 ps
CPU time 502.38 seconds
Started Jun 29 05:27:53 PM PDT 24
Finished Jun 29 05:36:17 PM PDT 24
Peak memory 267388 kb
Host smart-77f7f177-053b-4bdb-9221-be7f2554be7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125953674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1125953674
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2851658531
Short name T910
Test name
Test status
Simulation time 591580364 ps
CPU time 3.7 seconds
Started Jun 29 05:27:57 PM PDT 24
Finished Jun 29 05:28:01 PM PDT 24
Peak memory 233164 kb
Host smart-57e85329-89cd-4bc1-b6bc-5bea58c1b9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851658531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2851658531
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2065364765
Short name T930
Test name
Test status
Simulation time 7647098074 ps
CPU time 63.74 seconds
Started Jun 29 05:27:58 PM PDT 24
Finished Jun 29 05:29:02 PM PDT 24
Peak memory 250920 kb
Host smart-7324e502-f9f3-4783-87a7-e1907d1785c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065364765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2065364765
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2618337301
Short name T676
Test name
Test status
Simulation time 2984513881 ps
CPU time 3.88 seconds
Started Jun 29 05:27:50 PM PDT 24
Finished Jun 29 05:27:57 PM PDT 24
Peak memory 225056 kb
Host smart-9fae47da-ddfb-4e9f-a0bf-85a742a6c967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618337301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2618337301
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2852425889
Short name T454
Test name
Test status
Simulation time 34904213246 ps
CPU time 11.44 seconds
Started Jun 29 05:27:57 PM PDT 24
Finished Jun 29 05:28:09 PM PDT 24
Peak memory 240748 kb
Host smart-9e7267fd-2de1-41e3-8589-b0e8ea762586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852425889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2852425889
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3811881824
Short name T839
Test name
Test status
Simulation time 182686305 ps
CPU time 4.31 seconds
Started Jun 29 05:28:00 PM PDT 24
Finished Jun 29 05:28:05 PM PDT 24
Peak memory 223528 kb
Host smart-4793fd49-d627-4941-8103-a113927bcd62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3811881824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3811881824
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.208152458
Short name T169
Test name
Test status
Simulation time 29054874192 ps
CPU time 352.82 seconds
Started Jun 29 05:27:55 PM PDT 24
Finished Jun 29 05:33:49 PM PDT 24
Peak memory 267316 kb
Host smart-a0d80862-92c1-4d9c-8938-65b42d2192ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208152458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.208152458
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2951584087
Short name T881
Test name
Test status
Simulation time 865074860 ps
CPU time 9.48 seconds
Started Jun 29 05:28:01 PM PDT 24
Finished Jun 29 05:28:11 PM PDT 24
Peak memory 217156 kb
Host smart-f00b5493-bf6c-4750-81fc-b5a60f8b8f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951584087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2951584087
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3822809847
Short name T962
Test name
Test status
Simulation time 2115228995 ps
CPU time 6.03 seconds
Started Jun 29 05:28:10 PM PDT 24
Finished Jun 29 05:28:17 PM PDT 24
Peak memory 216776 kb
Host smart-bd264841-f737-4b20-966e-4afa2c00cd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822809847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3822809847
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.228762392
Short name T1008
Test name
Test status
Simulation time 31694598 ps
CPU time 1.9 seconds
Started Jun 29 05:28:00 PM PDT 24
Finished Jun 29 05:28:02 PM PDT 24
Peak memory 216828 kb
Host smart-89f76f99-0c6f-4e8f-a566-49b2c8be005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228762392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.228762392
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3143913796
Short name T551
Test name
Test status
Simulation time 98448884 ps
CPU time 0.99 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:27:53 PM PDT 24
Peak memory 206868 kb
Host smart-a9e5840c-7222-4623-9edf-1939c9a93992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143913796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3143913796
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2009586182
Short name T413
Test name
Test status
Simulation time 23491446 ps
CPU time 0.78 seconds
Started Jun 29 05:27:50 PM PDT 24
Finished Jun 29 05:27:54 PM PDT 24
Peak memory 205956 kb
Host smart-a30e3bea-ed73-4ecb-8bd5-f9ae760a8a91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009586182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2009586182
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3198442793
Short name T420
Test name
Test status
Simulation time 717402597 ps
CPU time 5.89 seconds
Started Jun 29 05:28:05 PM PDT 24
Finished Jun 29 05:28:12 PM PDT 24
Peak memory 224968 kb
Host smart-664c9673-3e4e-4000-8b13-e585231e59dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198442793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3198442793
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1316772202
Short name T375
Test name
Test status
Simulation time 52733365 ps
CPU time 0.76 seconds
Started Jun 29 05:27:51 PM PDT 24
Finished Jun 29 05:27:55 PM PDT 24
Peak memory 206064 kb
Host smart-10ad543f-1c70-47d7-a27e-82903a67775a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316772202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1316772202
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.727372759
Short name T457
Test name
Test status
Simulation time 12320802273 ps
CPU time 73.39 seconds
Started Jun 29 05:27:51 PM PDT 24
Finished Jun 29 05:29:07 PM PDT 24
Peak memory 249732 kb
Host smart-57ea50c9-c5fb-4997-a961-8fa8e86bc299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727372759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.727372759
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3218776452
Short name T229
Test name
Test status
Simulation time 47673227543 ps
CPU time 123.52 seconds
Started Jun 29 05:27:59 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 256904 kb
Host smart-694a6beb-7f1e-430a-8966-5b31cd215274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218776452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3218776452
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.753527371
Short name T914
Test name
Test status
Simulation time 9763794598 ps
CPU time 12.71 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:28:05 PM PDT 24
Peak memory 233352 kb
Host smart-140fe94d-6aef-4efd-9962-8b5c0a891036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753527371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.753527371
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.924191015
Short name T983
Test name
Test status
Simulation time 387092916768 ps
CPU time 181.78 seconds
Started Jun 29 05:27:59 PM PDT 24
Finished Jun 29 05:31:02 PM PDT 24
Peak memory 253668 kb
Host smart-13706890-c103-44fa-a13a-94a968033e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924191015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.924191015
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1552097099
Short name T93
Test name
Test status
Simulation time 11410501383 ps
CPU time 15.83 seconds
Started Jun 29 05:27:53 PM PDT 24
Finished Jun 29 05:28:11 PM PDT 24
Peak memory 233360 kb
Host smart-f10d9101-3e12-4a3e-8439-7b768bced074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552097099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1552097099
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.754087933
Short name T218
Test name
Test status
Simulation time 404003724 ps
CPU time 4.49 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:27:55 PM PDT 24
Peak memory 234192 kb
Host smart-c9669fdb-a024-448d-a53c-004a05113174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754087933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.754087933
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1575220612
Short name T233
Test name
Test status
Simulation time 4617803074 ps
CPU time 14.33 seconds
Started Jun 29 05:27:50 PM PDT 24
Finished Jun 29 05:28:08 PM PDT 24
Peak memory 233224 kb
Host smart-45eafc2b-9606-4e9f-8683-92cd597924d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575220612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1575220612
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3173510813
Short name T999
Test name
Test status
Simulation time 874629986 ps
CPU time 2.95 seconds
Started Jun 29 05:27:53 PM PDT 24
Finished Jun 29 05:27:58 PM PDT 24
Peak memory 233148 kb
Host smart-e122dcc9-e1bd-4ff0-beea-b03d434eb514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173510813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3173510813
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2341699504
Short name T733
Test name
Test status
Simulation time 937031362 ps
CPU time 7.94 seconds
Started Jun 29 05:27:58 PM PDT 24
Finished Jun 29 05:28:07 PM PDT 24
Peak memory 223664 kb
Host smart-9a7095ea-5a81-45be-a5c8-014e86040d25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2341699504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2341699504
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4091102917
Short name T32
Test name
Test status
Simulation time 153991049793 ps
CPU time 766.69 seconds
Started Jun 29 05:27:51 PM PDT 24
Finished Jun 29 05:40:40 PM PDT 24
Peak memory 282648 kb
Host smart-4be41c6d-8833-4c5b-842a-f44c1d64ffbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091102917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4091102917
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2461872060
Short name T652
Test name
Test status
Simulation time 531733968 ps
CPU time 3.51 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:27:56 PM PDT 24
Peak memory 216664 kb
Host smart-027c4f47-34e9-4791-9893-3f3ee53de79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461872060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2461872060
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2856139629
Short name T670
Test name
Test status
Simulation time 347866472 ps
CPU time 1.27 seconds
Started Jun 29 05:27:58 PM PDT 24
Finished Jun 29 05:28:00 PM PDT 24
Peak memory 208384 kb
Host smart-b17ad1d3-f01d-4dfa-9bd1-0cb8052d913a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856139629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2856139629
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2707726976
Short name T777
Test name
Test status
Simulation time 86536982 ps
CPU time 0.94 seconds
Started Jun 29 05:27:57 PM PDT 24
Finished Jun 29 05:27:59 PM PDT 24
Peak memory 207544 kb
Host smart-3005a2f0-b347-4d6d-96ab-c31088345ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707726976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2707726976
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1206769603
Short name T941
Test name
Test status
Simulation time 11831635 ps
CPU time 0.72 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:27:53 PM PDT 24
Peak memory 206108 kb
Host smart-69e71461-d87b-4ada-aefc-d6915f0a3fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206769603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1206769603
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3453771966
Short name T550
Test name
Test status
Simulation time 1915949202 ps
CPU time 3.16 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:27:56 PM PDT 24
Peak memory 224860 kb
Host smart-9a481c78-61c5-499b-9fec-1a11d30c86b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453771966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3453771966
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1813343643
Short name T488
Test name
Test status
Simulation time 65563742 ps
CPU time 0.7 seconds
Started Jun 29 05:28:05 PM PDT 24
Finished Jun 29 05:28:07 PM PDT 24
Peak memory 205400 kb
Host smart-8d8ca1b5-9a5f-4268-bfe4-7035af7ba695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813343643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1813343643
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3688754958
Short name T1004
Test name
Test status
Simulation time 2300041804 ps
CPU time 16.05 seconds
Started Jun 29 05:27:53 PM PDT 24
Finished Jun 29 05:28:11 PM PDT 24
Peak memory 225092 kb
Host smart-3a7391c4-7c7a-42ed-b156-60c99d3349cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688754958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3688754958
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1321420969
Short name T391
Test name
Test status
Simulation time 104023855 ps
CPU time 0.79 seconds
Started Jun 29 05:28:01 PM PDT 24
Finished Jun 29 05:28:02 PM PDT 24
Peak memory 206072 kb
Host smart-ecda6e5e-d144-46b1-8151-37d678dfb460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321420969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1321420969
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3053473758
Short name T850
Test name
Test status
Simulation time 76047633518 ps
CPU time 251.72 seconds
Started Jun 29 05:27:54 PM PDT 24
Finished Jun 29 05:32:07 PM PDT 24
Peak memory 254064 kb
Host smart-732f0a80-f15c-4501-b7de-e1ee196fe7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053473758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3053473758
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.858693137
Short name T884
Test name
Test status
Simulation time 126649425286 ps
CPU time 249.67 seconds
Started Jun 29 05:28:04 PM PDT 24
Finished Jun 29 05:32:14 PM PDT 24
Peak memory 252680 kb
Host smart-76ea63c4-f695-42e3-b2e7-5046d7947984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858693137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.858693137
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.607429661
Short name T37
Test name
Test status
Simulation time 76173935400 ps
CPU time 278.64 seconds
Started Jun 29 05:28:07 PM PDT 24
Finished Jun 29 05:32:47 PM PDT 24
Peak memory 273800 kb
Host smart-366e5829-04f7-4046-bd5c-b1c113caef20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607429661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.607429661
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.453506390
Short name T859
Test name
Test status
Simulation time 1438582046 ps
CPU time 18.17 seconds
Started Jun 29 05:27:51 PM PDT 24
Finished Jun 29 05:28:12 PM PDT 24
Peak memory 236328 kb
Host smart-55e2b766-2bcb-4ba2-80b1-10900cb5856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453506390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.453506390
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3372528912
Short name T97
Test name
Test status
Simulation time 11783094847 ps
CPU time 110.62 seconds
Started Jun 29 05:27:51 PM PDT 24
Finished Jun 29 05:29:45 PM PDT 24
Peak memory 241104 kb
Host smart-d5e934b2-134c-4db0-afb9-57a8be2ee357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372528912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3372528912
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.469807594
Short name T616
Test name
Test status
Simulation time 146226306 ps
CPU time 5.05 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:27:57 PM PDT 24
Peak memory 224964 kb
Host smart-3ec1548e-9a1d-46a6-a939-b724832229a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469807594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.469807594
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2450867992
Short name T703
Test name
Test status
Simulation time 4543154927 ps
CPU time 23.49 seconds
Started Jun 29 05:28:03 PM PDT 24
Finished Jun 29 05:28:26 PM PDT 24
Peak memory 225064 kb
Host smart-74e83ce5-2e62-4d6a-9617-4fa54b73342b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450867992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2450867992
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.4033161593
Short name T948
Test name
Test status
Simulation time 5668317209 ps
CPU time 17.09 seconds
Started Jun 29 05:27:55 PM PDT 24
Finished Jun 29 05:28:13 PM PDT 24
Peak memory 233316 kb
Host smart-e5dff655-8776-45ac-8c02-eff28a454aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033161593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.4033161593
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1604488831
Short name T973
Test name
Test status
Simulation time 10685156174 ps
CPU time 9.71 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:28:02 PM PDT 24
Peak memory 225164 kb
Host smart-ea0fb7a3-c07d-4b3c-b5d1-713dc9cd7b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604488831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1604488831
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1813897539
Short name T713
Test name
Test status
Simulation time 1594273769 ps
CPU time 10.11 seconds
Started Jun 29 05:27:52 PM PDT 24
Finished Jun 29 05:28:05 PM PDT 24
Peak memory 222464 kb
Host smart-7f7d6aa6-a2da-48ba-a8d0-c76ecc397021
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1813897539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1813897539
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.825386147
Short name T830
Test name
Test status
Simulation time 1446896399 ps
CPU time 14.43 seconds
Started Jun 29 05:27:59 PM PDT 24
Finished Jun 29 05:28:15 PM PDT 24
Peak memory 216960 kb
Host smart-a4c24b6f-37f4-4e5f-9cb6-a4b407f66fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825386147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.825386147
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.424934203
Short name T92
Test name
Test status
Simulation time 3636041286 ps
CPU time 13.76 seconds
Started Jun 29 05:27:56 PM PDT 24
Finished Jun 29 05:28:11 PM PDT 24
Peak memory 216944 kb
Host smart-964f39ff-32b5-454e-b1e3-97783e7fddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424934203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.424934203
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3657250000
Short name T747
Test name
Test status
Simulation time 65687812 ps
CPU time 1.72 seconds
Started Jun 29 05:27:50 PM PDT 24
Finished Jun 29 05:27:55 PM PDT 24
Peak memory 216884 kb
Host smart-bb16c99a-bc08-4a70-9a2d-6575f5075924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657250000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3657250000
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.393372501
Short name T915
Test name
Test status
Simulation time 38366267 ps
CPU time 0.77 seconds
Started Jun 29 05:27:52 PM PDT 24
Finished Jun 29 05:27:55 PM PDT 24
Peak memory 206448 kb
Host smart-42422346-a956-4435-8987-3b1162592f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393372501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.393372501
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2387233950
Short name T912
Test name
Test status
Simulation time 8080260506 ps
CPU time 10.88 seconds
Started Jun 29 05:27:52 PM PDT 24
Finished Jun 29 05:28:05 PM PDT 24
Peak memory 225140 kb
Host smart-828d65f6-98f9-44ab-bb00-710faecb4a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387233950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2387233950
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3315779016
Short name T598
Test name
Test status
Simulation time 24066945 ps
CPU time 0.72 seconds
Started Jun 29 05:27:59 PM PDT 24
Finished Jun 29 05:28:00 PM PDT 24
Peak memory 205940 kb
Host smart-d275c995-0f32-4254-8c63-bce1b79c58cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315779016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3315779016
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3561736461
Short name T361
Test name
Test status
Simulation time 181236649 ps
CPU time 2.3 seconds
Started Jun 29 05:28:04 PM PDT 24
Finished Jun 29 05:28:07 PM PDT 24
Peak memory 224636 kb
Host smart-b3b61894-19d7-4179-a496-10466fdeb06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561736461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3561736461
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2041240117
Short name T942
Test name
Test status
Simulation time 17761354 ps
CPU time 0.79 seconds
Started Jun 29 05:28:05 PM PDT 24
Finished Jun 29 05:28:07 PM PDT 24
Peak memory 207036 kb
Host smart-9a44989d-d626-4251-8b45-00ec4e493ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041240117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2041240117
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1096317522
Short name T207
Test name
Test status
Simulation time 217977051034 ps
CPU time 141.25 seconds
Started Jun 29 05:28:10 PM PDT 24
Finished Jun 29 05:30:33 PM PDT 24
Peak memory 250752 kb
Host smart-b90ca1b8-ca32-4091-afdf-f352ce109ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096317522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1096317522
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2085806371
Short name T195
Test name
Test status
Simulation time 15643326668 ps
CPU time 100.23 seconds
Started Jun 29 05:28:00 PM PDT 24
Finished Jun 29 05:29:41 PM PDT 24
Peak memory 262624 kb
Host smart-ab62bf45-d481-4114-8037-fde0cb482db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085806371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2085806371
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.236766276
Short name T81
Test name
Test status
Simulation time 172741556563 ps
CPU time 262.18 seconds
Started Jun 29 05:28:06 PM PDT 24
Finished Jun 29 05:32:30 PM PDT 24
Peak memory 252572 kb
Host smart-4dbcb500-fcfa-45dd-882d-5c9411278f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236766276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.236766276
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2257643419
Short name T306
Test name
Test status
Simulation time 2114686752 ps
CPU time 37.47 seconds
Started Jun 29 05:28:06 PM PDT 24
Finished Jun 29 05:28:44 PM PDT 24
Peak memory 237292 kb
Host smart-2a37147b-78ad-4242-a544-27bef0101dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257643419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2257643419
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.9927897
Short name T766
Test name
Test status
Simulation time 164978248089 ps
CPU time 206.16 seconds
Started Jun 29 05:28:04 PM PDT 24
Finished Jun 29 05:31:30 PM PDT 24
Peak memory 249744 kb
Host smart-dff7289d-4ce4-4865-a062-cfb31ceb6505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9927897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.9927897
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2886921556
Short name T772
Test name
Test status
Simulation time 351127834 ps
CPU time 3.98 seconds
Started Jun 29 05:28:02 PM PDT 24
Finished Jun 29 05:28:07 PM PDT 24
Peak memory 233168 kb
Host smart-71f77e83-9385-4abb-b5b1-e5d7514678e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886921556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2886921556
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.4168900649
Short name T237
Test name
Test status
Simulation time 4156342117 ps
CPU time 54.28 seconds
Started Jun 29 05:27:59 PM PDT 24
Finished Jun 29 05:28:54 PM PDT 24
Peak memory 228848 kb
Host smart-d239aaa4-6c31-4cb1-a965-3e95c6c196ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168900649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4168900649
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.700658285
Short name T920
Test name
Test status
Simulation time 111538562 ps
CPU time 2.28 seconds
Started Jun 29 05:28:01 PM PDT 24
Finished Jun 29 05:28:04 PM PDT 24
Peak memory 233036 kb
Host smart-a0fa4354-971e-4a16-9b3f-46bebe0d37dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700658285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.700658285
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2279398395
Short name T275
Test name
Test status
Simulation time 2155425819 ps
CPU time 6.99 seconds
Started Jun 29 05:28:01 PM PDT 24
Finished Jun 29 05:28:09 PM PDT 24
Peak memory 225164 kb
Host smart-019ffd88-288e-4b75-945f-2911ab3548c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279398395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2279398395
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1602515806
Short name T854
Test name
Test status
Simulation time 1106933424 ps
CPU time 14.35 seconds
Started Jun 29 05:27:59 PM PDT 24
Finished Jun 29 05:28:14 PM PDT 24
Peak memory 222620 kb
Host smart-42797e06-e8cb-4cf6-8b94-fe4e0866c3ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1602515806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1602515806
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1590928430
Short name T22
Test name
Test status
Simulation time 10097059468 ps
CPU time 18.58 seconds
Started Jun 29 05:27:59 PM PDT 24
Finished Jun 29 05:28:18 PM PDT 24
Peak memory 225220 kb
Host smart-1efab210-6248-4001-93cf-f0f175a02bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590928430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1590928430
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.744489012
Short name T537
Test name
Test status
Simulation time 19858882286 ps
CPU time 29.72 seconds
Started Jun 29 05:28:04 PM PDT 24
Finished Jun 29 05:28:34 PM PDT 24
Peak memory 216876 kb
Host smart-f212786e-c90c-46e6-9617-030400a8fcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744489012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.744489012
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2964977232
Short name T343
Test name
Test status
Simulation time 299561074 ps
CPU time 2.02 seconds
Started Jun 29 05:28:01 PM PDT 24
Finished Jun 29 05:28:03 PM PDT 24
Peak memory 216584 kb
Host smart-637c506d-569b-4115-98fc-96a2b3cea913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964977232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2964977232
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2985996422
Short name T354
Test name
Test status
Simulation time 383507344 ps
CPU time 1.11 seconds
Started Jun 29 05:28:08 PM PDT 24
Finished Jun 29 05:28:10 PM PDT 24
Peak memory 216588 kb
Host smart-9ea95897-1b4d-402f-81ad-ea87da920527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985996422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2985996422
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1818163994
Short name T641
Test name
Test status
Simulation time 311175508 ps
CPU time 0.92 seconds
Started Jun 29 05:28:09 PM PDT 24
Finished Jun 29 05:28:10 PM PDT 24
Peak memory 206472 kb
Host smart-a8bcea86-1243-4c62-980b-1d31ee7956c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818163994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1818163994
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3668270417
Short name T980
Test name
Test status
Simulation time 2954436531 ps
CPU time 4.75 seconds
Started Jun 29 05:28:02 PM PDT 24
Finished Jun 29 05:28:07 PM PDT 24
Peak memory 225108 kb
Host smart-1da9b0ba-16cb-4166-9182-e1e56bf05e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668270417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3668270417
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3761078843
Short name T373
Test name
Test status
Simulation time 16735036 ps
CPU time 0.75 seconds
Started Jun 29 05:28:08 PM PDT 24
Finished Jun 29 05:28:10 PM PDT 24
Peak memory 205956 kb
Host smart-bf4efdbf-dac6-4aaf-a2a4-693f9bce802c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761078843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3761078843
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2473380358
Short name T671
Test name
Test status
Simulation time 4740397665 ps
CPU time 6.9 seconds
Started Jun 29 05:28:06 PM PDT 24
Finished Jun 29 05:28:14 PM PDT 24
Peak memory 225092 kb
Host smart-2d45e4e8-1a1e-4a96-b26e-30aac23ead0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473380358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2473380358
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.54411828
Short name T336
Test name
Test status
Simulation time 52381041 ps
CPU time 0.75 seconds
Started Jun 29 05:27:58 PM PDT 24
Finished Jun 29 05:27:59 PM PDT 24
Peak memory 206396 kb
Host smart-6c6bceb9-d1e7-49c3-933e-95f8d4ff0674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54411828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.54411828
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.773218390
Short name T925
Test name
Test status
Simulation time 84308965674 ps
CPU time 223.62 seconds
Started Jun 29 05:28:12 PM PDT 24
Finished Jun 29 05:31:57 PM PDT 24
Peak memory 267088 kb
Host smart-be74807c-fc01-4272-9432-01cb2f2191cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773218390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.773218390
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4104731307
Short name T619
Test name
Test status
Simulation time 7102248197 ps
CPU time 66.46 seconds
Started Jun 29 05:28:03 PM PDT 24
Finished Jun 29 05:29:10 PM PDT 24
Peak memory 249840 kb
Host smart-4b3b9612-f976-4f8c-9898-296c8316eb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104731307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4104731307
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.297006411
Short name T833
Test name
Test status
Simulation time 116680608194 ps
CPU time 361.78 seconds
Started Jun 29 05:28:02 PM PDT 24
Finished Jun 29 05:34:04 PM PDT 24
Peak memory 273848 kb
Host smart-4ace5fd7-8cb0-4a62-ad2b-0ba074263a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297006411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.297006411
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2209460371
Short name T627
Test name
Test status
Simulation time 431419404 ps
CPU time 4.12 seconds
Started Jun 29 05:28:05 PM PDT 24
Finished Jun 29 05:28:10 PM PDT 24
Peak memory 225020 kb
Host smart-2cbd6e29-eeec-4be8-bb69-36938237703c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209460371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2209460371
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3359965231
Short name T199
Test name
Test status
Simulation time 48731634524 ps
CPU time 127.28 seconds
Started Jun 29 05:28:04 PM PDT 24
Finished Jun 29 05:30:11 PM PDT 24
Peak memory 252660 kb
Host smart-5a10d8f6-151e-405d-882f-f7470b19c061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359965231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3359965231
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2362052667
Short name T979
Test name
Test status
Simulation time 911573711 ps
CPU time 5.83 seconds
Started Jun 29 05:28:05 PM PDT 24
Finished Jun 29 05:28:12 PM PDT 24
Peak memory 233232 kb
Host smart-9bcbd15a-f755-48a7-979a-00305c60ce22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362052667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2362052667
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1673277556
Short name T274
Test name
Test status
Simulation time 12785543457 ps
CPU time 49.13 seconds
Started Jun 29 05:28:05 PM PDT 24
Finished Jun 29 05:28:56 PM PDT 24
Peak memory 237016 kb
Host smart-2da1974d-8e19-4fc5-b214-e46a07323bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673277556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1673277556
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2700607633
Short name T446
Test name
Test status
Simulation time 15775622561 ps
CPU time 18.95 seconds
Started Jun 29 05:28:00 PM PDT 24
Finished Jun 29 05:28:20 PM PDT 24
Peak memory 251808 kb
Host smart-57cfafe6-6e9d-4bb5-9813-887bef1a651b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700607633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2700607633
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1598225044
Short name T743
Test name
Test status
Simulation time 435889277 ps
CPU time 4.27 seconds
Started Jun 29 05:28:10 PM PDT 24
Finished Jun 29 05:28:16 PM PDT 24
Peak memory 233076 kb
Host smart-d24b869c-83a2-425a-ad2f-93f51e5be57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598225044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1598225044
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1294238877
Short name T442
Test name
Test status
Simulation time 217943976 ps
CPU time 4.25 seconds
Started Jun 29 05:28:00 PM PDT 24
Finished Jun 29 05:28:05 PM PDT 24
Peak memory 223716 kb
Host smart-8a6d752d-fcf0-4b1b-b2e6-f6c224d37163
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1294238877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1294238877
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3714041181
Short name T933
Test name
Test status
Simulation time 12007693723 ps
CPU time 199.6 seconds
Started Jun 29 05:28:02 PM PDT 24
Finished Jun 29 05:31:22 PM PDT 24
Peak memory 267688 kb
Host smart-dc691271-008b-451e-8706-2f6e1d5e9f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714041181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3714041181
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.414197787
Short name T593
Test name
Test status
Simulation time 20008536364 ps
CPU time 20.4 seconds
Started Jun 29 05:28:03 PM PDT 24
Finished Jun 29 05:28:23 PM PDT 24
Peak memory 216948 kb
Host smart-b74571fa-fa42-450b-ac46-40783f6a34fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414197787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.414197787
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3550569444
Short name T788
Test name
Test status
Simulation time 805223239 ps
CPU time 5.14 seconds
Started Jun 29 05:27:59 PM PDT 24
Finished Jun 29 05:28:05 PM PDT 24
Peak memory 216784 kb
Host smart-c290c12d-c481-4fa2-9635-a55674026cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550569444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3550569444
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3761966418
Short name T888
Test name
Test status
Simulation time 42807695 ps
CPU time 1.53 seconds
Started Jun 29 05:28:12 PM PDT 24
Finished Jun 29 05:28:16 PM PDT 24
Peak memory 216828 kb
Host smart-d7597c4f-db78-4e4f-bf39-2d2a10b7dc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761966418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3761966418
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2304252261
Short name T89
Test name
Test status
Simulation time 101105542 ps
CPU time 0.88 seconds
Started Jun 29 05:28:06 PM PDT 24
Finished Jun 29 05:28:08 PM PDT 24
Peak memory 206460 kb
Host smart-b1f0d485-0588-4e82-b55f-5c9b63cc53c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304252261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2304252261
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1229628391
Short name T502
Test name
Test status
Simulation time 1329240575 ps
CPU time 6.51 seconds
Started Jun 29 05:28:02 PM PDT 24
Finished Jun 29 05:28:09 PM PDT 24
Peak memory 233076 kb
Host smart-8caa1cc3-6f4f-4dfe-8b6c-65c1f9c301fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229628391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1229628391
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1013005857
Short name T366
Test name
Test status
Simulation time 123256803 ps
CPU time 0.72 seconds
Started Jun 29 05:27:16 PM PDT 24
Finished Jun 29 05:27:18 PM PDT 24
Peak memory 206312 kb
Host smart-ce25be8a-daf3-428d-9887-79635d6529b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013005857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
013005857
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3248990439
Short name T845
Test name
Test status
Simulation time 412293405 ps
CPU time 7.12 seconds
Started Jun 29 05:27:18 PM PDT 24
Finished Jun 29 05:27:27 PM PDT 24
Peak memory 233364 kb
Host smart-e06f66cc-b84f-4e12-ae61-84974d99d416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248990439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3248990439
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.4073568292
Short name T338
Test name
Test status
Simulation time 47551608 ps
CPU time 0.76 seconds
Started Jun 29 05:27:09 PM PDT 24
Finished Jun 29 05:27:10 PM PDT 24
Peak memory 207428 kb
Host smart-cc6935ea-3baf-46e5-9c17-b56cb1ea5f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073568292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4073568292
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3765985142
Short name T193
Test name
Test status
Simulation time 28539790908 ps
CPU time 59.97 seconds
Started Jun 29 05:27:18 PM PDT 24
Finished Jun 29 05:28:19 PM PDT 24
Peak memory 249748 kb
Host smart-17fc3053-5ab8-493c-993c-32b1008a29bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765985142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3765985142
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3204379901
Short name T213
Test name
Test status
Simulation time 23149236739 ps
CPU time 137.59 seconds
Started Jun 29 05:27:12 PM PDT 24
Finished Jun 29 05:29:30 PM PDT 24
Peak memory 273372 kb
Host smart-11368433-7efe-48d2-ae5e-3e0c34fefdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204379901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3204379901
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2569626777
Short name T952
Test name
Test status
Simulation time 48390742966 ps
CPU time 204.72 seconds
Started Jun 29 05:27:10 PM PDT 24
Finished Jun 29 05:30:36 PM PDT 24
Peak memory 255660 kb
Host smart-75ff763a-ffa4-4917-b750-fedfcdab26e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569626777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2569626777
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3357385093
Short name T228
Test name
Test status
Simulation time 1208060450 ps
CPU time 5.3 seconds
Started Jun 29 05:27:09 PM PDT 24
Finished Jun 29 05:27:16 PM PDT 24
Peak memory 232300 kb
Host smart-e4feae26-84d0-42a9-9a10-d0f716afab05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357385093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3357385093
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3509334050
Short name T995
Test name
Test status
Simulation time 129153213809 ps
CPU time 108.47 seconds
Started Jun 29 05:27:09 PM PDT 24
Finished Jun 29 05:28:59 PM PDT 24
Peak memory 249656 kb
Host smart-a75b4a42-4f86-40f3-9937-f2a15f67324b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509334050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3509334050
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.409049664
Short name T279
Test name
Test status
Simulation time 4792559754 ps
CPU time 11.66 seconds
Started Jun 29 05:27:07 PM PDT 24
Finished Jun 29 05:27:20 PM PDT 24
Peak memory 225012 kb
Host smart-d51803c5-32c1-446f-9238-cbb039e61bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409049664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.409049664
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.792293511
Short name T7
Test name
Test status
Simulation time 14900185061 ps
CPU time 35.89 seconds
Started Jun 29 05:27:17 PM PDT 24
Finished Jun 29 05:27:55 PM PDT 24
Peak memory 225104 kb
Host smart-ecf7fe06-7803-4dcd-8c62-de27d80725af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792293511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.792293511
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4085859223
Short name T518
Test name
Test status
Simulation time 1020681519 ps
CPU time 7.58 seconds
Started Jun 29 05:27:13 PM PDT 24
Finished Jun 29 05:27:21 PM PDT 24
Peak memory 233156 kb
Host smart-bbbfb0c2-1bd7-4ec2-9959-26e309d99431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085859223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4085859223
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3405456538
Short name T874
Test name
Test status
Simulation time 26614050263 ps
CPU time 15.16 seconds
Started Jun 29 05:27:08 PM PDT 24
Finished Jun 29 05:27:24 PM PDT 24
Peak memory 233344 kb
Host smart-f88ef3e3-397e-49cd-a327-84960c8113b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405456538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3405456538
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1325413402
Short name T901
Test name
Test status
Simulation time 568238160 ps
CPU time 6.48 seconds
Started Jun 29 05:27:16 PM PDT 24
Finished Jun 29 05:27:23 PM PDT 24
Peak memory 222008 kb
Host smart-691da464-e282-4e41-91dd-97491397f519
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1325413402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1325413402
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3213909175
Short name T67
Test name
Test status
Simulation time 117264422 ps
CPU time 1.07 seconds
Started Jun 29 05:27:16 PM PDT 24
Finished Jun 29 05:27:18 PM PDT 24
Peak memory 236364 kb
Host smart-fbd0db22-8b48-4f8b-8c8a-3cb03da06111
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213909175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3213909175
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.745269657
Short name T695
Test name
Test status
Simulation time 94534471840 ps
CPU time 218.87 seconds
Started Jun 29 05:27:09 PM PDT 24
Finished Jun 29 05:30:49 PM PDT 24
Peak memory 266016 kb
Host smart-4a60af15-6808-48fb-afb2-ffab8723b4ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745269657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.745269657
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3222552668
Short name T326
Test name
Test status
Simulation time 10414082841 ps
CPU time 18.62 seconds
Started Jun 29 05:27:11 PM PDT 24
Finished Jun 29 05:27:31 PM PDT 24
Peak memory 220456 kb
Host smart-46af12b4-91a0-432d-ac47-c07cb86b3b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222552668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3222552668
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4036478567
Short name T385
Test name
Test status
Simulation time 786418563 ps
CPU time 5.69 seconds
Started Jun 29 05:27:01 PM PDT 24
Finished Jun 29 05:27:08 PM PDT 24
Peak memory 216812 kb
Host smart-9f3bc26c-8776-4162-9775-265d2e53f5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036478567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4036478567
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3440802646
Short name T458
Test name
Test status
Simulation time 337631529 ps
CPU time 2.32 seconds
Started Jun 29 05:27:11 PM PDT 24
Finished Jun 29 05:27:14 PM PDT 24
Peak memory 216768 kb
Host smart-f8b54fac-60be-4673-a98a-439eabfaad65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440802646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3440802646
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2296300279
Short name T513
Test name
Test status
Simulation time 106267199 ps
CPU time 1.07 seconds
Started Jun 29 05:27:12 PM PDT 24
Finished Jun 29 05:27:14 PM PDT 24
Peak memory 206668 kb
Host smart-1e421e72-7567-4a2f-a26e-5d86375867d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296300279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2296300279
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3077989771
Short name T255
Test name
Test status
Simulation time 609390900 ps
CPU time 7.27 seconds
Started Jun 29 05:27:24 PM PDT 24
Finished Jun 29 05:27:32 PM PDT 24
Peak memory 233132 kb
Host smart-cbb30d0b-3db7-49f9-b9dd-041ba746a567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077989771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3077989771
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.4118594746
Short name T408
Test name
Test status
Simulation time 19141625 ps
CPU time 0.75 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:16 PM PDT 24
Peak memory 205396 kb
Host smart-9fa9cd8f-9579-4f1e-aba8-549ac0796f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118594746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
4118594746
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4011894970
Short name T468
Test name
Test status
Simulation time 457377945 ps
CPU time 2.17 seconds
Started Jun 29 05:28:08 PM PDT 24
Finished Jun 29 05:28:11 PM PDT 24
Peak memory 225028 kb
Host smart-84784c02-f919-414d-9cfa-c51bf57f35dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011894970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4011894970
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2683364572
Short name T143
Test name
Test status
Simulation time 23131244 ps
CPU time 0.85 seconds
Started Jun 29 05:28:05 PM PDT 24
Finished Jun 29 05:28:06 PM PDT 24
Peak memory 207304 kb
Host smart-b453b1bf-1de1-4942-9ee1-27b874fd4405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683364572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2683364572
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3071547495
Short name T663
Test name
Test status
Simulation time 54288827886 ps
CPU time 194.33 seconds
Started Jun 29 05:28:12 PM PDT 24
Finished Jun 29 05:31:28 PM PDT 24
Peak memory 253368 kb
Host smart-d982cc4b-35b7-4a98-9631-7eecf5ea4fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071547495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3071547495
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.375670624
Short name T866
Test name
Test status
Simulation time 13656210271 ps
CPU time 96.3 seconds
Started Jun 29 05:28:14 PM PDT 24
Finished Jun 29 05:29:52 PM PDT 24
Peak memory 249852 kb
Host smart-a9ac99a6-d8aa-4963-8a57-d0b28c9ce199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375670624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.375670624
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3592906525
Short name T786
Test name
Test status
Simulation time 1987119921 ps
CPU time 26.34 seconds
Started Jun 29 05:28:14 PM PDT 24
Finished Jun 29 05:28:42 PM PDT 24
Peak memory 218420 kb
Host smart-61601940-ef28-45a1-9cf6-009b30fd9a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592906525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3592906525
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3107522959
Short name T899
Test name
Test status
Simulation time 11272333053 ps
CPU time 33.62 seconds
Started Jun 29 05:28:06 PM PDT 24
Finished Jun 29 05:28:41 PM PDT 24
Peak memory 225136 kb
Host smart-a952a571-1b02-4cca-b7e8-e0adfb890f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107522959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3107522959
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.48118826
Short name T1011
Test name
Test status
Simulation time 2854527158 ps
CPU time 13.48 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:29 PM PDT 24
Peak memory 233256 kb
Host smart-3e01a621-6ca5-40a2-9637-c8e9af4d1b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48118826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.48118826
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1239898825
Short name T278
Test name
Test status
Simulation time 2645152150 ps
CPU time 11.51 seconds
Started Jun 29 05:28:12 PM PDT 24
Finished Jun 29 05:28:26 PM PDT 24
Peak memory 241388 kb
Host smart-9abc93d1-5794-4130-8cb7-3aca0ec7c773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239898825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1239898825
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2978957305
Short name T470
Test name
Test status
Simulation time 297136418 ps
CPU time 5.12 seconds
Started Jun 29 05:28:03 PM PDT 24
Finished Jun 29 05:28:08 PM PDT 24
Peak memory 233240 kb
Host smart-2180b63b-109c-481b-9177-d6aee445b483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978957305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2978957305
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1515556355
Short name T599
Test name
Test status
Simulation time 3123440420 ps
CPU time 4.87 seconds
Started Jun 29 05:28:06 PM PDT 24
Finished Jun 29 05:28:12 PM PDT 24
Peak memory 221044 kb
Host smart-6a96519e-612b-43c7-a848-c990f409e3b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1515556355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1515556355
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.4192038048
Short name T324
Test name
Test status
Simulation time 3349473039 ps
CPU time 18.06 seconds
Started Jun 29 05:28:05 PM PDT 24
Finished Jun 29 05:28:24 PM PDT 24
Peak memory 216880 kb
Host smart-baf6af79-a28b-42e3-9844-3e06c496a62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192038048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4192038048
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3739150851
Short name T411
Test name
Test status
Simulation time 997244792 ps
CPU time 3.64 seconds
Started Jun 29 05:28:05 PM PDT 24
Finished Jun 29 05:28:09 PM PDT 24
Peak memory 216832 kb
Host smart-eab13799-312e-4cac-8184-2885c81fb0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739150851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3739150851
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.4100450222
Short name T891
Test name
Test status
Simulation time 62822878 ps
CPU time 0.93 seconds
Started Jun 29 05:28:02 PM PDT 24
Finished Jun 29 05:28:03 PM PDT 24
Peak memory 207432 kb
Host smart-f0927d5b-1b65-406a-9456-4478686801a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100450222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4100450222
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2109030652
Short name T752
Test name
Test status
Simulation time 36802826 ps
CPU time 0.72 seconds
Started Jun 29 05:28:06 PM PDT 24
Finished Jun 29 05:28:08 PM PDT 24
Peak memory 206092 kb
Host smart-3169349a-1b93-4b36-8d24-4d40ed4edddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109030652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2109030652
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3861958835
Short name T916
Test name
Test status
Simulation time 4704517768 ps
CPU time 9.57 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:25 PM PDT 24
Peak memory 241316 kb
Host smart-5e2fe48f-d01d-4e50-905d-00231baa9122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861958835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3861958835
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.155779417
Short name T549
Test name
Test status
Simulation time 26811640 ps
CPU time 0.74 seconds
Started Jun 29 05:28:18 PM PDT 24
Finished Jun 29 05:28:19 PM PDT 24
Peak memory 205400 kb
Host smart-e9fd2620-5cff-416d-b1c5-61aa0540e9b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155779417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.155779417
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2059994517
Short name T683
Test name
Test status
Simulation time 4394607509 ps
CPU time 9.65 seconds
Started Jun 29 05:28:11 PM PDT 24
Finished Jun 29 05:28:22 PM PDT 24
Peak memory 233280 kb
Host smart-f9652284-36a0-400f-849b-bf6abe78dd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059994517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2059994517
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2063105119
Short name T429
Test name
Test status
Simulation time 54465658 ps
CPU time 0.74 seconds
Started Jun 29 05:28:08 PM PDT 24
Finished Jun 29 05:28:10 PM PDT 24
Peak memory 206356 kb
Host smart-5fbddefa-f307-4f36-9dd2-371e04f18e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063105119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2063105119
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3973403630
Short name T908
Test name
Test status
Simulation time 217647013306 ps
CPU time 273 seconds
Started Jun 29 05:28:12 PM PDT 24
Finished Jun 29 05:32:47 PM PDT 24
Peak memory 254800 kb
Host smart-0b27c63e-24c8-4288-9722-db07cb65fb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973403630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3973403630
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1290547743
Short name T292
Test name
Test status
Simulation time 17545875974 ps
CPU time 227.91 seconds
Started Jun 29 05:28:05 PM PDT 24
Finished Jun 29 05:31:54 PM PDT 24
Peak memory 256708 kb
Host smart-027cd2a9-07f2-40db-8a8a-3c08cb171212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290547743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1290547743
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1576674082
Short name T694
Test name
Test status
Simulation time 2845021263 ps
CPU time 26.99 seconds
Started Jun 29 05:28:04 PM PDT 24
Finished Jun 29 05:28:32 PM PDT 24
Peak memory 225252 kb
Host smart-ffc73455-800d-4138-8d90-2d8ba9e70a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576674082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1576674082
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.35207213
Short name T2
Test name
Test status
Simulation time 999461922 ps
CPU time 10.35 seconds
Started Jun 29 05:28:12 PM PDT 24
Finished Jun 29 05:28:24 PM PDT 24
Peak memory 233640 kb
Host smart-3b1896b4-fc92-436e-a797-31d1fd8d7c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35207213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.35207213
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.4213858647
Short name T184
Test name
Test status
Simulation time 33098544940 ps
CPU time 37.07 seconds
Started Jun 29 05:28:11 PM PDT 24
Finished Jun 29 05:28:49 PM PDT 24
Peak memory 237108 kb
Host smart-b66d8634-d83e-40c8-87b3-6529c02645b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213858647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.4213858647
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1822758097
Short name T198
Test name
Test status
Simulation time 109507180 ps
CPU time 4.46 seconds
Started Jun 29 05:28:11 PM PDT 24
Finished Jun 29 05:28:17 PM PDT 24
Peak memory 233164 kb
Host smart-f23658b5-dd1b-4232-9e98-d24a907eaf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822758097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1822758097
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2156277817
Short name T222
Test name
Test status
Simulation time 12866656735 ps
CPU time 112.74 seconds
Started Jun 29 05:28:08 PM PDT 24
Finished Jun 29 05:30:02 PM PDT 24
Peak memory 240676 kb
Host smart-46128399-7a01-42c8-a9d9-8409e1902909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156277817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2156277817
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2291813158
Short name T970
Test name
Test status
Simulation time 89746173 ps
CPU time 2.25 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:18 PM PDT 24
Peak memory 224348 kb
Host smart-f0dc1e65-c5a8-4dac-9c62-c32963db02a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291813158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2291813158
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2781128939
Short name T892
Test name
Test status
Simulation time 23265988546 ps
CPU time 7.96 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:23 PM PDT 24
Peak memory 225060 kb
Host smart-69e177bf-15cd-4ce5-84f6-ac9cb723bf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781128939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2781128939
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2768981446
Short name T360
Test name
Test status
Simulation time 1139362592 ps
CPU time 9.13 seconds
Started Jun 29 05:28:12 PM PDT 24
Finished Jun 29 05:28:24 PM PDT 24
Peak memory 223444 kb
Host smart-d5fe78d2-2035-4d04-b5c5-57fc4f0ce62a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2768981446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2768981446
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.89695405
Short name T170
Test name
Test status
Simulation time 40932836214 ps
CPU time 371.89 seconds
Started Jun 29 05:28:07 PM PDT 24
Finished Jun 29 05:34:20 PM PDT 24
Peak memory 251644 kb
Host smart-bd30ede5-eff8-4e41-86ab-fdf7ea0b7c52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89695405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress
_all.89695405
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1887527442
Short name T327
Test name
Test status
Simulation time 3283543905 ps
CPU time 15.06 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:30 PM PDT 24
Peak memory 216904 kb
Host smart-b11b9d25-fe1a-4eee-8024-ff806e63484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887527442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1887527442
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2949261333
Short name T665
Test name
Test status
Simulation time 2901596881 ps
CPU time 9.57 seconds
Started Jun 29 05:28:12 PM PDT 24
Finished Jun 29 05:28:24 PM PDT 24
Peak memory 216900 kb
Host smart-0da7a338-2e1d-42be-8729-e30ecf01de9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949261333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2949261333
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3267521642
Short name T718
Test name
Test status
Simulation time 238047464 ps
CPU time 1.37 seconds
Started Jun 29 05:28:11 PM PDT 24
Finished Jun 29 05:28:13 PM PDT 24
Peak memory 216768 kb
Host smart-a831e27c-f6c0-4c1a-a944-c5da075ade58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267521642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3267521642
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1448673257
Short name T812
Test name
Test status
Simulation time 119306933 ps
CPU time 0.78 seconds
Started Jun 29 05:28:10 PM PDT 24
Finished Jun 29 05:28:12 PM PDT 24
Peak memory 206456 kb
Host smart-c17c5e5d-87ec-4bd2-8db3-c71526e44cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448673257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1448673257
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3049859659
Short name T696
Test name
Test status
Simulation time 24424224791 ps
CPU time 11.37 seconds
Started Jun 29 05:28:14 PM PDT 24
Finished Jun 29 05:28:27 PM PDT 24
Peak memory 239188 kb
Host smart-1a5e51af-f119-425b-a598-daed5d3467a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049859659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3049859659
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1440687837
Short name T380
Test name
Test status
Simulation time 34223912 ps
CPU time 0.73 seconds
Started Jun 29 05:28:18 PM PDT 24
Finished Jun 29 05:28:19 PM PDT 24
Peak memory 205360 kb
Host smart-91611687-9197-4c42-9933-d5c2354df0f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440687837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1440687837
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.823209152
Short name T256
Test name
Test status
Simulation time 347101501 ps
CPU time 5.98 seconds
Started Jun 29 05:28:15 PM PDT 24
Finished Jun 29 05:28:22 PM PDT 24
Peak memory 225016 kb
Host smart-33300c86-228c-43ed-8155-1bd3fe4d6464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823209152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.823209152
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3806138101
Short name T416
Test name
Test status
Simulation time 30521051 ps
CPU time 0.84 seconds
Started Jun 29 05:28:09 PM PDT 24
Finished Jun 29 05:28:11 PM PDT 24
Peak memory 207084 kb
Host smart-11225ecd-4438-4dd8-be17-82e2ccfd67e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806138101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3806138101
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3742234191
Short name T491
Test name
Test status
Simulation time 4237212944 ps
CPU time 9.73 seconds
Started Jun 29 05:28:12 PM PDT 24
Finished Jun 29 05:28:24 PM PDT 24
Peak memory 225144 kb
Host smart-5afd8df1-05af-4b3e-8e8e-572060da5f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742234191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3742234191
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4017385023
Short name T922
Test name
Test status
Simulation time 16247914313 ps
CPU time 166.24 seconds
Started Jun 29 05:28:11 PM PDT 24
Finished Jun 29 05:30:58 PM PDT 24
Peak memory 254168 kb
Host smart-827fbf54-a876-43bf-befc-1e53a468269f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017385023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4017385023
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1613843984
Short name T419
Test name
Test status
Simulation time 17675867630 ps
CPU time 27.63 seconds
Started Jun 29 05:28:12 PM PDT 24
Finished Jun 29 05:28:42 PM PDT 24
Peak memory 218240 kb
Host smart-e318443e-c6a5-4093-8413-87c963be8a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613843984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1613843984
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3474588273
Short name T309
Test name
Test status
Simulation time 2319488058 ps
CPU time 5.08 seconds
Started Jun 29 05:28:22 PM PDT 24
Finished Jun 29 05:28:28 PM PDT 24
Peak memory 225096 kb
Host smart-a828b359-cee3-47e0-add4-606460d618bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474588273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3474588273
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3878117822
Short name T503
Test name
Test status
Simulation time 7068114284 ps
CPU time 23.97 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:39 PM PDT 24
Peak memory 241544 kb
Host smart-21f865d7-76d6-4261-92ce-3c745737c4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878117822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3878117822
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2426987316
Short name T692
Test name
Test status
Simulation time 1340984712 ps
CPU time 14.52 seconds
Started Jun 29 05:28:16 PM PDT 24
Finished Jun 29 05:28:31 PM PDT 24
Peak memory 224964 kb
Host smart-8e9bf0e2-6a77-4d83-8d1a-8751184d1607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426987316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2426987316
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4229557482
Short name T258
Test name
Test status
Simulation time 4571508573 ps
CPU time 13.53 seconds
Started Jun 29 05:28:12 PM PDT 24
Finished Jun 29 05:28:28 PM PDT 24
Peak memory 233304 kb
Host smart-1f648a33-2b04-43cb-bbce-22fe9f62f471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229557482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4229557482
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.79639947
Short name T8
Test name
Test status
Simulation time 462013003 ps
CPU time 5.95 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:21 PM PDT 24
Peak memory 233012 kb
Host smart-c46b2783-2c96-469f-b67b-08ccd113e2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79639947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.79639947
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.831319354
Short name T556
Test name
Test status
Simulation time 36133675 ps
CPU time 2.26 seconds
Started Jun 29 05:28:10 PM PDT 24
Finished Jun 29 05:28:13 PM PDT 24
Peak memory 224908 kb
Host smart-9f173e8e-1d0f-48c6-89bf-f994770b1f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831319354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.831319354
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.968924284
Short name T158
Test name
Test status
Simulation time 1841030295 ps
CPU time 9.87 seconds
Started Jun 29 05:28:11 PM PDT 24
Finished Jun 29 05:28:23 PM PDT 24
Peak memory 219864 kb
Host smart-41beb477-7548-4646-ab7c-3451b3905a25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=968924284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.968924284
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.769058501
Short name T280
Test name
Test status
Simulation time 26681666417 ps
CPU time 146.75 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:30:42 PM PDT 24
Peak memory 266352 kb
Host smart-57e0efe1-d850-433b-9cad-5ab187d7d60c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769058501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.769058501
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1380647294
Short name T837
Test name
Test status
Simulation time 2016117289 ps
CPU time 5.01 seconds
Started Jun 29 05:28:11 PM PDT 24
Finished Jun 29 05:28:18 PM PDT 24
Peak memory 216984 kb
Host smart-1b76a572-b1dd-4db9-bd35-7fa969ad58fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380647294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1380647294
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3205728288
Short name T972
Test name
Test status
Simulation time 2860498407 ps
CPU time 5.45 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:21 PM PDT 24
Peak memory 216956 kb
Host smart-817a7af9-b5c9-4f96-add9-fd913369af56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205728288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3205728288
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.832497694
Short name T384
Test name
Test status
Simulation time 33301066 ps
CPU time 1.04 seconds
Started Jun 29 05:28:07 PM PDT 24
Finished Jun 29 05:28:09 PM PDT 24
Peak memory 208336 kb
Host smart-1e9efc0b-798e-4a04-bd72-e9d65172f06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832497694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.832497694
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1466893391
Short name T740
Test name
Test status
Simulation time 295012712 ps
CPU time 0.98 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:16 PM PDT 24
Peak memory 206952 kb
Host smart-e45fa98e-590d-41af-862b-f86d0c65902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466893391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1466893391
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2146369852
Short name T614
Test name
Test status
Simulation time 3273403735 ps
CPU time 7.93 seconds
Started Jun 29 05:28:15 PM PDT 24
Finished Jun 29 05:28:24 PM PDT 24
Peak memory 225064 kb
Host smart-bfe7b306-4285-43d0-8788-95995c1ee8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146369852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2146369852
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.782920434
Short name T398
Test name
Test status
Simulation time 12726278 ps
CPU time 0.75 seconds
Started Jun 29 05:28:15 PM PDT 24
Finished Jun 29 05:28:17 PM PDT 24
Peak memory 205964 kb
Host smart-258ff371-6d00-4fb6-8552-321114032041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782920434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.782920434
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.197945756
Short name T146
Test name
Test status
Simulation time 109640606 ps
CPU time 2.61 seconds
Started Jun 29 05:28:15 PM PDT 24
Finished Jun 29 05:28:19 PM PDT 24
Peak memory 233248 kb
Host smart-b3378d29-16a9-47a4-9b0a-e97b9e3c7142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197945756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.197945756
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1958697988
Short name T358
Test name
Test status
Simulation time 57331165 ps
CPU time 0.82 seconds
Started Jun 29 05:28:12 PM PDT 24
Finished Jun 29 05:28:15 PM PDT 24
Peak memory 207120 kb
Host smart-62217d80-f2a7-4da0-b30b-494ecebf8560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958697988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1958697988
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2339388656
Short name T601
Test name
Test status
Simulation time 16229568684 ps
CPU time 135.48 seconds
Started Jun 29 05:28:14 PM PDT 24
Finished Jun 29 05:30:31 PM PDT 24
Peak memory 254372 kb
Host smart-3ff9f6ca-8b77-4dbb-a2d5-f6b300b92eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339388656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2339388656
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1076103316
Short name T397
Test name
Test status
Simulation time 7195101326 ps
CPU time 69.48 seconds
Started Jun 29 05:28:19 PM PDT 24
Finished Jun 29 05:29:29 PM PDT 24
Peak memory 241400 kb
Host smart-cc38a507-7f03-4129-9866-9b69a387a745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076103316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1076103316
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.415315012
Short name T744
Test name
Test status
Simulation time 271455841247 ps
CPU time 147.82 seconds
Started Jun 29 05:28:14 PM PDT 24
Finished Jun 29 05:30:44 PM PDT 24
Peak memory 238460 kb
Host smart-edbb2a1a-ce6b-4d54-afa1-9db8e1d21c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415315012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.415315012
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3674922628
Short name T374
Test name
Test status
Simulation time 455864324 ps
CPU time 2.88 seconds
Started Jun 29 05:28:19 PM PDT 24
Finished Jun 29 05:28:22 PM PDT 24
Peak memory 225008 kb
Host smart-6ce6803b-51ef-4ee6-85f3-56669771c44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674922628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3674922628
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.151659952
Short name T273
Test name
Test status
Simulation time 18938952421 ps
CPU time 98.52 seconds
Started Jun 29 05:28:14 PM PDT 24
Finished Jun 29 05:29:54 PM PDT 24
Peak memory 257248 kb
Host smart-ac2a073a-f731-4a4c-a7a9-98f57ae514b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151659952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.151659952
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3065328416
Short name T492
Test name
Test status
Simulation time 5875291866 ps
CPU time 14.82 seconds
Started Jun 29 05:28:19 PM PDT 24
Finished Jun 29 05:28:34 PM PDT 24
Peak memory 233364 kb
Host smart-a0a156bb-ff37-442c-8c17-0d8ffa4e9343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065328416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3065328416
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3688218943
Short name T719
Test name
Test status
Simulation time 23463569146 ps
CPU time 55.27 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:29:11 PM PDT 24
Peak memory 225112 kb
Host smart-0397e492-bdd8-4fbb-b31b-fe4062c4490a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688218943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3688218943
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2066209537
Short name T267
Test name
Test status
Simulation time 237812922 ps
CPU time 2.37 seconds
Started Jun 29 05:28:14 PM PDT 24
Finished Jun 29 05:28:18 PM PDT 24
Peak memory 233168 kb
Host smart-34e889c2-2e30-4623-bbc7-3e3aaf189db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066209537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2066209537
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1296738874
Short name T461
Test name
Test status
Simulation time 8293445020 ps
CPU time 11.11 seconds
Started Jun 29 05:28:14 PM PDT 24
Finished Jun 29 05:28:27 PM PDT 24
Peak memory 241280 kb
Host smart-9007ef10-fe55-430d-8cdb-0348f45ce879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296738874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1296738874
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2944369109
Short name T755
Test name
Test status
Simulation time 2001874941 ps
CPU time 15.28 seconds
Started Jun 29 05:28:16 PM PDT 24
Finished Jun 29 05:28:32 PM PDT 24
Peak memory 221012 kb
Host smart-c8bba6f2-029d-45ca-b39a-43c26482969c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2944369109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2944369109
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1795897748
Short name T148
Test name
Test status
Simulation time 13450827551 ps
CPU time 190.95 seconds
Started Jun 29 05:28:14 PM PDT 24
Finished Jun 29 05:31:27 PM PDT 24
Peak memory 266216 kb
Host smart-ddd5ecbc-e198-4b3f-8ea2-d43c05342e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795897748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1795897748
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3825201849
Short name T691
Test name
Test status
Simulation time 22948715334 ps
CPU time 24.16 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:40 PM PDT 24
Peak memory 220496 kb
Host smart-86b6f579-a837-42c1-8898-88a8105a50b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825201849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3825201849
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2538997955
Short name T359
Test name
Test status
Simulation time 593053726 ps
CPU time 1.65 seconds
Started Jun 29 05:28:14 PM PDT 24
Finished Jun 29 05:28:18 PM PDT 24
Peak memory 208376 kb
Host smart-a91aaa99-fc38-4e23-864d-11989197858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538997955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2538997955
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.945492565
Short name T753
Test name
Test status
Simulation time 527684690 ps
CPU time 5.54 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:21 PM PDT 24
Peak memory 216768 kb
Host smart-9bfa0af6-85f5-465e-b719-523f6c215d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945492565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.945492565
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2738769253
Short name T613
Test name
Test status
Simulation time 101757203 ps
CPU time 0.93 seconds
Started Jun 29 05:28:14 PM PDT 24
Finished Jun 29 05:28:17 PM PDT 24
Peak memory 206364 kb
Host smart-4c7511d7-e5f3-417b-a7b1-46611c92a647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738769253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2738769253
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3118744535
Short name T905
Test name
Test status
Simulation time 538280098 ps
CPU time 3.06 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:18 PM PDT 24
Peak memory 225016 kb
Host smart-0ccafe16-e0a4-4d7e-81a9-56e486a90eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118744535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3118744535
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1698004202
Short name T415
Test name
Test status
Simulation time 13264322 ps
CPU time 0.81 seconds
Started Jun 29 05:28:25 PM PDT 24
Finished Jun 29 05:28:27 PM PDT 24
Peak memory 205932 kb
Host smart-8de6db24-83ec-4836-bad5-2a07558e51b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698004202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1698004202
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1238248230
Short name T947
Test name
Test status
Simulation time 118304079 ps
CPU time 2.34 seconds
Started Jun 29 05:28:21 PM PDT 24
Finished Jun 29 05:28:24 PM PDT 24
Peak memory 233180 kb
Host smart-0f8bd29f-90f9-44a9-89f8-ec42c35a678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238248230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1238248230
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2904503674
Short name T802
Test name
Test status
Simulation time 55478477 ps
CPU time 0.81 seconds
Started Jun 29 05:28:25 PM PDT 24
Finished Jun 29 05:28:26 PM PDT 24
Peak memory 207112 kb
Host smart-ecabe666-543a-4c44-9dc9-6e54c41baa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904503674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2904503674
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1716508719
Short name T234
Test name
Test status
Simulation time 5382689908 ps
CPU time 44.72 seconds
Started Jun 29 05:28:21 PM PDT 24
Finished Jun 29 05:29:06 PM PDT 24
Peak memory 249852 kb
Host smart-3afde7b0-a538-4519-97c1-07a81c3047b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716508719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1716508719
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.4077065894
Short name T906
Test name
Test status
Simulation time 21655933326 ps
CPU time 64.45 seconds
Started Jun 29 05:28:26 PM PDT 24
Finished Jun 29 05:29:31 PM PDT 24
Peak memory 249728 kb
Host smart-0410df47-0b93-4c02-8094-559747018004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077065894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4077065894
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.206196493
Short name T291
Test name
Test status
Simulation time 56429583515 ps
CPU time 262.66 seconds
Started Jun 29 05:28:27 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 258012 kb
Host smart-30505291-b9cf-4eae-b234-51bf8f211d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206196493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.206196493
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2405489081
Short name T564
Test name
Test status
Simulation time 433719592 ps
CPU time 9.09 seconds
Started Jun 29 05:28:21 PM PDT 24
Finished Jun 29 05:28:31 PM PDT 24
Peak memory 233268 kb
Host smart-b2ca0b49-5918-48c4-8d20-5c46ece384a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405489081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2405489081
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.458953423
Short name T271
Test name
Test status
Simulation time 93536134372 ps
CPU time 186.2 seconds
Started Jun 29 05:28:23 PM PDT 24
Finished Jun 29 05:31:30 PM PDT 24
Peak memory 253748 kb
Host smart-4d9dbb86-13a1-4b7a-8541-c5423a95261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458953423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.458953423
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3342660725
Short name T666
Test name
Test status
Simulation time 8313464290 ps
CPU time 18.4 seconds
Started Jun 29 05:28:18 PM PDT 24
Finished Jun 29 05:28:37 PM PDT 24
Peak memory 233360 kb
Host smart-4a720d76-c3a0-4b35-97f4-d870b539df59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342660725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3342660725
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3411862001
Short name T653
Test name
Test status
Simulation time 36344284596 ps
CPU time 107.4 seconds
Started Jun 29 05:28:23 PM PDT 24
Finished Jun 29 05:30:11 PM PDT 24
Peak memory 236692 kb
Host smart-eff980b4-5f6d-4a7d-ba71-e1be090f88e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411862001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3411862001
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.228725580
Short name T856
Test name
Test status
Simulation time 215902380 ps
CPU time 3.25 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:19 PM PDT 24
Peak memory 233204 kb
Host smart-decb5b54-5a21-4199-b985-3e3ce75fe770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228725580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.228725580
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1225031407
Short name T223
Test name
Test status
Simulation time 1211144521 ps
CPU time 9.04 seconds
Started Jun 29 05:28:19 PM PDT 24
Finished Jun 29 05:28:29 PM PDT 24
Peak memory 225040 kb
Host smart-35fe6121-f237-43da-80b9-d6d3fe608b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225031407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1225031407
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3285914310
Short name T546
Test name
Test status
Simulation time 273456303 ps
CPU time 3.49 seconds
Started Jun 29 05:28:26 PM PDT 24
Finished Jun 29 05:28:30 PM PDT 24
Peak memory 219348 kb
Host smart-e2f5e67b-63d9-4679-a94b-7bc0163cc112
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3285914310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3285914310
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.612068703
Short name T846
Test name
Test status
Simulation time 239248871193 ps
CPU time 579.86 seconds
Started Jun 29 05:28:22 PM PDT 24
Finished Jun 29 05:38:02 PM PDT 24
Peak memory 266164 kb
Host smart-b4196c18-0435-4f95-8e39-046677800ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612068703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.612068703
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1173576087
Short name T433
Test name
Test status
Simulation time 1055971652 ps
CPU time 10.34 seconds
Started Jun 29 05:28:19 PM PDT 24
Finished Jun 29 05:28:30 PM PDT 24
Peak memory 216780 kb
Host smart-857bd2d5-6a66-4d3f-a177-31eb35a9ba60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173576087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1173576087
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3030035550
Short name T852
Test name
Test status
Simulation time 1467807791 ps
CPU time 4.62 seconds
Started Jun 29 05:28:18 PM PDT 24
Finished Jun 29 05:28:23 PM PDT 24
Peak memory 216772 kb
Host smart-1bae917b-df28-4522-88c8-d154ee7a8d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030035550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3030035550
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3727076632
Short name T625
Test name
Test status
Simulation time 160007481 ps
CPU time 2.24 seconds
Started Jun 29 05:28:13 PM PDT 24
Finished Jun 29 05:28:17 PM PDT 24
Peak memory 216820 kb
Host smart-a61fc6a4-e9c9-4005-a35d-63fe7721b852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727076632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3727076632
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1051333940
Short name T829
Test name
Test status
Simulation time 55795800 ps
CPU time 0.78 seconds
Started Jun 29 05:28:18 PM PDT 24
Finished Jun 29 05:28:19 PM PDT 24
Peak memory 206452 kb
Host smart-cf66ee47-b1c8-45dc-9bf3-610e2d127108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051333940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1051333940
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3501223537
Short name T611
Test name
Test status
Simulation time 47921486 ps
CPU time 2.55 seconds
Started Jun 29 05:28:20 PM PDT 24
Finished Jun 29 05:28:23 PM PDT 24
Peak memory 232936 kb
Host smart-0511aa83-e1ed-4b96-a5de-45dc5d00f6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501223537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3501223537
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1125862133
Short name T764
Test name
Test status
Simulation time 16327462 ps
CPU time 0.72 seconds
Started Jun 29 05:28:28 PM PDT 24
Finished Jun 29 05:28:29 PM PDT 24
Peak memory 205372 kb
Host smart-879017c0-27a6-4440-9c23-f873f00fb5b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125862133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1125862133
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3667876727
Short name T742
Test name
Test status
Simulation time 635116450 ps
CPU time 7.95 seconds
Started Jun 29 05:28:23 PM PDT 24
Finished Jun 29 05:28:31 PM PDT 24
Peak memory 225024 kb
Host smart-06871d6d-f270-47a4-90a8-c19904ad284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667876727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3667876727
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.480439183
Short name T789
Test name
Test status
Simulation time 30649310 ps
CPU time 0.87 seconds
Started Jun 29 05:28:26 PM PDT 24
Finished Jun 29 05:28:28 PM PDT 24
Peak memory 207112 kb
Host smart-35bf1742-049c-4f8b-b7c1-faa4668148c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480439183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.480439183
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.596185022
Short name T926
Test name
Test status
Simulation time 43288380 ps
CPU time 0.8 seconds
Started Jun 29 05:28:22 PM PDT 24
Finished Jun 29 05:28:23 PM PDT 24
Peak memory 216404 kb
Host smart-d3ca2237-23cd-4b9c-88d3-a2c01d24881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596185022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.596185022
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1983890878
Short name T816
Test name
Test status
Simulation time 28119838795 ps
CPU time 33.63 seconds
Started Jun 29 05:28:28 PM PDT 24
Finished Jun 29 05:29:02 PM PDT 24
Peak memory 218448 kb
Host smart-06d12f4b-94c1-431e-a518-9b6e7d543c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983890878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1983890878
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1439894957
Short name T572
Test name
Test status
Simulation time 8006243752 ps
CPU time 12.46 seconds
Started Jun 29 05:28:28 PM PDT 24
Finished Jun 29 05:28:41 PM PDT 24
Peak memory 218592 kb
Host smart-3713e2f2-692a-4bef-8f12-7e5ab1c6b022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439894957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1439894957
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2026503221
Short name T43
Test name
Test status
Simulation time 847991434 ps
CPU time 8.44 seconds
Started Jun 29 05:28:21 PM PDT 24
Finished Jun 29 05:28:29 PM PDT 24
Peak memory 233224 kb
Host smart-7f6db095-2ac4-462f-a419-451ed58a57a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026503221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2026503221
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3284544835
Short name T560
Test name
Test status
Simulation time 100216736241 ps
CPU time 150.75 seconds
Started Jun 29 05:28:20 PM PDT 24
Finished Jun 29 05:30:51 PM PDT 24
Peak memory 254556 kb
Host smart-7755ba64-30e4-4f43-9642-fb0c4aa77089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284544835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3284544835
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4125314707
Short name T878
Test name
Test status
Simulation time 312269712 ps
CPU time 5.76 seconds
Started Jun 29 05:28:21 PM PDT 24
Finished Jun 29 05:28:27 PM PDT 24
Peak memory 233092 kb
Host smart-f0ff1268-cfd0-4aaa-a88d-cca5928d84db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125314707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4125314707
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3927073477
Short name T254
Test name
Test status
Simulation time 3569742723 ps
CPU time 10.01 seconds
Started Jun 29 05:28:20 PM PDT 24
Finished Jun 29 05:28:30 PM PDT 24
Peak memory 233308 kb
Host smart-2f802cd3-ba79-4744-ab8b-cd2385d50eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927073477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3927073477
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2393089178
Short name T645
Test name
Test status
Simulation time 2736447836 ps
CPU time 6.2 seconds
Started Jun 29 05:28:26 PM PDT 24
Finished Jun 29 05:28:33 PM PDT 24
Peak memory 225080 kb
Host smart-9f7b83e6-e3c0-46cc-ba48-52df50d4fea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393089178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2393089178
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1380665825
Short name T532
Test name
Test status
Simulation time 374276377 ps
CPU time 2.19 seconds
Started Jun 29 05:28:27 PM PDT 24
Finished Jun 29 05:28:30 PM PDT 24
Peak memory 224776 kb
Host smart-d1a588f6-459d-401f-96df-066b36a79f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380665825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1380665825
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.485607859
Short name T392
Test name
Test status
Simulation time 6040248290 ps
CPU time 10.34 seconds
Started Jun 29 05:28:28 PM PDT 24
Finished Jun 29 05:28:38 PM PDT 24
Peak memory 223704 kb
Host smart-979af36c-ee8b-4af6-bdae-ac350dff0e05
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=485607859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.485607859
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1817772490
Short name T284
Test name
Test status
Simulation time 6835101881 ps
CPU time 52.87 seconds
Started Jun 29 05:28:28 PM PDT 24
Finished Jun 29 05:29:21 PM PDT 24
Peak memory 257564 kb
Host smart-c6791bd1-6ae8-414f-8a34-e2ffce39a1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817772490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1817772490
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.773999836
Short name T140
Test name
Test status
Simulation time 3952513601 ps
CPU time 32.46 seconds
Started Jun 29 05:28:23 PM PDT 24
Finished Jun 29 05:28:56 PM PDT 24
Peak memory 216948 kb
Host smart-e33f60e3-91f3-4736-944a-8fb8d5a8f8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773999836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.773999836
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2988648791
Short name T949
Test name
Test status
Simulation time 13718266752 ps
CPU time 20.96 seconds
Started Jun 29 05:28:21 PM PDT 24
Finished Jun 29 05:28:43 PM PDT 24
Peak memory 216868 kb
Host smart-715bb6b7-ae1f-4528-b397-29cb85968b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988648791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2988648791
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2634585832
Short name T579
Test name
Test status
Simulation time 14407806 ps
CPU time 0.78 seconds
Started Jun 29 05:28:22 PM PDT 24
Finished Jun 29 05:28:23 PM PDT 24
Peak memory 206408 kb
Host smart-1acf7c41-4d09-45ed-819e-17722ac35a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634585832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2634585832
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1015910342
Short name T886
Test name
Test status
Simulation time 27995816 ps
CPU time 0.86 seconds
Started Jun 29 05:28:23 PM PDT 24
Finished Jun 29 05:28:24 PM PDT 24
Peak memory 206452 kb
Host smart-370ca965-daa1-44d6-b536-f5a9b10380f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015910342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1015910342
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1009541881
Short name T414
Test name
Test status
Simulation time 181312349 ps
CPU time 4.7 seconds
Started Jun 29 05:28:25 PM PDT 24
Finished Jun 29 05:28:30 PM PDT 24
Peak memory 233228 kb
Host smart-832a8a62-e28e-40b3-b998-35f226f06485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009541881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1009541881
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2787961022
Short name T780
Test name
Test status
Simulation time 21973300 ps
CPU time 0.74 seconds
Started Jun 29 05:28:30 PM PDT 24
Finished Jun 29 05:28:31 PM PDT 24
Peak memory 205340 kb
Host smart-f28bc3eb-d35c-4b7e-8a87-7a69ec8646a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787961022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2787961022
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2956186387
Short name T540
Test name
Test status
Simulation time 2432900524 ps
CPU time 7.81 seconds
Started Jun 29 05:28:29 PM PDT 24
Finished Jun 29 05:28:37 PM PDT 24
Peak memory 225092 kb
Host smart-e4c7eae8-ecee-4e51-9d9a-b147402d266c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956186387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2956186387
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3015590364
Short name T795
Test name
Test status
Simulation time 15338671 ps
CPU time 0.79 seconds
Started Jun 29 05:28:28 PM PDT 24
Finished Jun 29 05:28:29 PM PDT 24
Peak memory 207068 kb
Host smart-e7a8b999-2731-4395-a57b-fe15be7ec9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015590364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3015590364
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2037154207
Short name T196
Test name
Test status
Simulation time 19221015409 ps
CPU time 164.94 seconds
Started Jun 29 05:28:31 PM PDT 24
Finished Jun 29 05:31:17 PM PDT 24
Peak memory 258240 kb
Host smart-c2e711c0-7df3-451c-a0b4-4052995bd56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037154207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2037154207
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.263894740
Short name T961
Test name
Test status
Simulation time 29587781037 ps
CPU time 117.46 seconds
Started Jun 29 05:28:30 PM PDT 24
Finished Jun 29 05:30:28 PM PDT 24
Peak memory 249876 kb
Host smart-64afae16-890c-49f0-9143-041261beeba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263894740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.263894740
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3581186852
Short name T353
Test name
Test status
Simulation time 1294354974 ps
CPU time 4.05 seconds
Started Jun 29 05:28:28 PM PDT 24
Finished Jun 29 05:28:32 PM PDT 24
Peak memory 224940 kb
Host smart-24c49799-dab2-4af5-8040-435e0e920c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581186852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3581186852
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1325199937
Short name T287
Test name
Test status
Simulation time 73202584864 ps
CPU time 191.46 seconds
Started Jun 29 05:28:29 PM PDT 24
Finished Jun 29 05:31:41 PM PDT 24
Peak memory 262948 kb
Host smart-600b4119-a51e-43fe-a19d-26ae161257e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325199937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1325199937
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3391490505
Short name T748
Test name
Test status
Simulation time 5732208808 ps
CPU time 17.25 seconds
Started Jun 29 05:28:29 PM PDT 24
Finished Jun 29 05:28:47 PM PDT 24
Peak memory 225084 kb
Host smart-555d6b7f-d9c7-4062-9e67-28f74c152f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391490505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3391490505
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3817103291
Short name T567
Test name
Test status
Simulation time 3196688040 ps
CPU time 26.82 seconds
Started Jun 29 05:28:30 PM PDT 24
Finished Jun 29 05:28:58 PM PDT 24
Peak memory 225084 kb
Host smart-90732d29-4bbb-4f7e-9c4c-f85a0151166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817103291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3817103291
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2357283516
Short name T527
Test name
Test status
Simulation time 725397816 ps
CPU time 2.78 seconds
Started Jun 29 05:28:27 PM PDT 24
Finished Jun 29 05:28:30 PM PDT 24
Peak memory 233152 kb
Host smart-8c34c96b-84a5-423f-8797-76dc8505737b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357283516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2357283516
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3534896099
Short name T919
Test name
Test status
Simulation time 495839624 ps
CPU time 3.64 seconds
Started Jun 29 05:28:28 PM PDT 24
Finished Jun 29 05:28:33 PM PDT 24
Peak memory 233196 kb
Host smart-a6bbc17c-bdfe-4f91-adc7-0281b35a145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534896099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3534896099
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1339479476
Short name T3
Test name
Test status
Simulation time 7360421128 ps
CPU time 10.24 seconds
Started Jun 29 05:28:27 PM PDT 24
Finished Jun 29 05:28:38 PM PDT 24
Peak memory 223712 kb
Host smart-c0e63e65-17b8-4af2-85d5-40372d881c3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1339479476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1339479476
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2375150693
Short name T822
Test name
Test status
Simulation time 3050708637 ps
CPU time 10.8 seconds
Started Jun 29 05:28:28 PM PDT 24
Finished Jun 29 05:28:40 PM PDT 24
Peak memory 217256 kb
Host smart-0b44178c-e585-47f8-9626-b1ccdafd91f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375150693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2375150693
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2201648328
Short name T900
Test name
Test status
Simulation time 4483245266 ps
CPU time 5.89 seconds
Started Jun 29 05:28:29 PM PDT 24
Finished Jun 29 05:28:35 PM PDT 24
Peak memory 216816 kb
Host smart-dcf85689-de65-4708-8532-fc0ffafb33e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201648328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2201648328
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.258127537
Short name T548
Test name
Test status
Simulation time 218769197 ps
CPU time 3.08 seconds
Started Jun 29 05:28:29 PM PDT 24
Finished Jun 29 05:28:32 PM PDT 24
Peak memory 216864 kb
Host smart-56e6e04f-fec8-43bc-9835-7d73844e7193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258127537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.258127537
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3959670693
Short name T346
Test name
Test status
Simulation time 35414989 ps
CPU time 0.81 seconds
Started Jun 29 05:28:29 PM PDT 24
Finished Jun 29 05:28:30 PM PDT 24
Peak memory 206452 kb
Host smart-cefc7d92-3d1c-4d97-9248-18b7f9e86872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959670693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3959670693
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1824957526
Short name T819
Test name
Test status
Simulation time 259133806 ps
CPU time 4.16 seconds
Started Jun 29 05:28:27 PM PDT 24
Finished Jun 29 05:28:31 PM PDT 24
Peak memory 233140 kb
Host smart-a320dc5a-2428-4bed-995a-c4c880a8f4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824957526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1824957526
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2240860643
Short name T60
Test name
Test status
Simulation time 14422015 ps
CPU time 0.8 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:28:41 PM PDT 24
Peak memory 205400 kb
Host smart-c8134d62-d9d8-4ddb-b735-5e03da69add3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240860643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2240860643
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3104721170
Short name T495
Test name
Test status
Simulation time 163445581 ps
CPU time 3.76 seconds
Started Jun 29 05:28:35 PM PDT 24
Finished Jun 29 05:28:39 PM PDT 24
Peak memory 224968 kb
Host smart-848cfbf4-6171-4d9b-acd7-1510cfff1c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104721170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3104721170
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2619714647
Short name T893
Test name
Test status
Simulation time 50150529 ps
CPU time 0.77 seconds
Started Jun 29 05:28:31 PM PDT 24
Finished Jun 29 05:28:33 PM PDT 24
Peak memory 206072 kb
Host smart-e2dc9b40-77a2-4d66-a76a-e82f941ad4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619714647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2619714647
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3190034510
Short name T293
Test name
Test status
Simulation time 427992655996 ps
CPU time 302.96 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:33:42 PM PDT 24
Peak memory 266060 kb
Host smart-ba556806-7bb8-401e-8020-e16264b7c6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190034510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3190034510
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.480332164
Short name T149
Test name
Test status
Simulation time 7243874222 ps
CPU time 122.4 seconds
Started Jun 29 05:28:40 PM PDT 24
Finished Jun 29 05:30:43 PM PDT 24
Peak memory 253528 kb
Host smart-b47c9be3-c765-42ea-bb23-ce1a919ffe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480332164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.480332164
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1818329031
Short name T74
Test name
Test status
Simulation time 275197197 ps
CPU time 4.27 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:28:44 PM PDT 24
Peak memory 241400 kb
Host smart-b2d6d5ab-da3d-42af-bae7-57888e9e90a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818329031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1818329031
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.455830782
Short name T566
Test name
Test status
Simulation time 192597215339 ps
CPU time 319.62 seconds
Started Jun 29 05:28:36 PM PDT 24
Finished Jun 29 05:33:56 PM PDT 24
Peak memory 255252 kb
Host smart-9f683bed-1560-4217-915f-edbdc181d0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455830782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.455830782
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3906596020
Short name T340
Test name
Test status
Simulation time 6630435956 ps
CPU time 24.75 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:29:04 PM PDT 24
Peak memory 233304 kb
Host smart-dc50e003-79e8-466a-823d-68d5c9cfada1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906596020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3906596020
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.503049950
Short name T250
Test name
Test status
Simulation time 3148630041 ps
CPU time 42.2 seconds
Started Jun 29 05:28:37 PM PDT 24
Finished Jun 29 05:29:20 PM PDT 24
Peak memory 225136 kb
Host smart-8aa418c4-c32f-4a5d-9c6d-37a57cebfbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503049950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.503049950
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3343808063
Short name T401
Test name
Test status
Simulation time 346441247 ps
CPU time 2.2 seconds
Started Jun 29 05:28:37 PM PDT 24
Finished Jun 29 05:28:40 PM PDT 24
Peak memory 224676 kb
Host smart-27bed3c6-fbdf-43e6-a182-a9b76895226f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343808063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3343808063
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4086005045
Short name T232
Test name
Test status
Simulation time 1522179877 ps
CPU time 7.62 seconds
Started Jun 29 05:28:36 PM PDT 24
Finished Jun 29 05:28:44 PM PDT 24
Peak memory 233176 kb
Host smart-87bcbd42-2bcc-41fb-98be-1f90291ccdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086005045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4086005045
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2139471428
Short name T589
Test name
Test status
Simulation time 106827986 ps
CPU time 4.36 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:28:45 PM PDT 24
Peak memory 223484 kb
Host smart-04917840-fc05-47e4-bb3f-4b428fc12465
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2139471428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2139471428
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1278071443
Short name T53
Test name
Test status
Simulation time 155395483643 ps
CPU time 227.53 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:32:28 PM PDT 24
Peak memory 282624 kb
Host smart-650badaf-da4e-494c-8334-d5d3504b9f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278071443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1278071443
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.171081710
Short name T658
Test name
Test status
Simulation time 877445723 ps
CPU time 14.58 seconds
Started Jun 29 05:28:30 PM PDT 24
Finished Jun 29 05:28:45 PM PDT 24
Peak memory 216840 kb
Host smart-fe08e4c8-8208-43aa-8354-3b28d681e0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171081710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.171081710
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1706194734
Short name T467
Test name
Test status
Simulation time 7808885792 ps
CPU time 10.45 seconds
Started Jun 29 05:28:31 PM PDT 24
Finished Jun 29 05:28:42 PM PDT 24
Peak memory 216964 kb
Host smart-e65e75c3-2447-4148-b920-1c82866b4c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706194734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1706194734
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.405651891
Short name T946
Test name
Test status
Simulation time 77017628 ps
CPU time 2.88 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:28:42 PM PDT 24
Peak memory 216772 kb
Host smart-9d642b52-067a-4d11-a7c9-31c8d409a8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405651891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.405651891
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1749185095
Short name T460
Test name
Test status
Simulation time 98700811 ps
CPU time 1.05 seconds
Started Jun 29 05:28:30 PM PDT 24
Finished Jun 29 05:28:31 PM PDT 24
Peak memory 206452 kb
Host smart-9c95ad9b-c340-4806-be1b-c45c7fcac971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749185095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1749185095
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.990074188
Short name T465
Test name
Test status
Simulation time 397370990 ps
CPU time 3.72 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:28:44 PM PDT 24
Peak memory 233076 kb
Host smart-06c6873e-f218-4ac3-9c80-6ac60bfcd4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990074188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.990074188
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2399860946
Short name T763
Test name
Test status
Simulation time 30777446 ps
CPU time 0.73 seconds
Started Jun 29 05:28:42 PM PDT 24
Finished Jun 29 05:28:43 PM PDT 24
Peak memory 205912 kb
Host smart-4ec251e1-e00d-4afc-9146-27041bb2b4fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399860946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2399860946
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3358656205
Short name T705
Test name
Test status
Simulation time 814305244 ps
CPU time 9.47 seconds
Started Jun 29 05:28:42 PM PDT 24
Finished Jun 29 05:28:52 PM PDT 24
Peak memory 233192 kb
Host smart-4381f686-5c15-4ed6-b338-16bf30eec2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358656205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3358656205
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3415951395
Short name T629
Test name
Test status
Simulation time 17839601 ps
CPU time 0.82 seconds
Started Jun 29 05:28:37 PM PDT 24
Finished Jun 29 05:28:39 PM PDT 24
Peak memory 207424 kb
Host smart-d341ca16-ca41-4006-9d6b-e535289327b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415951395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3415951395
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.780799494
Short name T190
Test name
Test status
Simulation time 2088109080 ps
CPU time 37.8 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:29:17 PM PDT 24
Peak memory 249520 kb
Host smart-4d69668a-b53b-4360-8f31-2d28ef7b76c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780799494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.780799494
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1951597759
Short name T797
Test name
Test status
Simulation time 31526101259 ps
CPU time 130.91 seconds
Started Jun 29 05:28:36 PM PDT 24
Finished Jun 29 05:30:47 PM PDT 24
Peak memory 265492 kb
Host smart-1c2a1f56-a20f-45d6-81b1-04a2271d8ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951597759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1951597759
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1501187843
Short name T212
Test name
Test status
Simulation time 6869131422 ps
CPU time 101.42 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:30:21 PM PDT 24
Peak memory 256432 kb
Host smart-62402279-a273-4fe4-b596-e88807e0243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501187843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1501187843
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.449295266
Short name T313
Test name
Test status
Simulation time 609941738 ps
CPU time 12.48 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:28:52 PM PDT 24
Peak memory 224968 kb
Host smart-393de9af-5eff-4f87-b44c-4de294f67e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449295266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.449295266
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2020144966
Short name T635
Test name
Test status
Simulation time 3460004341 ps
CPU time 50.92 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:29:31 PM PDT 24
Peak memory 250056 kb
Host smart-63c8844c-e6e0-4c5e-b685-a7da4e73e2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020144966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2020144966
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1811177601
Short name T993
Test name
Test status
Simulation time 1229902154 ps
CPU time 5.6 seconds
Started Jun 29 05:28:37 PM PDT 24
Finished Jun 29 05:28:43 PM PDT 24
Peak memory 224980 kb
Host smart-9b0d9c4d-872a-4caa-b4c0-718642bdd097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811177601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1811177601
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.744994782
Short name T975
Test name
Test status
Simulation time 1853781798 ps
CPU time 28.1 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:29:07 PM PDT 24
Peak memory 225020 kb
Host smart-32d3dbdc-dfdd-4279-bd6a-206f77e6a583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744994782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.744994782
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3803635496
Short name T344
Test name
Test status
Simulation time 274609149 ps
CPU time 2.28 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:28:43 PM PDT 24
Peak memory 224980 kb
Host smart-a357f15f-128f-445b-aa44-1e5c2cf64d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803635496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3803635496
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1997923640
Short name T581
Test name
Test status
Simulation time 1896019221 ps
CPU time 5.46 seconds
Started Jun 29 05:28:37 PM PDT 24
Finished Jun 29 05:28:43 PM PDT 24
Peak memory 233188 kb
Host smart-497c0a27-9b53-4393-8f45-703fb79f36cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997923640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1997923640
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2707287741
Short name T395
Test name
Test status
Simulation time 443336212 ps
CPU time 4.32 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:28:43 PM PDT 24
Peak memory 221160 kb
Host smart-9b51c2ec-9ce8-4404-b21b-58c2c89a661f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2707287741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2707287741
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.794587345
Short name T167
Test name
Test status
Simulation time 93179698 ps
CPU time 0.94 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:28:40 PM PDT 24
Peak memory 207380 kb
Host smart-ba5b247f-5f88-414e-8f52-711029bdf783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794587345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.794587345
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2852417875
Short name T840
Test name
Test status
Simulation time 537188709 ps
CPU time 2.39 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:28:43 PM PDT 24
Peak memory 219588 kb
Host smart-e4b4be27-632d-4312-a623-37d5bf8370b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852417875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2852417875
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.984291863
Short name T427
Test name
Test status
Simulation time 2829375923 ps
CPU time 7.63 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:28:48 PM PDT 24
Peak memory 216888 kb
Host smart-844c6705-b49b-4e67-970c-0066757a5926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984291863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.984291863
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1853189982
Short name T330
Test name
Test status
Simulation time 94619706 ps
CPU time 3.27 seconds
Started Jun 29 05:28:37 PM PDT 24
Finished Jun 29 05:28:41 PM PDT 24
Peak memory 216792 kb
Host smart-b3119ae6-b876-4dfc-8b41-881785d38f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853189982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1853189982
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.562603093
Short name T363
Test name
Test status
Simulation time 490292426 ps
CPU time 0.92 seconds
Started Jun 29 05:28:37 PM PDT 24
Finished Jun 29 05:28:38 PM PDT 24
Peak memory 206448 kb
Host smart-0478cc02-0d30-47b8-b057-e5a7dcc2118c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562603093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.562603093
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1549148995
Short name T260
Test name
Test status
Simulation time 5977736010 ps
CPU time 14.09 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:28:54 PM PDT 24
Peak memory 225140 kb
Host smart-8653c368-9c55-42fa-973e-14497fcffff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549148995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1549148995
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3146767061
Short name T145
Test name
Test status
Simulation time 44765296 ps
CPU time 0.74 seconds
Started Jun 29 05:28:37 PM PDT 24
Finished Jun 29 05:28:38 PM PDT 24
Peak memory 205964 kb
Host smart-fad85112-e4a4-46a2-a27c-bb8352d549ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146767061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3146767061
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1811339820
Short name T259
Test name
Test status
Simulation time 111155474 ps
CPU time 2.43 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:28:43 PM PDT 24
Peak memory 224616 kb
Host smart-2443b5f2-3695-4c44-baa0-ca881d12a9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811339820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1811339820
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2487459386
Short name T377
Test name
Test status
Simulation time 194254284 ps
CPU time 0.84 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:28:41 PM PDT 24
Peak memory 207016 kb
Host smart-c411a52b-32c1-49f5-8272-20f21d125486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487459386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2487459386
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.4188619667
Short name T858
Test name
Test status
Simulation time 6573070877 ps
CPU time 47.71 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:29:28 PM PDT 24
Peak memory 241540 kb
Host smart-01087aaf-50be-433c-86d8-8d59174cc2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188619667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.4188619667
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2727396756
Short name T785
Test name
Test status
Simulation time 88511601726 ps
CPU time 229.16 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:32:28 PM PDT 24
Peak memory 249848 kb
Host smart-a5af20e7-1885-4bd8-882b-19f0a558ed0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727396756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2727396756
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.253493922
Short name T887
Test name
Test status
Simulation time 289194469739 ps
CPU time 725.07 seconds
Started Jun 29 05:28:41 PM PDT 24
Finished Jun 29 05:40:46 PM PDT 24
Peak memory 266244 kb
Host smart-0aa19072-2821-4816-abdc-9eaff994a44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253493922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.253493922
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3005864659
Short name T1015
Test name
Test status
Simulation time 6330914556 ps
CPU time 10.68 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:28:50 PM PDT 24
Peak memory 233308 kb
Host smart-32938e7f-ad14-4bd2-8c6b-167a666813d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005864659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3005864659
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3415339102
Short name T96
Test name
Test status
Simulation time 31780941098 ps
CPU time 75.18 seconds
Started Jun 29 05:28:40 PM PDT 24
Finished Jun 29 05:29:56 PM PDT 24
Peak memory 252412 kb
Host smart-629eb2be-e476-4080-b323-19bc41f8755d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415339102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3415339102
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2960391504
Short name T989
Test name
Test status
Simulation time 2753443462 ps
CPU time 24.05 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:29:04 PM PDT 24
Peak memory 233332 kb
Host smart-e48e2095-1087-4d58-ae89-f5b1fba4bb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960391504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2960391504
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1671643960
Short name T632
Test name
Test status
Simulation time 19820398018 ps
CPU time 45.35 seconds
Started Jun 29 05:28:36 PM PDT 24
Finished Jun 29 05:29:22 PM PDT 24
Peak memory 233280 kb
Host smart-7d81e699-8f3c-4559-a6d6-904c10e561bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671643960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1671643960
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.282830208
Short name T735
Test name
Test status
Simulation time 2968786586 ps
CPU time 13.96 seconds
Started Jun 29 05:28:41 PM PDT 24
Finished Jun 29 05:28:56 PM PDT 24
Peak memory 233328 kb
Host smart-fd90f9aa-6dc3-4836-8b00-81630ea4cbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282830208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.282830208
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1476066976
Short name T484
Test name
Test status
Simulation time 263104137 ps
CPU time 2.71 seconds
Started Jun 29 05:28:36 PM PDT 24
Finished Jun 29 05:28:39 PM PDT 24
Peak memory 225040 kb
Host smart-25b561e1-b257-4145-a44c-031147bc2b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476066976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1476066976
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3054908490
Short name T847
Test name
Test status
Simulation time 2072905517 ps
CPU time 6.48 seconds
Started Jun 29 05:28:43 PM PDT 24
Finished Jun 29 05:28:50 PM PDT 24
Peak memory 222488 kb
Host smart-b2821cb2-fd1d-4ac5-8527-cd4d8eb729a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3054908490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3054908490
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.839987571
Short name T996
Test name
Test status
Simulation time 270778064249 ps
CPU time 354.94 seconds
Started Jun 29 05:28:41 PM PDT 24
Finished Jun 29 05:34:37 PM PDT 24
Peak memory 274324 kb
Host smart-58422c60-597f-41fa-80f4-225b9d3e910b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839987571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.839987571
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1932443135
Short name T582
Test name
Test status
Simulation time 34041093778 ps
CPU time 24.06 seconds
Started Jun 29 05:28:42 PM PDT 24
Finished Jun 29 05:29:06 PM PDT 24
Peak memory 216968 kb
Host smart-90d831c2-7315-466a-bdb5-4bab17517857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932443135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1932443135
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2826633910
Short name T352
Test name
Test status
Simulation time 54221935360 ps
CPU time 24.79 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:29:04 PM PDT 24
Peak memory 217072 kb
Host smart-c3182cc3-b99d-44d2-bdcf-c09a9a6bfbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826633910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2826633910
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2213669171
Short name T873
Test name
Test status
Simulation time 214588088 ps
CPU time 1.36 seconds
Started Jun 29 05:28:40 PM PDT 24
Finished Jun 29 05:28:42 PM PDT 24
Peak memory 216788 kb
Host smart-a637e641-1060-42c2-9a53-a2b121501290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213669171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2213669171
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.4072361781
Short name T478
Test name
Test status
Simulation time 154578722 ps
CPU time 0.99 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:28:41 PM PDT 24
Peak memory 206500 kb
Host smart-f8e66f87-24de-472d-a739-a997f1e1b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072361781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.4072361781
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1879910869
Short name T588
Test name
Test status
Simulation time 1596129839 ps
CPU time 9.24 seconds
Started Jun 29 05:28:39 PM PDT 24
Finished Jun 29 05:28:49 PM PDT 24
Peak memory 224964 kb
Host smart-8ff31d2f-7f6b-4ee0-83a1-a8cf9c9fd3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879910869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1879910869
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3719780247
Short name T459
Test name
Test status
Simulation time 20912102 ps
CPU time 0.73 seconds
Started Jun 29 05:27:26 PM PDT 24
Finished Jun 29 05:27:27 PM PDT 24
Peak memory 205952 kb
Host smart-7790092b-0181-4f3d-9dd3-8c2127be1f21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719780247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
719780247
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.896645886
Short name T382
Test name
Test status
Simulation time 94164189 ps
CPU time 2.93 seconds
Started Jun 29 05:27:18 PM PDT 24
Finished Jun 29 05:27:23 PM PDT 24
Peak memory 233176 kb
Host smart-f3829524-dbdb-466f-b314-c01bda22b8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896645886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.896645886
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3944183651
Short name T844
Test name
Test status
Simulation time 41462569 ps
CPU time 0.77 seconds
Started Jun 29 05:27:10 PM PDT 24
Finished Jun 29 05:27:11 PM PDT 24
Peak memory 206060 kb
Host smart-88f69258-9ef3-46bf-8020-add3fea7c7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944183651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3944183651
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2140777036
Short name T211
Test name
Test status
Simulation time 94607331785 ps
CPU time 91.98 seconds
Started Jun 29 05:27:17 PM PDT 24
Finished Jun 29 05:28:51 PM PDT 24
Peak memory 233840 kb
Host smart-70dc602c-9599-49b1-8474-8a3be85a65de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140777036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2140777036
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3456349023
Short name T462
Test name
Test status
Simulation time 144527686 ps
CPU time 2.25 seconds
Started Jun 29 05:27:25 PM PDT 24
Finished Jun 29 05:27:28 PM PDT 24
Peak memory 224960 kb
Host smart-0571c34b-0052-4831-9b77-b982a353764f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456349023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3456349023
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.116648541
Short name T728
Test name
Test status
Simulation time 2920479688 ps
CPU time 37.49 seconds
Started Jun 29 05:27:15 PM PDT 24
Finished Jun 29 05:27:53 PM PDT 24
Peak memory 236852 kb
Host smart-6ed66cbe-7971-4472-9670-1b3ba6e8dd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116648541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
116648541
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1067954072
Short name T510
Test name
Test status
Simulation time 919689559 ps
CPU time 4.03 seconds
Started Jun 29 05:27:10 PM PDT 24
Finished Jun 29 05:27:14 PM PDT 24
Peak memory 233184 kb
Host smart-4b09c1e6-4e49-4795-a394-0d65e07cc6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067954072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1067954072
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.791239648
Short name T889
Test name
Test status
Simulation time 13790406221 ps
CPU time 109.19 seconds
Started Jun 29 05:27:09 PM PDT 24
Finished Jun 29 05:28:59 PM PDT 24
Peak memory 251384 kb
Host smart-854cb45a-4dc7-4e6a-a583-1a34a329a89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791239648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.791239648
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1116747269
Short name T674
Test name
Test status
Simulation time 1320140570 ps
CPU time 8.63 seconds
Started Jun 29 05:27:12 PM PDT 24
Finished Jun 29 05:27:21 PM PDT 24
Peak memory 224972 kb
Host smart-6a68c0dd-4303-44c5-bc34-f9f64fc44ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116747269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1116747269
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.8959816
Short name T452
Test name
Test status
Simulation time 1442852501 ps
CPU time 6.58 seconds
Started Jun 29 05:27:09 PM PDT 24
Finished Jun 29 05:27:16 PM PDT 24
Peak memory 233132 kb
Host smart-17ef5688-63cf-423a-bc15-17a150931c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8959816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.8959816
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1837979838
Short name T794
Test name
Test status
Simulation time 736416922 ps
CPU time 5.8 seconds
Started Jun 29 05:27:11 PM PDT 24
Finished Jun 29 05:27:17 PM PDT 24
Peak memory 219532 kb
Host smart-01c6a760-1bc3-4906-b162-0395aa0d7599
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1837979838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1837979838
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3065289504
Short name T69
Test name
Test status
Simulation time 184157149 ps
CPU time 1.19 seconds
Started Jun 29 05:27:17 PM PDT 24
Finished Jun 29 05:27:20 PM PDT 24
Peak memory 236416 kb
Host smart-b4dee924-9479-41c6-87c5-544a2e0cbe57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065289504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3065289504
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1194000773
Short name T57
Test name
Test status
Simulation time 179458202911 ps
CPU time 470.97 seconds
Started Jun 29 05:27:11 PM PDT 24
Finished Jun 29 05:35:03 PM PDT 24
Peak memory 282556 kb
Host smart-e0d26ce9-f7f4-49b1-8298-26502a219c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194000773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1194000773
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3952475948
Short name T545
Test name
Test status
Simulation time 1612285423 ps
CPU time 9.54 seconds
Started Jun 29 05:27:16 PM PDT 24
Finished Jun 29 05:27:26 PM PDT 24
Peak memory 216796 kb
Host smart-2eba8b74-134f-4c62-9c30-bb9c0c153550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952475948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3952475948
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2074669295
Short name T403
Test name
Test status
Simulation time 1710986818 ps
CPU time 5.25 seconds
Started Jun 29 05:27:14 PM PDT 24
Finished Jun 29 05:27:19 PM PDT 24
Peak memory 216812 kb
Host smart-341fb011-c7b9-4206-aab2-a963ad5b91ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074669295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2074669295
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2449595458
Short name T35
Test name
Test status
Simulation time 561814401 ps
CPU time 1.85 seconds
Started Jun 29 05:27:16 PM PDT 24
Finished Jun 29 05:27:18 PM PDT 24
Peak memory 216820 kb
Host smart-3022fb96-1fa4-4c6b-9bbf-d7286f7bd0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449595458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2449595458
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1478352593
Short name T958
Test name
Test status
Simulation time 33900404 ps
CPU time 0.85 seconds
Started Jun 29 05:27:16 PM PDT 24
Finished Jun 29 05:27:17 PM PDT 24
Peak memory 206460 kb
Host smart-e56839f9-def1-4b2b-a39d-31ac497f20f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478352593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1478352593
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.237983555
Short name T801
Test name
Test status
Simulation time 2219926317 ps
CPU time 7.77 seconds
Started Jun 29 05:27:21 PM PDT 24
Finished Jun 29 05:27:29 PM PDT 24
Peak memory 225128 kb
Host smart-9cd51069-45ad-4883-9793-3e763c49629c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237983555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.237983555
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2452229612
Short name T61
Test name
Test status
Simulation time 47216046 ps
CPU time 0.74 seconds
Started Jun 29 05:28:48 PM PDT 24
Finished Jun 29 05:28:50 PM PDT 24
Peak memory 205932 kb
Host smart-db88b448-af1c-469f-95ba-6b5665b28beb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452229612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2452229612
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1878656294
Short name T610
Test name
Test status
Simulation time 289911478 ps
CPU time 4.47 seconds
Started Jun 29 05:28:47 PM PDT 24
Finished Jun 29 05:28:52 PM PDT 24
Peak memory 233076 kb
Host smart-478354f9-477b-400c-b74f-ea23215aabd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878656294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1878656294
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3402855277
Short name T339
Test name
Test status
Simulation time 37383510 ps
CPU time 0.84 seconds
Started Jun 29 05:28:37 PM PDT 24
Finished Jun 29 05:28:39 PM PDT 24
Peak memory 207016 kb
Host smart-a66eaa4f-a362-47e5-88d1-9dab740cd649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402855277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3402855277
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2381524614
Short name T189
Test name
Test status
Simulation time 15553448363 ps
CPU time 119.16 seconds
Started Jun 29 05:28:48 PM PDT 24
Finished Jun 29 05:30:48 PM PDT 24
Peak memory 249732 kb
Host smart-4479bb1a-3cd4-444c-8a23-1eba4c03ebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381524614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2381524614
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1370065220
Short name T272
Test name
Test status
Simulation time 57011794080 ps
CPU time 459.95 seconds
Started Jun 29 05:28:49 PM PDT 24
Finished Jun 29 05:36:30 PM PDT 24
Peak memory 257476 kb
Host smart-a14f7669-0f28-4805-a1da-bcdb324ffeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370065220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1370065220
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.484452810
Short name T389
Test name
Test status
Simulation time 7903586333 ps
CPU time 73.43 seconds
Started Jun 29 05:28:47 PM PDT 24
Finished Jun 29 05:30:02 PM PDT 24
Peak memory 240752 kb
Host smart-fe248f7e-b842-447c-a8f6-4d9e86afa5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484452810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.484452810
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2603062803
Short name T311
Test name
Test status
Simulation time 147947194 ps
CPU time 6.54 seconds
Started Jun 29 05:28:47 PM PDT 24
Finished Jun 29 05:28:55 PM PDT 24
Peak memory 235372 kb
Host smart-81697add-6458-4cea-8955-1b29228434e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603062803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2603062803
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3786944868
Short name T806
Test name
Test status
Simulation time 1100363496 ps
CPU time 6.09 seconds
Started Jun 29 05:28:47 PM PDT 24
Finished Jun 29 05:28:54 PM PDT 24
Peak memory 224960 kb
Host smart-41bc43af-312d-4b16-a428-6f21ac1d14ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786944868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3786944868
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3887695625
Short name T276
Test name
Test status
Simulation time 2163824008 ps
CPU time 19.48 seconds
Started Jun 29 05:28:50 PM PDT 24
Finished Jun 29 05:29:10 PM PDT 24
Peak memory 224964 kb
Host smart-7e04e8d0-fce4-403a-824a-187230266076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887695625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3887695625
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3780282325
Short name T724
Test name
Test status
Simulation time 1701037553 ps
CPU time 10.01 seconds
Started Jun 29 05:28:47 PM PDT 24
Finished Jun 29 05:28:58 PM PDT 24
Peak memory 233208 kb
Host smart-c1c62a84-9271-49a3-a935-600fceeffc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780282325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3780282325
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.100625214
Short name T634
Test name
Test status
Simulation time 372670570 ps
CPU time 5.51 seconds
Started Jun 29 05:28:45 PM PDT 24
Finished Jun 29 05:28:51 PM PDT 24
Peak memory 233232 kb
Host smart-2090ae4f-efb6-49f7-a437-04ea1e6766a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100625214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.100625214
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.465962220
Short name T778
Test name
Test status
Simulation time 454072311 ps
CPU time 3.7 seconds
Started Jun 29 05:28:45 PM PDT 24
Finished Jun 29 05:28:49 PM PDT 24
Peak memory 219964 kb
Host smart-95a70446-09af-4bc4-a34f-26161f6e59d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=465962220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.465962220
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3407179887
Short name T166
Test name
Test status
Simulation time 93680163769 ps
CPU time 127.22 seconds
Started Jun 29 05:28:46 PM PDT 24
Finished Jun 29 05:30:55 PM PDT 24
Peak memory 240216 kb
Host smart-7a672b55-e279-4a1b-85eb-15bb4797e9a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407179887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3407179887
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.963996229
Short name T783
Test name
Test status
Simulation time 11766626946 ps
CPU time 15.26 seconds
Started Jun 29 05:28:42 PM PDT 24
Finished Jun 29 05:28:57 PM PDT 24
Peak memory 216988 kb
Host smart-72c33efd-facd-46f1-84cd-23462ab20479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963996229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.963996229
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1661751161
Short name T931
Test name
Test status
Simulation time 7735744228 ps
CPU time 17.45 seconds
Started Jun 29 05:28:38 PM PDT 24
Finished Jun 29 05:28:57 PM PDT 24
Peak memory 216912 kb
Host smart-9245f755-780c-4298-a339-216cefe7979a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661751161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1661751161
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1583973597
Short name T418
Test name
Test status
Simulation time 319317969 ps
CPU time 1.4 seconds
Started Jun 29 05:28:49 PM PDT 24
Finished Jun 29 05:28:51 PM PDT 24
Peak memory 216704 kb
Host smart-1f08e029-6800-47cb-8734-fe36ef489725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583973597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1583973597
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1625814114
Short name T600
Test name
Test status
Simulation time 55459456 ps
CPU time 0.81 seconds
Started Jun 29 05:28:49 PM PDT 24
Finished Jun 29 05:28:50 PM PDT 24
Peak memory 206476 kb
Host smart-485f217c-977f-4ba6-8eaf-d686670ab374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625814114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1625814114
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3844416374
Short name T174
Test name
Test status
Simulation time 1398991582 ps
CPU time 7.53 seconds
Started Jun 29 05:28:46 PM PDT 24
Finished Jun 29 05:28:55 PM PDT 24
Peak memory 233104 kb
Host smart-6e018c8b-7717-4f2c-b259-1934bc6f04fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844416374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3844416374
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3511925400
Short name T538
Test name
Test status
Simulation time 20277077 ps
CPU time 0.77 seconds
Started Jun 29 05:28:45 PM PDT 24
Finished Jun 29 05:28:47 PM PDT 24
Peak memory 205868 kb
Host smart-d67a4809-70a3-483e-b3cf-bcc6bb43296d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511925400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3511925400
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.210442975
Short name T661
Test name
Test status
Simulation time 34260492 ps
CPU time 2.44 seconds
Started Jun 29 05:28:49 PM PDT 24
Finished Jun 29 05:28:52 PM PDT 24
Peak memory 233208 kb
Host smart-b6e2cc93-9d66-4445-9012-d08338fc5319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210442975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.210442975
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2186274974
Short name T885
Test name
Test status
Simulation time 16021835 ps
CPU time 0.76 seconds
Started Jun 29 05:28:49 PM PDT 24
Finished Jun 29 05:28:50 PM PDT 24
Peak memory 205912 kb
Host smart-00a12c36-510a-48a7-a0b0-f455e4ba9975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186274974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2186274974
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3918855684
Short name T247
Test name
Test status
Simulation time 24670149752 ps
CPU time 171.79 seconds
Started Jun 29 05:28:47 PM PDT 24
Finished Jun 29 05:31:40 PM PDT 24
Peak memory 238324 kb
Host smart-6e210859-b235-4a77-94ad-87ffe4a1b804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918855684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3918855684
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2865598473
Short name T697
Test name
Test status
Simulation time 38828519831 ps
CPU time 122.97 seconds
Started Jun 29 05:28:46 PM PDT 24
Finished Jun 29 05:30:50 PM PDT 24
Peak memory 249844 kb
Host smart-e1f6c585-641f-4453-a857-27f7d1f10364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865598473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2865598473
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.155205695
Short name T296
Test name
Test status
Simulation time 9741881378 ps
CPU time 34.3 seconds
Started Jun 29 05:28:46 PM PDT 24
Finished Jun 29 05:29:21 PM PDT 24
Peak memory 239348 kb
Host smart-0f17c467-a607-4b0e-8d29-c8784373b46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155205695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.155205695
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2136085768
Short name T388
Test name
Test status
Simulation time 207811834 ps
CPU time 7.43 seconds
Started Jun 29 05:28:47 PM PDT 24
Finished Jun 29 05:28:56 PM PDT 24
Peak memory 249828 kb
Host smart-e41b52b9-5aef-460c-8e95-041fd717903f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136085768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2136085768
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.823972393
Short name T216
Test name
Test status
Simulation time 139996881660 ps
CPU time 166.86 seconds
Started Jun 29 05:28:46 PM PDT 24
Finished Jun 29 05:31:33 PM PDT 24
Peak memory 253956 kb
Host smart-2f40d2f7-a754-47de-aa3d-9a8ea037e2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823972393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.823972393
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.441282441
Short name T813
Test name
Test status
Simulation time 1156431225 ps
CPU time 15.15 seconds
Started Jun 29 05:28:46 PM PDT 24
Finished Jun 29 05:29:02 PM PDT 24
Peak memory 233232 kb
Host smart-f014714e-05c5-4824-958a-34bcaa2c1a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441282441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.441282441
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3025841346
Short name T1
Test name
Test status
Simulation time 3404828352 ps
CPU time 13.33 seconds
Started Jun 29 05:28:46 PM PDT 24
Finished Jun 29 05:29:01 PM PDT 24
Peak memory 225084 kb
Host smart-377b67a1-ba06-433f-b672-3dbbdf23d6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025841346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3025841346
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.874052261
Short name T732
Test name
Test status
Simulation time 1082857313 ps
CPU time 7.11 seconds
Started Jun 29 05:28:48 PM PDT 24
Finished Jun 29 05:28:56 PM PDT 24
Peak memory 236340 kb
Host smart-0ed0a8b1-1bc6-4ad9-b8e1-6cba0e1480e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874052261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.874052261
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.816508825
Short name T483
Test name
Test status
Simulation time 463598479 ps
CPU time 2.78 seconds
Started Jun 29 05:28:48 PM PDT 24
Finished Jun 29 05:28:52 PM PDT 24
Peak memory 233152 kb
Host smart-ead3c00f-3888-4476-a965-02a478b38ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816508825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.816508825
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4064807193
Short name T943
Test name
Test status
Simulation time 405215076 ps
CPU time 5.83 seconds
Started Jun 29 05:28:47 PM PDT 24
Finished Jun 29 05:28:54 PM PDT 24
Peak memory 221160 kb
Host smart-3d2fca30-30dc-41ce-873b-fd665c4bb144
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4064807193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4064807193
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3715122204
Short name T65
Test name
Test status
Simulation time 168162887 ps
CPU time 1.01 seconds
Started Jun 29 05:28:45 PM PDT 24
Finished Jun 29 05:28:46 PM PDT 24
Peak memory 207124 kb
Host smart-0afe0828-089f-4d3f-9d53-140d0cdb1b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715122204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3715122204
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.796167835
Short name T25
Test name
Test status
Simulation time 3805525042 ps
CPU time 14.85 seconds
Started Jun 29 05:28:45 PM PDT 24
Finished Jun 29 05:29:01 PM PDT 24
Peak memory 220464 kb
Host smart-eaa838d2-8d9c-4dc5-912a-3d16eb92b763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796167835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.796167835
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3132590241
Short name T865
Test name
Test status
Simulation time 101543722 ps
CPU time 1.46 seconds
Started Jun 29 05:28:47 PM PDT 24
Finished Jun 29 05:28:49 PM PDT 24
Peak memory 208324 kb
Host smart-084b842c-d287-4a5e-8f84-fe0f85deec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132590241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3132590241
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.517235067
Short name T871
Test name
Test status
Simulation time 130488085 ps
CPU time 1.18 seconds
Started Jun 29 05:28:45 PM PDT 24
Finished Jun 29 05:28:47 PM PDT 24
Peak memory 208380 kb
Host smart-4ac81514-0922-4e71-b414-06548879b44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517235067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.517235067
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.593206914
Short name T367
Test name
Test status
Simulation time 57669104 ps
CPU time 0.82 seconds
Started Jun 29 05:28:46 PM PDT 24
Finished Jun 29 05:28:48 PM PDT 24
Peak memory 206448 kb
Host smart-765d1754-4fa7-4ca2-b622-3688d799d5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593206914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.593206914
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2811501501
Short name T436
Test name
Test status
Simulation time 11135688872 ps
CPU time 19.68 seconds
Started Jun 29 05:28:45 PM PDT 24
Finished Jun 29 05:29:05 PM PDT 24
Peak memory 249684 kb
Host smart-35b3873f-f3d0-4921-8e3f-7b43d1cce215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811501501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2811501501
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.498496101
Short name T370
Test name
Test status
Simulation time 52106766 ps
CPU time 0.71 seconds
Started Jun 29 05:29:00 PM PDT 24
Finished Jun 29 05:29:02 PM PDT 24
Peak memory 205984 kb
Host smart-67f34ecd-01b9-4fe2-b01f-9ad7ac2bf559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498496101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.498496101
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.553068258
Short name T775
Test name
Test status
Simulation time 141792065 ps
CPU time 3.67 seconds
Started Jun 29 05:28:47 PM PDT 24
Finished Jun 29 05:28:52 PM PDT 24
Peak memory 224956 kb
Host smart-32a7a51b-5822-4c55-8170-1b630a1205b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553068258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.553068258
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3471764468
Short name T511
Test name
Test status
Simulation time 62703967 ps
CPU time 0.79 seconds
Started Jun 29 05:28:47 PM PDT 24
Finished Jun 29 05:28:49 PM PDT 24
Peak memory 206000 kb
Host smart-9a91c9f1-0ff2-4434-bb35-076e7bc7dcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471764468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3471764468
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1933699707
Short name T917
Test name
Test status
Simulation time 4669722034 ps
CPU time 62.45 seconds
Started Jun 29 05:28:57 PM PDT 24
Finished Jun 29 05:30:01 PM PDT 24
Peak memory 257896 kb
Host smart-8f913001-d271-402f-b2ef-f0713d0101d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933699707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1933699707
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.898750476
Short name T150
Test name
Test status
Simulation time 24668741583 ps
CPU time 257.71 seconds
Started Jun 29 05:28:58 PM PDT 24
Finished Jun 29 05:33:16 PM PDT 24
Peak memory 263720 kb
Host smart-aaf8826f-5dda-4769-ab24-e309df854cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898750476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.898750476
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2069984532
Short name T505
Test name
Test status
Simulation time 1847949982 ps
CPU time 33.91 seconds
Started Jun 29 05:29:01 PM PDT 24
Finished Jun 29 05:29:35 PM PDT 24
Peak memory 255020 kb
Host smart-78c4c1dc-b926-4d88-b696-939ad6f342dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069984532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2069984532
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2373543794
Short name T1005
Test name
Test status
Simulation time 496742670 ps
CPU time 7.13 seconds
Started Jun 29 05:28:57 PM PDT 24
Finished Jun 29 05:29:05 PM PDT 24
Peak memory 230884 kb
Host smart-47f9ae36-1c9a-4846-8941-16626388c57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373543794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2373543794
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2541815055
Short name T711
Test name
Test status
Simulation time 5001802234 ps
CPU time 49.78 seconds
Started Jun 29 05:28:56 PM PDT 24
Finished Jun 29 05:29:46 PM PDT 24
Peak memory 249724 kb
Host smart-8c9302cb-699a-45e6-b5d9-d39bf6c378b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541815055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2541815055
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.418998345
Short name T348
Test name
Test status
Simulation time 2927298837 ps
CPU time 8.8 seconds
Started Jun 29 05:28:46 PM PDT 24
Finished Jun 29 05:28:56 PM PDT 24
Peak memory 233348 kb
Host smart-d1a83189-2a9e-4c9d-8425-6f0877e01a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418998345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.418998345
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.4079713351
Short name T264
Test name
Test status
Simulation time 4084438898 ps
CPU time 17.83 seconds
Started Jun 29 05:28:47 PM PDT 24
Finished Jun 29 05:29:06 PM PDT 24
Peak memory 233520 kb
Host smart-ba6e085e-636f-4d2b-b492-3f86a8a19cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079713351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4079713351
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1842921418
Short name T531
Test name
Test status
Simulation time 7811839568 ps
CPU time 17.92 seconds
Started Jun 29 05:28:48 PM PDT 24
Finished Jun 29 05:29:07 PM PDT 24
Peak memory 225052 kb
Host smart-df160749-2e67-40e5-9b30-4fac2c0196bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842921418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1842921418
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4087973031
Short name T430
Test name
Test status
Simulation time 49360718 ps
CPU time 2.85 seconds
Started Jun 29 05:28:47 PM PDT 24
Finished Jun 29 05:28:51 PM PDT 24
Peak memory 233164 kb
Host smart-7da261ea-b52b-4cfb-abd8-71ea47c58f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087973031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4087973031
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3060381421
Short name T990
Test name
Test status
Simulation time 4217416171 ps
CPU time 22.1 seconds
Started Jun 29 05:28:58 PM PDT 24
Finished Jun 29 05:29:21 PM PDT 24
Peak memory 219920 kb
Host smart-08682356-f603-455a-9b3a-17cb884388ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3060381421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3060381421
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2358585767
Short name T570
Test name
Test status
Simulation time 42376994268 ps
CPU time 151.9 seconds
Started Jun 29 05:28:57 PM PDT 24
Finished Jun 29 05:31:29 PM PDT 24
Peak memory 257344 kb
Host smart-d047e3f2-2b58-4d69-9524-3b4f8b5f2083
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358585767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2358585767
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.453266929
Short name T320
Test name
Test status
Simulation time 1501704045 ps
CPU time 22 seconds
Started Jun 29 05:28:46 PM PDT 24
Finished Jun 29 05:29:08 PM PDT 24
Peak memory 220056 kb
Host smart-e3f06c03-c49d-4640-956f-5bbd6a724276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453266929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.453266929
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1142231892
Short name T638
Test name
Test status
Simulation time 39615376 ps
CPU time 0.71 seconds
Started Jun 29 05:28:46 PM PDT 24
Finished Jun 29 05:28:48 PM PDT 24
Peak memory 206184 kb
Host smart-f9e3ff27-8b1a-4740-bab5-111310e58d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142231892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1142231892
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.227783472
Short name T71
Test name
Test status
Simulation time 253987436 ps
CPU time 4.43 seconds
Started Jun 29 05:28:48 PM PDT 24
Finished Jun 29 05:28:53 PM PDT 24
Peak memory 216824 kb
Host smart-b94554b2-03de-4856-b02e-4b3531bfe5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227783472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.227783472
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.4046789927
Short name T506
Test name
Test status
Simulation time 27176017 ps
CPU time 0.77 seconds
Started Jun 29 05:28:49 PM PDT 24
Finished Jun 29 05:28:51 PM PDT 24
Peak memory 206336 kb
Host smart-a1291c8e-70b5-4c23-9108-a2ca8e24525b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046789927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.4046789927
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1453734655
Short name T745
Test name
Test status
Simulation time 1775566297 ps
CPU time 5 seconds
Started Jun 29 05:28:49 PM PDT 24
Finished Jun 29 05:28:55 PM PDT 24
Peak memory 233184 kb
Host smart-839d19e4-af20-4e9e-8f54-dfeb653b43ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453734655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1453734655
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.939879541
Short name T750
Test name
Test status
Simulation time 43949778 ps
CPU time 0.73 seconds
Started Jun 29 05:28:55 PM PDT 24
Finished Jun 29 05:28:56 PM PDT 24
Peak memory 205980 kb
Host smart-94a4134b-656f-4907-9c4f-71aa2ab01966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939879541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.939879541
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3438800198
Short name T779
Test name
Test status
Simulation time 275620503 ps
CPU time 2.34 seconds
Started Jun 29 05:28:55 PM PDT 24
Finished Jun 29 05:28:58 PM PDT 24
Peak memory 232984 kb
Host smart-67c27d8c-3654-4de2-80a0-528ff113f32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438800198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3438800198
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.370414583
Short name T26
Test name
Test status
Simulation time 14819145 ps
CPU time 0.8 seconds
Started Jun 29 05:28:58 PM PDT 24
Finished Jun 29 05:28:59 PM PDT 24
Peak memory 206088 kb
Host smart-ca6000f2-9897-4336-90e1-994a953d6bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370414583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.370414583
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3258293196
Short name T940
Test name
Test status
Simulation time 28580589938 ps
CPU time 129.24 seconds
Started Jun 29 05:28:57 PM PDT 24
Finished Jun 29 05:31:08 PM PDT 24
Peak memory 256248 kb
Host smart-6dbadf70-5fc1-4853-a0d5-ad620f5bec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258293196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3258293196
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2572460763
Short name T42
Test name
Test status
Simulation time 27482448395 ps
CPU time 34.06 seconds
Started Jun 29 05:28:59 PM PDT 24
Finished Jun 29 05:29:33 PM PDT 24
Peak memory 238996 kb
Host smart-c68318d7-08f0-4375-a151-0416acfe9bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572460763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2572460763
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3646387123
Short name T75
Test name
Test status
Simulation time 16633766396 ps
CPU time 60.34 seconds
Started Jun 29 05:28:57 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 266228 kb
Host smart-fb153e3b-c2bc-4dc4-9469-e2cc461eefa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646387123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3646387123
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3098665593
Short name T573
Test name
Test status
Simulation time 654117376 ps
CPU time 4.97 seconds
Started Jun 29 05:28:57 PM PDT 24
Finished Jun 29 05:29:03 PM PDT 24
Peak memory 225008 kb
Host smart-5f593815-fc6a-4439-a9ac-6768e09170bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098665593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3098665593
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.415094489
Short name T607
Test name
Test status
Simulation time 38945396578 ps
CPU time 74.92 seconds
Started Jun 29 05:28:57 PM PDT 24
Finished Jun 29 05:30:13 PM PDT 24
Peak memory 251000 kb
Host smart-86cdc53f-1ad9-466f-b281-b19cdf3ef729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415094489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.415094489
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3382992670
Short name T603
Test name
Test status
Simulation time 134392201 ps
CPU time 4.33 seconds
Started Jun 29 05:28:57 PM PDT 24
Finished Jun 29 05:29:02 PM PDT 24
Peak memory 225024 kb
Host smart-ad1d6b00-8e0c-495c-9e7a-1409bcb96715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382992670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3382992670
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2383820483
Short name T1007
Test name
Test status
Simulation time 1313870938 ps
CPU time 8.9 seconds
Started Jun 29 05:28:57 PM PDT 24
Finished Jun 29 05:29:07 PM PDT 24
Peak memory 235676 kb
Host smart-dbf78d5e-8b97-4d9a-940e-f3b9e1e37fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383820483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2383820483
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3063869170
Short name T981
Test name
Test status
Simulation time 289672820 ps
CPU time 2.72 seconds
Started Jun 29 05:28:56 PM PDT 24
Finished Jun 29 05:29:00 PM PDT 24
Peak memory 224876 kb
Host smart-9314b57d-6e16-4362-a3c0-ea08d12ac16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063869170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3063869170
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1914155565
Short name T656
Test name
Test status
Simulation time 4817754805 ps
CPU time 9.06 seconds
Started Jun 29 05:29:00 PM PDT 24
Finished Jun 29 05:29:10 PM PDT 24
Peak memory 233284 kb
Host smart-065e482c-25f3-406c-b41f-2b0edee7b952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914155565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1914155565
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3990217079
Short name T456
Test name
Test status
Simulation time 762225780 ps
CPU time 7.52 seconds
Started Jun 29 05:28:59 PM PDT 24
Finished Jun 29 05:29:07 PM PDT 24
Peak memory 221024 kb
Host smart-8ee7f47d-97ac-4e71-a50b-27df4fbf3fe9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3990217079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3990217079
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3371001498
Short name T144
Test name
Test status
Simulation time 3213162074 ps
CPU time 16.29 seconds
Started Jun 29 05:28:58 PM PDT 24
Finished Jun 29 05:29:15 PM PDT 24
Peak memory 233432 kb
Host smart-dcfdf3c0-3f3b-427d-9b1d-cfc47a27addd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371001498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3371001498
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1315041865
Short name T504
Test name
Test status
Simulation time 7190919503 ps
CPU time 14.65 seconds
Started Jun 29 05:28:55 PM PDT 24
Finished Jun 29 05:29:10 PM PDT 24
Peak memory 217120 kb
Host smart-81d1a377-f97e-4c56-9750-5bd406c6951b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315041865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1315041865
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1399272685
Short name T432
Test name
Test status
Simulation time 129054291 ps
CPU time 1.13 seconds
Started Jun 29 05:28:57 PM PDT 24
Finished Jun 29 05:28:59 PM PDT 24
Peak memory 207616 kb
Host smart-544372ec-7422-44c0-b9b9-fd5b15f8bccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399272685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1399272685
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1212208078
Short name T329
Test name
Test status
Simulation time 109693648 ps
CPU time 1.08 seconds
Started Jun 29 05:28:57 PM PDT 24
Finished Jun 29 05:28:58 PM PDT 24
Peak memory 208372 kb
Host smart-1d1df9a6-d71f-4f8e-9d40-767a70e52f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212208078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1212208078
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.944991063
Short name T590
Test name
Test status
Simulation time 218792040 ps
CPU time 0.77 seconds
Started Jun 29 05:28:58 PM PDT 24
Finished Jun 29 05:29:00 PM PDT 24
Peak memory 206452 kb
Host smart-934d058d-0d83-4386-b489-43432f39a92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944991063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.944991063
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2935700698
Short name T224
Test name
Test status
Simulation time 5218701321 ps
CPU time 6.14 seconds
Started Jun 29 05:28:56 PM PDT 24
Finished Jun 29 05:29:03 PM PDT 24
Peak memory 225008 kb
Host smart-1c9d65cf-685b-4894-97b0-80985764458e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935700698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2935700698
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3410801911
Short name T520
Test name
Test status
Simulation time 10889114 ps
CPU time 0.71 seconds
Started Jun 29 05:29:01 PM PDT 24
Finished Jun 29 05:29:03 PM PDT 24
Peak memory 205896 kb
Host smart-732fedda-554d-4562-9d43-63ad43a2ece4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410801911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3410801911
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.575078454
Short name T596
Test name
Test status
Simulation time 1877650685 ps
CPU time 8.74 seconds
Started Jun 29 05:28:57 PM PDT 24
Finished Jun 29 05:29:06 PM PDT 24
Peak memory 233204 kb
Host smart-38bd132f-ceb1-4bc3-aaa7-8ef5adda2bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575078454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.575078454
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3182127578
Short name T648
Test name
Test status
Simulation time 37796832 ps
CPU time 0.81 seconds
Started Jun 29 05:28:58 PM PDT 24
Finished Jun 29 05:29:00 PM PDT 24
Peak memory 207088 kb
Host smart-76031102-6063-41e7-8ca8-4e2f0bcc2c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182127578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3182127578
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3558973245
Short name T716
Test name
Test status
Simulation time 6759911523 ps
CPU time 30.77 seconds
Started Jun 29 05:29:03 PM PDT 24
Finished Jun 29 05:29:34 PM PDT 24
Peak memory 225140 kb
Host smart-bd568f6f-6a07-4793-a5c3-eff2bf50351a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558973245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3558973245
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1203165056
Short name T792
Test name
Test status
Simulation time 11262880961 ps
CPU time 85.58 seconds
Started Jun 29 05:29:00 PM PDT 24
Finished Jun 29 05:30:26 PM PDT 24
Peak memory 256688 kb
Host smart-df502c85-49e8-45e3-af0a-1e9ec976ca95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203165056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1203165056
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.873794068
Short name T290
Test name
Test status
Simulation time 15158376739 ps
CPU time 80.15 seconds
Started Jun 29 05:29:03 PM PDT 24
Finished Jun 29 05:30:24 PM PDT 24
Peak memory 249888 kb
Host smart-0b81b626-0b6b-4dd1-b56c-d6431902b053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873794068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.873794068
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.525075238
Short name T303
Test name
Test status
Simulation time 1598447695 ps
CPU time 12.18 seconds
Started Jun 29 05:29:00 PM PDT 24
Finished Jun 29 05:29:13 PM PDT 24
Peak memory 233248 kb
Host smart-23af3d58-53e7-4021-bb55-e2cdbbb6da57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525075238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.525075238
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3336614504
Short name T302
Test name
Test status
Simulation time 12800784257 ps
CPU time 45.11 seconds
Started Jun 29 05:28:59 PM PDT 24
Finished Jun 29 05:29:45 PM PDT 24
Peak memory 250188 kb
Host smart-67796726-70dc-4742-8cd2-7498bd269cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336614504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3336614504
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3032095791
Short name T201
Test name
Test status
Simulation time 374001337 ps
CPU time 4.78 seconds
Started Jun 29 05:28:55 PM PDT 24
Finished Jun 29 05:29:00 PM PDT 24
Peak memory 224880 kb
Host smart-f98807e5-dc2e-4df7-ac2c-3da98f9640fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032095791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3032095791
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1806086643
Short name T139
Test name
Test status
Simulation time 842406423 ps
CPU time 7.51 seconds
Started Jun 29 05:28:56 PM PDT 24
Finished Jun 29 05:29:04 PM PDT 24
Peak memory 240644 kb
Host smart-82377336-cf2f-418a-a02e-224e371352ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806086643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1806086643
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1312943398
Short name T288
Test name
Test status
Simulation time 13220962021 ps
CPU time 29.6 seconds
Started Jun 29 05:28:58 PM PDT 24
Finished Jun 29 05:29:29 PM PDT 24
Peak memory 234716 kb
Host smart-60ba3dae-4a36-40e5-9ef2-0b4ee962bd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312943398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1312943398
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2460773930
Short name T47
Test name
Test status
Simulation time 13092893869 ps
CPU time 12.42 seconds
Started Jun 29 05:29:00 PM PDT 24
Finished Jun 29 05:29:12 PM PDT 24
Peak memory 234032 kb
Host smart-5514a9ec-9b19-4286-935e-eb3fe0cafef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460773930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2460773930
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2987077604
Short name T956
Test name
Test status
Simulation time 1446333144 ps
CPU time 8.48 seconds
Started Jun 29 05:28:58 PM PDT 24
Finished Jun 29 05:29:07 PM PDT 24
Peak memory 221060 kb
Host smart-1a272e73-ef37-4cc8-bf11-e38850fa5cde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2987077604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2987077604
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2940545252
Short name T770
Test name
Test status
Simulation time 75619612 ps
CPU time 1.02 seconds
Started Jun 29 05:29:06 PM PDT 24
Finished Jun 29 05:29:08 PM PDT 24
Peak memory 207400 kb
Host smart-d5864a9a-b5aa-4788-9c00-bacaeff1c20b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940545252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2940545252
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3200903985
Short name T497
Test name
Test status
Simulation time 3140203020 ps
CPU time 25.09 seconds
Started Jun 29 05:28:58 PM PDT 24
Finished Jun 29 05:29:24 PM PDT 24
Peak memory 216956 kb
Host smart-db0d1176-deac-42ba-9a4e-19054b7d40d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200903985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3200903985
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2341029271
Short name T688
Test name
Test status
Simulation time 966406467 ps
CPU time 4.96 seconds
Started Jun 29 05:29:00 PM PDT 24
Finished Jun 29 05:29:05 PM PDT 24
Peak memory 216828 kb
Host smart-9b924e62-d060-4b43-8248-9ce4e72e6760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341029271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2341029271
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1478709778
Short name T568
Test name
Test status
Simulation time 146889814 ps
CPU time 1.23 seconds
Started Jun 29 05:28:59 PM PDT 24
Finished Jun 29 05:29:01 PM PDT 24
Peak memory 208380 kb
Host smart-6046a917-9de8-4198-95ba-579d4e9ed528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478709778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1478709778
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.307554346
Short name T818
Test name
Test status
Simulation time 52678612 ps
CPU time 0.74 seconds
Started Jun 29 05:28:58 PM PDT 24
Finished Jun 29 05:29:00 PM PDT 24
Peak memory 206452 kb
Host smart-d0c2e12a-c047-45d2-aa23-2113ddf19a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307554346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.307554346
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3999168296
Short name T215
Test name
Test status
Simulation time 1160193693 ps
CPU time 5.96 seconds
Started Jun 29 05:29:00 PM PDT 24
Finished Jun 29 05:29:07 PM PDT 24
Peak memory 233192 kb
Host smart-9184e601-66a6-4c26-9a1f-930598ccb7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999168296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3999168296
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.236913209
Short name T704
Test name
Test status
Simulation time 16374224 ps
CPU time 0.75 seconds
Started Jun 29 05:29:04 PM PDT 24
Finished Jun 29 05:29:05 PM PDT 24
Peak memory 205976 kb
Host smart-3d6a100b-3c5e-4f3c-90dc-9a534dab0152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236913209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.236913209
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3154864997
Short name T574
Test name
Test status
Simulation time 966799811 ps
CPU time 4.25 seconds
Started Jun 29 05:29:05 PM PDT 24
Finished Jun 29 05:29:11 PM PDT 24
Peak memory 224944 kb
Host smart-918d4bc0-5cba-4963-93d7-e30e8c5d2aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154864997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3154864997
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2445641049
Short name T475
Test name
Test status
Simulation time 134481851 ps
CPU time 0.82 seconds
Started Jun 29 05:29:01 PM PDT 24
Finished Jun 29 05:29:03 PM PDT 24
Peak memory 207084 kb
Host smart-73340f4e-0d09-4f18-955c-807ee26a94ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445641049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2445641049
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3836257438
Short name T1002
Test name
Test status
Simulation time 163999125421 ps
CPU time 225.92 seconds
Started Jun 29 05:29:03 PM PDT 24
Finished Jun 29 05:32:50 PM PDT 24
Peak memory 239948 kb
Host smart-431db80c-1555-47ab-ac5b-5eb1ac63eee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836257438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3836257438
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1272871984
Short name T316
Test name
Test status
Simulation time 8841238786 ps
CPU time 13.48 seconds
Started Jun 29 05:29:00 PM PDT 24
Finished Jun 29 05:29:14 PM PDT 24
Peak memory 218480 kb
Host smart-8fc309dc-4c26-4d0f-b890-5750ae665711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272871984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1272871984
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4276291043
Short name T689
Test name
Test status
Simulation time 16194886316 ps
CPU time 43.44 seconds
Started Jun 29 05:29:04 PM PDT 24
Finished Jun 29 05:29:48 PM PDT 24
Peak memory 251968 kb
Host smart-7275d066-c0f1-4ff8-ad53-3cf8b7eac7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276291043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4276291043
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1860014830
Short name T690
Test name
Test status
Simulation time 41783734 ps
CPU time 2.79 seconds
Started Jun 29 05:29:01 PM PDT 24
Finished Jun 29 05:29:05 PM PDT 24
Peak memory 233116 kb
Host smart-2b3685fd-b064-4297-86e0-ad7e6bfb58d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860014830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1860014830
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.244863485
Short name T1012
Test name
Test status
Simulation time 177388408 ps
CPU time 4.03 seconds
Started Jun 29 05:29:05 PM PDT 24
Finished Jun 29 05:29:10 PM PDT 24
Peak memory 224928 kb
Host smart-239f2c9f-8a81-4ab3-83c0-399c574cf6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244863485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.244863485
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.909644727
Short name T880
Test name
Test status
Simulation time 1185410862 ps
CPU time 10.26 seconds
Started Jun 29 05:29:02 PM PDT 24
Finished Jun 29 05:29:13 PM PDT 24
Peak memory 233084 kb
Host smart-7058cb02-6119-47d5-8c1e-5ccf298eba54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909644727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.909644727
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3878135092
Short name T911
Test name
Test status
Simulation time 5458482288 ps
CPU time 17.52 seconds
Started Jun 29 05:29:01 PM PDT 24
Finished Jun 29 05:29:19 PM PDT 24
Peak memory 233256 kb
Host smart-42baaa82-a74a-45ee-85da-03c8d47a154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878135092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3878135092
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.332969680
Short name T516
Test name
Test status
Simulation time 4037240913 ps
CPU time 8.85 seconds
Started Jun 29 05:29:04 PM PDT 24
Finished Jun 29 05:29:14 PM PDT 24
Peak memory 241456 kb
Host smart-367eaa52-b442-4ec8-81b3-991c44dc3289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332969680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.332969680
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.273032316
Short name T650
Test name
Test status
Simulation time 3865658024 ps
CPU time 8.03 seconds
Started Jun 29 05:29:05 PM PDT 24
Finished Jun 29 05:29:14 PM PDT 24
Peak memory 219936 kb
Host smart-cc4f2a67-6221-4273-a0e4-d79557f3d2d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=273032316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.273032316
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.141326167
Short name T553
Test name
Test status
Simulation time 27326773348 ps
CPU time 41.23 seconds
Started Jun 29 05:29:02 PM PDT 24
Finished Jun 29 05:29:44 PM PDT 24
Peak memory 221440 kb
Host smart-80219419-152d-4bd0-ac7d-d553008ba4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141326167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.141326167
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1305238460
Short name T345
Test name
Test status
Simulation time 5298746443 ps
CPU time 15.42 seconds
Started Jun 29 05:29:04 PM PDT 24
Finished Jun 29 05:29:20 PM PDT 24
Peak memory 216944 kb
Host smart-168ea4f3-3865-4f4d-b779-161ea0ae7925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305238460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1305238460
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.68240145
Short name T76
Test name
Test status
Simulation time 247598275 ps
CPU time 2.69 seconds
Started Jun 29 05:29:01 PM PDT 24
Finished Jun 29 05:29:04 PM PDT 24
Peak memory 216760 kb
Host smart-05b8fa8e-5515-46c2-a595-993cd64d4b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68240145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.68240145
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.275694794
Short name T91
Test name
Test status
Simulation time 22752025 ps
CPU time 0.79 seconds
Started Jun 29 05:29:05 PM PDT 24
Finished Jun 29 05:29:07 PM PDT 24
Peak memory 206456 kb
Host smart-ad19ffca-ccf0-49ab-ab60-af84a1cbe72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275694794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.275694794
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.754120691
Short name T903
Test name
Test status
Simulation time 631204415 ps
CPU time 7.51 seconds
Started Jun 29 05:29:06 PM PDT 24
Finished Jun 29 05:29:15 PM PDT 24
Peak memory 233108 kb
Host smart-04d1105d-9a8f-45f2-9df2-13ee372bf8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754120691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.754120691
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.937232325
Short name T528
Test name
Test status
Simulation time 20352230 ps
CPU time 0.7 seconds
Started Jun 29 05:29:05 PM PDT 24
Finished Jun 29 05:29:07 PM PDT 24
Peak memory 205936 kb
Host smart-ee9dbac4-cbc7-4414-a533-020cb4074b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937232325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.937232325
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1142567119
Short name T437
Test name
Test status
Simulation time 1927036652 ps
CPU time 6.62 seconds
Started Jun 29 05:29:02 PM PDT 24
Finished Jun 29 05:29:10 PM PDT 24
Peak memory 224968 kb
Host smart-79668a57-138b-4ae1-b06e-0c312df1755f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142567119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1142567119
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2638841366
Short name T342
Test name
Test status
Simulation time 17866181 ps
CPU time 0.8 seconds
Started Jun 29 05:29:01 PM PDT 24
Finished Jun 29 05:29:02 PM PDT 24
Peak memory 207096 kb
Host smart-119db2d4-914c-4847-aace-3f5535c677f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638841366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2638841366
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3820206295
Short name T725
Test name
Test status
Simulation time 42123836676 ps
CPU time 107.07 seconds
Started Jun 29 05:29:03 PM PDT 24
Finished Jun 29 05:30:51 PM PDT 24
Peak memory 249748 kb
Host smart-2ed2d713-ef8a-4123-96e7-30afc9f5026c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820206295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3820206295
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.35624858
Short name T265
Test name
Test status
Simulation time 28218715555 ps
CPU time 143.5 seconds
Started Jun 29 05:29:03 PM PDT 24
Finished Jun 29 05:31:27 PM PDT 24
Peak memory 249960 kb
Host smart-89e7c03d-77f2-4cdd-a8a1-a6bdea26dadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35624858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.35624858
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1753645808
Short name T759
Test name
Test status
Simulation time 82909670203 ps
CPU time 142.87 seconds
Started Jun 29 05:29:05 PM PDT 24
Finished Jun 29 05:31:29 PM PDT 24
Peak memory 254364 kb
Host smart-93da5004-c935-4af2-86b2-20fdbd989c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753645808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1753645808
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1675735497
Short name T929
Test name
Test status
Simulation time 3728281823 ps
CPU time 80.99 seconds
Started Jun 29 05:29:02 PM PDT 24
Finished Jun 29 05:30:24 PM PDT 24
Peak memory 266240 kb
Host smart-a2f30853-2edc-4a52-8aa9-a75d06ad40a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675735497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1675735497
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1946625457
Short name T252
Test name
Test status
Simulation time 185665791 ps
CPU time 2.41 seconds
Started Jun 29 05:29:05 PM PDT 24
Finished Jun 29 05:29:09 PM PDT 24
Peak memory 233160 kb
Host smart-71047ebc-24ea-468e-8ec4-9c6b13447d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946625457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1946625457
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2000913140
Short name T515
Test name
Test status
Simulation time 13899314060 ps
CPU time 27 seconds
Started Jun 29 05:29:05 PM PDT 24
Finished Jun 29 05:29:33 PM PDT 24
Peak memory 233216 kb
Host smart-5eefe493-cca3-4f29-9df7-b35b1050dd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000913140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2000913140
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.479723192
Short name T723
Test name
Test status
Simulation time 1096783354 ps
CPU time 6.42 seconds
Started Jun 29 05:29:01 PM PDT 24
Finished Jun 29 05:29:08 PM PDT 24
Peak memory 233176 kb
Host smart-163e59af-46e5-4c14-ab8f-906703230c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479723192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.479723192
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3526775868
Short name T10
Test name
Test status
Simulation time 383868283 ps
CPU time 2.39 seconds
Started Jun 29 05:29:00 PM PDT 24
Finished Jun 29 05:29:03 PM PDT 24
Peak memory 233184 kb
Host smart-4bdf050d-09eb-49ef-8996-74079e262f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526775868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3526775868
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2343461925
Short name T894
Test name
Test status
Simulation time 575526171 ps
CPU time 7.69 seconds
Started Jun 29 05:29:02 PM PDT 24
Finished Jun 29 05:29:10 PM PDT 24
Peak memory 219580 kb
Host smart-1948e7fc-a100-48ba-a2b0-e59ebbaec7b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2343461925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2343461925
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1779044386
Short name T662
Test name
Test status
Simulation time 24118166961 ps
CPU time 100.54 seconds
Started Jun 29 05:29:08 PM PDT 24
Finished Jun 29 05:30:50 PM PDT 24
Peak memory 266276 kb
Host smart-ebe8b75c-dd34-4c95-8f20-98a94a29c92c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779044386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1779044386
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1786685219
Short name T836
Test name
Test status
Simulation time 4951872104 ps
CPU time 31.17 seconds
Started Jun 29 05:29:00 PM PDT 24
Finished Jun 29 05:29:32 PM PDT 24
Peak memory 216896 kb
Host smart-5aad891d-8bad-4a24-bd61-eb87b08b6156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786685219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1786685219
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2630701485
Short name T682
Test name
Test status
Simulation time 1013395343 ps
CPU time 5.92 seconds
Started Jun 29 05:29:07 PM PDT 24
Finished Jun 29 05:29:14 PM PDT 24
Peak memory 216692 kb
Host smart-214d5b8a-351d-49e3-8db1-5f52f984bc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630701485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2630701485
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.379588330
Short name T684
Test name
Test status
Simulation time 487491284 ps
CPU time 4.22 seconds
Started Jun 29 05:29:01 PM PDT 24
Finished Jun 29 05:29:06 PM PDT 24
Peak memory 216768 kb
Host smart-0c0cdb7e-b818-466e-bbb8-c4d60e2d418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379588330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.379588330
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3483198608
Short name T623
Test name
Test status
Simulation time 12348008 ps
CPU time 0.72 seconds
Started Jun 29 05:29:05 PM PDT 24
Finished Jun 29 05:29:07 PM PDT 24
Peak memory 206120 kb
Host smart-53fbcc7b-778b-4112-bc20-e211f82afd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483198608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3483198608
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.294187142
Short name T781
Test name
Test status
Simulation time 1175599285 ps
CPU time 10.68 seconds
Started Jun 29 05:29:05 PM PDT 24
Finished Jun 29 05:29:17 PM PDT 24
Peak memory 249000 kb
Host smart-ffc7958a-7221-457c-99f9-c060c2045e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294187142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.294187142
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3818814027
Short name T843
Test name
Test status
Simulation time 14672683 ps
CPU time 0.77 seconds
Started Jun 29 05:29:07 PM PDT 24
Finished Jun 29 05:29:09 PM PDT 24
Peak memory 205912 kb
Host smart-0be3551e-1eca-4928-8ee6-074b88c9c4e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818814027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3818814027
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1591652750
Short name T826
Test name
Test status
Simulation time 156304806 ps
CPU time 4.39 seconds
Started Jun 29 05:29:09 PM PDT 24
Finished Jun 29 05:29:15 PM PDT 24
Peak memory 225016 kb
Host smart-ecaa7a5f-1e62-446a-bd90-507a623aa83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591652750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1591652750
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3020954194
Short name T982
Test name
Test status
Simulation time 46846964 ps
CPU time 0.77 seconds
Started Jun 29 05:29:04 PM PDT 24
Finished Jun 29 05:29:06 PM PDT 24
Peak memory 207424 kb
Host smart-c97777b1-7a15-4962-a810-5be4380dfa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020954194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3020954194
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3688530681
Short name T294
Test name
Test status
Simulation time 30836574774 ps
CPU time 147.38 seconds
Started Jun 29 05:29:10 PM PDT 24
Finished Jun 29 05:31:39 PM PDT 24
Peak memory 249736 kb
Host smart-b63bb737-41e1-4e54-be26-a59206d12363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688530681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3688530681
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1326552874
Short name T27
Test name
Test status
Simulation time 27632816238 ps
CPU time 256.39 seconds
Started Jun 29 05:29:12 PM PDT 24
Finished Jun 29 05:33:29 PM PDT 24
Peak memory 235500 kb
Host smart-0aea4065-ac97-41da-b424-21c55f65d4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326552874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1326552874
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2210032250
Short name T269
Test name
Test status
Simulation time 4894506805 ps
CPU time 105.29 seconds
Started Jun 29 05:29:09 PM PDT 24
Finished Jun 29 05:30:56 PM PDT 24
Peak memory 266188 kb
Host smart-0f8fa10d-971c-4c15-8476-7c90cf4b9a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210032250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2210032250
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2830696802
Short name T155
Test name
Test status
Simulation time 2637070585 ps
CPU time 11.58 seconds
Started Jun 29 05:29:06 PM PDT 24
Finished Jun 29 05:29:19 PM PDT 24
Peak memory 225144 kb
Host smart-11175c90-d890-4f6c-bf8b-710ca191b619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830696802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2830696802
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2712331751
Short name T295
Test name
Test status
Simulation time 15554229251 ps
CPU time 154.3 seconds
Started Jun 29 05:29:08 PM PDT 24
Finished Jun 29 05:31:44 PM PDT 24
Peak memory 257848 kb
Host smart-1870e06f-6184-4e72-873c-2997b2b63186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712331751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2712331751
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.579176871
Short name T241
Test name
Test status
Simulation time 4514014734 ps
CPU time 10.39 seconds
Started Jun 29 05:29:05 PM PDT 24
Finished Jun 29 05:29:17 PM PDT 24
Peak memory 233288 kb
Host smart-f1202acd-6a9d-4885-9ba5-2eeb570616f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579176871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.579176871
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.386546261
Short name T715
Test name
Test status
Simulation time 1565005180 ps
CPU time 9.92 seconds
Started Jun 29 05:29:06 PM PDT 24
Finished Jun 29 05:29:17 PM PDT 24
Peak memory 239976 kb
Host smart-a429de9d-c645-4f4e-8cdf-0322507b1443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386546261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.386546261
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3759433346
Short name T571
Test name
Test status
Simulation time 886072123 ps
CPU time 5.72 seconds
Started Jun 29 05:29:02 PM PDT 24
Finished Jun 29 05:29:08 PM PDT 24
Peak memory 224948 kb
Host smart-5655ed20-8698-4357-8310-24203f0ca168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759433346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3759433346
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2588174409
Short name T877
Test name
Test status
Simulation time 354426620 ps
CPU time 3.27 seconds
Started Jun 29 05:29:06 PM PDT 24
Finished Jun 29 05:29:10 PM PDT 24
Peak memory 233164 kb
Host smart-cd181215-a7db-4167-9db5-63961774c1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588174409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2588174409
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.545897504
Short name T749
Test name
Test status
Simulation time 1130787176 ps
CPU time 14.61 seconds
Started Jun 29 05:29:09 PM PDT 24
Finished Jun 29 05:29:25 PM PDT 24
Peak memory 220556 kb
Host smart-467eaf35-1ba0-4cc3-a6c5-63c799718e8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=545897504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.545897504
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3074676505
Short name T808
Test name
Test status
Simulation time 99881715485 ps
CPU time 264.21 seconds
Started Jun 29 05:29:07 PM PDT 24
Finished Jun 29 05:33:32 PM PDT 24
Peak memory 255756 kb
Host smart-2cb33398-8ed6-40a8-8ee9-a69f96d3d7f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074676505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3074676505
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1336160966
Short name T28
Test name
Test status
Simulation time 176411978 ps
CPU time 2.68 seconds
Started Jun 29 05:29:04 PM PDT 24
Finished Jun 29 05:29:08 PM PDT 24
Peak memory 216792 kb
Host smart-aeeab240-2f28-4d19-b4c1-5498a4f13a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336160966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1336160966
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.352436499
Short name T824
Test name
Test status
Simulation time 3664842977 ps
CPU time 6.67 seconds
Started Jun 29 05:29:08 PM PDT 24
Finished Jun 29 05:29:17 PM PDT 24
Peak memory 216824 kb
Host smart-83b436d5-cd8c-40db-a1d2-3224de4f5afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352436499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.352436499
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1523926606
Short name T722
Test name
Test status
Simulation time 88710612 ps
CPU time 5.4 seconds
Started Jun 29 05:29:04 PM PDT 24
Finished Jun 29 05:29:11 PM PDT 24
Peak memory 216784 kb
Host smart-70918d73-0dd1-4d64-9df6-ad06ab919ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523926606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1523926606
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3613642610
Short name T739
Test name
Test status
Simulation time 35799286 ps
CPU time 0.79 seconds
Started Jun 29 05:29:07 PM PDT 24
Finished Jun 29 05:29:09 PM PDT 24
Peak memory 206452 kb
Host smart-be05fb5e-29b7-4e7f-ac6a-d5e3cb4b567b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613642610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3613642610
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2577748559
Short name T685
Test name
Test status
Simulation time 378661570 ps
CPU time 2.46 seconds
Started Jun 29 05:29:02 PM PDT 24
Finished Jun 29 05:29:05 PM PDT 24
Peak memory 224912 kb
Host smart-d3053ca6-4b29-4c43-a012-3e70d4461fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577748559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2577748559
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1723240847
Short name T565
Test name
Test status
Simulation time 37370610 ps
CPU time 0.7 seconds
Started Jun 29 05:29:07 PM PDT 24
Finished Jun 29 05:29:09 PM PDT 24
Peak memory 206260 kb
Host smart-2a050fe1-7eb5-4368-a01a-32694a6071a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723240847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1723240847
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1728955994
Short name T282
Test name
Test status
Simulation time 82380545 ps
CPU time 2.66 seconds
Started Jun 29 05:29:07 PM PDT 24
Finished Jun 29 05:29:11 PM PDT 24
Peak memory 233180 kb
Host smart-ab8520ea-a41c-4378-8044-904d519267e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728955994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1728955994
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2565517975
Short name T796
Test name
Test status
Simulation time 20001511 ps
CPU time 0.78 seconds
Started Jun 29 05:29:12 PM PDT 24
Finished Jun 29 05:29:14 PM PDT 24
Peak memory 207024 kb
Host smart-99bf85e8-dde2-46c1-8288-e976a4eafa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565517975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2565517975
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1991564160
Short name T904
Test name
Test status
Simulation time 22422581727 ps
CPU time 50.29 seconds
Started Jun 29 05:29:12 PM PDT 24
Finished Jun 29 05:30:03 PM PDT 24
Peak memory 257696 kb
Host smart-50465c10-129b-4633-9868-3013b72c1eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991564160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1991564160
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2997570634
Short name T263
Test name
Test status
Simulation time 6940455137 ps
CPU time 60.84 seconds
Started Jun 29 05:29:10 PM PDT 24
Finished Jun 29 05:30:12 PM PDT 24
Peak memory 241020 kb
Host smart-fb60a79e-8930-4905-b8ea-6224b9d4c09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997570634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2997570634
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.133257137
Short name T529
Test name
Test status
Simulation time 18819789090 ps
CPU time 169.48 seconds
Started Jun 29 05:29:08 PM PDT 24
Finished Jun 29 05:31:59 PM PDT 24
Peak memory 250880 kb
Host smart-d80cb90b-7b86-43d3-b906-11f40ef6cd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133257137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.133257137
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2392729901
Short name T721
Test name
Test status
Simulation time 3226967817 ps
CPU time 36.94 seconds
Started Jun 29 05:29:10 PM PDT 24
Finished Jun 29 05:29:48 PM PDT 24
Peak memory 233340 kb
Host smart-a3035557-91d6-4d4b-9da8-5b5ac73b512a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392729901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2392729901
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2009024313
Short name T94
Test name
Test status
Simulation time 4902673442 ps
CPU time 44.26 seconds
Started Jun 29 05:29:09 PM PDT 24
Finished Jun 29 05:29:55 PM PDT 24
Peak memory 254528 kb
Host smart-4318f5f6-88b4-42a6-879d-eaf0f21537ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009024313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2009024313
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2236950612
Short name T870
Test name
Test status
Simulation time 3306002015 ps
CPU time 7.39 seconds
Started Jun 29 05:29:08 PM PDT 24
Finished Jun 29 05:29:17 PM PDT 24
Peak memory 225092 kb
Host smart-b72d4692-158f-4cc7-b3ea-3331c33c4edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236950612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2236950612
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.986912083
Short name T924
Test name
Test status
Simulation time 2960317054 ps
CPU time 13.66 seconds
Started Jun 29 05:29:09 PM PDT 24
Finished Jun 29 05:29:24 PM PDT 24
Peak memory 233260 kb
Host smart-30fbd047-7379-45f2-b1a9-0b0c48a34311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986912083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.986912083
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1415772661
Short name T464
Test name
Test status
Simulation time 8739971106 ps
CPU time 25.56 seconds
Started Jun 29 05:29:08 PM PDT 24
Finished Jun 29 05:29:35 PM PDT 24
Peak memory 239688 kb
Host smart-79f8ac5c-5aa2-4e11-ac30-0eb3db497a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415772661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1415772661
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4069147487
Short name T244
Test name
Test status
Simulation time 718882638 ps
CPU time 3.17 seconds
Started Jun 29 05:29:12 PM PDT 24
Finished Jun 29 05:29:16 PM PDT 24
Peak memory 233128 kb
Host smart-cf429f0d-8b99-440d-bc43-5b4533bd208c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069147487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4069147487
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1043221172
Short name T480
Test name
Test status
Simulation time 210423121 ps
CPU time 5.11 seconds
Started Jun 29 05:29:08 PM PDT 24
Finished Jun 29 05:29:14 PM PDT 24
Peak memory 221104 kb
Host smart-eb03d84b-ec95-45ac-8fd7-69a629bb8e66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1043221172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1043221172
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1306762456
Short name T934
Test name
Test status
Simulation time 2966083337 ps
CPU time 21.59 seconds
Started Jun 29 05:29:08 PM PDT 24
Finished Jun 29 05:29:31 PM PDT 24
Peak memory 249720 kb
Host smart-03701d46-3b51-42ce-bece-9e65cfd429a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306762456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1306762456
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.915647130
Short name T875
Test name
Test status
Simulation time 2875121009 ps
CPU time 21.56 seconds
Started Jun 29 05:29:09 PM PDT 24
Finished Jun 29 05:29:32 PM PDT 24
Peak memory 217120 kb
Host smart-b631fadb-c884-4dad-8fed-b30bcd5291cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915647130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.915647130
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.752463098
Short name T672
Test name
Test status
Simulation time 15875355472 ps
CPU time 13.54 seconds
Started Jun 29 05:29:07 PM PDT 24
Finished Jun 29 05:29:22 PM PDT 24
Peak memory 217128 kb
Host smart-a7c668f9-6a56-409f-8c8d-3c496d0b598d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752463098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.752463098
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.710805895
Short name T331
Test name
Test status
Simulation time 96300375 ps
CPU time 0.88 seconds
Started Jun 29 05:29:07 PM PDT 24
Finished Jun 29 05:29:09 PM PDT 24
Peak memory 207456 kb
Host smart-ac4fb5c4-2f07-445c-8e9e-5839daad41f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710805895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.710805895
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3314637762
Short name T890
Test name
Test status
Simulation time 40417445 ps
CPU time 0.73 seconds
Started Jun 29 05:29:08 PM PDT 24
Finished Jun 29 05:29:11 PM PDT 24
Peak memory 206456 kb
Host smart-952f24fa-fcc1-416c-a0ae-953daba37e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314637762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3314637762
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2097539125
Short name T202
Test name
Test status
Simulation time 4302059294 ps
CPU time 8.71 seconds
Started Jun 29 05:29:09 PM PDT 24
Finished Jun 29 05:29:19 PM PDT 24
Peak memory 225076 kb
Host smart-cac39db2-90c0-4e3c-9b95-a166d22f002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097539125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2097539125
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3400146789
Short name T575
Test name
Test status
Simulation time 23068353 ps
CPU time 0.77 seconds
Started Jun 29 05:29:16 PM PDT 24
Finished Jun 29 05:29:18 PM PDT 24
Peak memory 205976 kb
Host smart-a8205703-19d3-47e9-a1df-e8bfb341edff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400146789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3400146789
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2446175700
Short name T469
Test name
Test status
Simulation time 33141773 ps
CPU time 2.54 seconds
Started Jun 29 05:29:10 PM PDT 24
Finished Jun 29 05:29:14 PM PDT 24
Peak memory 233020 kb
Host smart-0a9b69d5-f390-4ff5-818a-6655280be6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446175700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2446175700
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2764278675
Short name T337
Test name
Test status
Simulation time 85869029 ps
CPU time 0.83 seconds
Started Jun 29 05:29:08 PM PDT 24
Finished Jun 29 05:29:11 PM PDT 24
Peak memory 207092 kb
Host smart-0aa90f96-2483-412b-8e8b-c05ca4c7a6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764278675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2764278675
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1132588964
Short name T668
Test name
Test status
Simulation time 14599528434 ps
CPU time 45.01 seconds
Started Jun 29 05:29:18 PM PDT 24
Finished Jun 29 05:30:03 PM PDT 24
Peak memory 233312 kb
Host smart-ce5a3091-7622-4ca5-aacc-27dcb5bb2ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132588964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1132588964
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3061744167
Short name T814
Test name
Test status
Simulation time 826509943 ps
CPU time 8.52 seconds
Started Jun 29 05:29:12 PM PDT 24
Finished Jun 29 05:29:21 PM PDT 24
Peak memory 224952 kb
Host smart-4fdbd752-4396-48c1-9bc4-6221177fa24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061744167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3061744167
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2173424383
Short name T227
Test name
Test status
Simulation time 4123968198 ps
CPU time 27.67 seconds
Started Jun 29 05:29:09 PM PDT 24
Finished Jun 29 05:29:38 PM PDT 24
Peak memory 225072 kb
Host smart-5832ff0b-3c84-4888-9f3d-15919003e24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173424383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2173424383
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.873965002
Short name T440
Test name
Test status
Simulation time 5263886877 ps
CPU time 12.79 seconds
Started Jun 29 05:29:11 PM PDT 24
Finished Jun 29 05:29:24 PM PDT 24
Peak memory 233280 kb
Host smart-d1e751bf-9e91-4219-a86a-a12937077243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873965002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.873965002
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.626968978
Short name T99
Test name
Test status
Simulation time 4197861568 ps
CPU time 9.01 seconds
Started Jun 29 05:29:07 PM PDT 24
Finished Jun 29 05:29:17 PM PDT 24
Peak memory 233308 kb
Host smart-d31a3fba-a412-4fcd-9906-96a0ee568817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626968978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.626968978
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2650540412
Short name T406
Test name
Test status
Simulation time 400458378 ps
CPU time 2.3 seconds
Started Jun 29 05:29:08 PM PDT 24
Finished Jun 29 05:29:12 PM PDT 24
Peak memory 225004 kb
Host smart-9e07f36f-cf47-4419-85c8-002e8975664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650540412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2650540412
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4139469689
Short name T431
Test name
Test status
Simulation time 594705000 ps
CPU time 5.31 seconds
Started Jun 29 05:29:15 PM PDT 24
Finished Jun 29 05:29:21 PM PDT 24
Peak memory 223592 kb
Host smart-d1fd6140-5b26-4870-af55-eb8b3a6fe27d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4139469689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4139469689
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2709888911
Short name T978
Test name
Test status
Simulation time 58284192 ps
CPU time 1.03 seconds
Started Jun 29 05:29:16 PM PDT 24
Finished Jun 29 05:29:18 PM PDT 24
Peak memory 208048 kb
Host smart-4f59c4f1-a700-4b3a-8553-ff580fe60694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709888911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2709888911
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2372514762
Short name T73
Test name
Test status
Simulation time 887618109 ps
CPU time 8.67 seconds
Started Jun 29 05:29:09 PM PDT 24
Finished Jun 29 05:29:19 PM PDT 24
Peak memory 216936 kb
Host smart-e5fbc427-99ff-4c8c-ae12-8edf2a3fa6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372514762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2372514762
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3557996198
Short name T362
Test name
Test status
Simulation time 4000696532 ps
CPU time 4.12 seconds
Started Jun 29 05:29:06 PM PDT 24
Finished Jun 29 05:29:12 PM PDT 24
Peak memory 216964 kb
Host smart-8789845b-1bcb-44ee-8224-cec70cfd5835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557996198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3557996198
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.406245659
Short name T534
Test name
Test status
Simulation time 170812371 ps
CPU time 1.33 seconds
Started Jun 29 05:29:10 PM PDT 24
Finished Jun 29 05:29:13 PM PDT 24
Peak memory 216816 kb
Host smart-b2ad2c90-a15e-449e-896d-02582b103533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406245659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.406245659
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2479968868
Short name T90
Test name
Test status
Simulation time 49916930 ps
CPU time 0.78 seconds
Started Jun 29 05:29:12 PM PDT 24
Finished Jun 29 05:29:13 PM PDT 24
Peak memory 206456 kb
Host smart-90e89f77-1bb2-4caf-a18e-59e6bf5d62f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479968868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2479968868
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3133836423
Short name T760
Test name
Test status
Simulation time 8117415872 ps
CPU time 10.9 seconds
Started Jun 29 05:29:12 PM PDT 24
Finished Jun 29 05:29:24 PM PDT 24
Peak memory 233268 kb
Host smart-c5380902-56ff-474b-8fef-0cbbd4c36cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133836423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3133836423
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3930543058
Short name T349
Test name
Test status
Simulation time 10950708 ps
CPU time 0.73 seconds
Started Jun 29 05:27:28 PM PDT 24
Finished Jun 29 05:27:29 PM PDT 24
Peak memory 206288 kb
Host smart-191c0e56-428a-46d3-94f7-472eb35c6940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930543058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
930543058
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2350260402
Short name T923
Test name
Test status
Simulation time 248915621 ps
CPU time 2.7 seconds
Started Jun 29 05:27:15 PM PDT 24
Finished Jun 29 05:27:19 PM PDT 24
Peak memory 225012 kb
Host smart-10615396-86bb-4625-a500-186e08725b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350260402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2350260402
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3127694221
Short name T347
Test name
Test status
Simulation time 60876373 ps
CPU time 0.82 seconds
Started Jun 29 05:27:19 PM PDT 24
Finished Jun 29 05:27:21 PM PDT 24
Peak memory 206072 kb
Host smart-db18f435-4ad7-42f6-9891-2e5334ad7868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127694221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3127694221
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2028966452
Short name T868
Test name
Test status
Simulation time 4465913203 ps
CPU time 96.66 seconds
Started Jun 29 05:27:27 PM PDT 24
Finished Jun 29 05:29:04 PM PDT 24
Peak memory 255136 kb
Host smart-1bb8b040-26da-4660-bf1f-b123e5dcc96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028966452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2028966452
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2827797194
Short name T539
Test name
Test status
Simulation time 38702310743 ps
CPU time 86.44 seconds
Started Jun 29 05:27:17 PM PDT 24
Finished Jun 29 05:28:45 PM PDT 24
Peak memory 256236 kb
Host smart-c5eefcd8-c5a5-4c9e-81ad-caff8ca5613e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827797194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2827797194
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.4163910183
Short name T841
Test name
Test status
Simulation time 94961602521 ps
CPU time 407.34 seconds
Started Jun 29 05:27:17 PM PDT 24
Finished Jun 29 05:34:05 PM PDT 24
Peak memory 267820 kb
Host smart-9569c53c-b8c2-4dd3-a3e1-52a5028e6091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163910183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.4163910183
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.204763781
Short name T314
Test name
Test status
Simulation time 500676263 ps
CPU time 10.46 seconds
Started Jun 29 05:27:17 PM PDT 24
Finished Jun 29 05:27:29 PM PDT 24
Peak memory 233640 kb
Host smart-0dbb139c-0fa6-4f6c-99fb-768b55571ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204763781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.204763781
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1723817846
Short name T838
Test name
Test status
Simulation time 6178355700 ps
CPU time 85.85 seconds
Started Jun 29 05:27:09 PM PDT 24
Finished Jun 29 05:28:36 PM PDT 24
Peak memory 253700 kb
Host smart-f6571b93-8083-4b6b-8bc3-ed5dfb029975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723817846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1723817846
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.730442036
Short name T647
Test name
Test status
Simulation time 233425780 ps
CPU time 2.26 seconds
Started Jun 29 05:27:15 PM PDT 24
Finished Jun 29 05:27:18 PM PDT 24
Peak memory 224732 kb
Host smart-771dd50c-e640-45ac-b9a9-80e87160b8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730442036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.730442036
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.799137987
Short name T423
Test name
Test status
Simulation time 117260000 ps
CPU time 2.51 seconds
Started Jun 29 05:27:12 PM PDT 24
Finished Jun 29 05:27:16 PM PDT 24
Peak memory 232972 kb
Host smart-95c3361b-0100-4a19-91cf-88e05aeba7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799137987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.799137987
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3540259541
Short name T998
Test name
Test status
Simulation time 3617546572 ps
CPU time 13.93 seconds
Started Jun 29 05:27:25 PM PDT 24
Finished Jun 29 05:27:39 PM PDT 24
Peak memory 233316 kb
Host smart-24ac4bbb-b82d-4384-baf0-86566614a61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540259541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3540259541
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2203972042
Short name T281
Test name
Test status
Simulation time 859762671 ps
CPU time 3.24 seconds
Started Jun 29 05:27:13 PM PDT 24
Finished Jun 29 05:27:17 PM PDT 24
Peak memory 233192 kb
Host smart-e561d89d-f774-4d3e-bcde-f8d11229f1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203972042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2203972042
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2901486590
Short name T994
Test name
Test status
Simulation time 3149414143 ps
CPU time 7.66 seconds
Started Jun 29 05:27:14 PM PDT 24
Finished Jun 29 05:27:22 PM PDT 24
Peak memory 223640 kb
Host smart-09bc6f84-b5e0-4edf-a6a6-e7caa74d7fb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2901486590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2901486590
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2486817913
Short name T70
Test name
Test status
Simulation time 146675274 ps
CPU time 1.29 seconds
Started Jun 29 05:27:24 PM PDT 24
Finished Jun 29 05:27:25 PM PDT 24
Peak memory 236908 kb
Host smart-b6f2fa85-41b8-46e3-ae83-42b4cfd906fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486817913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2486817913
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2084221913
Short name T147
Test name
Test status
Simulation time 54748188866 ps
CPU time 605.42 seconds
Started Jun 29 05:27:16 PM PDT 24
Finished Jun 29 05:37:22 PM PDT 24
Peak memory 266264 kb
Host smart-93db9c85-fb6c-46ea-9029-acea399e7017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084221913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2084221913
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2209193378
Short name T964
Test name
Test status
Simulation time 361478282 ps
CPU time 5.78 seconds
Started Jun 29 05:27:11 PM PDT 24
Finished Jun 29 05:27:17 PM PDT 24
Peak memory 216984 kb
Host smart-94be5916-86dd-45e7-8fff-d118f4bfa1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209193378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2209193378
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.745789059
Short name T444
Test name
Test status
Simulation time 10729972969 ps
CPU time 9.28 seconds
Started Jun 29 05:27:10 PM PDT 24
Finished Jun 29 05:27:20 PM PDT 24
Peak memory 216952 kb
Host smart-0461430d-929f-4fec-b13f-4d014cc35b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745789059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.745789059
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3263870478
Short name T834
Test name
Test status
Simulation time 22017775 ps
CPU time 0.74 seconds
Started Jun 29 05:27:28 PM PDT 24
Finished Jun 29 05:27:29 PM PDT 24
Peak memory 206396 kb
Host smart-a6a81411-47b3-47bd-adb1-ef828703ae5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263870478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3263870478
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.853407103
Short name T369
Test name
Test status
Simulation time 43516466 ps
CPU time 0.83 seconds
Started Jun 29 05:27:12 PM PDT 24
Finished Jun 29 05:27:14 PM PDT 24
Peak memory 206456 kb
Host smart-d4eaae16-9b44-4bfd-8034-2d104e7a5763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853407103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.853407103
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.402540690
Short name T249
Test name
Test status
Simulation time 2416062424 ps
CPU time 10.34 seconds
Started Jun 29 05:27:22 PM PDT 24
Finished Jun 29 05:27:33 PM PDT 24
Peak memory 225072 kb
Host smart-3fee89bd-12f4-4b68-a43b-90d52bfaf681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402540690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.402540690
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.856208665
Short name T351
Test name
Test status
Simulation time 33011239 ps
CPU time 0.7 seconds
Started Jun 29 05:29:23 PM PDT 24
Finished Jun 29 05:29:25 PM PDT 24
Peak memory 205396 kb
Host smart-3b08f9aa-80c9-422b-9d45-0bbace88c353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856208665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.856208665
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3023336850
Short name T774
Test name
Test status
Simulation time 7258818292 ps
CPU time 11.69 seconds
Started Jun 29 05:29:16 PM PDT 24
Finished Jun 29 05:29:29 PM PDT 24
Peak memory 225068 kb
Host smart-d70c1dd7-1a8d-46f0-8018-25607b3c52f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023336850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3023336850
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1153090397
Short name T341
Test name
Test status
Simulation time 17529899 ps
CPU time 0.8 seconds
Started Jun 29 05:29:15 PM PDT 24
Finished Jun 29 05:29:16 PM PDT 24
Peak memory 207096 kb
Host smart-a4cc935f-4fee-4176-988b-dd5be724f86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153090397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1153090397
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3889739598
Short name T1013
Test name
Test status
Simulation time 4275961267 ps
CPU time 5.41 seconds
Started Jun 29 05:29:20 PM PDT 24
Finished Jun 29 05:29:25 PM PDT 24
Peak memory 235900 kb
Host smart-314d69cb-61ce-4994-9c94-d6432b411424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889739598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3889739598
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2995084624
Short name T55
Test name
Test status
Simulation time 269138208560 ps
CPU time 281.29 seconds
Started Jun 29 05:29:17 PM PDT 24
Finished Jun 29 05:33:59 PM PDT 24
Peak memory 273064 kb
Host smart-7daf5b09-10c0-4c4a-a4dd-016090d39c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995084624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2995084624
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1113719911
Short name T963
Test name
Test status
Simulation time 32431125667 ps
CPU time 300.37 seconds
Started Jun 29 05:29:16 PM PDT 24
Finished Jun 29 05:34:18 PM PDT 24
Peak memory 256912 kb
Host smart-082f180a-d1f8-4d1e-a79f-b07a051090f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113719911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1113719911
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4286498576
Short name T307
Test name
Test status
Simulation time 2236970329 ps
CPU time 29.72 seconds
Started Jun 29 05:29:16 PM PDT 24
Finished Jun 29 05:29:47 PM PDT 24
Peak memory 233824 kb
Host smart-75acb228-1e3a-4840-903b-f76ef461141d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286498576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4286498576
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1075538015
Short name T561
Test name
Test status
Simulation time 3220926435 ps
CPU time 45.06 seconds
Started Jun 29 05:29:16 PM PDT 24
Finished Jun 29 05:30:02 PM PDT 24
Peak memory 249720 kb
Host smart-d47d2314-ebe9-4b2e-8803-1712401584bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075538015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1075538015
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.344770149
Short name T447
Test name
Test status
Simulation time 593574187 ps
CPU time 5.43 seconds
Started Jun 29 05:29:17 PM PDT 24
Finished Jun 29 05:29:23 PM PDT 24
Peak memory 233184 kb
Host smart-a255eb4d-4c05-4c01-9538-f0010d1ddc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344770149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.344770149
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.683372236
Short name T793
Test name
Test status
Simulation time 6778198853 ps
CPU time 22.92 seconds
Started Jun 29 05:29:17 PM PDT 24
Finished Jun 29 05:29:40 PM PDT 24
Peak memory 233280 kb
Host smart-3054da8e-a8d0-4cdd-a363-1d3f2dcb86a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683372236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.683372236
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1605827251
Short name T597
Test name
Test status
Simulation time 11641198760 ps
CPU time 11.36 seconds
Started Jun 29 05:29:16 PM PDT 24
Finished Jun 29 05:29:28 PM PDT 24
Peak memory 232552 kb
Host smart-fa750850-b09b-40a8-b71a-cd7b8d64ae23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605827251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1605827251
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3880274331
Short name T592
Test name
Test status
Simulation time 1539864040 ps
CPU time 5.67 seconds
Started Jun 29 05:29:19 PM PDT 24
Finished Jun 29 05:29:25 PM PDT 24
Peak memory 224952 kb
Host smart-db3e3e41-c1d8-4710-ab68-d0807d924c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880274331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3880274331
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3723082605
Short name T78
Test name
Test status
Simulation time 561782840 ps
CPU time 4.76 seconds
Started Jun 29 05:29:15 PM PDT 24
Finished Jun 29 05:29:20 PM PDT 24
Peak memory 221184 kb
Host smart-f9aca8d7-9fa8-44ce-869f-f3b2e715d9a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3723082605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3723082605
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.493135191
Short name T790
Test name
Test status
Simulation time 4276435774 ps
CPU time 17.17 seconds
Started Jun 29 05:29:23 PM PDT 24
Finished Jun 29 05:29:41 PM PDT 24
Peak memory 240184 kb
Host smart-3c85f24c-7ab3-486e-9f1b-a78e9c7ccca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493135191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.493135191
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2474812785
Short name T317
Test name
Test status
Simulation time 12454633276 ps
CPU time 22.9 seconds
Started Jun 29 05:29:15 PM PDT 24
Finished Jun 29 05:29:38 PM PDT 24
Peak memory 216956 kb
Host smart-e4fdc980-8eb1-4dcc-a9a3-744f39ee28ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474812785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2474812785
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1595225143
Short name T485
Test name
Test status
Simulation time 3902281021 ps
CPU time 4.97 seconds
Started Jun 29 05:29:17 PM PDT 24
Finished Jun 29 05:29:23 PM PDT 24
Peak memory 216916 kb
Host smart-ba8fc4c6-89e0-4dfc-8dbc-c30894ffa893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595225143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1595225143
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.480926706
Short name T758
Test name
Test status
Simulation time 14328662 ps
CPU time 0.88 seconds
Started Jun 29 05:29:16 PM PDT 24
Finished Jun 29 05:29:17 PM PDT 24
Peak memory 207224 kb
Host smart-d615ecd7-62b4-4fcb-be0f-cf474fec7693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480926706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.480926706
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3716579969
Short name T487
Test name
Test status
Simulation time 150604033 ps
CPU time 0.88 seconds
Started Jun 29 05:29:16 PM PDT 24
Finished Jun 29 05:29:18 PM PDT 24
Peak memory 206460 kb
Host smart-202abb72-0764-4f29-81fa-e7e6a84a6b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716579969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3716579969
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2238699966
Short name T257
Test name
Test status
Simulation time 22097132484 ps
CPU time 20.44 seconds
Started Jun 29 05:29:16 PM PDT 24
Finished Jun 29 05:29:38 PM PDT 24
Peak memory 225084 kb
Host smart-d7704a15-220d-43b7-86ce-c1d6bb4088e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238699966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2238699966
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2220564005
Short name T681
Test name
Test status
Simulation time 36552691 ps
CPU time 0.75 seconds
Started Jun 29 05:29:23 PM PDT 24
Finished Jun 29 05:29:24 PM PDT 24
Peak memory 206336 kb
Host smart-aaed738d-81a0-4161-90f3-39e5561955a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220564005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2220564005
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2281038047
Short name T72
Test name
Test status
Simulation time 137169995 ps
CPU time 2.85 seconds
Started Jun 29 05:29:28 PM PDT 24
Finished Jun 29 05:29:31 PM PDT 24
Peak memory 233112 kb
Host smart-3fbe7fad-9035-4b5f-8332-4903bf6127bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281038047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2281038047
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1787346303
Short name T791
Test name
Test status
Simulation time 21555735 ps
CPU time 0.82 seconds
Started Jun 29 05:29:26 PM PDT 24
Finished Jun 29 05:29:27 PM PDT 24
Peak memory 207084 kb
Host smart-295bda62-abd8-4252-a9b1-cb8bdc3e757f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787346303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1787346303
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1579989249
Short name T240
Test name
Test status
Simulation time 2913297105 ps
CPU time 57.09 seconds
Started Jun 29 05:29:24 PM PDT 24
Finished Jun 29 05:30:21 PM PDT 24
Peak memory 250736 kb
Host smart-d95c72ad-fe67-4b16-ae0f-94c35f45515b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579989249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1579989249
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1143763597
Short name T422
Test name
Test status
Simulation time 11978732740 ps
CPU time 73.83 seconds
Started Jun 29 05:29:26 PM PDT 24
Finished Jun 29 05:30:40 PM PDT 24
Peak memory 250960 kb
Host smart-7ac00f1c-7865-44b7-b42f-1c8bdc9e54d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143763597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1143763597
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3163558713
Short name T800
Test name
Test status
Simulation time 9145220995 ps
CPU time 73.95 seconds
Started Jun 29 05:29:24 PM PDT 24
Finished Jun 29 05:30:39 PM PDT 24
Peak memory 249864 kb
Host smart-e0a23eaf-29bf-4edb-94a0-bc40cf7a8489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163558713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3163558713
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2303008291
Short name T541
Test name
Test status
Simulation time 2876762767 ps
CPU time 46.59 seconds
Started Jun 29 05:29:23 PM PDT 24
Finished Jun 29 05:30:11 PM PDT 24
Peak memory 233296 kb
Host smart-305e4717-84d5-4081-a200-3cd0ab6f504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303008291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2303008291
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1133312090
Short name T335
Test name
Test status
Simulation time 13182306 ps
CPU time 0.79 seconds
Started Jun 29 05:29:22 PM PDT 24
Finished Jun 29 05:29:23 PM PDT 24
Peak memory 216404 kb
Host smart-f1b0f56a-023c-48e8-9e53-cfdab78cc9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133312090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1133312090
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2429538577
Short name T782
Test name
Test status
Simulation time 4583019007 ps
CPU time 12.79 seconds
Started Jun 29 05:29:30 PM PDT 24
Finished Jun 29 05:29:43 PM PDT 24
Peak memory 233300 kb
Host smart-1973b91a-bb13-4501-88a7-719a8169f430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429538577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2429538577
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2403765873
Short name T712
Test name
Test status
Simulation time 1362570227 ps
CPU time 9.1 seconds
Started Jun 29 05:29:23 PM PDT 24
Finished Jun 29 05:29:32 PM PDT 24
Peak memory 233144 kb
Host smart-35ad353b-afb1-4c7c-a9bb-fdcf6325ce08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403765873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2403765873
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.775581034
Short name T334
Test name
Test status
Simulation time 214302840 ps
CPU time 2.23 seconds
Started Jun 29 05:29:25 PM PDT 24
Finished Jun 29 05:29:28 PM PDT 24
Peak memory 224400 kb
Host smart-b0a06f9d-6f98-417c-a585-73c46ee8e39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775581034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.775581034
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.106977246
Short name T730
Test name
Test status
Simulation time 149453772 ps
CPU time 3.2 seconds
Started Jun 29 05:29:26 PM PDT 24
Finished Jun 29 05:29:29 PM PDT 24
Peak memory 225028 kb
Host smart-7114c10b-2f4a-468c-9a19-fa7f9e4dc2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106977246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.106977246
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.463112600
Short name T985
Test name
Test status
Simulation time 25329072755 ps
CPU time 15.49 seconds
Started Jun 29 05:29:23 PM PDT 24
Finished Jun 29 05:29:39 PM PDT 24
Peak memory 222712 kb
Host smart-972ec2d3-c80a-49d1-9174-4b63afeb9bae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=463112600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.463112600
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2259959069
Short name T557
Test name
Test status
Simulation time 4980667432 ps
CPU time 26.53 seconds
Started Jun 29 05:29:24 PM PDT 24
Finished Jun 29 05:29:51 PM PDT 24
Peak memory 216976 kb
Host smart-2ccca73d-8aea-4f85-a246-207d68b8cf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259959069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2259959069
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3865632273
Short name T425
Test name
Test status
Simulation time 2954228808 ps
CPU time 3.24 seconds
Started Jun 29 05:29:24 PM PDT 24
Finished Jun 29 05:29:27 PM PDT 24
Peak memory 216896 kb
Host smart-f2d6ccaf-e95e-431a-9bdb-8d3d27ce1c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865632273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3865632273
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.807201163
Short name T1000
Test name
Test status
Simulation time 142423897 ps
CPU time 1.01 seconds
Started Jun 29 05:29:25 PM PDT 24
Finished Jun 29 05:29:26 PM PDT 24
Peak memory 207504 kb
Host smart-5452cfd9-85cf-4632-b304-6470cac33fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807201163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.807201163
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.4051297390
Short name T955
Test name
Test status
Simulation time 316656004 ps
CPU time 0.81 seconds
Started Jun 29 05:29:26 PM PDT 24
Finished Jun 29 05:29:27 PM PDT 24
Peak memory 206452 kb
Host smart-ab7b9cdf-6cd2-4710-82d3-df35720fdff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051297390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.4051297390
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.922147494
Short name T804
Test name
Test status
Simulation time 14192201121 ps
CPU time 40.08 seconds
Started Jun 29 05:29:26 PM PDT 24
Finished Jun 29 05:30:06 PM PDT 24
Peak memory 235276 kb
Host smart-1a844ddb-97a6-4d22-b1ca-937c27c8af65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922147494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.922147494
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3683314920
Short name T371
Test name
Test status
Simulation time 29757722 ps
CPU time 0.7 seconds
Started Jun 29 05:29:33 PM PDT 24
Finished Jun 29 05:29:34 PM PDT 24
Peak memory 205888 kb
Host smart-d5d44cfb-7602-41c7-98a3-efb2682aad1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683314920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3683314920
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3953868117
Short name T823
Test name
Test status
Simulation time 809206097 ps
CPU time 10.01 seconds
Started Jun 29 05:29:25 PM PDT 24
Finished Jun 29 05:29:36 PM PDT 24
Peak memory 225000 kb
Host smart-18f43a52-ea50-4c99-afdb-bb30c3158d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953868117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3953868117
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2752317129
Short name T992
Test name
Test status
Simulation time 14685443 ps
CPU time 0.77 seconds
Started Jun 29 05:29:26 PM PDT 24
Finished Jun 29 05:29:27 PM PDT 24
Peak memory 207424 kb
Host smart-51bb9d34-a04a-4711-ba6b-0613e263e443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752317129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2752317129
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2819447449
Short name T80
Test name
Test status
Simulation time 184439180179 ps
CPU time 289.23 seconds
Started Jun 29 05:29:30 PM PDT 24
Finished Jun 29 05:34:19 PM PDT 24
Peak memory 255016 kb
Host smart-ef72070d-91bf-483d-a73a-2108865bec02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819447449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2819447449
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.282979877
Short name T552
Test name
Test status
Simulation time 13857964761 ps
CPU time 70.81 seconds
Started Jun 29 05:29:31 PM PDT 24
Finished Jun 29 05:30:43 PM PDT 24
Peak memory 263972 kb
Host smart-118ff73b-67b7-4286-ba15-ca52d7dc1722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282979877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.282979877
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4044088801
Short name T439
Test name
Test status
Simulation time 66610336846 ps
CPU time 122.66 seconds
Started Jun 29 05:29:32 PM PDT 24
Finished Jun 29 05:31:35 PM PDT 24
Peak memory 253308 kb
Host smart-9b467625-84ed-4be9-af72-19a06ff17b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044088801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4044088801
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.4259541646
Short name T771
Test name
Test status
Simulation time 40830891597 ps
CPU time 31.34 seconds
Started Jun 29 05:29:30 PM PDT 24
Finished Jun 29 05:30:02 PM PDT 24
Peak memory 252192 kb
Host smart-14cf5c38-8dd0-4a3e-842b-2e1bfce70977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259541646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.4259541646
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2770811563
Short name T562
Test name
Test status
Simulation time 42712769611 ps
CPU time 182.4 seconds
Started Jun 29 05:29:30 PM PDT 24
Finished Jun 29 05:32:33 PM PDT 24
Peak memory 253384 kb
Host smart-1631619f-f291-4820-8f9a-03eca4cb5504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770811563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2770811563
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1782105748
Short name T119
Test name
Test status
Simulation time 262332090 ps
CPU time 5.4 seconds
Started Jun 29 05:29:25 PM PDT 24
Finished Jun 29 05:29:31 PM PDT 24
Peak memory 233144 kb
Host smart-71d74556-61a5-495b-ba1a-b4d36689c1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782105748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1782105748
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2575578324
Short name T530
Test name
Test status
Simulation time 316549216 ps
CPU time 2.44 seconds
Started Jun 29 05:29:22 PM PDT 24
Finished Jun 29 05:29:25 PM PDT 24
Peak memory 233180 kb
Host smart-cb8814bb-2c13-442e-b88f-7163b623d74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575578324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2575578324
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4294944757
Short name T48
Test name
Test status
Simulation time 296157963 ps
CPU time 5.98 seconds
Started Jun 29 05:29:26 PM PDT 24
Finished Jun 29 05:29:32 PM PDT 24
Peak memory 233128 kb
Host smart-78a7c7eb-d499-4824-9f02-29606097724f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294944757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4294944757
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2083664821
Short name T214
Test name
Test status
Simulation time 9585638060 ps
CPU time 25.47 seconds
Started Jun 29 05:29:26 PM PDT 24
Finished Jun 29 05:29:52 PM PDT 24
Peak memory 233316 kb
Host smart-03526df8-ccd2-4aae-b4e0-0171d449a97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083664821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2083664821
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.247958871
Short name T365
Test name
Test status
Simulation time 2131355998 ps
CPU time 5.19 seconds
Started Jun 29 05:29:31 PM PDT 24
Finished Jun 29 05:29:37 PM PDT 24
Peak memory 223164 kb
Host smart-1de0866f-b748-4cc0-a6dc-97704f450be6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=247958871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.247958871
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2477978089
Short name T631
Test name
Test status
Simulation time 1428987396 ps
CPU time 5.77 seconds
Started Jun 29 05:29:30 PM PDT 24
Finished Jun 29 05:29:37 PM PDT 24
Peak memory 220352 kb
Host smart-5eef454b-0b44-4a0c-ad97-e8b9f42ad0e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477978089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2477978089
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2724389821
Short name T991
Test name
Test status
Simulation time 1414469277 ps
CPU time 16.64 seconds
Started Jun 29 05:29:24 PM PDT 24
Finished Jun 29 05:29:41 PM PDT 24
Peak memory 220532 kb
Host smart-9a69362a-7382-4c48-baca-6c065b899ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724389821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2724389821
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3848920387
Short name T606
Test name
Test status
Simulation time 3670671616 ps
CPU time 3.34 seconds
Started Jun 29 05:29:23 PM PDT 24
Finished Jun 29 05:29:27 PM PDT 24
Peak memory 217732 kb
Host smart-d07ada06-302e-4cf1-b0de-be2baf59776b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848920387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3848920387
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.609476991
Short name T761
Test name
Test status
Simulation time 41121414 ps
CPU time 0.82 seconds
Started Jun 29 05:29:28 PM PDT 24
Finished Jun 29 05:29:29 PM PDT 24
Peak memory 206384 kb
Host smart-021bb6f1-2cea-476a-8efd-a60497c73d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609476991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.609476991
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3625391870
Short name T643
Test name
Test status
Simulation time 20496821 ps
CPU time 0.8 seconds
Started Jun 29 05:29:27 PM PDT 24
Finished Jun 29 05:29:28 PM PDT 24
Peak memory 206452 kb
Host smart-efc36af1-370e-4959-a8d0-4f3696057741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625391870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3625391870
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.466848720
Short name T455
Test name
Test status
Simulation time 305620954 ps
CPU time 2.46 seconds
Started Jun 29 05:29:25 PM PDT 24
Finished Jun 29 05:29:28 PM PDT 24
Peak memory 224764 kb
Host smart-b6dfc3bb-7528-4e47-95ba-d52196a759ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466848720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.466848720
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2392792475
Short name T936
Test name
Test status
Simulation time 31105375 ps
CPU time 0.71 seconds
Started Jun 29 05:29:32 PM PDT 24
Finished Jun 29 05:29:33 PM PDT 24
Peak memory 206284 kb
Host smart-233bcdfc-8ede-4628-bf44-63559d0f35ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392792475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2392792475
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1773194784
Short name T188
Test name
Test status
Simulation time 54100851 ps
CPU time 2.48 seconds
Started Jun 29 05:29:33 PM PDT 24
Finished Jun 29 05:29:36 PM PDT 24
Peak memory 224932 kb
Host smart-0948a411-d7ae-4712-b8e0-9cf25d87a4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773194784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1773194784
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.961893004
Short name T498
Test name
Test status
Simulation time 19648676 ps
CPU time 0.79 seconds
Started Jun 29 05:29:31 PM PDT 24
Finished Jun 29 05:29:33 PM PDT 24
Peak memory 206964 kb
Host smart-15e854a4-fb03-49c1-a06e-d7b976e9d409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961893004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.961893004
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1436814366
Short name T299
Test name
Test status
Simulation time 44914752368 ps
CPU time 346.12 seconds
Started Jun 29 05:29:43 PM PDT 24
Finished Jun 29 05:35:30 PM PDT 24
Peak memory 265324 kb
Host smart-8c253b28-cff2-454c-9563-3e79f271870a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436814366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1436814366
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1067838570
Short name T501
Test name
Test status
Simulation time 14820034551 ps
CPU time 78.64 seconds
Started Jun 29 05:29:30 PM PDT 24
Finished Jun 29 05:30:49 PM PDT 24
Peak memory 249844 kb
Host smart-4dc75a02-d785-4ac3-a4b7-c2f5394f390d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067838570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1067838570
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.235698839
Short name T825
Test name
Test status
Simulation time 1001144396 ps
CPU time 3.45 seconds
Started Jun 29 05:29:33 PM PDT 24
Finished Jun 29 05:29:37 PM PDT 24
Peak memory 233200 kb
Host smart-b9abcf85-b5e9-4d6b-9f65-211e54a88ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235698839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.235698839
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3976756314
Short name T186
Test name
Test status
Simulation time 10788846826 ps
CPU time 92.77 seconds
Started Jun 29 05:29:33 PM PDT 24
Finished Jun 29 05:31:06 PM PDT 24
Peak memory 250244 kb
Host smart-ea8818db-bca1-4512-92f5-661d7ff07a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976756314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3976756314
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2054350150
Short name T622
Test name
Test status
Simulation time 2583653711 ps
CPU time 12.57 seconds
Started Jun 29 05:29:43 PM PDT 24
Finished Jun 29 05:29:57 PM PDT 24
Peak memory 225120 kb
Host smart-f050fae7-5fd0-4870-9a0c-325a3d6e7051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054350150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2054350150
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1545588835
Short name T907
Test name
Test status
Simulation time 24063057941 ps
CPU time 89.11 seconds
Started Jun 29 05:29:43 PM PDT 24
Finished Jun 29 05:31:13 PM PDT 24
Peak memory 233312 kb
Host smart-0bde5a3f-b80e-42c9-a13d-9651e7dbfd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545588835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1545588835
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1567210761
Short name T243
Test name
Test status
Simulation time 4359059978 ps
CPU time 13.23 seconds
Started Jun 29 05:29:33 PM PDT 24
Finished Jun 29 05:29:46 PM PDT 24
Peak memory 225008 kb
Host smart-6b634a5d-9132-48cb-8d85-70a60b2f3f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567210761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1567210761
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1039101271
Short name T79
Test name
Test status
Simulation time 1732000956 ps
CPU time 4.9 seconds
Started Jun 29 05:29:31 PM PDT 24
Finished Jun 29 05:29:36 PM PDT 24
Peak memory 225012 kb
Host smart-74d52c45-a553-4251-9833-fe5125fda672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039101271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1039101271
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2015038132
Short name T533
Test name
Test status
Simulation time 1602295004 ps
CPU time 10.12 seconds
Started Jun 29 05:29:32 PM PDT 24
Finished Jun 29 05:29:43 PM PDT 24
Peak memory 222652 kb
Host smart-c69d3def-5aaa-4636-a1a4-a72e5da21efa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2015038132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2015038132
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.738388227
Short name T727
Test name
Test status
Simulation time 9350291978 ps
CPU time 131.85 seconds
Started Jun 29 05:29:44 PM PDT 24
Finished Jun 29 05:31:57 PM PDT 24
Peak memory 249920 kb
Host smart-b93ee9c5-5dee-4361-b069-01d0e7601546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738388227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.738388227
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3196017509
Short name T746
Test name
Test status
Simulation time 2132250248 ps
CPU time 30.11 seconds
Started Jun 29 05:29:32 PM PDT 24
Finished Jun 29 05:30:02 PM PDT 24
Peak memory 217124 kb
Host smart-23d21e72-10be-4402-9cee-c0f080e5a1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196017509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3196017509
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.996987261
Short name T876
Test name
Test status
Simulation time 2923353493 ps
CPU time 3.02 seconds
Started Jun 29 05:29:31 PM PDT 24
Finished Jun 29 05:29:34 PM PDT 24
Peak memory 216916 kb
Host smart-1f1da1fb-245d-4d6d-aa4d-73fa4daf9a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996987261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.996987261
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1865402357
Short name T471
Test name
Test status
Simulation time 109767221 ps
CPU time 1.68 seconds
Started Jun 29 05:29:47 PM PDT 24
Finished Jun 29 05:29:50 PM PDT 24
Peak memory 216844 kb
Host smart-c64681b5-578b-47d8-920d-c5b787825355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865402357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1865402357
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2546819573
Short name T898
Test name
Test status
Simulation time 20912017 ps
CPU time 0.76 seconds
Started Jun 29 05:29:31 PM PDT 24
Finished Jun 29 05:29:32 PM PDT 24
Peak memory 206452 kb
Host smart-34f8d359-c483-4060-8ab4-79b9b86c8d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546819573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2546819573
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.47012060
Short name T494
Test name
Test status
Simulation time 12183242020 ps
CPU time 44.87 seconds
Started Jun 29 05:29:31 PM PDT 24
Finished Jun 29 05:30:16 PM PDT 24
Peak memory 236332 kb
Host smart-235c2f77-7fbb-47cd-bad1-4ee0ba399cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47012060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.47012060
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1597259875
Short name T633
Test name
Test status
Simulation time 11622777 ps
CPU time 0.72 seconds
Started Jun 29 05:29:44 PM PDT 24
Finished Jun 29 05:29:46 PM PDT 24
Peak memory 205280 kb
Host smart-2313ca0c-4535-47d0-8bde-3977160f2f47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597259875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1597259875
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2595336144
Short name T409
Test name
Test status
Simulation time 48823173 ps
CPU time 2.63 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:29:49 PM PDT 24
Peak memory 232964 kb
Host smart-b530121f-5724-4981-b795-b6ca86cd2814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595336144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2595336144
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.943324800
Short name T636
Test name
Test status
Simulation time 44837552 ps
CPU time 0.76 seconds
Started Jun 29 05:29:47 PM PDT 24
Finished Jun 29 05:29:49 PM PDT 24
Peak memory 206064 kb
Host smart-953ccca6-0409-4ee3-813c-6f1cdf82e608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943324800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.943324800
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1712763011
Short name T714
Test name
Test status
Simulation time 11345738567 ps
CPU time 131.21 seconds
Started Jun 29 05:29:44 PM PDT 24
Finished Jun 29 05:31:57 PM PDT 24
Peak memory 249840 kb
Host smart-f5b27228-08e3-4ef5-b5f1-92b770308bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712763011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1712763011
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4125954867
Short name T909
Test name
Test status
Simulation time 48284282 ps
CPU time 2.92 seconds
Started Jun 29 05:29:47 PM PDT 24
Finished Jun 29 05:29:51 PM PDT 24
Peak memory 233420 kb
Host smart-36db0da1-8f53-4cab-882a-e8b5724901be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125954867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4125954867
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1059603725
Short name T927
Test name
Test status
Simulation time 4424239295 ps
CPU time 31.21 seconds
Started Jun 29 05:29:43 PM PDT 24
Finished Jun 29 05:30:16 PM PDT 24
Peak memory 249724 kb
Host smart-31569346-2ce7-4995-b483-45bd00005848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059603725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1059603725
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1827835714
Short name T525
Test name
Test status
Simulation time 1989912938 ps
CPU time 3.33 seconds
Started Jun 29 05:29:31 PM PDT 24
Finished Jun 29 05:29:35 PM PDT 24
Peak memory 224972 kb
Host smart-86ae9e16-7eae-4d14-b0ad-b98f6032fc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827835714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1827835714
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3688210212
Short name T602
Test name
Test status
Simulation time 33850409132 ps
CPU time 63.18 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:30:50 PM PDT 24
Peak memory 241364 kb
Host smart-6487c185-60af-44b8-9e4d-584f030f14e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688210212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3688210212
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2347860336
Short name T203
Test name
Test status
Simulation time 12206840942 ps
CPU time 43.45 seconds
Started Jun 29 05:29:30 PM PDT 24
Finished Jun 29 05:30:14 PM PDT 24
Peak memory 233336 kb
Host smart-347eb121-bcd8-4fad-adbe-a7eaf2fa9971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347860336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2347860336
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2845750216
Short name T261
Test name
Test status
Simulation time 1208348715 ps
CPU time 6.18 seconds
Started Jun 29 05:29:31 PM PDT 24
Finished Jun 29 05:29:38 PM PDT 24
Peak memory 233128 kb
Host smart-14c027f4-4a40-4feb-b632-be4c7d581137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845750216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2845750216
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2410916329
Short name T977
Test name
Test status
Simulation time 441812602 ps
CPU time 5.95 seconds
Started Jun 29 05:29:43 PM PDT 24
Finished Jun 29 05:29:50 PM PDT 24
Peak memory 222800 kb
Host smart-a63e768c-bd1c-4f84-b98c-8366aba0c818
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2410916329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2410916329
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2828544467
Short name T221
Test name
Test status
Simulation time 81322106438 ps
CPU time 390.79 seconds
Started Jun 29 05:29:44 PM PDT 24
Finished Jun 29 05:36:16 PM PDT 24
Peak memory 271596 kb
Host smart-14c542fa-ec03-47c7-a47c-9a8b6e2ac3ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828544467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2828544467
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2821195679
Short name T768
Test name
Test status
Simulation time 6276131609 ps
CPU time 9.72 seconds
Started Jun 29 05:29:43 PM PDT 24
Finished Jun 29 05:29:54 PM PDT 24
Peak memory 216832 kb
Host smart-0fda1dda-6bec-41a5-a2ed-f74f121e381d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821195679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2821195679
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3020099723
Short name T687
Test name
Test status
Simulation time 11651099474 ps
CPU time 12.83 seconds
Started Jun 29 05:29:32 PM PDT 24
Finished Jun 29 05:29:46 PM PDT 24
Peak memory 216900 kb
Host smart-ff2c570f-8264-45c3-8468-4b4c0abf382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020099723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3020099723
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.283831759
Short name T855
Test name
Test status
Simulation time 109739218 ps
CPU time 1.18 seconds
Started Jun 29 05:29:44 PM PDT 24
Finished Jun 29 05:29:46 PM PDT 24
Peak memory 207708 kb
Host smart-88398fde-7f5c-49cb-b256-bd89c87351af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283831759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.283831759
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3796593293
Short name T637
Test name
Test status
Simulation time 35651887 ps
CPU time 0.7 seconds
Started Jun 29 05:29:30 PM PDT 24
Finished Jun 29 05:29:32 PM PDT 24
Peak memory 206116 kb
Host smart-6dbbbf7e-94cc-49db-ae38-f8a5de8f069d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796593293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3796593293
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2661034282
Short name T809
Test name
Test status
Simulation time 171372337916 ps
CPU time 28.53 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:30:15 PM PDT 24
Peak memory 233340 kb
Host smart-8d43d030-f891-412c-9107-2f74fdb4bc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661034282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2661034282
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4092695187
Short name T368
Test name
Test status
Simulation time 13042949 ps
CPU time 0.73 seconds
Started Jun 29 05:29:48 PM PDT 24
Finished Jun 29 05:29:50 PM PDT 24
Peak memory 205260 kb
Host smart-b0f785b8-ad60-451c-a39d-d2d1503a483b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092695187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4092695187
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1711943072
Short name T726
Test name
Test status
Simulation time 265817897 ps
CPU time 5.49 seconds
Started Jun 29 05:29:48 PM PDT 24
Finished Jun 29 05:29:55 PM PDT 24
Peak memory 224912 kb
Host smart-8ceb8fef-6cec-4eec-b044-f10465eaa17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711943072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1711943072
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1463134721
Short name T428
Test name
Test status
Simulation time 67283388 ps
CPU time 0.89 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:29:47 PM PDT 24
Peak memory 207108 kb
Host smart-19f0f51e-1cfb-4169-836a-8d06e33be1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463134721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1463134721
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2962479258
Short name T298
Test name
Test status
Simulation time 29196843595 ps
CPU time 211.51 seconds
Started Jun 29 05:29:44 PM PDT 24
Finished Jun 29 05:33:17 PM PDT 24
Peak memory 249732 kb
Host smart-9a47c8c9-3cff-4da6-945d-24da1be6d3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962479258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2962479258
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2331844350
Short name T239
Test name
Test status
Simulation time 437988096062 ps
CPU time 284.45 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:34:30 PM PDT 24
Peak memory 258220 kb
Host smart-2db5793c-66e2-4c20-980f-c160ea97bfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331844350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2331844350
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1516942880
Short name T831
Test name
Test status
Simulation time 2862465822 ps
CPU time 72.44 seconds
Started Jun 29 05:29:43 PM PDT 24
Finished Jun 29 05:30:57 PM PDT 24
Peak memory 256320 kb
Host smart-d0116519-4abf-4c94-9e62-878a13957978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516942880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1516942880
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4094469035
Short name T312
Test name
Test status
Simulation time 227024053 ps
CPU time 7.2 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:29:53 PM PDT 24
Peak memory 238344 kb
Host smart-35dfa3a0-de09-439f-9d40-a821f24574a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094469035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4094469035
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3225702503
Short name T394
Test name
Test status
Simulation time 23288576 ps
CPU time 0.83 seconds
Started Jun 29 05:29:47 PM PDT 24
Finished Jun 29 05:29:50 PM PDT 24
Peak memory 216860 kb
Host smart-a80b329d-a323-4cb6-b441-18a68111113b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225702503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3225702503
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.162535025
Short name T220
Test name
Test status
Simulation time 1289911548 ps
CPU time 6.56 seconds
Started Jun 29 05:29:43 PM PDT 24
Finished Jun 29 05:29:50 PM PDT 24
Peak memory 224964 kb
Host smart-a65c40b3-587b-4295-af52-ea7598b74b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162535025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.162535025
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2898211758
Short name T238
Test name
Test status
Simulation time 15503310962 ps
CPU time 29.79 seconds
Started Jun 29 05:29:48 PM PDT 24
Finished Jun 29 05:30:19 PM PDT 24
Peak memory 240856 kb
Host smart-3e41975a-58a5-431a-afd0-dc447e8645d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898211758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2898211758
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2486989308
Short name T654
Test name
Test status
Simulation time 11815462253 ps
CPU time 10.97 seconds
Started Jun 29 05:29:43 PM PDT 24
Finished Jun 29 05:29:56 PM PDT 24
Peak memory 233232 kb
Host smart-c1a7d35f-5958-4716-80ce-b95c61cb6be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486989308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2486989308
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3206736246
Short name T821
Test name
Test status
Simulation time 5524802861 ps
CPU time 6.97 seconds
Started Jun 29 05:29:46 PM PDT 24
Finished Jun 29 05:29:55 PM PDT 24
Peak memory 233288 kb
Host smart-50a26dab-2e74-49a4-9117-d5bfbd9af460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206736246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3206736246
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2480759097
Short name T563
Test name
Test status
Simulation time 945487702 ps
CPU time 3.82 seconds
Started Jun 29 05:29:42 PM PDT 24
Finished Jun 29 05:29:47 PM PDT 24
Peak memory 219244 kb
Host smart-ea8deffa-6bc7-4f47-b772-7593b4188adc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2480759097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2480759097
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3934399389
Short name T18
Test name
Test status
Simulation time 68977836 ps
CPU time 0.99 seconds
Started Jun 29 05:29:42 PM PDT 24
Finished Jun 29 05:29:43 PM PDT 24
Peak memory 207384 kb
Host smart-57e2b3bf-581a-4477-813e-a5d9def6c4a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934399389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3934399389
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4208517549
Short name T171
Test name
Test status
Simulation time 542079907 ps
CPU time 5.73 seconds
Started Jun 29 05:29:43 PM PDT 24
Finished Jun 29 05:29:51 PM PDT 24
Peak memory 216832 kb
Host smart-7c609603-c82c-44ad-a4b2-0f3370d97ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208517549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4208517549
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1735789809
Short name T450
Test name
Test status
Simulation time 945182754 ps
CPU time 3.89 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:29:50 PM PDT 24
Peak memory 216792 kb
Host smart-40a5b1c0-9191-471c-9d0d-7a82310e2656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735789809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1735789809
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3931177685
Short name T4
Test name
Test status
Simulation time 33609836 ps
CPU time 0.82 seconds
Started Jun 29 05:29:46 PM PDT 24
Finished Jun 29 05:29:48 PM PDT 24
Peak memory 206468 kb
Host smart-92d70237-fd02-4a38-841f-f703adaa58bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931177685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3931177685
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2603367553
Short name T396
Test name
Test status
Simulation time 398439228 ps
CPU time 0.89 seconds
Started Jun 29 05:29:44 PM PDT 24
Finished Jun 29 05:29:46 PM PDT 24
Peak memory 206452 kb
Host smart-df36291a-4ea8-47ee-bb23-b53f9100f120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603367553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2603367553
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1460016016
Short name T987
Test name
Test status
Simulation time 1235792061 ps
CPU time 6.25 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:29:52 PM PDT 24
Peak memory 233132 kb
Host smart-dcc7f09d-4bfc-46d3-9511-41ebacf6d69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460016016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1460016016
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1067389861
Short name T1006
Test name
Test status
Simulation time 11941469 ps
CPU time 0.75 seconds
Started Jun 29 05:29:52 PM PDT 24
Finished Jun 29 05:29:54 PM PDT 24
Peak memory 205292 kb
Host smart-8a9d2ea7-6266-4b8b-ac64-f6aadcaf724a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067389861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1067389861
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1591818430
Short name T9
Test name
Test status
Simulation time 130401787 ps
CPU time 2.64 seconds
Started Jun 29 05:29:47 PM PDT 24
Finished Jun 29 05:29:52 PM PDT 24
Peak memory 224964 kb
Host smart-9d799bca-7036-48bd-a9a9-3f3c167d3731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591818430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1591818430
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.31785671
Short name T356
Test name
Test status
Simulation time 65368707 ps
CPU time 0.73 seconds
Started Jun 29 05:29:44 PM PDT 24
Finished Jun 29 05:29:46 PM PDT 24
Peak memory 207056 kb
Host smart-76868484-ba5f-480e-aa8e-ede052033ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31785671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.31785671
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3110348216
Short name T405
Test name
Test status
Simulation time 2617039580 ps
CPU time 27.19 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:30:13 PM PDT 24
Peak memory 239836 kb
Host smart-fe94959b-a8f5-4899-b1b8-29e5b155c6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110348216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3110348216
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2337890852
Short name T677
Test name
Test status
Simulation time 7638718091 ps
CPU time 88.46 seconds
Started Jun 29 05:29:50 PM PDT 24
Finished Jun 29 05:31:20 PM PDT 24
Peak memory 258048 kb
Host smart-d541f5e0-2a31-4db0-b65f-21c76c890eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337890852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2337890852
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1604521168
Short name T473
Test name
Test status
Simulation time 1572603602 ps
CPU time 8.56 seconds
Started Jun 29 05:29:52 PM PDT 24
Finished Jun 29 05:30:01 PM PDT 24
Peak memory 233172 kb
Host smart-e1637027-2f80-4781-8451-a715fe1e4bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604521168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1604521168
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4164703219
Short name T945
Test name
Test status
Simulation time 5295861964 ps
CPU time 38.28 seconds
Started Jun 29 05:29:47 PM PDT 24
Finished Jun 29 05:30:27 PM PDT 24
Peak memory 257836 kb
Host smart-613d240f-7fda-40a5-b10b-672f7a0d9209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164703219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4164703219
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2162583727
Short name T702
Test name
Test status
Simulation time 535539635 ps
CPU time 3.65 seconds
Started Jun 29 05:29:47 PM PDT 24
Finished Jun 29 05:29:52 PM PDT 24
Peak memory 233172 kb
Host smart-e491467b-fe59-41b9-b151-3155aa17de97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162583727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2162583727
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3806672381
Short name T897
Test name
Test status
Simulation time 289135956 ps
CPU time 2.61 seconds
Started Jun 29 05:29:46 PM PDT 24
Finished Jun 29 05:29:50 PM PDT 24
Peak memory 224964 kb
Host smart-df173076-a5df-47d8-a92c-9fa48fe4488c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806672381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3806672381
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.224849789
Short name T615
Test name
Test status
Simulation time 12605050978 ps
CPU time 15.76 seconds
Started Jun 29 05:29:49 PM PDT 24
Finished Jun 29 05:30:07 PM PDT 24
Peak memory 233284 kb
Host smart-cb646100-ee61-4a0b-9761-03f3df6bbefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224849789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.224849789
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1771418645
Short name T390
Test name
Test status
Simulation time 24552450225 ps
CPU time 19.97 seconds
Started Jun 29 05:29:44 PM PDT 24
Finished Jun 29 05:30:06 PM PDT 24
Peak memory 233232 kb
Host smart-40f6a982-9895-425c-ab87-69d0503df902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771418645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1771418645
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3648272165
Short name T738
Test name
Test status
Simulation time 4199537276 ps
CPU time 11.73 seconds
Started Jun 29 05:29:50 PM PDT 24
Finished Jun 29 05:30:03 PM PDT 24
Peak memory 223736 kb
Host smart-8a805a40-7edf-49dc-b7c0-2a8ee93eeb0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3648272165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3648272165
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.30968366
Short name T13
Test name
Test status
Simulation time 71078241 ps
CPU time 1.09 seconds
Started Jun 29 05:29:47 PM PDT 24
Finished Jun 29 05:29:50 PM PDT 24
Peak memory 207636 kb
Host smart-820856e6-0c59-40fd-895e-c2d2fadf6224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30968366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress
_all.30968366
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1300607213
Short name T951
Test name
Test status
Simulation time 751815059 ps
CPU time 2.59 seconds
Started Jun 29 05:29:46 PM PDT 24
Finished Jun 29 05:29:50 PM PDT 24
Peak memory 216784 kb
Host smart-62cb115e-2001-4db6-a995-d2c3059d1fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300607213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1300607213
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2531637750
Short name T5
Test name
Test status
Simulation time 109870829 ps
CPU time 0.71 seconds
Started Jun 29 05:29:44 PM PDT 24
Finished Jun 29 05:29:46 PM PDT 24
Peak memory 206180 kb
Host smart-068f27a5-33dc-4141-a206-d5144e64f7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531637750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2531637750
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3970366987
Short name T407
Test name
Test status
Simulation time 183870896 ps
CPU time 1.19 seconds
Started Jun 29 05:29:49 PM PDT 24
Finished Jun 29 05:29:52 PM PDT 24
Peak memory 208204 kb
Host smart-42253d49-5779-459e-820e-df01a7140787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970366987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3970366987
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3743669800
Short name T628
Test name
Test status
Simulation time 33090264 ps
CPU time 0.87 seconds
Started Jun 29 05:29:48 PM PDT 24
Finished Jun 29 05:29:51 PM PDT 24
Peak memory 206368 kb
Host smart-a4de3e61-08f4-40ec-ab91-0122b7ceca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743669800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3743669800
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3925660106
Short name T587
Test name
Test status
Simulation time 6156509445 ps
CPU time 10.15 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:29:57 PM PDT 24
Peak memory 225140 kb
Host smart-0078bcc7-8141-42c1-9117-8c67dc1dba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925660106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3925660106
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2740798781
Short name T355
Test name
Test status
Simulation time 36272945 ps
CPU time 0.73 seconds
Started Jun 29 05:29:47 PM PDT 24
Finished Jun 29 05:29:50 PM PDT 24
Peak memory 206224 kb
Host smart-ba985b8c-42de-4ad0-a1d4-13c336d60205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740798781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2740798781
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2690287140
Short name T828
Test name
Test status
Simulation time 64262894 ps
CPU time 2.63 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:29:49 PM PDT 24
Peak memory 233192 kb
Host smart-ebc3d423-32ed-441c-9ee3-683bf473a7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690287140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2690287140
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1545200553
Short name T811
Test name
Test status
Simulation time 19616782 ps
CPU time 0.82 seconds
Started Jun 29 05:29:49 PM PDT 24
Finished Jun 29 05:29:51 PM PDT 24
Peak memory 207424 kb
Host smart-1f32d820-48fc-4416-b2fe-8de52a0e9fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545200553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1545200553
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1498190441
Short name T236
Test name
Test status
Simulation time 21301789418 ps
CPU time 208.87 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:33:15 PM PDT 24
Peak memory 266104 kb
Host smart-75734dd1-7fe6-493d-ab2f-1a6261a6ddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498190441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1498190441
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.747662714
Short name T1010
Test name
Test status
Simulation time 43646590147 ps
CPU time 87.77 seconds
Started Jun 29 05:29:49 PM PDT 24
Finished Jun 29 05:31:19 PM PDT 24
Peak memory 249860 kb
Host smart-4d276277-cbc6-40d8-98cb-587d867b4365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747662714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.747662714
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.397715484
Short name T965
Test name
Test status
Simulation time 25154909518 ps
CPU time 115.93 seconds
Started Jun 29 05:29:46 PM PDT 24
Finished Jun 29 05:31:43 PM PDT 24
Peak memory 249812 kb
Host smart-77e08d31-2724-49af-97e5-19b2e74ff2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397715484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.397715484
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3594337628
Short name T536
Test name
Test status
Simulation time 46066085 ps
CPU time 2.78 seconds
Started Jun 29 05:29:48 PM PDT 24
Finished Jun 29 05:29:53 PM PDT 24
Peak memory 224972 kb
Host smart-237b53ea-65b1-456b-8969-7273c8596284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594337628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3594337628
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3475873926
Short name T734
Test name
Test status
Simulation time 16459825268 ps
CPU time 113.15 seconds
Started Jun 29 05:29:46 PM PDT 24
Finished Jun 29 05:31:40 PM PDT 24
Peak memory 225132 kb
Host smart-a54dfb2d-e633-40ee-9a9d-bb25fb9d0ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475873926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3475873926
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2127339303
Short name T251
Test name
Test status
Simulation time 116198632 ps
CPU time 3.07 seconds
Started Jun 29 05:29:52 PM PDT 24
Finished Jun 29 05:29:56 PM PDT 24
Peak memory 233116 kb
Host smart-93a303b8-7716-4b38-8b22-96ed10154b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127339303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2127339303
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3926418082
Short name T842
Test name
Test status
Simulation time 104965994 ps
CPU time 3.71 seconds
Started Jun 29 05:29:47 PM PDT 24
Finished Jun 29 05:29:53 PM PDT 24
Peak memory 233224 kb
Host smart-76ed8869-96e0-40dc-ba2f-b39c99d4bc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926418082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3926418082
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.455275452
Short name T605
Test name
Test status
Simulation time 798854708 ps
CPU time 6.28 seconds
Started Jun 29 05:29:48 PM PDT 24
Finished Jun 29 05:29:56 PM PDT 24
Peak memory 224964 kb
Host smart-a752ae2e-f05a-4a05-88b4-fc39c385bb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455275452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.455275452
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3251206770
Short name T205
Test name
Test status
Simulation time 3378805281 ps
CPU time 13.33 seconds
Started Jun 29 05:29:48 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 233304 kb
Host smart-0833faa2-aaf0-4126-a000-ccbbcd8359dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251206770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3251206770
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2943181984
Short name T466
Test name
Test status
Simulation time 7656809958 ps
CPU time 11.27 seconds
Started Jun 29 05:29:48 PM PDT 24
Finished Jun 29 05:30:02 PM PDT 24
Peak memory 220412 kb
Host smart-5a3ce537-a09b-428e-a0cd-4486494d0d47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2943181984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2943181984
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1878344629
Short name T971
Test name
Test status
Simulation time 233332434 ps
CPU time 1.17 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:29:48 PM PDT 24
Peak memory 208296 kb
Host smart-36469bc6-34de-426f-83d2-5e9f47fc098c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878344629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1878344629
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.469894605
Short name T708
Test name
Test status
Simulation time 1329529678 ps
CPU time 14.48 seconds
Started Jun 29 05:29:47 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 220644 kb
Host smart-5583145c-a91d-495a-abb3-380f733ce8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469894605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.469894605
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1393654177
Short name T669
Test name
Test status
Simulation time 10384303 ps
CPU time 0.69 seconds
Started Jun 29 05:29:47 PM PDT 24
Finished Jun 29 05:29:49 PM PDT 24
Peak memory 206140 kb
Host smart-2720e07a-4736-4886-b71b-84361014fb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393654177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1393654177
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2287617714
Short name T578
Test name
Test status
Simulation time 36858626 ps
CPU time 0.98 seconds
Started Jun 29 05:29:44 PM PDT 24
Finished Jun 29 05:29:46 PM PDT 24
Peak memory 207484 kb
Host smart-9813b8d9-fb6c-4fb4-a149-0714326307e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287617714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2287617714
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2895342423
Short name T500
Test name
Test status
Simulation time 93161990 ps
CPU time 0.84 seconds
Started Jun 29 05:29:46 PM PDT 24
Finished Jun 29 05:29:48 PM PDT 24
Peak memory 206380 kb
Host smart-b4d375f0-f58e-464e-a2a5-b214bb315931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895342423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2895342423
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4249524160
Short name T266
Test name
Test status
Simulation time 371020206 ps
CPU time 3.03 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:29:50 PM PDT 24
Peak memory 236196 kb
Host smart-c64af8ae-4b11-47c1-a5ca-6e66de09d79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249524160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4249524160
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3474821475
Short name T378
Test name
Test status
Simulation time 13255478 ps
CPU time 0.7 seconds
Started Jun 29 05:29:50 PM PDT 24
Finished Jun 29 05:29:52 PM PDT 24
Peak memory 205956 kb
Host smart-e56fe9e2-c44f-4330-9a14-2fc4bf63e878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474821475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3474821475
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1134374975
Short name T141
Test name
Test status
Simulation time 252330936 ps
CPU time 2.04 seconds
Started Jun 29 05:29:54 PM PDT 24
Finished Jun 29 05:29:56 PM PDT 24
Peak memory 224908 kb
Host smart-93601f9b-d6e7-4403-a1c8-fa187dce533b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134374975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1134374975
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3512984507
Short name T815
Test name
Test status
Simulation time 56193590 ps
CPU time 0.83 seconds
Started Jun 29 05:29:54 PM PDT 24
Finished Jun 29 05:29:55 PM PDT 24
Peak memory 207068 kb
Host smart-ba68ff48-70dd-46ba-b1eb-e66419ce2907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512984507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3512984507
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.976370928
Short name T197
Test name
Test status
Simulation time 106380224901 ps
CPU time 224.79 seconds
Started Jun 29 05:29:49 PM PDT 24
Finished Jun 29 05:33:36 PM PDT 24
Peak memory 249916 kb
Host smart-414d7a00-ee02-4d93-bc7b-65b7a554903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976370928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.976370928
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.57687774
Short name T655
Test name
Test status
Simulation time 8542362186 ps
CPU time 43.86 seconds
Started Jun 29 05:29:54 PM PDT 24
Finished Jun 29 05:30:39 PM PDT 24
Peak memory 218276 kb
Host smart-5e48d3f8-7c3c-4f3d-b2cf-1a8a5b9bf089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57687774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.57687774
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2161183761
Short name T301
Test name
Test status
Simulation time 2479850945 ps
CPU time 66 seconds
Started Jun 29 05:29:54 PM PDT 24
Finished Jun 29 05:31:00 PM PDT 24
Peak memory 252132 kb
Host smart-4023ded4-cc5a-41a5-b235-f822b94d059d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161183761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2161183761
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.955526794
Short name T509
Test name
Test status
Simulation time 2716548557 ps
CPU time 6.07 seconds
Started Jun 29 05:29:49 PM PDT 24
Finished Jun 29 05:29:57 PM PDT 24
Peak memory 241548 kb
Host smart-e74d1f4b-ac97-46e5-9a8d-2ff0f4cc16cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955526794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.955526794
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1442313685
Short name T862
Test name
Test status
Simulation time 8213350563 ps
CPU time 37.49 seconds
Started Jun 29 05:29:49 PM PDT 24
Finished Jun 29 05:30:28 PM PDT 24
Peak memory 255192 kb
Host smart-9c23ef8d-cd9f-4111-b384-fb305c0241b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442313685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1442313685
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2740731902
Short name T937
Test name
Test status
Simulation time 1419034118 ps
CPU time 7.77 seconds
Started Jun 29 05:29:52 PM PDT 24
Finished Jun 29 05:30:01 PM PDT 24
Peak memory 224964 kb
Host smart-51298bad-cb94-4af4-9fe1-bae4a1341d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740731902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2740731902
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1761065378
Short name T52
Test name
Test status
Simulation time 2894266900 ps
CPU time 23.68 seconds
Started Jun 29 05:29:48 PM PDT 24
Finished Jun 29 05:30:13 PM PDT 24
Peak memory 233264 kb
Host smart-9264aacd-e4f5-4b18-861c-5b328fcb9870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761065378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1761065378
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.440312891
Short name T966
Test name
Test status
Simulation time 8454155610 ps
CPU time 5.88 seconds
Started Jun 29 05:29:49 PM PDT 24
Finished Jun 29 05:29:57 PM PDT 24
Peak memory 233336 kb
Host smart-37288f92-72b3-4876-9f82-75353243c146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440312891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.440312891
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3287903988
Short name T863
Test name
Test status
Simulation time 1126249147 ps
CPU time 5.72 seconds
Started Jun 29 05:29:49 PM PDT 24
Finished Jun 29 05:29:57 PM PDT 24
Peak memory 241304 kb
Host smart-5845144a-f809-41e8-b32b-3f7124d270cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287903988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3287903988
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.51834296
Short name T969
Test name
Test status
Simulation time 1615069229 ps
CPU time 9.67 seconds
Started Jun 29 05:29:50 PM PDT 24
Finished Jun 29 05:30:01 PM PDT 24
Peak memory 222572 kb
Host smart-72955ad3-1eb9-4195-8455-ca6de15f9514
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=51834296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direc
t.51834296
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3967452348
Short name T332
Test name
Test status
Simulation time 83282214387 ps
CPU time 84.23 seconds
Started Jun 29 05:29:54 PM PDT 24
Finished Jun 29 05:31:19 PM PDT 24
Peak memory 255656 kb
Host smart-fb052623-4ccf-440f-a000-60ef82131a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967452348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3967452348
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2524832377
Short name T507
Test name
Test status
Simulation time 3109224556 ps
CPU time 13.45 seconds
Started Jun 29 05:29:45 PM PDT 24
Finished Jun 29 05:30:00 PM PDT 24
Peak memory 217292 kb
Host smart-582b8297-ed54-434e-a730-7f324dbec4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524832377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2524832377
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3710634719
Short name T88
Test name
Test status
Simulation time 288633131 ps
CPU time 2.44 seconds
Started Jun 29 05:29:48 PM PDT 24
Finished Jun 29 05:29:53 PM PDT 24
Peak memory 216760 kb
Host smart-1910e6d7-70c8-4605-b372-ce70c77aa4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710634719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3710634719
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2984862328
Short name T857
Test name
Test status
Simulation time 28317066 ps
CPU time 1.28 seconds
Started Jun 29 05:29:50 PM PDT 24
Finished Jun 29 05:29:52 PM PDT 24
Peak memory 216208 kb
Host smart-960f1ddc-ea73-417d-ad7f-c9d3b5d4785d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984862328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2984862328
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1038442544
Short name T555
Test name
Test status
Simulation time 71897609 ps
CPU time 0.96 seconds
Started Jun 29 05:29:48 PM PDT 24
Finished Jun 29 05:29:51 PM PDT 24
Peak memory 206452 kb
Host smart-c14d3433-e700-4e3d-b99e-6279683f3293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038442544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1038442544
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2818540941
Short name T45
Test name
Test status
Simulation time 988405667 ps
CPU time 7.11 seconds
Started Jun 29 05:29:46 PM PDT 24
Finished Jun 29 05:29:55 PM PDT 24
Peak memory 240652 kb
Host smart-63176341-d435-4a95-babe-b665400afee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818540941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2818540941
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3968602923
Short name T544
Test name
Test status
Simulation time 13884076 ps
CPU time 0.77 seconds
Started Jun 29 05:29:55 PM PDT 24
Finished Jun 29 05:29:57 PM PDT 24
Peak memory 206252 kb
Host smart-3c10e496-b28c-4278-b846-631a71e4d47e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968602923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3968602923
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.366475008
Short name T968
Test name
Test status
Simulation time 821099329 ps
CPU time 7.76 seconds
Started Jun 29 05:29:52 PM PDT 24
Finished Jun 29 05:30:01 PM PDT 24
Peak memory 233088 kb
Host smart-9e10c469-b1f5-4bbe-8efd-edc8385900ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366475008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.366475008
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1533007226
Short name T986
Test name
Test status
Simulation time 49800592 ps
CPU time 0.79 seconds
Started Jun 29 05:29:55 PM PDT 24
Finished Jun 29 05:29:57 PM PDT 24
Peak memory 206400 kb
Host smart-eb3d7ee6-de62-487a-ba14-d14db29d9e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533007226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1533007226
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2906378424
Short name T976
Test name
Test status
Simulation time 29824050459 ps
CPU time 96.32 seconds
Started Jun 29 05:29:54 PM PDT 24
Finished Jun 29 05:31:31 PM PDT 24
Peak memory 257604 kb
Host smart-8d48c77d-1bad-402b-a490-307d251c8b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906378424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2906378424
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2647527777
Short name T664
Test name
Test status
Simulation time 178378662280 ps
CPU time 298.73 seconds
Started Jun 29 05:29:55 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 253600 kb
Host smart-37c6a57b-2b48-43ff-8012-9f37bd48b296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647527777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2647527777
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1918200738
Short name T754
Test name
Test status
Simulation time 251025974 ps
CPU time 6.6 seconds
Started Jun 29 05:29:55 PM PDT 24
Finished Jun 29 05:30:03 PM PDT 24
Peak memory 233112 kb
Host smart-a497ee40-802d-40d4-9701-28a21fea9790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918200738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1918200738
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3260452956
Short name T95
Test name
Test status
Simulation time 1494032784 ps
CPU time 24.51 seconds
Started Jun 29 05:29:53 PM PDT 24
Finished Jun 29 05:30:18 PM PDT 24
Peak memory 257640 kb
Host smart-cddf2bf2-b448-434a-9386-0048b04d0c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260452956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3260452956
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.299906187
Short name T984
Test name
Test status
Simulation time 614900040 ps
CPU time 6.25 seconds
Started Jun 29 05:29:55 PM PDT 24
Finished Jun 29 05:30:02 PM PDT 24
Peak memory 224892 kb
Host smart-3856dacc-2095-4a29-8ffa-280d5795f736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299906187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.299906187
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2473217877
Short name T853
Test name
Test status
Simulation time 1204377912 ps
CPU time 7.9 seconds
Started Jun 29 05:29:54 PM PDT 24
Finished Jun 29 05:30:03 PM PDT 24
Peak memory 241092 kb
Host smart-fc8b3264-8829-44ca-b262-98f5aeff3ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473217877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2473217877
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.431711410
Short name T526
Test name
Test status
Simulation time 127132220 ps
CPU time 2.65 seconds
Started Jun 29 05:29:53 PM PDT 24
Finished Jun 29 05:29:56 PM PDT 24
Peak memory 232944 kb
Host smart-33e1b92d-6b19-4d5b-a71e-2dcc45d69e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431711410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.431711410
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3587575971
Short name T46
Test name
Test status
Simulation time 220344873 ps
CPU time 2.46 seconds
Started Jun 29 05:29:54 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 224956 kb
Host smart-f2ace496-6c84-41de-80b1-1843574d13a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587575971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3587575971
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3833810775
Short name T521
Test name
Test status
Simulation time 353119656 ps
CPU time 8.36 seconds
Started Jun 29 05:29:54 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 221332 kb
Host smart-855520c2-525e-4ba8-a489-55aa1f2d209a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3833810775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3833810775
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2499791342
Short name T16
Test name
Test status
Simulation time 9091041908 ps
CPU time 70.07 seconds
Started Jun 29 05:29:53 PM PDT 24
Finished Jun 29 05:31:03 PM PDT 24
Peak memory 249720 kb
Host smart-3b0566c6-7e3e-4d77-a04e-c45807745e7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499791342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2499791342
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3808892364
Short name T709
Test name
Test status
Simulation time 4946370186 ps
CPU time 6.73 seconds
Started Jun 29 05:29:58 PM PDT 24
Finished Jun 29 05:30:05 PM PDT 24
Peak memory 217008 kb
Host smart-12d8045c-b946-470e-b46e-ffa53f84d192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808892364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3808892364
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3366571520
Short name T477
Test name
Test status
Simulation time 700799191 ps
CPU time 5.89 seconds
Started Jun 29 05:29:57 PM PDT 24
Finished Jun 29 05:30:04 PM PDT 24
Peak memory 216760 kb
Host smart-192c5334-41f5-4dd7-b9fb-d02353cfb872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366571520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3366571520
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.673152458
Short name T626
Test name
Test status
Simulation time 66864626 ps
CPU time 1.26 seconds
Started Jun 29 05:29:55 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 208388 kb
Host smart-c3e97478-856e-4bc0-ac2c-bd8006977d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673152458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.673152458
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.4181202259
Short name T412
Test name
Test status
Simulation time 124002150 ps
CPU time 0.87 seconds
Started Jun 29 05:29:55 PM PDT 24
Finished Jun 29 05:29:56 PM PDT 24
Peak memory 207472 kb
Host smart-2f10bcf8-2354-4638-be1b-739f067fd765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181202259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.4181202259
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3712961440
Short name T769
Test name
Test status
Simulation time 50354472321 ps
CPU time 13.22 seconds
Started Jun 29 05:29:56 PM PDT 24
Finished Jun 29 05:30:10 PM PDT 24
Peak memory 233256 kb
Host smart-ab60d88c-850a-4715-ba6a-6c0f5721c57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712961440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3712961440
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.841563956
Short name T1003
Test name
Test status
Simulation time 41797101 ps
CPU time 0.72 seconds
Started Jun 29 05:27:17 PM PDT 24
Finished Jun 29 05:27:20 PM PDT 24
Peak memory 205400 kb
Host smart-86867f99-8759-45ab-8796-970721506dce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841563956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.841563956
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2951522175
Short name T585
Test name
Test status
Simulation time 907252174 ps
CPU time 2.9 seconds
Started Jun 29 05:27:19 PM PDT 24
Finished Jun 29 05:27:23 PM PDT 24
Peak memory 224980 kb
Host smart-7c6c95b8-2788-4919-b981-f604a883a1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951522175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2951522175
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3076312975
Short name T496
Test name
Test status
Simulation time 21711930 ps
CPU time 0.82 seconds
Started Jun 29 05:27:22 PM PDT 24
Finished Jun 29 05:27:23 PM PDT 24
Peak memory 207108 kb
Host smart-05de4a33-78fc-4b2a-b89c-fa189d194eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076312975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3076312975
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4134871941
Short name T612
Test name
Test status
Simulation time 49510099709 ps
CPU time 109.23 seconds
Started Jun 29 05:27:32 PM PDT 24
Finished Jun 29 05:29:23 PM PDT 24
Peak memory 249812 kb
Host smart-9b67f4e1-71ce-4b7a-911c-4966da67abf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134871941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4134871941
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3426120385
Short name T490
Test name
Test status
Simulation time 2246680893 ps
CPU time 26.05 seconds
Started Jun 29 05:27:32 PM PDT 24
Finished Jun 29 05:27:59 PM PDT 24
Peak memory 238860 kb
Host smart-271b4cff-4bbb-4750-aac2-9eff927976ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426120385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3426120385
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1576162518
Short name T451
Test name
Test status
Simulation time 8896002951 ps
CPU time 77.95 seconds
Started Jun 29 05:27:21 PM PDT 24
Finished Jun 29 05:28:40 PM PDT 24
Peak memory 249676 kb
Host smart-c39230d5-38bb-4922-93b6-7829b32b1e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576162518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1576162518
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2585066404
Short name T807
Test name
Test status
Simulation time 155799793 ps
CPU time 3.52 seconds
Started Jun 29 05:27:25 PM PDT 24
Finished Jun 29 05:27:29 PM PDT 24
Peak memory 233096 kb
Host smart-2e77f52f-462b-4e7d-a704-0c8c3a790e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585066404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2585066404
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1404788611
Short name T586
Test name
Test status
Simulation time 2546332730 ps
CPU time 24.69 seconds
Started Jun 29 05:27:19 PM PDT 24
Finished Jun 29 05:27:45 PM PDT 24
Peak memory 240080 kb
Host smart-16583ec2-6984-44db-96fa-848ce331f6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404788611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1404788611
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.446821543
Short name T499
Test name
Test status
Simulation time 1902764729 ps
CPU time 5.97 seconds
Started Jun 29 05:27:22 PM PDT 24
Finished Jun 29 05:27:29 PM PDT 24
Peak memory 224964 kb
Host smart-61df9728-2647-449a-b7b8-c8ccfbd541b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446821543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
446821543
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4198579728
Short name T225
Test name
Test status
Simulation time 822912747 ps
CPU time 7.31 seconds
Started Jun 29 05:27:19 PM PDT 24
Finished Jun 29 05:27:28 PM PDT 24
Peak memory 240820 kb
Host smart-2025e8f2-b42d-4128-99a5-a418374c986b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198579728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4198579728
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2168369930
Short name T921
Test name
Test status
Simulation time 2257530321 ps
CPU time 22.85 seconds
Started Jun 29 05:27:18 PM PDT 24
Finished Jun 29 05:27:43 PM PDT 24
Peak memory 222752 kb
Host smart-826e307e-a875-430c-a3a9-351677cf256f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2168369930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2168369930
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1026278811
Short name T286
Test name
Test status
Simulation time 208589293844 ps
CPU time 504.35 seconds
Started Jun 29 05:27:17 PM PDT 24
Finished Jun 29 05:35:43 PM PDT 24
Peak memory 253248 kb
Host smart-e8b479f4-6ac4-49a9-a02b-a0d54e9723e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026278811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1026278811
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.610214988
Short name T172
Test name
Test status
Simulation time 3014502702 ps
CPU time 16.69 seconds
Started Jun 29 05:27:24 PM PDT 24
Finished Jun 29 05:27:41 PM PDT 24
Peak memory 216944 kb
Host smart-e58c7edc-2670-491d-a884-42d09f4eb6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610214988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.610214988
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1184574881
Short name T608
Test name
Test status
Simulation time 27116520 ps
CPU time 0.76 seconds
Started Jun 29 05:27:17 PM PDT 24
Finished Jun 29 05:27:19 PM PDT 24
Peak memory 206192 kb
Host smart-393ad3a2-2fd9-4902-82d3-7c95875ed794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184574881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1184574881
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1388907339
Short name T417
Test name
Test status
Simulation time 19869147 ps
CPU time 0.72 seconds
Started Jun 29 05:27:24 PM PDT 24
Finished Jun 29 05:27:25 PM PDT 24
Peak memory 206140 kb
Host smart-f3d4e78a-6ef3-42e1-bef5-bc39b204a4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388907339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1388907339
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2630171881
Short name T707
Test name
Test status
Simulation time 96189200 ps
CPU time 0.81 seconds
Started Jun 29 05:27:18 PM PDT 24
Finished Jun 29 05:27:20 PM PDT 24
Peak memory 206448 kb
Host smart-4bbf253d-c8e5-4e14-a67b-81185ee44c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630171881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2630171881
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2897341130
Short name T820
Test name
Test status
Simulation time 752371838 ps
CPU time 5.26 seconds
Started Jun 29 05:27:21 PM PDT 24
Finished Jun 29 05:27:27 PM PDT 24
Peak memory 233176 kb
Host smart-de15ec13-9b67-4cf7-8fea-9529294c3703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897341130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2897341130
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2978851863
Short name T357
Test name
Test status
Simulation time 37731052 ps
CPU time 0.72 seconds
Started Jun 29 05:27:16 PM PDT 24
Finished Jun 29 05:27:18 PM PDT 24
Peak memory 205400 kb
Host smart-b7cd83dc-6ea4-46ab-995e-b3fa0357a6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978851863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
978851863
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.232920118
Short name T399
Test name
Test status
Simulation time 2929499790 ps
CPU time 6.05 seconds
Started Jun 29 05:27:21 PM PDT 24
Finished Jun 29 05:27:28 PM PDT 24
Peak memory 233308 kb
Host smart-9de3d433-b52c-40e8-ac0f-3dc103717b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232920118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.232920118
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3958891258
Short name T617
Test name
Test status
Simulation time 273927587 ps
CPU time 0.81 seconds
Started Jun 29 05:27:18 PM PDT 24
Finished Jun 29 05:27:21 PM PDT 24
Peak memory 207424 kb
Host smart-58e4f91e-4c73-40ae-8e6c-4dba13eda51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958891258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3958891258
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3166411828
Short name T559
Test name
Test status
Simulation time 305903460 ps
CPU time 7.79 seconds
Started Jun 29 05:27:18 PM PDT 24
Finished Jun 29 05:27:27 PM PDT 24
Peak memory 224996 kb
Host smart-c784c6a6-18fe-472f-90c2-2f56345ef4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166411828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3166411828
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2492451758
Short name T245
Test name
Test status
Simulation time 899254054 ps
CPU time 20.24 seconds
Started Jun 29 05:27:30 PM PDT 24
Finished Jun 29 05:27:51 PM PDT 24
Peak memory 241448 kb
Host smart-476b301f-9dbf-4f3c-bb48-38560f746404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492451758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2492451758
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3259030267
Short name T974
Test name
Test status
Simulation time 26907744285 ps
CPU time 128.48 seconds
Started Jun 29 05:27:19 PM PDT 24
Finished Jun 29 05:29:29 PM PDT 24
Peak memory 254348 kb
Host smart-7abfd2a5-f828-4480-a4a4-6b842bdef4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259030267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3259030267
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.299144377
Short name T576
Test name
Test status
Simulation time 213758413 ps
CPU time 6.21 seconds
Started Jun 29 05:27:17 PM PDT 24
Finished Jun 29 05:27:25 PM PDT 24
Peak memory 225028 kb
Host smart-8799c32e-2739-4057-8de1-f9b87659db6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299144377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.299144377
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.947631825
Short name T787
Test name
Test status
Simulation time 12095956157 ps
CPU time 40.76 seconds
Started Jun 29 05:27:21 PM PDT 24
Finished Jun 29 05:28:02 PM PDT 24
Peak memory 237436 kb
Host smart-5d7ee4b6-b397-4456-9e5d-809bafbaacc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947631825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
947631825
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3860539733
Short name T481
Test name
Test status
Simulation time 967134700 ps
CPU time 6.34 seconds
Started Jun 29 05:27:23 PM PDT 24
Finished Jun 29 05:27:30 PM PDT 24
Peak memory 233212 kb
Host smart-829558a3-6e84-42ca-8395-4e49c34f31b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860539733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3860539733
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2156389983
Short name T558
Test name
Test status
Simulation time 75421316 ps
CPU time 2.63 seconds
Started Jun 29 05:27:19 PM PDT 24
Finished Jun 29 05:27:23 PM PDT 24
Peak memory 233164 kb
Host smart-fa975d38-fd69-4a6b-8f4a-7c649d845ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156389983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2156389983
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3812175739
Short name T960
Test name
Test status
Simulation time 182401049 ps
CPU time 3.98 seconds
Started Jun 29 05:27:28 PM PDT 24
Finished Jun 29 05:27:33 PM PDT 24
Peak memory 233136 kb
Host smart-d6ef836f-df08-486c-b313-2634cd37ac13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812175739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3812175739
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2015746693
Short name T426
Test name
Test status
Simulation time 1137024983 ps
CPU time 7.77 seconds
Started Jun 29 05:27:19 PM PDT 24
Finished Jun 29 05:27:28 PM PDT 24
Peak memory 241352 kb
Host smart-b8bb7434-5511-4e18-911e-642de9c20fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015746693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2015746693
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3410115542
Short name T159
Test name
Test status
Simulation time 5460597461 ps
CPU time 10.31 seconds
Started Jun 29 05:27:21 PM PDT 24
Finished Jun 29 05:27:32 PM PDT 24
Peak memory 221120 kb
Host smart-7d869eee-120a-4e54-9371-bb77a4fdef40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3410115542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3410115542
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.86145309
Short name T594
Test name
Test status
Simulation time 5271274254 ps
CPU time 22.83 seconds
Started Jun 29 05:27:15 PM PDT 24
Finished Jun 29 05:27:39 PM PDT 24
Peak memory 220956 kb
Host smart-bed49634-7dbd-4851-bede-e893a945171d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86145309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.86145309
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3630322561
Short name T609
Test name
Test status
Simulation time 3421054906 ps
CPU time 6.21 seconds
Started Jun 29 05:27:23 PM PDT 24
Finished Jun 29 05:27:30 PM PDT 24
Peak memory 216952 kb
Host smart-392af808-e443-4761-9b60-b516dc5616b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630322561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3630322561
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.116348243
Short name T376
Test name
Test status
Simulation time 19961375 ps
CPU time 0.97 seconds
Started Jun 29 05:27:16 PM PDT 24
Finished Jun 29 05:27:18 PM PDT 24
Peak memory 207524 kb
Host smart-b84a23ca-dad3-449a-b53c-af42766b1790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116348243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.116348243
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.736853737
Short name T421
Test name
Test status
Simulation time 26990006 ps
CPU time 0.68 seconds
Started Jun 29 05:27:22 PM PDT 24
Finished Jun 29 05:27:24 PM PDT 24
Peak memory 206116 kb
Host smart-fdba1ab7-e24f-4af7-912d-f78355843991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736853737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.736853737
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.749665394
Short name T424
Test name
Test status
Simulation time 2012874926 ps
CPU time 2.72 seconds
Started Jun 29 05:27:21 PM PDT 24
Finished Jun 29 05:27:25 PM PDT 24
Peak memory 224936 kb
Host smart-f91e7dcc-7bbe-4028-b2f7-65e54835af14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749665394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.749665394
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.903566813
Short name T393
Test name
Test status
Simulation time 68758446 ps
CPU time 0.77 seconds
Started Jun 29 05:27:26 PM PDT 24
Finished Jun 29 05:27:27 PM PDT 24
Peak memory 205940 kb
Host smart-122bafe6-6626-4eda-b976-8932f32971f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903566813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.903566813
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3287975805
Short name T882
Test name
Test status
Simulation time 37830419 ps
CPU time 2.47 seconds
Started Jun 29 05:27:25 PM PDT 24
Finished Jun 29 05:27:28 PM PDT 24
Peak memory 232940 kb
Host smart-504c847e-c31a-484c-92af-5aa0d97ead3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287975805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3287975805
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4024232775
Short name T463
Test name
Test status
Simulation time 44533194 ps
CPU time 0.81 seconds
Started Jun 29 05:27:21 PM PDT 24
Finished Jun 29 05:27:22 PM PDT 24
Peak memory 207084 kb
Host smart-f9ab6451-16a5-4e31-976e-9249d34179fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024232775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4024232775
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2389738329
Short name T620
Test name
Test status
Simulation time 36262923431 ps
CPU time 79.33 seconds
Started Jun 29 05:27:30 PM PDT 24
Finished Jun 29 05:28:50 PM PDT 24
Peak memory 238052 kb
Host smart-daac19a6-0c60-4ab0-b632-a3acf679e616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389738329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2389738329
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1487972830
Short name T87
Test name
Test status
Simulation time 8630003665 ps
CPU time 43.09 seconds
Started Jun 29 05:27:27 PM PDT 24
Finished Jun 29 05:28:11 PM PDT 24
Peak memory 250056 kb
Host smart-adae8f6f-01ec-4989-9025-fabacd6521ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487972830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1487972830
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2655688589
Short name T209
Test name
Test status
Simulation time 154323126513 ps
CPU time 382.64 seconds
Started Jun 29 05:27:29 PM PDT 24
Finished Jun 29 05:33:52 PM PDT 24
Peak memory 266208 kb
Host smart-465547dc-2177-45c8-a2b1-bc91436ddc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655688589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2655688589
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.475548089
Short name T310
Test name
Test status
Simulation time 481427055 ps
CPU time 11.97 seconds
Started Jun 29 05:27:26 PM PDT 24
Finished Jun 29 05:27:39 PM PDT 24
Peak memory 234732 kb
Host smart-a6ba59c8-a780-4bf6-a953-0b47b0ad5d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475548089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.475548089
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3686230413
Short name T185
Test name
Test status
Simulation time 21664039257 ps
CPU time 48.12 seconds
Started Jun 29 05:27:26 PM PDT 24
Finished Jun 29 05:28:15 PM PDT 24
Peak memory 239768 kb
Host smart-353819db-c527-46f7-8cfc-b358f28363b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686230413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3686230413
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2916255166
Short name T762
Test name
Test status
Simulation time 113576182 ps
CPU time 2.42 seconds
Started Jun 29 05:27:31 PM PDT 24
Finished Jun 29 05:27:35 PM PDT 24
Peak memory 233016 kb
Host smart-673e04ef-2f04-4d88-9699-090d18b34074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916255166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2916255166
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.4287995451
Short name T453
Test name
Test status
Simulation time 517875806 ps
CPU time 4.59 seconds
Started Jun 29 05:27:32 PM PDT 24
Finished Jun 29 05:27:38 PM PDT 24
Peak memory 225028 kb
Host smart-4f4270b0-a5d7-4418-8874-67b28253602e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287995451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.4287995451
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1285422458
Short name T246
Test name
Test status
Simulation time 3748955603 ps
CPU time 12.35 seconds
Started Jun 29 05:27:25 PM PDT 24
Finished Jun 29 05:27:38 PM PDT 24
Peak memory 225092 kb
Host smart-9c9f8497-b36a-445c-9e7c-66dc260dd626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285422458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1285422458
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3976269988
Short name T98
Test name
Test status
Simulation time 443427095 ps
CPU time 6.75 seconds
Started Jun 29 05:27:31 PM PDT 24
Finished Jun 29 05:27:39 PM PDT 24
Peak memory 241200 kb
Host smart-02d0e2b4-883b-4961-a76a-ffdf01893c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976269988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3976269988
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.242741184
Short name T678
Test name
Test status
Simulation time 173067571 ps
CPU time 4.75 seconds
Started Jun 29 05:27:33 PM PDT 24
Finished Jun 29 05:27:38 PM PDT 24
Peak memory 219452 kb
Host smart-4f6b6db9-f061-4601-af77-245a2f4322da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=242741184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.242741184
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1237428949
Short name T860
Test name
Test status
Simulation time 4853962380 ps
CPU time 19.46 seconds
Started Jun 29 05:27:25 PM PDT 24
Finished Jun 29 05:27:45 PM PDT 24
Peak memory 225288 kb
Host smart-8b20694b-8eaf-4ab1-a26e-214dd98f01ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237428949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1237428949
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2314894440
Short name T333
Test name
Test status
Simulation time 5276370971 ps
CPU time 27.9 seconds
Started Jun 29 05:27:26 PM PDT 24
Finished Jun 29 05:27:54 PM PDT 24
Peak memory 217228 kb
Host smart-63d7cb44-2d97-4c5b-a83d-2faca711ccd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314894440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2314894440
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3767425892
Short name T364
Test name
Test status
Simulation time 34715829469 ps
CPU time 17.4 seconds
Started Jun 29 05:27:19 PM PDT 24
Finished Jun 29 05:27:38 PM PDT 24
Peak memory 218072 kb
Host smart-011eadb8-a15c-49a4-9f6e-a3f62f85170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767425892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3767425892
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2450953696
Short name T618
Test name
Test status
Simulation time 37672034 ps
CPU time 1.56 seconds
Started Jun 29 05:27:24 PM PDT 24
Finished Jun 29 05:27:26 PM PDT 24
Peak memory 216760 kb
Host smart-240ce01d-7ee7-49ee-9711-5f6b35ad2d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450953696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2450953696
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2940566252
Short name T547
Test name
Test status
Simulation time 97930963 ps
CPU time 0.92 seconds
Started Jun 29 05:27:26 PM PDT 24
Finished Jun 29 05:27:28 PM PDT 24
Peak memory 206420 kb
Host smart-77861b23-f75d-461f-a554-24bf6e4fbbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940566252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2940566252
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1626154732
Short name T604
Test name
Test status
Simulation time 8081752150 ps
CPU time 28.12 seconds
Started Jun 29 05:27:30 PM PDT 24
Finished Jun 29 05:27:59 PM PDT 24
Peak memory 233240 kb
Host smart-24c7012a-2b6f-490b-a543-1b433eb681b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626154732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1626154732
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2130437170
Short name T944
Test name
Test status
Simulation time 12491176 ps
CPU time 0.72 seconds
Started Jun 29 05:27:51 PM PDT 24
Finished Jun 29 05:27:55 PM PDT 24
Peak memory 205400 kb
Host smart-99651ca4-5e75-4ebd-80d5-31b0a7e90abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130437170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
130437170
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.4093213529
Short name T686
Test name
Test status
Simulation time 67587476 ps
CPU time 2.36 seconds
Started Jun 29 05:27:29 PM PDT 24
Finished Jun 29 05:27:32 PM PDT 24
Peak memory 233108 kb
Host smart-a4cd2a43-ba65-461d-9eb0-0d33f5fd6ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093213529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4093213529
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1530355087
Short name T435
Test name
Test status
Simulation time 18242925 ps
CPU time 0.8 seconds
Started Jun 29 05:27:25 PM PDT 24
Finished Jun 29 05:27:27 PM PDT 24
Peak memory 206056 kb
Host smart-5e0a32c6-0048-4a5a-8068-a5d35ee3749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530355087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1530355087
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3867350484
Short name T535
Test name
Test status
Simulation time 29938712788 ps
CPU time 117.07 seconds
Started Jun 29 05:27:31 PM PDT 24
Finished Jun 29 05:29:29 PM PDT 24
Peak memory 249740 kb
Host smart-d9592f98-ae05-4670-9884-f83bc194097f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867350484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3867350484
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2323923281
Short name T699
Test name
Test status
Simulation time 10437551412 ps
CPU time 59.33 seconds
Started Jun 29 05:27:25 PM PDT 24
Finished Jun 29 05:28:25 PM PDT 24
Peak memory 271092 kb
Host smart-8c522051-de59-4286-af33-7b72b66ac456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323923281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2323923281
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3756839734
Short name T54
Test name
Test status
Simulation time 5916658903 ps
CPU time 31 seconds
Started Jun 29 05:27:29 PM PDT 24
Finished Jun 29 05:28:01 PM PDT 24
Peak memory 250896 kb
Host smart-8a289b05-3ea3-4de2-856c-2a49f1a91939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756839734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3756839734
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3894700422
Short name T41
Test name
Test status
Simulation time 1069014638 ps
CPU time 17.6 seconds
Started Jun 29 05:27:30 PM PDT 24
Finished Jun 29 05:27:49 PM PDT 24
Peak memory 241612 kb
Host smart-015eb247-5b5e-4385-9ab9-479946710b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894700422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3894700422
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1210979713
Short name T798
Test name
Test status
Simulation time 5376751368 ps
CPU time 35.43 seconds
Started Jun 29 05:27:26 PM PDT 24
Finished Jun 29 05:28:02 PM PDT 24
Peak memory 249736 kb
Host smart-47ac5bf2-4972-4890-bd4e-fb41cfbdf7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210979713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1210979713
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.138671464
Short name T679
Test name
Test status
Simulation time 330739739 ps
CPU time 6.92 seconds
Started Jun 29 05:27:35 PM PDT 24
Finished Jun 29 05:27:42 PM PDT 24
Peak memory 225012 kb
Host smart-d300f6d4-0707-45b4-a339-dcda765971f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138671464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.138671464
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3243183001
Short name T44
Test name
Test status
Simulation time 42961397019 ps
CPU time 87.71 seconds
Started Jun 29 05:27:30 PM PDT 24
Finished Jun 29 05:28:58 PM PDT 24
Peak memory 233248 kb
Host smart-306c7cc1-7478-4024-8c2b-6989ca58b2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243183001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3243183001
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.328292111
Short name T646
Test name
Test status
Simulation time 1147081874 ps
CPU time 5.34 seconds
Started Jun 29 05:27:26 PM PDT 24
Finished Jun 29 05:27:33 PM PDT 24
Peak memory 233104 kb
Host smart-7b3a748c-99d1-4e93-9715-f68beee31f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328292111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
328292111
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4109276508
Short name T706
Test name
Test status
Simulation time 15510698706 ps
CPU time 20.59 seconds
Started Jun 29 05:27:29 PM PDT 24
Finished Jun 29 05:27:50 PM PDT 24
Peak memory 240476 kb
Host smart-55a62c8d-1237-4934-8b70-67b197b27543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109276508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4109276508
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3856781525
Short name T523
Test name
Test status
Simulation time 843367769 ps
CPU time 12.16 seconds
Started Jun 29 05:27:31 PM PDT 24
Finished Jun 29 05:27:45 PM PDT 24
Peak memory 219752 kb
Host smart-72f8658a-70bf-40a6-a088-fc598e003942
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3856781525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3856781525
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1690406881
Short name T30
Test name
Test status
Simulation time 49317593207 ps
CPU time 139.02 seconds
Started Jun 29 05:27:29 PM PDT 24
Finished Jun 29 05:29:49 PM PDT 24
Peak memory 249868 kb
Host smart-679c3233-67be-4e1b-bada-317e1e596924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690406881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1690406881
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.832986631
Short name T328
Test name
Test status
Simulation time 2348263090 ps
CPU time 13.94 seconds
Started Jun 29 05:27:31 PM PDT 24
Finished Jun 29 05:27:46 PM PDT 24
Peak memory 216868 kb
Host smart-ccb17f1a-ad3a-4ef6-94e3-32d7336ed6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832986631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.832986631
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1024274319
Short name T659
Test name
Test status
Simulation time 5009756219 ps
CPU time 8.26 seconds
Started Jun 29 05:27:33 PM PDT 24
Finished Jun 29 05:27:42 PM PDT 24
Peak memory 216896 kb
Host smart-a8595917-4778-4e50-b931-95a056b065b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024274319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1024274319
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3505095768
Short name T1016
Test name
Test status
Simulation time 115276016 ps
CPU time 1.1 seconds
Started Jun 29 05:27:28 PM PDT 24
Finished Jun 29 05:27:30 PM PDT 24
Peak memory 208396 kb
Host smart-bddba1e6-86f9-462e-8e0d-2b4b73ef36cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505095768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3505095768
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.833057738
Short name T486
Test name
Test status
Simulation time 94338744 ps
CPU time 0.95 seconds
Started Jun 29 05:27:36 PM PDT 24
Finished Jun 29 05:27:37 PM PDT 24
Peak memory 207432 kb
Host smart-24c00953-437c-496e-8b62-1a70125cd4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833057738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.833057738
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4216562673
Short name T913
Test name
Test status
Simulation time 235821809 ps
CPU time 2.32 seconds
Started Jun 29 05:27:27 PM PDT 24
Finished Jun 29 05:27:30 PM PDT 24
Peak memory 224924 kb
Host smart-7ddd5209-7f43-4c25-a08c-ac1a745fcd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216562673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4216562673
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.325028322
Short name T817
Test name
Test status
Simulation time 20587525 ps
CPU time 0.78 seconds
Started Jun 29 05:27:49 PM PDT 24
Finished Jun 29 05:27:53 PM PDT 24
Peak memory 205396 kb
Host smart-beaddfd3-2d9c-4442-b9a6-700cb073abd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325028322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.325028322
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.725730138
Short name T710
Test name
Test status
Simulation time 1139765137 ps
CPU time 5.63 seconds
Started Jun 29 05:27:42 PM PDT 24
Finished Jun 29 05:27:48 PM PDT 24
Peak memory 233112 kb
Host smart-4ad47052-a3c1-44c2-98da-2b382c6ab14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725730138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.725730138
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1633017637
Short name T438
Test name
Test status
Simulation time 48678372 ps
CPU time 0.77 seconds
Started Jun 29 05:27:29 PM PDT 24
Finished Jun 29 05:27:31 PM PDT 24
Peak memory 206064 kb
Host smart-04fee47a-9e4d-4cc5-8675-340966e0b2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633017637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1633017637
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2359489240
Short name T248
Test name
Test status
Simulation time 10156447477 ps
CPU time 50.02 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:28:40 PM PDT 24
Peak memory 257188 kb
Host smart-3b00ae1f-e090-4390-b132-997ce0342763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359489240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2359489240
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3865073893
Short name T325
Test name
Test status
Simulation time 4635442320 ps
CPU time 7.94 seconds
Started Jun 29 05:27:40 PM PDT 24
Finished Jun 29 05:27:48 PM PDT 24
Peak memory 218204 kb
Host smart-75f25c8d-bb8c-41db-ab87-afbd0a189142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865073893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3865073893
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2816760772
Short name T262
Test name
Test status
Simulation time 2493795522 ps
CPU time 42.73 seconds
Started Jun 29 05:27:47 PM PDT 24
Finished Jun 29 05:28:32 PM PDT 24
Peak memory 234492 kb
Host smart-6443bf7f-c65e-4904-b9a9-7b52ff978403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816760772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2816760772
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3883618528
Short name T308
Test name
Test status
Simulation time 2737462293 ps
CPU time 31.46 seconds
Started Jun 29 05:27:45 PM PDT 24
Finished Jun 29 05:28:18 PM PDT 24
Peak memory 225144 kb
Host smart-61b8241b-da9f-414c-ac26-5981a0746b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883618528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3883618528
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2162621945
Short name T583
Test name
Test status
Simulation time 12093803928 ps
CPU time 44.51 seconds
Started Jun 29 05:27:40 PM PDT 24
Finished Jun 29 05:28:25 PM PDT 24
Peak memory 249712 kb
Host smart-f3ed1256-0572-4e1e-b385-31c63367bad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162621945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2162621945
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2196250671
Short name T210
Test name
Test status
Simulation time 4006464954 ps
CPU time 26.68 seconds
Started Jun 29 05:27:31 PM PDT 24
Finished Jun 29 05:27:59 PM PDT 24
Peak memory 225092 kb
Host smart-adbc3ce5-80c4-4538-937e-baa74b117961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196250671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2196250671
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1786571645
Short name T776
Test name
Test status
Simulation time 1159762819 ps
CPU time 4.94 seconds
Started Jun 29 05:27:48 PM PDT 24
Finished Jun 29 05:27:55 PM PDT 24
Peak memory 233176 kb
Host smart-c40f4dce-d2a7-4b54-b57a-912dc2cc4c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786571645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1786571645
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2365558588
Short name T918
Test name
Test status
Simulation time 368006877 ps
CPU time 5.62 seconds
Started Jun 29 05:27:25 PM PDT 24
Finished Jun 29 05:27:32 PM PDT 24
Peak memory 233204 kb
Host smart-67b33cf6-65ab-427d-8d2f-93c39db77667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365558588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2365558588
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2518887846
Short name T404
Test name
Test status
Simulation time 941819394 ps
CPU time 3.7 seconds
Started Jun 29 05:27:31 PM PDT 24
Finished Jun 29 05:27:35 PM PDT 24
Peak memory 224952 kb
Host smart-5de1c01a-d44f-44d7-989f-dae1e081a343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518887846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2518887846
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2652476902
Short name T957
Test name
Test status
Simulation time 5739282562 ps
CPU time 10.01 seconds
Started Jun 29 05:27:30 PM PDT 24
Finished Jun 29 05:27:41 PM PDT 24
Peak memory 222328 kb
Host smart-2794d7a0-5e5e-4aca-afe5-50135daa4d89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2652476902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2652476902
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3368736261
Short name T861
Test name
Test status
Simulation time 49318956449 ps
CPU time 430.19 seconds
Started Jun 29 05:27:44 PM PDT 24
Finished Jun 29 05:34:55 PM PDT 24
Peak memory 267236 kb
Host smart-d6067938-f795-44f2-b79c-d90c5070b4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368736261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3368736261
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1253271906
Short name T729
Test name
Test status
Simulation time 5564671085 ps
CPU time 18.04 seconds
Started Jun 29 05:27:25 PM PDT 24
Finished Jun 29 05:27:43 PM PDT 24
Peak memory 216952 kb
Host smart-a9e0b052-11eb-49d7-a7e8-040bd8f76c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253271906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1253271906
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1743873756
Short name T624
Test name
Test status
Simulation time 28900602999 ps
CPU time 18.96 seconds
Started Jun 29 05:27:25 PM PDT 24
Finished Jun 29 05:27:44 PM PDT 24
Peak memory 216916 kb
Host smart-11039a6b-051d-4275-b20a-bb0ec4e03593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743873756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1743873756
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3874145417
Short name T584
Test name
Test status
Simulation time 119357434 ps
CPU time 1.6 seconds
Started Jun 29 05:27:31 PM PDT 24
Finished Jun 29 05:27:34 PM PDT 24
Peak memory 216820 kb
Host smart-986ecef1-eb60-498d-9a9a-ac7772e85fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874145417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3874145417
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3769377792
Short name T479
Test name
Test status
Simulation time 175405876 ps
CPU time 0.81 seconds
Started Jun 29 05:27:29 PM PDT 24
Finished Jun 29 05:27:30 PM PDT 24
Peak memory 206460 kb
Host smart-25d31a8a-cb9b-4fe8-8e32-397817879e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769377792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3769377792
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.139694069
Short name T208
Test name
Test status
Simulation time 893600564 ps
CPU time 8.26 seconds
Started Jun 29 05:27:46 PM PDT 24
Finished Jun 29 05:27:55 PM PDT 24
Peak memory 238252 kb
Host smart-b0d8cce7-b30e-450d-b396-8ef40a25c720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139694069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.139694069
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%