Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2632010	1			T1	1		T4	21509		T5	1
all_values[1]	2632010	1			T1	1		T4	21509		T5	1
all_values[2]	2632010	1			T1	1		T4	21509		T5	1
all_values[3]	2632010	1			T1	1		T4	21509		T5	1
all_values[4]	2632010	1			T1	1		T4	21509		T5	1
all_values[5]	2632010	1			T1	1		T4	21509		T5	1
all_values[6]	2632010	1			T1	1		T4	21509		T5	1
all_values[7]	2632010	1			T1	1		T4	21509		T5	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20740737

1

T1

8

T4

172072

T5

8

auto[1]

315343

1

T14

16663

T17

2462

T19

55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21029942

1

T1

8

T4

171898

T5

8

auto[1]

26138

1

T4

174

T14

196

T52

26

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2601338	1			T1	1		T4	21402		T5	1
all_values[0]	auto[0]	auto[1]	12358	1			T4	107		T14	1		T52	13
all_values[0]	auto[1]	auto[0]	17822	1			T14	3232		T17	2		T19	4
all_values[0]	auto[1]	auto[1]	492	1			T14	98		T17	1		T19	3
all_values[1]	auto[0]	auto[0]	2591943	1			T1	1		T4	21457		T5	1
all_values[1]	auto[0]	auto[1]	7858	1			T4	52		T14	1		T52	13
all_values[1]	auto[1]	auto[0]	31798	1			T14	3273		T17	2		T19	7
all_values[1]	auto[1]	auto[1]	411	1			T14	59		T17	1		T19	3
all_values[2]	auto[0]	auto[0]	2591455	1			T1	1		T4	21494		T5	1
all_values[2]	auto[0]	auto[1]	2865	1			T4	15		T14	24		T49	4
all_values[2]	auto[1]	auto[0]	37409	1			T14	1		T17	811		T19	1
all_values[2]	auto[1]	auto[1]	281	1			T14	1		T17	2		T19	3
all_values[3]	auto[0]	auto[0]	2540694	1			T1	1		T4	21509		T5	1
all_values[3]	auto[0]	auto[1]	176	1			T17	2		T19	3		T22	3
all_values[3]	auto[1]	auto[0]	90940	1			T14	3331		T17	2		T19	3
all_values[3]	auto[1]	auto[1]	200	1			T14	2		T17	3		T19	1
all_values[4]	auto[0]	auto[0]	2554273	1			T1	1		T4	21509		T5	1
all_values[4]	auto[0]	auto[1]	171	1			T14	4		T17	2		T19	2
all_values[4]	auto[1]	auto[0]	77369	1			T17	1		T19	8		T22	2
all_values[4]	auto[1]	auto[1]	197	1			T14	2		T17	4		T19	4
all_values[5]	auto[0]	auto[0]	2614990	1			T1	1		T4	21509		T5	1
all_values[5]	auto[0]	auto[1]	170	1			T14	1		T17	2		T19	4
all_values[5]	auto[1]	auto[0]	16663	1			T14	3330		T17	812		T19	5
all_values[5]	auto[1]	auto[1]	187	1			T14	1		T17	3		T19	1
all_values[6]	auto[0]	auto[0]	2613412	1			T1	1		T4	21509		T5	1
all_values[6]	auto[0]	auto[1]	184	1			T19	6		T22	2		T34	1
all_values[6]	auto[1]	auto[0]	18214	1			T14	1		T17	816		T19	4
all_values[6]	auto[1]	auto[1]	200	1			T14	1		T19	2		T22	4
all_values[7]	auto[0]	auto[0]	2608674	1			T1	1		T4	21509		T5	1
all_values[7]	auto[0]	auto[1]	176	1			T14	1		T17	2		T19	5
all_values[7]	auto[1]	auto[0]	22948	1			T14	3331		T17	1		T19	2
all_values[7]	auto[1]	auto[1]	212	1			T17	1		T19	4		T21	3