Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34951	1			T1	2		T4	110		T5	6
auto[SpiFlashAddrCfg]	7661	1			T4	49		T5	2		T6	8
auto[SpiFlashAddr3b]	9326	1			T4	40		T5	4		T6	2
auto[SpiFlashAddr4b]	7861	1			T4	47		T5	6		T6	11

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34213

1

T1

2

T4

135

T6

18

auto[1]

25586

1

T4

111

T5

18

T6

56

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32296

1

T1

2

T4

111

T5

8

auto[1]

27503

1

T4

135

T5

10

T6

57

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39760	1			T1	2		T4	130		T5	4
values[1]	1173	1			T4	7		T9	8		T14	14
values[2]	1513	1			T4	3		T6	4		T9	10
values[3]	1523	1			T4	7		T5	4		T6	5
values[4]	1482	1			T4	9		T7	8		T9	17
values[5]	1475	1			T4	8		T6	1		T9	7
values[6]	1455	1			T4	12		T9	12		T14	8
values[7]	1459	1			T4	8		T5	2		T6	1
values[8]	9959	1			T4	62		T5	8		T6	10

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31818

1

T1

2

T4

246

T5

18

auto[1]

27981

1

T6

74

T15

183

T40

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56480

1

T1

2

T4

230

T5

18

write

3319

1

T4

16

T6

3

T9

14

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19668

1

T1

2

T4

104

T5

8

valids[0x1]

40131

1

T4

142

T5

10

T6

53

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1604	1			T4	8		T9	9		T14	8
internal_process_ops[0x5a]	1617	1			T4	6		T6	1		T7	8
internal_process_ops[0x05]	20802	1			T4	40		T5	4		T6	38
internal_process_ops[0x35]	1618	1			T4	6		T6	2		T9	4
internal_process_ops[0x15]	1540	1			T4	5		T6	1		T9	5
internal_process_ops[0x03]	1074	1			T4	7		T6	1		T9	8
internal_process_ops[0x0b]	1033	1			T4	7		T5	4		T9	8
internal_process_ops[0x3b]	1088	1			T4	8		T5	2		T9	7
internal_process_ops[0x6b]	1132	1			T4	9		T9	5		T14	6
internal_process_ops[0xbb]	1100	1			T4	7		T9	6		T14	8
internal_process_ops[0xeb]	1035	1			T4	6		T9	7		T14	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58158

1

T1

2

T4

236

T5

18

auto[1]

1641

1

T4

10

T6

2

T9

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57370

1

T1

2

T4

236

T5

18

auto[1]

2429

1

T4

10

T6

3

T9

15

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10865

1

T1

2

T4

67

T7

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6257

1

T4

36

T5

6

T9

32

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2105

1

T4

17

T9

22

T14

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1921

1

T4

30

T5

2

T9

17

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2666

1

T4

21

T7

8

T9

22

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2196

1

T4

16

T5

4

T9

25

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2205

1

T4

20

T9

39

T14

11

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1956

1

T4

23

T5

6

T9

18

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

124

1

T4

2

T14

1

T46

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

75

1

T4

4

T9

1

T14

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

74

1

T9

1

T39

3

T48

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

98

1

T4

1

T9

1

T25

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

130

1

T9

4

T25

1

T53

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

81

1

T14

1

T49

1

T17

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

94

1

T9

2

T14

2

T17

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

100

1

T4

2

T46

2

T45

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

120

1

T4

1

T25

1

T39

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

100

1

T14

2

T39

3

T45

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

93

1

T4

1

T9

2

T14

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

122

1

T4

1

T14

2

T46

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

129

1

T4

2

T9

1

T14

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

110

1

T4

1

T14

3

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

105

1

T9

2

T25

1

T46

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

92

1

T4

1

T14

2

T25

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10049

1

T6

10

T15

51

T43

119

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6949

1

T6

42

T15

96

T43

47

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1391

1

T6

1

T15

4

T43

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1452

1

T6

5

T15

3

T43

13

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1854

1

T15

6

T43

17

T84

34

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1759

1

T6

2

T15

8

T43

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1433

1

T6

4

T15

3

T40

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1422

1

T6

7

T15

4

T43

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

92

1

T6

1

T43

1

T84

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

113

1

T96

3

T83

3

T170

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

136

1

T15

5

T96

1

T171

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

119

1

T84

1

T172

1

T83

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

91

1

T84

5

T172

1

T171

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

67

1

T6

2

T43

1

T172

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

113

1

T84

1

T172

2

T171

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

116

1

T43

3

T84

1

T172

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

88

1

T43

3

T84

5

T172

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

143

1

T84

1

T96

2

T171

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

73

1

T15

1

T17

2

T173

6

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

112

1

T15

2

T43

2

T84

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

90

1

T172

1

T96

1

T83

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

92

1

T96

1

T83

2

T17

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

126

1

T43

6

T84

2

T83

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

101

1

T172

2

T170

1

T174

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4108	1			T1	2		T4	41		T9	50
auto[0]	values[0]	valids[0x1]	16033	1			T4	89		T5	4		T7	4
auto[0]	values[1]	valids[0x1]	634	1			T4	7		T9	8		T14	14
auto[0]	values[2]	valids[0x0]	591	1			T4	3		T9	3		T14	7
auto[0]	values[2]	valids[0x1]	275	1			T9	7		T46	2		T39	1
auto[0]	values[3]	valids[0x0]	563	1			T4	3		T9	7		T14	4
auto[0]	values[3]	valids[0x1]	313	1			T4	4		T5	4		T9	4
auto[0]	values[4]	valids[0x0]	512	1			T4	4		T9	8		T14	13
auto[0]	values[4]	valids[0x1]	337	1			T4	5		T7	8		T9	9
auto[0]	values[5]	valids[0x0]	603	1			T4	5		T9	4		T14	9
auto[0]	values[5]	valids[0x1]	278	1			T4	3		T9	3		T14	2
auto[0]	values[6]	valids[0x0]	539	1			T4	9		T9	8		T14	2
auto[0]	values[6]	valids[0x1]	305	1			T4	3		T9	4		T14	6
auto[0]	values[7]	valids[0x0]	566	1			T4	1		T9	9		T14	3
auto[0]	values[7]	valids[0x1]	318	1			T4	7		T5	2		T9	6
auto[0]	values[8]	valids[0x0]	3714	1			T4	38		T5	8		T9	33
auto[0]	values[8]	valids[0x1]	2129	1			T4	24		T9	13		T14	14
auto[1]	values[0]	valids[0x0]	3872	1			T6	8		T15	13		T43	42
auto[1]	values[0]	valids[0x1]	15747	1			T6	45		T15	137		T43	149
auto[1]	values[1]	valids[0x1]	539	1			T15	4		T43	10		T84	3
auto[1]	values[2]	valids[0x0]	358	1			T6	1		T15	1		T43	5
auto[1]	values[2]	valids[0x1]	289	1			T6	3		T15	1		T43	3
auto[1]	values[3]	valids[0x0]	404	1			T6	5		T15	1		T43	4
auto[1]	values[3]	valids[0x1]	243	1			T84	3		T96	2		T171	2
auto[1]	values[4]	valids[0x0]	380	1			T15	4		T43	3		T84	1
auto[1]	values[4]	valids[0x1]	253	1			T15	1		T43	3		T84	2
auto[1]	values[5]	valids[0x0]	332	1			T43	7		T84	4		T172	2
auto[1]	values[5]	valids[0x1]	262	1			T6	1		T15	3		T43	5
auto[1]	values[6]	valids[0x0]	384	1			T40	1		T43	1		T84	10
auto[1]	values[6]	valids[0x1]	227	1			T84	1		T172	2		T96	2
auto[1]	values[7]	valids[0x0]	317	1			T6	1		T15	2		T43	2
auto[1]	values[7]	valids[0x1]	258	1			T43	1		T84	6		T96	6
auto[1]	values[8]	valids[0x0]	2425	1			T6	6		T15	10		T43	14
auto[1]	values[8]	valids[0x1]	1691	1			T6	4		T15	6		T43	11