Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3588551

1

T1

22

T4

22640

T5

1

auto[1]

31060

1

T4

26

T6

34

T9

1081

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134735

1

T1

22

T4

62

T5

1

auto[1]

2484876

1

T4

22604

T6

4796

T7

2538

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	735743	1			T1	16		T4	1059		T5	1
auto[524288:1048575]	432892	1			T4	4310		T6	658		T7	1286
auto[1048576:1572863]	416376	1			T1	1		T4	23		T6	10
auto[1572864:2097151]	398693	1			T4	7475		T7	651		T9	485
auto[2097152:2621439]	396005	1			T1	5		T4	1760		T7	67
auto[2621440:3145727]	430013	1			T4	6170		T6	1319		T7	36
auto[3145728:3670015]	404058	1			T4	1		T6	11		T9	4437
auto[3670016:4194303]	405831	1			T4	1868		T6	2380		T7	3

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2521188

1

T1

7

T4

22666

T5

1

auto[1]

1098423

1

T1

15

T6

1

T7

1496

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3252958

1

T1

22

T4

14771

T5

1

auto[1]

366653

1

T4

7895

T6

11

T9

1017

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	262812	1			T1	16		T4	5		T5	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	415815	1			T4	537		T6	429		T7	1268
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	141367	1			T4	4		T6	3		T7	84
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	250399	1			T4	2514		T6	655		T7	1202
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	124522	1			T1	1		T4	3		T7	522
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	248417	1			T4	6		T14	1		T25	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	117792	1			T4	6		T7	583		T9	45
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	241447	1			T4	4017		T7	68		T9	20
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	105451	1			T1	5		T4	5		T7	67
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	239463	1			T4	1487		T9	1019		T14	5351
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	124865	1			T4	11		T6	2		T7	36
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	245123	1			T4	6156		T6	1300		T14	514
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	105295	1			T6	1		T9	52		T14	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	254377	1			T6	1		T9	4200		T14	641
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	139378	1			T4	1		T6	1		T7	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	211822	1			T4	1		T6	2379		T9	4172
auto[0]	auto[1]	auto[0:524287]	auto[0]	1405	1			T6	1		T9	7		T14	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	49269	1			T4	512		T9	3		T25	509
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1524	1			T4	4		T9	7		T14	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	36088	1			T4	1784		T14	2		T25	1674
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	565	1			T4	6		T6	1		T9	7
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	38484	1			T4	2		T6	1		T9	379
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	370	1			T4	3		T9	23		T25	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	36085	1			T4	3449		T84	5		T171	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	758	1			T4	3		T9	6		T25	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	46831	1			T4	257		T25	1		T46	1822
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	531	1			T9	4		T25	3		T46	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	55767	1			T25	1		T45	9		T84	793
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1524	1			T4	1		T9	27		T14	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	40072	1			T46	2922		T39	256		T43	66
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2339	1			T9	38		T14	7		T25	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	48594	1			T4	1866		T9	1		T14	4
auto[1]	auto[0]	auto[0:524287]	auto[0]	629	1			T4	2		T14	3		T15	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	4397	1			T4	3		T14	20		T15	85
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	428	1			T4	1		T9	2		T39	7
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2229	1			T4	3		T39	36		T43	14
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	402	1			T4	1		T14	1		T25	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3615	1			T14	2		T25	15		T39	10
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	460	1			T9	7		T39	1		T84	29
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2330	1			T9	390		T39	4		T84	142
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	376	1			T4	1		T9	13		T14	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2578	1			T4	4		T14	4		T15	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	425	1			T4	2		T6	1		T84	18
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1858	1			T4	1		T6	16		T47	8
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	437	1			T6	1		T9	24		T14	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1915	1			T6	8		T9	128		T14	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	361	1			T9	2		T14	1		T46	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2173	1			T14	3		T39	18		T172	14
auto[1]	auto[1]	auto[0:524287]	auto[0]	120	1			T172	1		T96	9		T49	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	1296	1			T172	7		T96	61		T49	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	109	1			T46	3		T84	11		T171	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	748	1			T171	38		T233	1		T221	34
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	70	1			T4	2		T6	1		T9	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	301	1			T4	3		T6	7		T25	49
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	33	1			T83	1		T81	2		T21	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	176	1			T83	21		T81	21		T21	8
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	91	1			T4	1		T9	2		T25	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	457	1			T4	2		T25	18		T17	95
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	117	1			T9	7		T25	1		T45	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1327	1			T25	8		T198	1		T21	14
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	69	1			T9	6		T96	12		T171	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	369	1			T171	43		T234	28		T192	34
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	110	1			T9	13		T14	4		T83	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1054	1			T9	484		T14	24		T83	8

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2134822	1			T1	7		T4	14753		T5	1
auto[0]	auto[0]	auto[1]	1093523	1			T1	15		T7	1496		T13	301
auto[0]	auto[1]	auto[0]	356046	1			T4	7887		T6	3		T9	502
auto[0]	auto[1]	auto[1]	4160	1			T25	2		T172	1		T171	1
auto[1]	auto[0]	auto[0]	23973	1			T4	18		T6	25		T9	558
auto[1]	auto[0]	auto[1]	640	1			T6	1		T9	8		T46	2
auto[1]	auto[1]	auto[0]	6347	1			T4	8		T6	8		T9	510
auto[1]	auto[1]	auto[1]	100	1			T9	5		T46	1		T39	1