Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2632010	1			T1	1		T4	21509		T5	1
all_pins[1]	2632010	1			T1	1		T4	21509		T5	1
all_pins[2]	2632010	1			T1	1		T4	21509		T5	1
all_pins[3]	2632010	1			T1	1		T4	21509		T5	1
all_pins[4]	2632010	1			T1	1		T4	21509		T5	1
all_pins[5]	2632010	1			T1	1		T4	21509		T5	1
all_pins[6]	2632010	1			T1	1		T4	21509		T5	1
all_pins[7]	2632010	1			T1	1		T4	21509		T5	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21036051	1			T1	8		T4	172072		T5	8
values[0x1]	20029	1			T14	593		T17	24		T19	21
transitions[0x0=>0x1]	19398	1			T14	527		T17	19		T19	16
transitions[0x1=>0x0]	19411	1			T14	527		T17	19		T19	16

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2631493	1			T1	1		T4	21509		T5	1
all_pins[0]	values[0x1]	517	1			T14	110		T17	1		T19	3
all_pins[0]	transitions[0x0=>0x1]	317	1			T14	46		T19	3		T22	1
all_pins[0]	transitions[0x1=>0x0]	232	1			T14	3		T19	3		T21	2
all_pins[1]	values[0x0]	2631578	1			T1	1		T4	21509		T5	1
all_pins[1]	values[0x1]	432	1			T14	67		T17	1		T19	3
all_pins[1]	transitions[0x0=>0x1]	322	1			T14	67		T17	1		T19	2
all_pins[1]	transitions[0x1=>0x0]	188	1			T14	1		T17	11		T19	2
all_pins[2]	values[0x0]	2631712	1			T1	1		T4	21509		T5	1
all_pins[2]	values[0x1]	298	1			T14	1		T17	11		T19	3
all_pins[2]	transitions[0x0=>0x1]	252	1			T17	11		T19	3		T21	1
all_pins[2]	transitions[0x1=>0x0]	154	1			T14	1		T17	3		T19	1
all_pins[3]	values[0x0]	2631810	1			T1	1		T4	21509		T5	1
all_pins[3]	values[0x1]	200	1			T14	2		T17	3		T19	1
all_pins[3]	transitions[0x0=>0x1]	139	1			T14	1		T17	1		T22	2
all_pins[3]	transitions[0x1=>0x0]	136	1			T14	1		T17	2		T19	3
all_pins[4]	values[0x0]	2631813	1			T1	1		T4	21509		T5	1
all_pins[4]	values[0x1]	197	1			T14	2		T17	4		T19	4
all_pins[4]	transitions[0x0=>0x1]	143	1			T14	2		T17	2		T19	4
all_pins[4]	transitions[0x1=>0x0]	843	1			T14	410		T17	1		T19	1
all_pins[5]	values[0x0]	2631113	1			T1	1		T4	21509		T5	1
all_pins[5]	values[0x1]	897	1			T14	410		T17	3		T19	1
all_pins[5]	transitions[0x0=>0x1]	856	1			T14	410		T17	3		T19	1
all_pins[5]	transitions[0x1=>0x0]	17235	1			T14	1		T19	2		T22	3
all_pins[6]	values[0x0]	2614734	1			T1	1		T4	21509		T5	1
all_pins[6]	values[0x1]	17276	1			T14	1		T19	2		T22	4
all_pins[6]	transitions[0x0=>0x1]	17218	1			T14	1		T19	1		T22	2
all_pins[6]	transitions[0x1=>0x0]	154	1			T17	1		T19	3		T21	3
all_pins[7]	values[0x0]	2631798	1			T1	1		T4	21509		T5	1
all_pins[7]	values[0x1]	212	1			T17	1		T19	4		T21	3
all_pins[7]	transitions[0x0=>0x1]	151	1			T17	1		T19	2		T21	3
all_pins[7]	transitions[0x1=>0x0]	469	1			T14	110		T17	1		T19	1