Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18710

1

T1

2

T4

135

T7

12

auto[1]

13108

1

T4

111

T5

18

T9

100

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4379	1			T9	40		T97	22		T46	60
values[1]	3488	1			T4	20		T9	40		T14	44
values[2]	3941	1			T14	20		T46	60		T199	64
values[3]	4040	1			T4	41		T5	18		T9	40
values[4]	4102	1			T4	50		T7	12		T9	20
values[5]	3625	1			T1	2		T4	20		T9	40
values[6]	4073	1			T4	20		T9	40		T14	20
values[7]	4170	1			T4	95		T9	20		T14	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3594	1			T4	20		T5	18		T9	40
values[1]	3262	1			T4	21		T14	52		T25	98
values[2]	3812	1			T1	2		T4	75		T9	40
values[3]	4226	1			T9	40		T14	59		T44	14
values[4]	3693	1			T4	20		T7	12		T9	20
values[5]	4071	1			T4	20		T9	20		T14	20
values[6]	4670	1			T4	67		T9	60		T14	24
values[7]	4490	1			T4	23		T9	20		T14	46

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	288	1			T46	12		T49	19		T17	14
auto[0]	values[0]	values[1]	278	1			T45	13		T49	14		T17	48
auto[0]	values[0]	values[2]	472	1			T9	16		T45	13		T188	15
auto[0]	values[0]	values[3]	424	1			T97	22		T191	12		T235	10
auto[0]	values[0]	values[4]	371	1			T46	15		T39	16		T48	13
auto[0]	values[0]	values[5]	255	1			T46	10		T236	4		T17	25
auto[0]	values[0]	values[6]	334	1			T228	8		T17	14		T64	10
auto[0]	values[0]	values[7]	347	1			T9	9		T39	7		T49	11
auto[0]	values[1]	values[0]	280	1			T39	17		T48	16		T188	21
auto[0]	values[1]	values[1]	172	1			T14	9		T45	9		T237	10
auto[0]	values[1]	values[2]	266	1			T49	14		T238	12		T21	12
auto[0]	values[1]	values[3]	262	1			T9	12		T45	16		T239	6
auto[0]	values[1]	values[4]	282	1			T197	17		T240	16		T241	9
auto[0]	values[1]	values[5]	178	1			T4	10		T191	40		T242	18
auto[0]	values[1]	values[6]	228	1			T9	9		T14	11		T45	14
auto[0]	values[1]	values[7]	252	1			T243	16		T191	13		T22	14
auto[0]	values[2]	values[0]	303	1			T46	9		T189	17		T223	12
auto[0]	values[2]	values[1]	161	1			T46	9		T61	16		T21	10
auto[0]	values[2]	values[2]	270	1			T244	10		T21	9		T227	17
auto[0]	values[2]	values[3]	361	1			T17	32		T223	23		T215	10
auto[0]	values[2]	values[4]	245	1			T49	14		T189	14		T223	10
auto[0]	values[2]	values[5]	171	1			T17	13		T21	14		T169	10
auto[0]	values[2]	values[6]	298	1			T46	8		T199	64		T49	18
auto[0]	values[2]	values[7]	512	1			T14	8		T245	16		T54	14
auto[0]	values[3]	values[0]	281	1			T9	12		T25	33		T39	13
auto[0]	values[3]	values[1]	259	1			T4	8		T25	9		T17	10
auto[0]	values[3]	values[2]	205	1			T9	10		T246	8		T195	70
auto[0]	values[3]	values[3]	325	1			T14	30		T45	14		T247	4
auto[0]	values[3]	values[4]	221	1			T192	10		T205	15		T197	12
auto[0]	values[3]	values[5]	262	1			T25	42		T190	9		T231	12
auto[0]	values[3]	values[6]	401	1			T4	12		T48	7		T191	17
auto[0]	values[3]	values[7]	209	1			T48	13		T17	6		T54	8
auto[0]	values[4]	values[0]	215	1			T212	4		T191	10		T165	26
auto[0]	values[4]	values[1]	322	1			T14	24		T248	8		T49	8
auto[0]	values[4]	values[2]	275	1			T4	24		T99	22		T47	13
auto[0]	values[4]	values[3]	307	1			T249	8		T105	16		T48	15
auto[0]	values[4]	values[4]	197	1			T7	12		T9	15		T46	14
auto[0]	values[4]	values[5]	406	1			T213	4		T93	6		T17	11
auto[0]	values[4]	values[6]	250	1			T45	6		T21	12		T227	11
auto[0]	values[4]	values[7]	445	1			T200	12		T49	11		T62	12
auto[0]	values[5]	values[0]	185	1			T48	13		T191	11		T21	15
auto[0]	values[5]	values[1]	236	1			T17	13		T191	9		T211	14
auto[0]	values[5]	values[2]	254	1			T1	2		T14	8		T49	12
auto[0]	values[5]	values[3]	210	1			T48	11		T193	75		T250	8
auto[0]	values[5]	values[4]	246	1			T4	13		T189	10		T169	13
auto[0]	values[5]	values[5]	324	1			T9	11		T14	12		T251	2
auto[0]	values[5]	values[6]	421	1			T9	9		T24	10		T39	23
auto[0]	values[5]	values[7]	241	1			T14	8		T190	14		T21	12
auto[0]	values[6]	values[0]	159	1			T4	13		T9	14		T49	10
auto[0]	values[6]	values[1]	166	1			T188	16		T221	12		T252	12
auto[0]	values[6]	values[2]	249	1			T47	11		T48	14		T253	12
auto[0]	values[6]	values[3]	491	1			T9	12		T14	10		T45	12
auto[0]	values[6]	values[4]	460	1			T39	29		T47	13		T17	20
auto[0]	values[6]	values[5]	386	1			T39	10		T45	13		T47	32
auto[0]	values[6]	values[6]	298	1			T45	10		T254	6		T255	12
auto[0]	values[6]	values[7]	233	1			T39	14		T256	6		T48	9
auto[0]	values[7]	values[0]	306	1			T39	16		T17	12		T54	12
auto[0]	values[7]	values[1]	295	1			T46	13		T191	11		T22	16
auto[0]	values[7]	values[2]	377	1			T4	10		T14	11		T257	4
auto[0]	values[7]	values[3]	247	1			T44	14		T17	27		T191	11
auto[0]	values[7]	values[4]	191	1			T46	11		T39	9		T17	15
auto[0]	values[7]	values[5]	276	1			T46	6		T218	4		T188	15
auto[0]	values[7]	values[6]	413	1			T4	31		T9	11		T216	4
auto[0]	values[7]	values[7]	456	1			T4	14		T209	6		T53	133
auto[1]	values[0]	values[0]	296	1			T46	8		T49	4		T17	108
auto[1]	values[0]	values[1]	114	1			T45	7		T49	8		T17	2
auto[1]	values[0]	values[2]	201	1			T9	4		T45	7		T188	5
auto[1]	values[0]	values[3]	226	1			T191	8		T189	12		T201	26
auto[1]	values[0]	values[4]	176	1			T46	5		T39	13		T48	7
auto[1]	values[0]	values[5]	272	1			T46	10		T17	16		T227	6
auto[1]	values[0]	values[6]	181	1			T228	12		T17	6		T21	3
auto[1]	values[0]	values[7]	144	1			T9	11		T39	13		T49	11
auto[1]	values[1]	values[0]	158	1			T39	12		T48	4		T188	19
auto[1]	values[1]	values[1]	180	1			T14	11		T45	11		T188	12
auto[1]	values[1]	values[2]	198	1			T49	6		T21	70		T22	5
auto[1]	values[1]	values[3]	97	1			T9	8		T45	4		T17	9
auto[1]	values[1]	values[4]	177	1			T197	3		T240	43		T241	23
auto[1]	values[1]	values[5]	160	1			T4	10		T191	20		T189	20
auto[1]	values[1]	values[6]	474	1			T9	11		T14	13		T45	6
auto[1]	values[1]	values[7]	124	1			T191	7		T22	6		T208	7
auto[1]	values[2]	values[0]	116	1			T46	11		T189	4		T223	14
auto[1]	values[2]	values[1]	250	1			T46	11		T258	26		T21	10
auto[1]	values[2]	values[2]	282	1			T21	11		T227	9		T193	10
auto[1]	values[2]	values[3]	243	1			T259	2		T17	14		T223	7
auto[1]	values[2]	values[4]	138	1			T49	9		T189	11		T223	10
auto[1]	values[2]	values[5]	127	1			T17	7		T21	6		T169	10
auto[1]	values[2]	values[6]	187	1			T46	12		T49	2		T21	5
auto[1]	values[2]	values[7]	277	1			T14	12		T54	6		T21	6
auto[1]	values[3]	values[0]	424	1			T5	18		T9	8		T25	23
auto[1]	values[3]	values[1]	259	1			T4	13		T25	89		T17	22
auto[1]	values[3]	values[2]	88	1			T9	10		T195	6		T205	11
auto[1]	values[3]	values[3]	347	1			T14	9		T45	6		T48	7
auto[1]	values[3]	values[4]	129	1			T192	21		T205	6		T197	8
auto[1]	values[3]	values[5]	207	1			T25	7		T190	14		T192	10
auto[1]	values[3]	values[6]	266	1			T4	8		T48	13		T191	23
auto[1]	values[3]	values[7]	157	1			T48	7		T17	18		T54	15
auto[1]	values[4]	values[0]	114	1			T191	10		T165	7		T169	9
auto[1]	values[4]	values[1]	171	1			T14	8		T49	12		T188	11
auto[1]	values[4]	values[2]	193	1			T4	26		T47	7		T191	8
auto[1]	values[4]	values[3]	110	1			T48	5		T196	4		T260	20
auto[1]	values[4]	values[4]	147	1			T9	5		T46	6		T39	8
auto[1]	values[4]	values[5]	334	1			T207	14		T17	9		T227	5
auto[1]	values[4]	values[6]	212	1			T45	14		T21	31		T227	10
auto[1]	values[4]	values[7]	404	1			T49	9		T21	8		T169	4
auto[1]	values[5]	values[0]	133	1			T48	7		T191	9		T21	7
auto[1]	values[5]	values[1]	136	1			T17	12		T191	11		T78	2
auto[1]	values[5]	values[2]	197	1			T14	40		T49	10		T261	20
auto[1]	values[5]	values[3]	92	1			T48	9		T193	9		T262	6
auto[1]	values[5]	values[4]	229	1			T4	7		T263	6		T189	10
auto[1]	values[5]	values[5]	219	1			T9	9		T14	8		T49	15
auto[1]	values[5]	values[6]	291	1			T9	11		T39	68		T232	9
auto[1]	values[5]	values[7]	211	1			T14	18		T190	8		T21	8
auto[1]	values[6]	values[0]	166	1			T4	7		T9	6		T49	10
auto[1]	values[6]	values[1]	82	1			T188	5		T221	8		T264	8
auto[1]	values[6]	values[2]	182	1			T47	31		T48	6		T189	11
auto[1]	values[6]	values[3]	281	1			T9	8		T14	10		T45	8
auto[1]	values[6]	values[4]	237	1			T39	9		T47	7		T17	11
auto[1]	values[6]	values[5]	261	1			T39	16		T45	7		T47	8
auto[1]	values[6]	values[6]	159	1			T45	10		T190	7		T54	15
auto[1]	values[6]	values[7]	263	1			T39	44		T48	11		T265	7
auto[1]	values[7]	values[0]	170	1			T39	8		T17	13		T54	8
auto[1]	values[7]	values[1]	181	1			T46	7		T191	9		T22	9
auto[1]	values[7]	values[2]	103	1			T4	15		T14	9		T193	11
auto[1]	values[7]	values[3]	203	1			T17	10		T191	9		T201	7
auto[1]	values[7]	values[4]	247	1			T46	9		T39	18		T17	25
auto[1]	values[7]	values[5]	233	1			T46	14		T188	10		T17	9
auto[1]	values[7]	values[6]	257	1			T4	16		T9	9		T48	3
auto[1]	values[7]	values[7]	215	1			T4	9		T189	9		T55	9