Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	416	1			T4	3		T9	6		T14	2
auto[ReadAddrCrossIntoMailbox]	299	1			T4	1		T9	2		T14	1
auto[ReadAddrCrossOutOfMailbox]	316	1			T4	4		T9	4		T14	2
auto[ReadAddrCrossAllMailbox]	208	1			T4	2		T9	1		T45	1
auto[ReadAddrOutsideMailbox]	3732	1			T4	34		T5	6		T9	28

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2424

1

T4

21

T5

3

T9

11

auto[1]

2547

1

T4

23

T5

3

T9

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	811	1			T4	7		T9	8		T14	7
read_ops[0x0b]	784	1			T4	7		T5	4		T9	8
read_ops[0x3b]	838	1			T4	8		T5	2		T9	7
read_ops[0x6b]	899	1			T4	9		T9	5		T14	6
read_ops[0xbb]	840	1			T4	7		T9	6		T14	8
read_ops[0xeb]	799	1			T4	6		T9	7		T14	5

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T9	1		T14	1		T104	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T4	1		T46	1		T104	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T48	1		T54	1		T246	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T9	1		T46	1		T190	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T4	2		T45	1		T21	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T9	2		T46	1		T47	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T4	1		T188	1		T21	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T17	1		T190	1		T21	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T4	1		T9	1		T14	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	357	1			T4	2		T9	3		T14	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T17	1		T190	1		T202	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T9	1		T39	1		T190	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T49	2		T17	2		T62	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T9	1		T25	1		T46	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T48	1		T191	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T21	3		T201	3		T154	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T62	1		T35	1		T266	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T62	1		T21	1		T201	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	237	1			T4	3		T5	2		T9	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	323	1			T4	4		T5	2		T9	5
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T4	1		T46	1		T39	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T9	1		T104	1		T48	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T14	1		T52	2		T188	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T4	1		T25	1		T17	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T4	1		T47	1		T17	3
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T9	1		T25	1		T48	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T48	1		T49	1		T190	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T9	1		T223	1		T192	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	322	1			T4	1		T5	1		T9	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	294	1			T4	4		T5	1		T9	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T52	1		T47	1		T48	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	48	1			T242	3		T169	2		T152	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T17	1		T154	1		T192	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T45	2		T188	1		T191	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T25	1		T52	2		T47	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T4	1		T46	2		T48	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T47	1		T48	1		T17	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T17	1		T190	1		T169	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	334	1			T4	3		T9	1		T25	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	323	1			T4	5		T9	4		T14	6
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T4	1		T9	1		T46	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T9	1		T14	1		T45	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T25	1		T39	1		T49	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T39	1		T45	1		T48	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T25	1		T46	1		T188	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T14	1		T39	1		T62	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T48	1		T220	1		T205	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T190	1		T21	1		T189	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	338	1			T4	4		T14	6		T97	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T4	2		T9	4		T97	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T25	2		T202	1		T154	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T9	1		T17	5		T165	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T21	1		T193	1		T221	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T47	1		T17	1		T54	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T9	1		T14	1		T48	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T39	1		T49	2		T17	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T45	1		T190	1		T201	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T4	1		T188	1		T21	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	305	1			T4	3		T9	3		T14	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	300	1			T4	2		T9	2		T14	2