Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4001	1			T9	20		T14	80		T25	36
values[1]	3673	1			T4	69		T5	18		T9	20
values[2]	3470	1			T9	20		T97	22		T46	20
values[3]	4241	1			T4	70		T9	20		T14	44
values[4]	4444	1			T4	23		T9	40		T14	40
values[5]	4223	1			T4	20		T9	20		T14	26
values[6]	4118	1			T1	2		T4	24		T9	60
values[7]	3648	1			T4	40		T7	12		T9	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4242	1			T4	20		T9	60		T14	39
values[1]	4027	1			T4	25		T5	18		T7	12
values[2]	3970	1			T9	40		T14	46		T46	40
values[3]	3929	1			T4	24		T14	24		T46	60
values[4]	4697	1			T1	2		T4	47		T9	20
values[5]	3873	1			T4	23		T25	56		T44	14
values[6]	3968	1			T4	87		T9	60		T14	88
values[7]	3112	1			T4	20		T9	20		T46	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31040

1

T1

2

T4

236

T5

18

auto[1]

778

1

T4

10

T9

2

T14

11

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	451	1			T48	20		T49	22		T190	20
auto[0]	values[0]	values[1]	577	1			T14	27		T251	2		T255	12
auto[0]	values[0]	values[2]	446	1			T46	20		T49	20		T21	20
auto[0]	values[0]	values[3]	572	1			T39	28		T47	18		T49	18
auto[0]	values[0]	values[4]	485	1			T39	20		T191	20		T192	170
auto[0]	values[0]	values[5]	507	1			T25	36		T248	8		T48	19
auto[0]	values[0]	values[6]	662	1			T9	20		T14	47		T39	25
auto[0]	values[0]	values[7]	213	1			T267	20		T215	25		T193	19
auto[0]	values[1]	values[0]	635	1			T14	37		T212	4		T45	19
auto[0]	values[1]	values[1]	441	1			T4	25		T5	18		T14	20
auto[0]	values[1]	values[2]	231	1			T9	20		T190	40		T268	8
auto[0]	values[1]	values[3]	484	1			T200	12		T269	2		T21	73
auto[0]	values[1]	values[4]	624	1			T39	67		T45	20		T239	6
auto[0]	values[1]	values[5]	321	1			T44	14		T237	10		T22	31
auto[0]	values[1]	values[6]	415	1			T4	42		T201	23		T192	55
auto[0]	values[1]	values[7]	423	1			T17	50		T189	24		T134	23
auto[0]	values[2]	values[0]	322	1			T9	20		T97	22		T17	39
auto[0]	values[2]	values[1]	278	1			T45	20		T254	6		T54	20
auto[0]	values[2]	values[2]	444	1			T17	52		T190	17		T221	71
auto[0]	values[2]	values[3]	445	1			T46	20		T39	34		T47	41
auto[0]	values[2]	values[4]	315	1			T48	20		T17	25		T189	18
auto[0]	values[2]	values[5]	629	1			T199	64		T99	22		T49	21
auto[0]	values[2]	values[6]	478	1			T39	20		T249	8		T17	21
auto[0]	values[2]	values[7]	455	1			T49	20		T191	18		T193	40
auto[0]	values[3]	values[0]	611	1			T46	17		T218	4		T17	25
auto[0]	values[3]	values[1]	538	1			T45	17		T216	4		T258	26
auto[0]	values[3]	values[2]	473	1			T14	18		T46	20		T188	20
auto[0]	values[3]	values[3]	701	1			T14	24		T17	20		T21	20
auto[0]	values[3]	values[4]	570	1			T4	46		T9	20		T53	133
auto[0]	values[3]	values[5]	438	1			T17	56		T21	107		T222	39
auto[0]	values[3]	values[6]	516	1			T4	22		T25	49		T192	31
auto[0]	values[3]	values[7]	298	1			T39	28		T191	20		T227	19
auto[0]	values[4]	values[0]	752	1			T47	19		T48	20		T64	10
auto[0]	values[4]	values[1]	395	1			T9	19		T188	20		T17	19
auto[0]	values[4]	values[2]	559	1			T45	18		T202	14		T235	10
auto[0]	values[4]	values[3]	651	1			T39	40		T45	20		T245	16
auto[0]	values[4]	values[4]	568	1			T14	19		T17	20		T189	21
auto[0]	values[4]	values[5]	556	1			T4	22		T25	19		T39	26
auto[0]	values[4]	values[6]	496	1			T9	20		T14	20		T46	18
auto[0]	values[4]	values[7]	355	1			T270	10		T271	8		T215	20
auto[0]	values[5]	values[0]	544	1			T46	20		T17	126		T152	20
auto[0]	values[5]	values[1]	524	1			T9	20		T52	22		T191	20
auto[0]	values[5]	values[2]	607	1			T14	26		T209	6		T213	4
auto[0]	values[5]	values[3]	402	1			T46	20		T45	20		T162	10
auto[0]	values[5]	values[4]	816	1			T25	94		T247	4		T49	20
auto[0]	values[5]	values[5]	440	1			T45	18		T185	4		T48	20
auto[0]	values[5]	values[6]	240	1			T39	35		T35	29		T195	23
auto[0]	values[5]	values[7]	546	1			T4	16		T105	16		T272	12
auto[0]	values[6]	values[0]	541	1			T9	20		T188	20		T228	19
auto[0]	values[6]	values[1]	701	1			T46	19		T48	20		T244	10
auto[0]	values[6]	values[2]	492	1			T17	39		T21	19		T231	12
auto[0]	values[6]	values[3]	364	1			T4	23		T17	20		T273	14
auto[0]	values[6]	values[4]	577	1			T1	2		T24	10		T48	20
auto[0]	values[6]	values[5]	381	1			T49	18		T152	20		T154	27
auto[0]	values[6]	values[6]	586	1			T9	20		T14	20		T236	4
auto[0]	values[6]	values[7]	386	1			T9	19		T46	19		T39	20
auto[0]	values[7]	values[0]	280	1			T4	20		T9	20		T104	8
auto[0]	values[7]	values[1]	468	1			T7	12		T17	120		T190	20
auto[0]	values[7]	values[2]	628	1			T9	20		T45	20		T21	56
auto[0]	values[7]	values[3]	222	1			T46	20		T45	20		T191	19
auto[0]	values[7]	values[4]	618	1			T21	20		T274	4		T215	20
auto[0]	values[7]	values[5]	511	1			T47	39		T189	20		T201	20
auto[0]	values[7]	values[6]	481	1			T4	20		T243	16		T54	21
auto[0]	values[7]	values[7]	355	1			T39	24		T49	22		T188	21
auto[1]	values[0]	values[0]	6	1			T190	1		T192	2		T275	1
auto[1]	values[0]	values[1]	20	1			T14	5		T260	2		T240	3
auto[1]	values[0]	values[2]	8	1			T152	1		T154	1		T55	1
auto[1]	values[0]	values[3]	11	1			T39	1		T47	2		T49	2
auto[1]	values[0]	values[4]	12	1			T192	4		T221	3		T276	1
auto[1]	values[0]	values[5]	15	1			T48	1		T190	3		T194	3
auto[1]	values[0]	values[6]	13	1			T14	1		T39	1		T48	3
auto[1]	values[0]	values[7]	3	1			T193	1		T277	1		T278	1
auto[1]	values[1]	values[0]	24	1			T14	2		T45	1		T48	1
auto[1]	values[1]	values[1]	12	1			T21	1		T223	2		T279	1
auto[1]	values[1]	values[2]	7	1			T190	2		T280	4		T281	1
auto[1]	values[1]	values[3]	11	1			T21	1		T223	1		T159	1
auto[1]	values[1]	values[4]	18	1			T39	4		T48	1		T188	2
auto[1]	values[1]	values[5]	13	1			T189	2		T282	2		T283	6
auto[1]	values[1]	values[6]	5	1			T4	2		T192	1		T284	1
auto[1]	values[1]	values[7]	9	1			T134	2		T285	2		T286	3
auto[1]	values[2]	values[0]	5	1			T17	1		T191	2		T22	1
auto[1]	values[2]	values[1]	5	1			T227	2		T287	1		T288	2
auto[1]	values[2]	values[2]	13	1			T17	1		T190	3		T221	3
auto[1]	values[2]	values[3]	18	1			T39	4		T47	1		T17	5
auto[1]	values[2]	values[4]	13	1			T189	2		T208	4		T221	1
auto[1]	values[2]	values[5]	11	1			T49	1		T289	1		T290	2
auto[1]	values[2]	values[6]	23	1			T17	5		T192	1		T215	1
auto[1]	values[2]	values[7]	16	1			T49	2		T191	2		T193	2
auto[1]	values[3]	values[0]	16	1			T46	3		T265	1		T134	4
auto[1]	values[3]	values[1]	23	1			T45	3		T190	2		T22	3
auto[1]	values[3]	values[2]	5	1			T14	2		T193	1		T285	2
auto[1]	values[3]	values[3]	12	1			T189	2		T291	4		T292	1
auto[1]	values[3]	values[4]	12	1			T4	1		T215	2		T195	1
auto[1]	values[3]	values[5]	8	1			T17	1		T21	1		T222	2
auto[1]	values[3]	values[6]	10	1			T4	1		T293	2		T240	2
auto[1]	values[3]	values[7]	10	1			T39	1		T227	2		T197	1
auto[1]	values[4]	values[0]	22	1			T47	1		T35	1		T294	1
auto[1]	values[4]	values[1]	7	1			T9	1		T17	1		T197	2
auto[1]	values[4]	values[2]	14	1			T45	2		T193	1		T295	2
auto[1]	values[4]	values[3]	13	1			T188	1		T201	1		T194	1
auto[1]	values[4]	values[4]	13	1			T14	1		T240	1		T296	4
auto[1]	values[4]	values[5]	16	1			T4	1		T25	1		T39	1
auto[1]	values[4]	values[6]	13	1			T46	2		T259	2		T54	3
auto[1]	values[4]	values[7]	14	1			T193	3		T241	4		T297	1
auto[1]	values[5]	values[0]	13	1			T17	2		T215	1		T221	3
auto[1]	values[5]	values[1]	14	1			T21	6		T284	2		T286	1
auto[1]	values[5]	values[2]	13	1			T169	2		T201	1		T223	2
auto[1]	values[5]	values[3]	9	1			T22	1		T298	2		T299	1
auto[1]	values[5]	values[4]	26	1			T25	4		T17	3		T152	2
auto[1]	values[5]	values[5]	7	1			T45	2		T295	1		T300	2
auto[1]	values[5]	values[6]	8	1			T39	3		T133	2		T134	1
auto[1]	values[5]	values[7]	14	1			T4	4		T301	1		T302	2
auto[1]	values[6]	values[0]	13	1			T228	1		T192	1		T195	3
auto[1]	values[6]	values[1]	15	1			T46	1		T227	1		T192	1
auto[1]	values[6]	values[2]	15	1			T17	1		T21	1		T284	2
auto[1]	values[6]	values[3]	7	1			T4	1		T17	1		T192	1
auto[1]	values[6]	values[4]	15	1			T169	1		T201	2		T303	1
auto[1]	values[6]	values[5]	10	1			T49	2		T290	3		T280	2
auto[1]	values[6]	values[6]	9	1			T260	1		T304	1		T203	1
auto[1]	values[6]	values[7]	6	1			T9	1		T46	1		T188	1
auto[1]	values[7]	values[0]	7	1			T191	2		T215	1		T304	1
auto[1]	values[7]	values[1]	9	1			T17	2		T201	3		T195	3
auto[1]	values[7]	values[2]	15	1			T223	2		T193	1		T241	1
auto[1]	values[7]	values[3]	7	1			T191	1		T225	1		T305	1
auto[1]	values[7]	values[4]	15	1			T35	1		T222	4		T196	3
auto[1]	values[7]	values[5]	10	1			T47	1		T189	1		T192	2
auto[1]	values[7]	values[6]	13	1			T54	2		T22	2		T201	1
auto[1]	values[7]	values[7]	9	1			T303	1		T265	2		T306	3